drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40 #include "core.h"
  41 #include "common.h"
  42
  43
  44 enum brcmf_pcie_state {
  45         BRCMFMAC_PCIE_STATE_DOWN,
  46         BRCMFMAC_PCIE_STATE_UP
  47 };
  48
  49 BRCMF_FW_NVRAM_DEF(43602, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  50 BRCMF_FW_NVRAM_DEF(4350, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  51 BRCMF_FW_NVRAM_DEF(4350C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  52 BRCMF_FW_NVRAM_DEF(4356, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  53 BRCMF_FW_NVRAM_DEF(43570, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  54 BRCMF_FW_NVRAM_DEF(4358, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  55 BRCMF_FW_NVRAM_DEF(4359, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  56 BRCMF_FW_NVRAM_DEF(4365B, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  57 BRCMF_FW_NVRAM_DEF(4365C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  58 BRCMF_FW_NVRAM_DEF(4366B, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  59 BRCMF_FW_NVRAM_DEF(4366C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  60 BRCMF_FW_NVRAM_DEF(4371, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  61
  62 static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
  63         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
  64         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
  65         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
  66         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
  67         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
  68         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
  69         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
  70         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
  71         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
  72         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
  73         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
  74         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
  75         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
  76         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
  77         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
  78         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
  79 };
  80
  81 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  82
  83 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  84
  85 /* backplane addres space accessed by BAR0 */
  86 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  87 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  88 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  89
  90 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  91 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  92
  93 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  94 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  95
  96 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  97 #define BRCMF_PCIE_REG_INTMASK                  0x94
  98 #define BRCMF_PCIE_REG_SBMBX                    0x98
  99
 100 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
 101
 102 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
 103 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
 104 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
 105 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
 106 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
 107 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
 108
 109 #define BRCMF_PCIE2_INTA                        0x01
 110 #define BRCMF_PCIE2_INTB                        0x02
 111
 112 #define BRCMF_PCIE_INT_0                        0x01
 113 #define BRCMF_PCIE_INT_1                        0x02
 114 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 115                                                  BRCMF_PCIE_INT_1)
 116
 117 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 118 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 119 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 120 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 121 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 122 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 123 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 124 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 125 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 126 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 127
 128 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 129                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 130                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 131                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 132                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 133                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 134                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 135                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 136
 137 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 138 #define BRCMF_PCIE_MAX_SHARED_VERSION           6
 139 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 140 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 141 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 142
 143 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 144 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 145
 146 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 147 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 148 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 149 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 150 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 151 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 152 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 153 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 154 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 155 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 156 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 157
 158 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 159 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 160 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 161 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 162
 163 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 164 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 165 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 166 #define BRCMF_RING_MEM_SZ                       16
 167 #define BRCMF_RING_STATE_SZ                     8
 168
 169 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 170
 171 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 172 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 173 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 174
 175 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 176 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 177
 178 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 179 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 180 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 181
 182 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 183 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 184 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 185 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 186
 187 #define BRCMF_PCIE_MBDATA_TIMEOUT               msecs_to_jiffies(2000)
 188
 189 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 190 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 191 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 192 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 193 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 194 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 195 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 196 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 197 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 198 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 199 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 200 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 201 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 202
 203 /* Magic number at a magic location to find RAM size */
 204 #define BRCMF_RAMSIZE_MAGIC                     0x534d4152      /* SMAR */
 205 #define BRCMF_RAMSIZE_OFFSET                    0x6c
 206
 207
 208 struct brcmf_pcie_console {
 209         u32 base_addr;
 210         u32 buf_addr;
 211         u32 bufsize;
 212         u32 read_idx;
 213         u8 log_str[256];
 214         u8 log_idx;
 215 };
 216
 217 struct brcmf_pcie_shared_info {
 218         u32 tcm_base_address;
 219         u32 flags;
 220         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 221         struct brcmf_pcie_ringbuf *flowrings;
 222         u16 max_rxbufpost;
 223         u16 max_flowrings;
 224         u16 max_submissionrings;
 225         u16 max_completionrings;
 226         u32 rx_dataoffset;
 227         u32 htod_mb_data_addr;
 228         u32 dtoh_mb_data_addr;
 229         u32 ring_info_addr;
 230         struct brcmf_pcie_console console;
 231         void *scratch;
 232         dma_addr_t scratch_dmahandle;
 233         void *ringupd;
 234         dma_addr_t ringupd_dmahandle;
 235         u8 version;
 236 };
 237
 238 struct brcmf_pcie_core_info {
 239         u32 base;
 240         u32 wrapbase;
 241 };
 242
 243 struct brcmf_pciedev_info {
 244         enum brcmf_pcie_state state;
 245         bool in_irq;
 246         struct pci_dev *pdev;
 247         char fw_name[BRCMF_FW_NAME_LEN];
 248         char nvram_name[BRCMF_FW_NAME_LEN];
 249         void __iomem *regs;
 250         void __iomem *tcm;
 251         u32 ram_base;
 252         u32 ram_size;
 253         struct brcmf_chip *ci;
 254         u32 coreid;
 255         struct brcmf_pcie_shared_info shared;
 256         wait_queue_head_t mbdata_resp_wait;
 257         bool mbdata_completed;
 258         bool irq_allocated;
 259         bool wowl_enabled;
 260         u8 dma_idx_sz;
 261         void *idxbuf;
 262         u32 idxbuf_sz;
 263         dma_addr_t idxbuf_dmahandle;
 264         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 265         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 266                           u16 value);
 267         struct brcmf_mp_device *settings;
 268 };
 269
 270 struct brcmf_pcie_ringbuf {
 271         struct brcmf_commonring commonring;
 272         dma_addr_t dma_handle;
 273         u32 w_idx_addr;
 274         u32 r_idx_addr;
 275         struct brcmf_pciedev_info *devinfo;
 276         u8 id;
 277 };
 278
 279 /**
 280  * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
 281  *
 282  * @ringmem: dongle memory pointer to ring memory location
 283  * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
 284  * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
 285  * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
 286  * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
 287  * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
 288  * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
 289  * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
 290  * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
 291  * @max_flowrings: maximum number of tx flow rings supported.
 292  * @max_submissionrings: maximum number of submission rings(h2d) supported.
 293  * @max_completionrings: maximum number of completion rings(d2h) supported.
 294  */
 295 struct brcmf_pcie_dhi_ringinfo {
 296         __le32                  ringmem;
 297         __le32                  h2d_w_idx_ptr;
 298         __le32                  h2d_r_idx_ptr;
 299         __le32                  d2h_w_idx_ptr;
 300         __le32                  d2h_r_idx_ptr;
 301         struct msgbuf_buf_addr  h2d_w_idx_hostaddr;
 302         struct msgbuf_buf_addr  h2d_r_idx_hostaddr;
 303         struct msgbuf_buf_addr  d2h_w_idx_hostaddr;
 304         struct msgbuf_buf_addr  d2h_r_idx_hostaddr;
 305         __le16                  max_flowrings;
 306         __le16                  max_submissionrings;
 307         __le16                  max_completionrings;
 308 };
 309
 310 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 311         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 312         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 313         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 314         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 315         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 316 };
 317
 318 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 319         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 320         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 321         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 322         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 323         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 324 };
 325
 326
 327 static u32
 328 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 329 {
 330         void __iomem *address = devinfo->regs + reg_offset;
 331
 332         return (ioread32(address));
 333 }
 334
 335
 336 static void
 337 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 338                        u32 value)
 339 {
 340         void __iomem *address = devinfo->regs + reg_offset;
 341
 342         iowrite32(value, address);
 343 }
 344
 345
 346 static u8
 347 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 348 {
 349         void __iomem *address = devinfo->tcm + mem_offset;
 350
 351         return (ioread8(address));
 352 }
 353
 354
 355 static u16
 356 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 357 {
 358         void __iomem *address = devinfo->tcm + mem_offset;
 359
 360         return (ioread16(address));
 361 }
 362
 363
 364 static void
 365 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 366                        u16 value)
 367 {
 368         void __iomem *address = devinfo->tcm + mem_offset;
 369
 370         iowrite16(value, address);
 371 }
 372
 373
 374 static u16
 375 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 376 {
 377         u16 *address = devinfo->idxbuf + mem_offset;
 378
 379         return (*(address));
 380 }
 381
 382
 383 static void
 384 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 385                      u16 value)
 386 {
 387         u16 *address = devinfo->idxbuf + mem_offset;
 388
 389         *(address) = value;
 390 }
 391
 392
 393 static u32
 394 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 395 {
 396         void __iomem *address = devinfo->tcm + mem_offset;
 397
 398         return (ioread32(address));
 399 }
 400
 401
 402 static void
 403 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 404                        u32 value)
 405 {
 406         void __iomem *address = devinfo->tcm + mem_offset;
 407
 408         iowrite32(value, address);
 409 }
 410
 411
 412 static u32
 413 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 414 {
 415         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 416
 417         return (ioread32(addr));
 418 }
 419
 420
 421 static void
 422 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 423                        u32 value)
 424 {
 425         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 426
 427         iowrite32(value, addr);
 428 }
 429
 430
 431 static void
 432 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 433                           void *srcaddr, u32 len)
 434 {
 435         void __iomem *address = devinfo->tcm + mem_offset;
 436         __le32 *src32;
 437         __le16 *src16;
 438         u8 *src8;
 439
 440         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 441                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 442                         src8 = (u8 *)srcaddr;
 443                         while (len) {
 444                                 iowrite8(*src8, address);
 445                                 address++;
 446                                 src8++;
 447                                 len--;
 448                         }
 449                 } else {
 450                         len = len / 2;
 451                         src16 = (__le16 *)srcaddr;
 452                         while (len) {
 453                                 iowrite16(le16_to_cpu(*src16), address);
 454                                 address += 2;
 455                                 src16++;
 456                                 len--;
 457                         }
 458                 }
 459         } else {
 460                 len = len / 4;
 461                 src32 = (__le32 *)srcaddr;
 462                 while (len) {
 463                         iowrite32(le32_to_cpu(*src32), address);
 464                         address += 4;
 465                         src32++;
 466                         len--;
 467                 }
 468         }
 469 }
 470
 471
 472 static void
 473 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 474                           void *dstaddr, u32 len)
 475 {
 476         void __iomem *address = devinfo->tcm + mem_offset;
 477         __le32 *dst32;
 478         __le16 *dst16;
 479         u8 *dst8;
 480
 481         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 482                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 483                         dst8 = (u8 *)dstaddr;
 484                         while (len) {
 485                                 *dst8 = ioread8(address);
 486                                 address++;
 487                                 dst8++;
 488                                 len--;
 489                         }
 490                 } else {
 491                         len = len / 2;
 492                         dst16 = (__le16 *)dstaddr;
 493                         while (len) {
 494                                 *dst16 = cpu_to_le16(ioread16(address));
 495                                 address += 2;
 496                                 dst16++;
 497                                 len--;
 498                         }
 499                 }
 500         } else {
 501                 len = len / 4;
 502                 dst32 = (__le32 *)dstaddr;
 503                 while (len) {
 504                         *dst32 = cpu_to_le32(ioread32(address));
 505                         address += 4;
 506                         dst32++;
 507                         len--;
 508                 }
 509         }
 510 }
 511
 512
 513 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 514                 CHIPCREGOFFS(reg), value)
 515
 516
 517 static void
 518 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 519 {
 520         const struct pci_dev *pdev = devinfo->pdev;
 521         struct brcmf_core *core;
 522         u32 bar0_win;
 523
 524         core = brcmf_chip_get_core(devinfo->ci, coreid);
 525         if (core) {
 526                 bar0_win = core->base;
 527                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 528                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 529                                           &bar0_win) == 0) {
 530                         if (bar0_win != core->base) {
 531                                 bar0_win = core->base;
 532                                 pci_write_config_dword(pdev,
 533                                                        BRCMF_PCIE_BAR0_WINDOW,
 534                                                        bar0_win);
 535                         }
 536                 }
 537         } else {
 538                 brcmf_err("Unsupported core selected %x\n", coreid);
 539         }
 540 }
 541
 542
 543 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 544 {
 545         struct brcmf_core *core;
 546         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 547                              BRCMF_PCIE_CFGREG_PM_CSR,
 548                              BRCMF_PCIE_CFGREG_MSI_CAP,
 549                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 550                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 551                              BRCMF_PCIE_CFGREG_MSI_DATA,
 552                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 553                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 554                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 555                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 556                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 557         u32 i;
 558         u32 val;
 559         u32 lsc;
 560
 561         if (!devinfo->ci)
 562                 return;
 563
 564         /* Disable ASPM */
 565         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 566         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 567                               &lsc);
 568         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 569         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 570                                val);
 571
 572         /* Watchdog reset */
 573         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 574         WRITECC32(devinfo, watchdog, 4);
 575         msleep(100);
 576
 577         /* Restore ASPM */
 578         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 579         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 580                                lsc);
 581
 582         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 583         if (core->rev <= 13) {
 584                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 585                         brcmf_pcie_write_reg32(devinfo,
 586                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 587                                                cfg_offset[i]);
 588                         val = brcmf_pcie_read_reg32(devinfo,
 589                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 590                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 591                                   cfg_offset[i], val);
 592                         brcmf_pcie_write_reg32(devinfo,
 593                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 594                                                val);
 595                 }
 596         }
 597 }
 598
 599
 600 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 601 {
 602         u32 config;
 603
 604         /* BAR1 window may not be sized properly */
 605         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 606         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 607         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 608         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 609
 610         device_wakeup_enable(&devinfo->pdev->dev);
 611 }
 612
 613
 614 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 615 {
 616         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 617                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 618                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 619                                        5);
 620                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 621                                        0);
 622                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 623                                        7);
 624                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 625                                        0);
 626         }
 627         return 0;
 628 }
 629
 630
 631 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 632                                           u32 resetintr)
 633 {
 634         struct brcmf_core *core;
 635
 636         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 637                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 638                 brcmf_chip_resetcore(core, 0, 0, 0);
 639         }
 640
 641         if (!brcmf_chip_set_active(devinfo->ci, resetintr))
 642                 return -EINVAL;
 643         return 0;
 644 }
 645
 646
 647 static int
 648 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 649 {
 650         struct brcmf_pcie_shared_info *shared;
 651         u32 addr;
 652         u32 cur_htod_mb_data;
 653         u32 i;
 654
 655         shared = &devinfo->shared;
 656         addr = shared->htod_mb_data_addr;
 657         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 658
 659         if (cur_htod_mb_data != 0)
 660                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 661                           cur_htod_mb_data);
 662
 663         i = 0;
 664         while (cur_htod_mb_data != 0) {
 665                 msleep(10);
 666                 i++;
 667                 if (i > 100)
 668                         return -EIO;
 669                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 670         }
 671
 672         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 673         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 674         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 675
 676         return 0;
 677 }
 678
 679
 680 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 681 {
 682         struct brcmf_pcie_shared_info *shared;
 683         u32 addr;
 684         u32 dtoh_mb_data;
 685
 686         shared = &devinfo->shared;
 687         addr = shared->dtoh_mb_data_addr;
 688         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 689
 690         if (!dtoh_mb_data)
 691                 return;
 692
 693         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 694
 695         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 696         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 697                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 698                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 699                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 700         }
 701         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 702                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 703         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 704                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 705                 devinfo->mbdata_completed = true;
 706                 wake_up(&devinfo->mbdata_resp_wait);
 707         }
 708 }
 709
 710
 711 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 712 {
 713         struct brcmf_pcie_shared_info *shared;
 714         struct brcmf_pcie_console *console;
 715         u32 addr;
 716
 717         shared = &devinfo->shared;
 718         console = &shared->console;
 719         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 720         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 721
 722         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 723         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 724         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 725         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 726
 727         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 728                   console->base_addr, console->buf_addr, console->bufsize);
 729 }
 730
 731
 732 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 733 {
 734         struct brcmf_pcie_console *console;
 735         u32 addr;
 736         u8 ch;
 737         u32 newidx;
 738
 739         if (!BRCMF_FWCON_ON())
 740                 return;
 741
 742         console = &devinfo->shared.console;
 743         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 744         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 745         while (newidx != console->read_idx) {
 746                 addr = console->buf_addr + console->read_idx;
 747                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 748                 console->read_idx++;
 749                 if (console->read_idx == console->bufsize)
 750                         console->read_idx = 0;
 751                 if (ch == '\r')
 752                         continue;
 753                 console->log_str[console->log_idx] = ch;
 754                 console->log_idx++;
 755                 if ((ch != '\n') &&
 756                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 757                         ch = '\n';
 758                         console->log_str[console->log_idx] = ch;
 759                         console->log_idx++;
 760                 }
 761                 if (ch == '\n') {
 762                         console->log_str[console->log_idx] = 0;
 763                         pr_debug("CONSOLE: %s", console->log_str);
 764                         console->log_idx = 0;
 765                 }
 766         }
 767 }
 768
 769
 770 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 771 {
 772         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
 773 }
 774
 775
 776 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 777 {
 778         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 779                                BRCMF_PCIE_MB_INT_D2H_DB |
 780                                BRCMF_PCIE_MB_INT_FN0_0 |
 781                                BRCMF_PCIE_MB_INT_FN0_1);
 782 }
 783
 784
 785 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
 786 {
 787         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 788
 789         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 790                 brcmf_pcie_intr_disable(devinfo);
 791                 brcmf_dbg(PCIE, "Enter\n");
 792                 return IRQ_WAKE_THREAD;
 793         }
 794         return IRQ_NONE;
 795 }
 796
 797
 798 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
 799 {
 800         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 801         u32 status;
 802
 803         devinfo->in_irq = true;
 804         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 805         brcmf_dbg(PCIE, "Enter %x\n", status);
 806         if (status) {
 807                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 808                                        status);
 809                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 810                               BRCMF_PCIE_MB_INT_FN0_1))
 811                         brcmf_pcie_handle_mb_data(devinfo);
 812                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 813                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 814                                 brcmf_proto_msgbuf_rx_trigger(
 815                                                         &devinfo->pdev->dev);
 816                 }
 817         }
 818         brcmf_pcie_bus_console_read(devinfo);
 819         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 820                 brcmf_pcie_intr_enable(devinfo);
 821         devinfo->in_irq = false;
 822         return IRQ_HANDLED;
 823 }
 824
 825
 826 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 827 {
 828         struct pci_dev *pdev;
 829
 830         pdev = devinfo->pdev;
 831
 832         brcmf_pcie_intr_disable(devinfo);
 833
 834         brcmf_dbg(PCIE, "Enter\n");
 835
 836         pci_enable_msi(pdev);
 837         if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
 838                                  brcmf_pcie_isr_thread, IRQF_SHARED,
 839                                  "brcmf_pcie_intr", devinfo)) {
 840                 pci_disable_msi(pdev);
 841                 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 842                 return -EIO;
 843         }
 844         devinfo->irq_allocated = true;
 845         return 0;
 846 }
 847
 848
 849 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 850 {
 851         struct pci_dev *pdev;
 852         u32 status;
 853         u32 count;
 854
 855         if (!devinfo->irq_allocated)
 856                 return;
 857
 858         pdev = devinfo->pdev;
 859
 860         brcmf_pcie_intr_disable(devinfo);
 861         free_irq(pdev->irq, devinfo);
 862         pci_disable_msi(pdev);
 863
 864         msleep(50);
 865         count = 0;
 866         while ((devinfo->in_irq) && (count < 20)) {
 867                 msleep(50);
 868                 count++;
 869         }
 870         if (devinfo->in_irq)
 871                 brcmf_err("Still in IRQ (processing) !!!\n");
 872
 873         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 874         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
 875
 876         devinfo->irq_allocated = false;
 877 }
 878
 879
 880 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 881 {
 882         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 883         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 884         struct brcmf_commonring *commonring = &ring->commonring;
 885
 886         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 887                 return -EIO;
 888
 889         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 890                   commonring->w_ptr, ring->id);
 891
 892         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 893
 894         return 0;
 895 }
 896
 897
 898 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 899 {
 900         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 901         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 902         struct brcmf_commonring *commonring = &ring->commonring;
 903
 904         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 905                 return -EIO;
 906
 907         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 908                   commonring->r_ptr, ring->id);
 909
 910         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 911
 912         return 0;
 913 }
 914
 915
 916 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 917 {
 918         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 919         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 920
 921         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 922                 return -EIO;
 923
 924         brcmf_dbg(PCIE, "RING !\n");
 925         /* Any arbitrary value will do, lets use 1 */
 926         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 927
 928         return 0;
 929 }
 930
 931
 932 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 933 {
 934         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 935         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 936         struct brcmf_commonring *commonring = &ring->commonring;
 937
 938         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 939                 return -EIO;
 940
 941         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
 942
 943         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 944                   commonring->w_ptr, ring->id);
 945
 946         return 0;
 947 }
 948
 949
 950 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 951 {
 952         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 953         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 954         struct brcmf_commonring *commonring = &ring->commonring;
 955
 956         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 957                 return -EIO;
 958
 959         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
 960
 961         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 962                   commonring->r_ptr, ring->id);
 963
 964         return 0;
 965 }
 966
 967
 968 static void *
 969 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
 970                                      u32 size, u32 tcm_dma_phys_addr,
 971                                      dma_addr_t *dma_handle)
 972 {
 973         void *ring;
 974         u64 address;
 975
 976         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
 977                                   GFP_KERNEL);
 978         if (!ring)
 979                 return NULL;
 980
 981         address = (u64)*dma_handle;
 982         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
 983                                address & 0xffffffff);
 984         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
 985
 986         memset(ring, 0, size);
 987
 988         return (ring);
 989 }
 990
 991
 992 static struct brcmf_pcie_ringbuf *
 993 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
 994                               u32 tcm_ring_phys_addr)
 995 {
 996         void *dma_buf;
 997         dma_addr_t dma_handle;
 998         struct brcmf_pcie_ringbuf *ring;
 999         u32 size;
1000         u32 addr;
1001
1002         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1003         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1004                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1005                         &dma_handle);
1006         if (!dma_buf)
1007                 return NULL;
1008
1009         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1010         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1011         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1012         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1013
1014         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1015         if (!ring) {
1016                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1017                                   dma_handle);
1018                 return NULL;
1019         }
1020         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1021                                 brcmf_ring_itemsize[ring_id], dma_buf);
1022         ring->dma_handle = dma_handle;
1023         ring->devinfo = devinfo;
1024         brcmf_commonring_register_cb(&ring->commonring,
1025                                      brcmf_pcie_ring_mb_ring_bell,
1026                                      brcmf_pcie_ring_mb_update_rptr,
1027                                      brcmf_pcie_ring_mb_update_wptr,
1028                                      brcmf_pcie_ring_mb_write_rptr,
1029                                      brcmf_pcie_ring_mb_write_wptr, ring);
1030
1031         return (ring);
1032 }
1033
1034
1035 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1036                                           struct brcmf_pcie_ringbuf *ring)
1037 {
1038         void *dma_buf;
1039         u32 size;
1040
1041         if (!ring)
1042                 return;
1043
1044         dma_buf = ring->commonring.buf_addr;
1045         if (dma_buf) {
1046                 size = ring->commonring.depth * ring->commonring.item_len;
1047                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1048         }
1049         kfree(ring);
1050 }
1051
1052
1053 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1054 {
1055         u32 i;
1056
1057         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1058                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1059                                               devinfo->shared.commonrings[i]);
1060                 devinfo->shared.commonrings[i] = NULL;
1061         }
1062         kfree(devinfo->shared.flowrings);
1063         devinfo->shared.flowrings = NULL;
1064         if (devinfo->idxbuf) {
1065                 dma_free_coherent(&devinfo->pdev->dev,
1066                                   devinfo->idxbuf_sz,
1067                                   devinfo->idxbuf,
1068                                   devinfo->idxbuf_dmahandle);
1069                 devinfo->idxbuf = NULL;
1070         }
1071 }
1072
1073
1074 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1075 {
1076         struct brcmf_pcie_ringbuf *ring;
1077         struct brcmf_pcie_ringbuf *rings;
1078         u32 d2h_w_idx_ptr;
1079         u32 d2h_r_idx_ptr;
1080         u32 h2d_w_idx_ptr;
1081         u32 h2d_r_idx_ptr;
1082         u32 ring_mem_ptr;
1083         u32 i;
1084         u64 address;
1085         u32 bufsz;
1086         u8 idx_offset;
1087         struct brcmf_pcie_dhi_ringinfo ringinfo;
1088         u16 max_flowrings;
1089         u16 max_submissionrings;
1090         u16 max_completionrings;
1091
1092         memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1093                       sizeof(ringinfo));
1094         if (devinfo->shared.version >= 6) {
1095                 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1096                 max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1097                 max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1098         } else {
1099                 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1100                 max_flowrings = max_submissionrings -
1101                                 BRCMF_NROF_H2D_COMMON_MSGRINGS;
1102                 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1103         }
1104
1105         if (devinfo->dma_idx_sz != 0) {
1106                 bufsz = (max_submissionrings + max_completionrings) *
1107                         devinfo->dma_idx_sz * 2;
1108                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1109                                                      &devinfo->idxbuf_dmahandle,
1110                                                      GFP_KERNEL);
1111                 if (!devinfo->idxbuf)
1112                         devinfo->dma_idx_sz = 0;
1113         }
1114
1115         if (devinfo->dma_idx_sz == 0) {
1116                 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1117                 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1118                 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1119                 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1120                 idx_offset = sizeof(u32);
1121                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1122                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1123                 brcmf_dbg(PCIE, "Using TCM indices\n");
1124         } else {
1125                 memset(devinfo->idxbuf, 0, bufsz);
1126                 devinfo->idxbuf_sz = bufsz;
1127                 idx_offset = devinfo->dma_idx_sz;
1128                 devinfo->write_ptr = brcmf_pcie_write_idx;
1129                 devinfo->read_ptr = brcmf_pcie_read_idx;
1130
1131                 h2d_w_idx_ptr = 0;
1132                 address = (u64)devinfo->idxbuf_dmahandle;
1133                 ringinfo.h2d_w_idx_hostaddr.low_addr =
1134                         cpu_to_le32(address & 0xffffffff);
1135                 ringinfo.h2d_w_idx_hostaddr.high_addr =
1136                         cpu_to_le32(address >> 32);
1137
1138                 h2d_r_idx_ptr = h2d_w_idx_ptr +
1139                                 max_submissionrings * idx_offset;
1140                 address += max_submissionrings * idx_offset;
1141                 ringinfo.h2d_r_idx_hostaddr.low_addr =
1142                         cpu_to_le32(address & 0xffffffff);
1143                 ringinfo.h2d_r_idx_hostaddr.high_addr =
1144                         cpu_to_le32(address >> 32);
1145
1146                 d2h_w_idx_ptr = h2d_r_idx_ptr +
1147                                 max_submissionrings * idx_offset;
1148                 address += max_submissionrings * idx_offset;
1149                 ringinfo.d2h_w_idx_hostaddr.low_addr =
1150                         cpu_to_le32(address & 0xffffffff);
1151                 ringinfo.d2h_w_idx_hostaddr.high_addr =
1152                         cpu_to_le32(address >> 32);
1153
1154                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1155                                 max_completionrings * idx_offset;
1156                 address += max_completionrings * idx_offset;
1157                 ringinfo.d2h_r_idx_hostaddr.low_addr =
1158                         cpu_to_le32(address & 0xffffffff);
1159                 ringinfo.d2h_r_idx_hostaddr.high_addr =
1160                         cpu_to_le32(address >> 32);
1161
1162                 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1163                             &ringinfo, sizeof(ringinfo));
1164                 brcmf_dbg(PCIE, "Using host memory indices\n");
1165         }
1166
1167         ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1168
1169         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1170                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1171                 if (!ring)
1172                         goto fail;
1173                 ring->w_idx_addr = h2d_w_idx_ptr;
1174                 ring->r_idx_addr = h2d_r_idx_ptr;
1175                 ring->id = i;
1176                 devinfo->shared.commonrings[i] = ring;
1177
1178                 h2d_w_idx_ptr += idx_offset;
1179                 h2d_r_idx_ptr += idx_offset;
1180                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1181         }
1182
1183         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1184              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1185                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1186                 if (!ring)
1187                         goto fail;
1188                 ring->w_idx_addr = d2h_w_idx_ptr;
1189                 ring->r_idx_addr = d2h_r_idx_ptr;
1190                 ring->id = i;
1191                 devinfo->shared.commonrings[i] = ring;
1192
1193                 d2h_w_idx_ptr += idx_offset;
1194                 d2h_r_idx_ptr += idx_offset;
1195                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1196         }
1197
1198         devinfo->shared.max_flowrings = max_flowrings;
1199         devinfo->shared.max_submissionrings = max_submissionrings;
1200         devinfo->shared.max_completionrings = max_completionrings;
1201         rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1202         if (!rings)
1203                 goto fail;
1204
1205         brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1206
1207         for (i = 0; i < max_flowrings; i++) {
1208                 ring = &rings[i];
1209                 ring->devinfo = devinfo;
1210                 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1211                 brcmf_commonring_register_cb(&ring->commonring,
1212                                              brcmf_pcie_ring_mb_ring_bell,
1213                                              brcmf_pcie_ring_mb_update_rptr,
1214                                              brcmf_pcie_ring_mb_update_wptr,
1215                                              brcmf_pcie_ring_mb_write_rptr,
1216                                              brcmf_pcie_ring_mb_write_wptr,
1217                                              ring);
1218                 ring->w_idx_addr = h2d_w_idx_ptr;
1219                 ring->r_idx_addr = h2d_r_idx_ptr;
1220                 h2d_w_idx_ptr += idx_offset;
1221                 h2d_r_idx_ptr += idx_offset;
1222         }
1223         devinfo->shared.flowrings = rings;
1224
1225         return 0;
1226
1227 fail:
1228         brcmf_err("Allocating ring buffers failed\n");
1229         brcmf_pcie_release_ringbuffers(devinfo);
1230         return -ENOMEM;
1231 }
1232
1233
1234 static void
1235 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1236 {
1237         if (devinfo->shared.scratch)
1238                 dma_free_coherent(&devinfo->pdev->dev,
1239                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1240                                   devinfo->shared.scratch,
1241                                   devinfo->shared.scratch_dmahandle);
1242         if (devinfo->shared.ringupd)
1243                 dma_free_coherent(&devinfo->pdev->dev,
1244                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1245                                   devinfo->shared.ringupd,
1246                                   devinfo->shared.ringupd_dmahandle);
1247 }
1248
1249 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1250 {
1251         u64 address;
1252         u32 addr;
1253
1254         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1255                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1256                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1257         if (!devinfo->shared.scratch)
1258                 goto fail;
1259
1260         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1261
1262         addr = devinfo->shared.tcm_base_address +
1263                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1264         address = (u64)devinfo->shared.scratch_dmahandle;
1265         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1266         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1267         addr = devinfo->shared.tcm_base_address +
1268                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1269         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1270
1271         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1272                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1273                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1274         if (!devinfo->shared.ringupd)
1275                 goto fail;
1276
1277         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1278
1279         addr = devinfo->shared.tcm_base_address +
1280                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1281         address = (u64)devinfo->shared.ringupd_dmahandle;
1282         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1283         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1284         addr = devinfo->shared.tcm_base_address +
1285                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1286         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1287         return 0;
1288
1289 fail:
1290         brcmf_err("Allocating scratch buffers failed\n");
1291         brcmf_pcie_release_scratchbuffers(devinfo);
1292         return -ENOMEM;
1293 }
1294
1295
1296 static void brcmf_pcie_down(struct device *dev)
1297 {
1298 }
1299
1300
1301 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1302 {
1303         return 0;
1304 }
1305
1306
1307 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1308                                 uint len)
1309 {
1310         return 0;
1311 }
1312
1313
1314 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1315                                 uint len)
1316 {
1317         return 0;
1318 }
1319
1320
1321 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1322 {
1323         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1324         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1325         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1326
1327         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1328         devinfo->wowl_enabled = enabled;
1329 }
1330
1331
1332 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1333 {
1334         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1335         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1336         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1337
1338         return devinfo->ci->ramsize - devinfo->ci->srsize;
1339 }
1340
1341
1342 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1343 {
1344         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1345         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1346         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1347
1348         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1349         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1350         return 0;
1351 }
1352
1353
1354 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1355         .txdata = brcmf_pcie_tx,
1356         .stop = brcmf_pcie_down,
1357         .txctl = brcmf_pcie_tx_ctlpkt,
1358         .rxctl = brcmf_pcie_rx_ctlpkt,
1359         .wowl_config = brcmf_pcie_wowl_config,
1360         .get_ramsize = brcmf_pcie_get_ramsize,
1361         .get_memdump = brcmf_pcie_get_memdump,
1362 };
1363
1364
1365 static void
1366 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1367                           u32 data_len)
1368 {
1369         __le32 *field;
1370         u32 newsize;
1371
1372         if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1373                 return;
1374
1375         field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1376         if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1377                 return;
1378         field++;
1379         newsize = le32_to_cpup(field);
1380
1381         brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1382                   newsize);
1383         devinfo->ci->ramsize = newsize;
1384 }
1385
1386
1387 static int
1388 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1389                                u32 sharedram_addr)
1390 {
1391         struct brcmf_pcie_shared_info *shared;
1392         u32 addr;
1393
1394         shared = &devinfo->shared;
1395         shared->tcm_base_address = sharedram_addr;
1396
1397         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1398         shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1399         brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1400         if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1401             (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1402                 brcmf_err("Unsupported PCIE version %d\n", shared->version);
1403                 return -EINVAL;
1404         }
1405
1406         /* check firmware support dma indicies */
1407         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1408                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1409                         devinfo->dma_idx_sz = sizeof(u16);
1410                 else
1411                         devinfo->dma_idx_sz = sizeof(u32);
1412         }
1413
1414         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1415         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1416         if (shared->max_rxbufpost == 0)
1417                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1418
1419         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1420         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1421
1422         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1423         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1424
1425         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1426         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1427
1428         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1429         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1430
1431         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1432                   shared->max_rxbufpost, shared->rx_dataoffset);
1433
1434         brcmf_pcie_bus_console_init(devinfo);
1435
1436         return 0;
1437 }
1438
1439
1440 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1441                                         const struct firmware *fw, void *nvram,
1442                                         u32 nvram_len)
1443 {
1444         u32 sharedram_addr;
1445         u32 sharedram_addr_written;
1446         u32 loop_counter;
1447         int err;
1448         u32 address;
1449         u32 resetintr;
1450
1451         brcmf_dbg(PCIE, "Halt ARM.\n");
1452         err = brcmf_pcie_enter_download_state(devinfo);
1453         if (err)
1454                 return err;
1455
1456         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1457         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1458                                   (void *)fw->data, fw->size);
1459
1460         resetintr = get_unaligned_le32(fw->data);
1461         release_firmware(fw);
1462
1463         /* reset last 4 bytes of RAM address. to be used for shared
1464          * area. This identifies when FW is running
1465          */
1466         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1467
1468         if (nvram) {
1469                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1470                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1471                           nvram_len;
1472                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1473                 brcmf_fw_nvram_free(nvram);
1474         } else {
1475                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1476                           devinfo->nvram_name);
1477         }
1478
1479         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1480                                                        devinfo->ci->ramsize -
1481                                                        4);
1482         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1483         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1484         if (err)
1485                 return err;
1486
1487         brcmf_dbg(PCIE, "Wait for FW init\n");
1488         sharedram_addr = sharedram_addr_written;
1489         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1490         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1491                 msleep(50);
1492                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1493                                                        devinfo->ci->ramsize -
1494                                                        4);
1495                 loop_counter--;
1496         }
1497         if (sharedram_addr == sharedram_addr_written) {
1498                 brcmf_err("FW failed to initialize\n");
1499                 return -ENODEV;
1500         }
1501         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1502
1503         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1504 }
1505
1506
1507 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1508 {
1509         struct pci_dev *pdev;
1510         int err;
1511         phys_addr_t  bar0_addr, bar1_addr;
1512         ulong bar1_size;
1513
1514         pdev = devinfo->pdev;
1515
1516         err = pci_enable_device(pdev);
1517         if (err) {
1518                 brcmf_err("pci_enable_device failed err=%d\n", err);
1519                 return err;
1520         }
1521
1522         pci_set_master(pdev);
1523
1524         /* Bar-0 mapped address */
1525         bar0_addr = pci_resource_start(pdev, 0);
1526         /* Bar-1 mapped address */
1527         bar1_addr = pci_resource_start(pdev, 2);
1528         /* read Bar-1 mapped memory range */
1529         bar1_size = pci_resource_len(pdev, 2);
1530         if ((bar1_size == 0) || (bar1_addr == 0)) {
1531                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1532                           bar1_size, (unsigned long long)bar1_addr);
1533                 return -EINVAL;
1534         }
1535
1536         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1537         devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size);
1538
1539         if (!devinfo->regs || !devinfo->tcm) {
1540                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1541                           devinfo->tcm);
1542                 return -EINVAL;
1543         }
1544         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1545                   devinfo->regs, (unsigned long long)bar0_addr);
1546         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1547                   devinfo->tcm, (unsigned long long)bar1_addr,
1548                   (unsigned int)bar1_size);
1549
1550         return 0;
1551 }
1552
1553
1554 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1555 {
1556         if (devinfo->tcm)
1557                 iounmap(devinfo->tcm);
1558         if (devinfo->regs)
1559                 iounmap(devinfo->regs);
1560
1561         pci_disable_device(devinfo->pdev);
1562 }
1563
1564
1565 static int brcmf_pcie_attach_bus(struct brcmf_pciedev_info *devinfo)
1566 {
1567         int ret;
1568
1569         /* Attach to the common driver interface */
1570         ret = brcmf_attach(&devinfo->pdev->dev, devinfo->settings);
1571         if (ret) {
1572                 brcmf_err("brcmf_attach failed\n");
1573         } else {
1574                 ret = brcmf_bus_started(&devinfo->pdev->dev);
1575                 if (ret)
1576                         brcmf_err("dongle is not responding\n");
1577         }
1578
1579         return ret;
1580 }
1581
1582
1583 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1584 {
1585         u32 ret_addr;
1586
1587         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1588         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1589         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1590
1591         return ret_addr;
1592 }
1593
1594
1595 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1596 {
1597         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1598
1599         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1600         return brcmf_pcie_read_reg32(devinfo, addr);
1601 }
1602
1603
1604 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1605 {
1606         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1607
1608         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1609         brcmf_pcie_write_reg32(devinfo, addr, value);
1610 }
1611
1612
1613 static int brcmf_pcie_buscoreprep(void *ctx)
1614 {
1615         return brcmf_pcie_get_resource(ctx);
1616 }
1617
1618
1619 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1620 {
1621         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1622         u32 val;
1623
1624         devinfo->ci = chip;
1625         brcmf_pcie_reset_device(devinfo);
1626
1627         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1628         if (val != 0xffffffff)
1629                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1630                                        val);
1631
1632         return 0;
1633 }
1634
1635
1636 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1637                                         u32 rstvec)
1638 {
1639         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1640
1641         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1642 }
1643
1644
1645 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1646         .prepare = brcmf_pcie_buscoreprep,
1647         .reset = brcmf_pcie_buscore_reset,
1648         .activate = brcmf_pcie_buscore_activate,
1649         .read32 = brcmf_pcie_buscore_read32,
1650         .write32 = brcmf_pcie_buscore_write32,
1651 };
1652
1653 static void brcmf_pcie_setup(struct device *dev, int ret,
1654                              const struct firmware *fw,
1655                              void *nvram, u32 nvram_len)
1656 {
1657         struct brcmf_bus *bus;
1658         struct brcmf_pciedev *pcie_bus_dev;
1659         struct brcmf_pciedev_info *devinfo;
1660         struct brcmf_commonring **flowrings;
1661         u32 i;
1662
1663         /* check firmware loading result */
1664         if (ret)
1665                 goto fail;
1666
1667         bus = dev_get_drvdata(dev);
1668         pcie_bus_dev = bus->bus_priv.pcie;
1669         devinfo = pcie_bus_dev->devinfo;
1670         brcmf_pcie_attach(devinfo);
1671
1672         /* Some of the firmwares have the size of the memory of the device
1673          * defined inside the firmware. This is because part of the memory in
1674          * the device is shared and the devision is determined by FW. Parse
1675          * the firmware and adjust the chip memory size now.
1676          */
1677         brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
1678
1679         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1680         if (ret)
1681                 goto fail;
1682
1683         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1684
1685         ret = brcmf_pcie_init_ringbuffers(devinfo);
1686         if (ret)
1687                 goto fail;
1688
1689         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1690         if (ret)
1691                 goto fail;
1692
1693         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1694         ret = brcmf_pcie_request_irq(devinfo);
1695         if (ret)
1696                 goto fail;
1697
1698         /* hook the commonrings in the bus structure. */
1699         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1700                 bus->msgbuf->commonrings[i] =
1701                                 &devinfo->shared.commonrings[i]->commonring;
1702
1703         flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
1704                             GFP_KERNEL);
1705         if (!flowrings)
1706                 goto fail;
1707
1708         for (i = 0; i < devinfo->shared.max_flowrings; i++)
1709                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1710         bus->msgbuf->flowrings = flowrings;
1711
1712         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1713         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1714         bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
1715
1716         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1717
1718         brcmf_pcie_intr_enable(devinfo);
1719         if (brcmf_pcie_attach_bus(devinfo) == 0)
1720                 return;
1721
1722         brcmf_pcie_bus_console_read(devinfo);
1723
1724 fail:
1725         device_release_driver(dev);
1726 }
1727
1728 static int
1729 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1730 {
1731         int ret;
1732         struct brcmf_pciedev_info *devinfo;
1733         struct brcmf_pciedev *pcie_bus_dev;
1734         struct brcmf_bus *bus;
1735         u16 domain_nr;
1736         u16 bus_nr;
1737
1738         domain_nr = pci_domain_nr(pdev->bus) + 1;
1739         bus_nr = pdev->bus->number;
1740         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1741                   domain_nr, bus_nr);
1742
1743         ret = -ENOMEM;
1744         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1745         if (devinfo == NULL)
1746                 return ret;
1747
1748         devinfo->pdev = pdev;
1749         pcie_bus_dev = NULL;
1750         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1751         if (IS_ERR(devinfo->ci)) {
1752                 ret = PTR_ERR(devinfo->ci);
1753                 devinfo->ci = NULL;
1754                 goto fail;
1755         }
1756
1757         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1758         if (pcie_bus_dev == NULL) {
1759                 ret = -ENOMEM;
1760                 goto fail;
1761         }
1762
1763         devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
1764                                                    BRCMF_BUSTYPE_PCIE,
1765                                                    devinfo->ci->chip,
1766                                                    devinfo->ci->chiprev);
1767         if (!devinfo->settings) {
1768                 ret = -ENOMEM;
1769                 goto fail;
1770         }
1771
1772         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1773         if (!bus) {
1774                 ret = -ENOMEM;
1775                 goto fail;
1776         }
1777         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1778         if (!bus->msgbuf) {
1779                 ret = -ENOMEM;
1780                 kfree(bus);
1781                 goto fail;
1782         }
1783
1784         /* hook it all together. */
1785         pcie_bus_dev->devinfo = devinfo;
1786         pcie_bus_dev->bus = bus;
1787         bus->dev = &pdev->dev;
1788         bus->bus_priv.pcie = pcie_bus_dev;
1789         bus->ops = &brcmf_pcie_bus_ops;
1790         bus->proto_type = BRCMF_PROTO_MSGBUF;
1791         bus->chip = devinfo->coreid;
1792         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1793         dev_set_drvdata(&pdev->dev, bus);
1794
1795         ret = brcmf_fw_map_chip_to_name(devinfo->ci->chip, devinfo->ci->chiprev,
1796                                         brcmf_pcie_fwnames,
1797                                         ARRAY_SIZE(brcmf_pcie_fwnames),
1798                                         devinfo->fw_name, devinfo->nvram_name);
1799         if (ret)
1800                 goto fail_bus;
1801
1802         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1803                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1804                                           devinfo->fw_name, devinfo->nvram_name,
1805                                           brcmf_pcie_setup, domain_nr, bus_nr);
1806         if (ret == 0)
1807                 return 0;
1808 fail_bus:
1809         kfree(bus->msgbuf);
1810         kfree(bus);
1811 fail:
1812         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1813         brcmf_pcie_release_resource(devinfo);
1814         if (devinfo->ci)
1815                 brcmf_chip_detach(devinfo->ci);
1816         if (devinfo->settings)
1817                 brcmf_release_module_param(devinfo->settings);
1818         kfree(pcie_bus_dev);
1819         kfree(devinfo);
1820         return ret;
1821 }
1822
1823
1824 static void
1825 brcmf_pcie_remove(struct pci_dev *pdev)
1826 {
1827         struct brcmf_pciedev_info *devinfo;
1828         struct brcmf_bus *bus;
1829
1830         brcmf_dbg(PCIE, "Enter\n");
1831
1832         bus = dev_get_drvdata(&pdev->dev);
1833         if (bus == NULL)
1834                 return;
1835
1836         devinfo = bus->bus_priv.pcie->devinfo;
1837
1838         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1839         if (devinfo->ci)
1840                 brcmf_pcie_intr_disable(devinfo);
1841
1842         brcmf_detach(&pdev->dev);
1843
1844         kfree(bus->bus_priv.pcie);
1845         kfree(bus->msgbuf->flowrings);
1846         kfree(bus->msgbuf);
1847         kfree(bus);
1848
1849         brcmf_pcie_release_irq(devinfo);
1850         brcmf_pcie_release_scratchbuffers(devinfo);
1851         brcmf_pcie_release_ringbuffers(devinfo);
1852         brcmf_pcie_reset_device(devinfo);
1853         brcmf_pcie_release_resource(devinfo);
1854
1855         if (devinfo->ci)
1856                 brcmf_chip_detach(devinfo->ci);
1857         if (devinfo->settings)
1858                 brcmf_release_module_param(devinfo->settings);
1859
1860         kfree(devinfo);
1861         dev_set_drvdata(&pdev->dev, NULL);
1862 }
1863
1864
1865 #ifdef CONFIG_PM
1866
1867
1868 static int brcmf_pcie_pm_enter_D3(struct device *dev)
1869 {
1870         struct brcmf_pciedev_info *devinfo;
1871         struct brcmf_bus *bus;
1872
1873         brcmf_dbg(PCIE, "Enter\n");
1874
1875         bus = dev_get_drvdata(dev);
1876         devinfo = bus->bus_priv.pcie->devinfo;
1877
1878         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1879
1880         devinfo->mbdata_completed = false;
1881         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1882
1883         wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
1884                            BRCMF_PCIE_MBDATA_TIMEOUT);
1885         if (!devinfo->mbdata_completed) {
1886                 brcmf_err("Timeout on response for entering D3 substate\n");
1887                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1888                 return -EIO;
1889         }
1890
1891         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1892
1893         return 0;
1894 }
1895
1896
1897 static int brcmf_pcie_pm_leave_D3(struct device *dev)
1898 {
1899         struct brcmf_pciedev_info *devinfo;
1900         struct brcmf_bus *bus;
1901         struct pci_dev *pdev;
1902         int err;
1903
1904         brcmf_dbg(PCIE, "Enter\n");
1905
1906         bus = dev_get_drvdata(dev);
1907         devinfo = bus->bus_priv.pcie->devinfo;
1908         brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
1909
1910         /* Check if device is still up and running, if so we are ready */
1911         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1912                 brcmf_dbg(PCIE, "Try to wakeup device....\n");
1913                 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
1914                         goto cleanup;
1915                 brcmf_dbg(PCIE, "Hot resume, continue....\n");
1916                 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1917                 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1918                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1919                 brcmf_pcie_intr_enable(devinfo);
1920                 return 0;
1921         }
1922
1923 cleanup:
1924         brcmf_chip_detach(devinfo->ci);
1925         devinfo->ci = NULL;
1926         pdev = devinfo->pdev;
1927         brcmf_pcie_remove(pdev);
1928
1929         err = brcmf_pcie_probe(pdev, NULL);
1930         if (err)
1931                 brcmf_err("probe after resume failed, err=%d\n", err);
1932
1933         return err;
1934 }
1935
1936
1937 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
1938         .suspend = brcmf_pcie_pm_enter_D3,
1939         .resume = brcmf_pcie_pm_leave_D3,
1940         .freeze = brcmf_pcie_pm_enter_D3,
1941         .restore = brcmf_pcie_pm_leave_D3,
1942 };
1943
1944
1945 #endif /* CONFIG_PM */
1946
1947
1948 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1949         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1950 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev)  { \
1951         BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1952         subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1953
1954 static const struct pci_device_id brcmf_pcie_devid_table[] = {
1955         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
1956         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1957         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1958         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1959         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
1960         BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
1961         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1962         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1963         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1964         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
1965         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
1966         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
1967         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
1968         BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365),
1969         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
1970         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
1971         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
1972         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
1973         { /* end: all zeroes */ }
1974 };
1975
1976
1977 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1978
1979
1980 static struct pci_driver brcmf_pciedrvr = {
1981         .node = {},
1982         .name = KBUILD_MODNAME,
1983         .id_table = brcmf_pcie_devid_table,
1984         .probe = brcmf_pcie_probe,
1985         .remove = brcmf_pcie_remove,
1986 #ifdef CONFIG_PM
1987         .driver.pm = &brcmf_pciedrvr_pm,
1988 #endif
1989 };
1990
1991
1992 void brcmf_pcie_register(void)
1993 {
1994         int err;
1995
1996         brcmf_dbg(PCIE, "Enter\n");
1997         err = pci_register_driver(&brcmf_pciedrvr);
1998         if (err)
1999                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2000 }
2001
2002
2003 void brcmf_pcie_exit(void)
2004 {
2005         brcmf_dbg(PCIE, "Enter\n");
2006         pci_unregister_driver(&brcmf_pciedrvr);
2007 }