drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <linux/io.h>
  26 #include <asm/unaligned.h>
  27
  28 #include <soc.h>
  29 #include <chipcommon.h>
  30 #include <brcmu_utils.h>
  31 #include <brcmu_wifi.h>
  32 #include <brcm_hw_ids.h>
  33
  34 #include "debug.h"
  35 #include "bus.h"
  36 #include "commonring.h"
  37 #include "msgbuf.h"
  38 #include "pcie.h"
  39 #include "firmware.h"
  40 #include "chip.h"
  41 #include "core.h"
  42 #include "common.h"
  43
  44
  45 enum brcmf_pcie_state {
  46         BRCMFMAC_PCIE_STATE_DOWN,
  47         BRCMFMAC_PCIE_STATE_UP
  48 };
  49
  50 BRCMF_FW_NVRAM_DEF(43602, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  51 BRCMF_FW_NVRAM_DEF(4350, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  52 BRCMF_FW_NVRAM_DEF(4350C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  53 BRCMF_FW_NVRAM_DEF(4356, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  54 BRCMF_FW_NVRAM_DEF(43570, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  55 BRCMF_FW_NVRAM_DEF(4358, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  56 BRCMF_FW_NVRAM_DEF(4359, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  57 BRCMF_FW_NVRAM_DEF(4365B, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  58 BRCMF_FW_NVRAM_DEF(4365C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  59 BRCMF_FW_NVRAM_DEF(4366B, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  60 BRCMF_FW_NVRAM_DEF(4366C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  61 BRCMF_FW_NVRAM_DEF(4371, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  62
  63 static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
  64         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
  65         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
  66         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
  67         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
  68         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
  69         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
  70         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
  71         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
  72         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
  73         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
  74         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
  75         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
  76         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
  77         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
  78         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
  79         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
  80 };
  81
  82 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  83
  84 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  85
  86 /* backplane addres space accessed by BAR0 */
  87 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  88 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  89 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  90
  91 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  92 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  93
  94 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  95 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  96
  97 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  98 #define BRCMF_PCIE_REG_INTMASK                  0x94
  99 #define BRCMF_PCIE_REG_SBMBX                    0x98
 100
 101 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
 102
 103 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
 104 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
 105 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
 106 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
 107 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
 108 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
 109
 110 #define BRCMF_PCIE2_INTA                        0x01
 111 #define BRCMF_PCIE2_INTB                        0x02
 112
 113 #define BRCMF_PCIE_INT_0                        0x01
 114 #define BRCMF_PCIE_INT_1                        0x02
 115 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 116                                                  BRCMF_PCIE_INT_1)
 117
 118 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 119 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 120 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 121 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 122 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 123 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 124 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 125 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 126 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 127 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 128
 129 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 130                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 131                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 132                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 133                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 134                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 135                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 136                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 137
 138 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 139 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 140 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 141 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 142 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 143
 144 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 145 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 146
 147 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 148 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 149 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 150 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 151 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 152 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 153 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 154 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 155 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 156 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 157 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 158
 159 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 160 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 161 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 162 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 163
 164 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 165 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 166 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 167 #define BRCMF_RING_MEM_SZ                       16
 168 #define BRCMF_RING_STATE_SZ                     8
 169
 170 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 171 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 172 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 173 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 174 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET   20
 175 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET   28
 176 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET   36
 177 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET   44
 178 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 179 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 180
 181 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 182
 183 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 184 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 185 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 186
 187 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 188 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 189
 190 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 191 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 192 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 193
 194 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 195 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 196 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 197 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 198
 199 #define BRCMF_PCIE_MBDATA_TIMEOUT               msecs_to_jiffies(2000)
 200
 201 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 202 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 203 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 204 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 205 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 206 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 207 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 208 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 209 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 210 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 211 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 212 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 213 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 214
 215 /* Magic number at a magic location to find RAM size */
 216 #define BRCMF_RAMSIZE_MAGIC                     0x534d4152      /* SMAR */
 217 #define BRCMF_RAMSIZE_OFFSET                    0x6c
 218
 219
 220 struct brcmf_pcie_console {
 221         u32 base_addr;
 222         u32 buf_addr;
 223         u32 bufsize;
 224         u32 read_idx;
 225         u8 log_str[256];
 226         u8 log_idx;
 227 };
 228
 229 struct brcmf_pcie_shared_info {
 230         u32 tcm_base_address;
 231         u32 flags;
 232         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 233         struct brcmf_pcie_ringbuf *flowrings;
 234         u16 max_rxbufpost;
 235         u32 nrof_flowrings;
 236         u32 rx_dataoffset;
 237         u32 htod_mb_data_addr;
 238         u32 dtoh_mb_data_addr;
 239         u32 ring_info_addr;
 240         struct brcmf_pcie_console console;
 241         void *scratch;
 242         dma_addr_t scratch_dmahandle;
 243         void *ringupd;
 244         dma_addr_t ringupd_dmahandle;
 245 };
 246
 247 struct brcmf_pcie_core_info {
 248         u32 base;
 249         u32 wrapbase;
 250 };
 251
 252 struct brcmf_pciedev_info {
 253         enum brcmf_pcie_state state;
 254         bool in_irq;
 255         struct pci_dev *pdev;
 256         char fw_name[BRCMF_FW_NAME_LEN];
 257         char nvram_name[BRCMF_FW_NAME_LEN];
 258         void __iomem *regs;
 259         void __iomem *tcm;
 260         u32 ram_base;
 261         u32 ram_size;
 262         struct brcmf_chip *ci;
 263         u32 coreid;
 264         struct brcmf_pcie_shared_info shared;
 265         wait_queue_head_t mbdata_resp_wait;
 266         bool mbdata_completed;
 267         bool irq_allocated;
 268         bool wowl_enabled;
 269         u8 dma_idx_sz;
 270         void *idxbuf;
 271         u32 idxbuf_sz;
 272         dma_addr_t idxbuf_dmahandle;
 273         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 274         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 275                           u16 value);
 276         struct brcmf_mp_device *settings;
 277 };
 278
 279 struct brcmf_pcie_ringbuf {
 280         struct brcmf_commonring commonring;
 281         dma_addr_t dma_handle;
 282         u32 w_idx_addr;
 283         u32 r_idx_addr;
 284         struct brcmf_pciedev_info *devinfo;
 285         u8 id;
 286 };
 287
 288
 289 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 290         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 291         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 292         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 293         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 294         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 295 };
 296
 297 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 298         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 299         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 300         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 301         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 302         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 303 };
 304
 305
 306 static u32
 307 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 308 {
 309         void __iomem *address = devinfo->regs + reg_offset;
 310
 311         return (ioread32(address));
 312 }
 313
 314
 315 static void
 316 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 317                        u32 value)
 318 {
 319         void __iomem *address = devinfo->regs + reg_offset;
 320
 321         iowrite32(value, address);
 322 }
 323
 324
 325 static u8
 326 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 327 {
 328         void __iomem *address = devinfo->tcm + mem_offset;
 329
 330         return (ioread8(address));
 331 }
 332
 333
 334 static u16
 335 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 336 {
 337         void __iomem *address = devinfo->tcm + mem_offset;
 338
 339         return (ioread16(address));
 340 }
 341
 342
 343 static void
 344 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 345                        u16 value)
 346 {
 347         void __iomem *address = devinfo->tcm + mem_offset;
 348
 349         iowrite16(value, address);
 350 }
 351
 352
 353 static u16
 354 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 355 {
 356         u16 *address = devinfo->idxbuf + mem_offset;
 357
 358         return (*(address));
 359 }
 360
 361
 362 static void
 363 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 364                      u16 value)
 365 {
 366         u16 *address = devinfo->idxbuf + mem_offset;
 367
 368         *(address) = value;
 369 }
 370
 371
 372 static u32
 373 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 374 {
 375         void __iomem *address = devinfo->tcm + mem_offset;
 376
 377         return (ioread32(address));
 378 }
 379
 380
 381 static void
 382 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 383                        u32 value)
 384 {
 385         void __iomem *address = devinfo->tcm + mem_offset;
 386
 387         iowrite32(value, address);
 388 }
 389
 390
 391 static u32
 392 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 393 {
 394         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 395
 396         return (ioread32(addr));
 397 }
 398
 399
 400 static void
 401 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 402                        u32 value)
 403 {
 404         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 405
 406         iowrite32(value, addr);
 407 }
 408
 409
 410 static void
 411 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 412                           void *dstaddr, u32 len)
 413 {
 414         void __iomem *address = devinfo->tcm + mem_offset;
 415         __le32 *dst32;
 416         __le16 *dst16;
 417         u8 *dst8;
 418
 419         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 420                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 421                         dst8 = (u8 *)dstaddr;
 422                         while (len) {
 423                                 *dst8 = ioread8(address);
 424                                 address++;
 425                                 dst8++;
 426                                 len--;
 427                         }
 428                 } else {
 429                         len = len / 2;
 430                         dst16 = (__le16 *)dstaddr;
 431                         while (len) {
 432                                 *dst16 = cpu_to_le16(ioread16(address));
 433                                 address += 2;
 434                                 dst16++;
 435                                 len--;
 436                         }
 437                 }
 438         } else {
 439                 len = len / 4;
 440                 dst32 = (__le32 *)dstaddr;
 441                 while (len) {
 442                         *dst32 = cpu_to_le32(ioread32(address));
 443                         address += 4;
 444                         dst32++;
 445                         len--;
 446                 }
 447         }
 448 }
 449
 450
 451 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 452                 CHIPCREGOFFS(reg), value)
 453
 454
 455 static void
 456 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 457 {
 458         const struct pci_dev *pdev = devinfo->pdev;
 459         struct brcmf_core *core;
 460         u32 bar0_win;
 461
 462         core = brcmf_chip_get_core(devinfo->ci, coreid);
 463         if (core) {
 464                 bar0_win = core->base;
 465                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 466                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 467                                           &bar0_win) == 0) {
 468                         if (bar0_win != core->base) {
 469                                 bar0_win = core->base;
 470                                 pci_write_config_dword(pdev,
 471                                                        BRCMF_PCIE_BAR0_WINDOW,
 472                                                        bar0_win);
 473                         }
 474                 }
 475         } else {
 476                 brcmf_err("Unsupported core selected %x\n", coreid);
 477         }
 478 }
 479
 480
 481 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 482 {
 483         struct brcmf_core *core;
 484         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 485                              BRCMF_PCIE_CFGREG_PM_CSR,
 486                              BRCMF_PCIE_CFGREG_MSI_CAP,
 487                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 488                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 489                              BRCMF_PCIE_CFGREG_MSI_DATA,
 490                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 491                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 492                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 493                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 494                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 495         u32 i;
 496         u32 val;
 497         u32 lsc;
 498
 499         if (!devinfo->ci)
 500                 return;
 501
 502         /* Disable ASPM */
 503         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 504         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 505                               &lsc);
 506         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 507         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 508                                val);
 509
 510         /* Watchdog reset */
 511         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 512         WRITECC32(devinfo, watchdog, 4);
 513         msleep(100);
 514
 515         /* Restore ASPM */
 516         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 517         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 518                                lsc);
 519
 520         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 521         if (core->rev <= 13) {
 522                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 523                         brcmf_pcie_write_reg32(devinfo,
 524                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 525                                                cfg_offset[i]);
 526                         val = brcmf_pcie_read_reg32(devinfo,
 527                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 528                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 529                                   cfg_offset[i], val);
 530                         brcmf_pcie_write_reg32(devinfo,
 531                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 532                                                val);
 533                 }
 534         }
 535 }
 536
 537
 538 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 539 {
 540         u32 config;
 541
 542         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 543         /* BAR1 window may not be sized properly */
 544         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 545         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 546         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 547         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 548
 549         device_wakeup_enable(&devinfo->pdev->dev);
 550 }
 551
 552
 553 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 554 {
 555         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 556                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 557                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 558                                        5);
 559                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 560                                        0);
 561                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 562                                        7);
 563                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 564                                        0);
 565         }
 566         return 0;
 567 }
 568
 569
 570 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 571                                           u32 resetintr)
 572 {
 573         struct brcmf_core *core;
 574
 575         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 576                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 577                 brcmf_chip_resetcore(core, 0, 0, 0);
 578         }
 579
 580         if (!brcmf_chip_set_active(devinfo->ci, resetintr))
 581                 return -EINVAL;
 582         return 0;
 583 }
 584
 585
 586 static int
 587 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 588 {
 589         struct brcmf_pcie_shared_info *shared;
 590         u32 addr;
 591         u32 cur_htod_mb_data;
 592         u32 i;
 593
 594         shared = &devinfo->shared;
 595         addr = shared->htod_mb_data_addr;
 596         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 597
 598         if (cur_htod_mb_data != 0)
 599                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 600                           cur_htod_mb_data);
 601
 602         i = 0;
 603         while (cur_htod_mb_data != 0) {
 604                 msleep(10);
 605                 i++;
 606                 if (i > 100)
 607                         return -EIO;
 608                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 609         }
 610
 611         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 612         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 613         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 614
 615         return 0;
 616 }
 617
 618
 619 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 620 {
 621         struct brcmf_pcie_shared_info *shared;
 622         u32 addr;
 623         u32 dtoh_mb_data;
 624
 625         shared = &devinfo->shared;
 626         addr = shared->dtoh_mb_data_addr;
 627         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 628
 629         if (!dtoh_mb_data)
 630                 return;
 631
 632         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 633
 634         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 635         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 636                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 637                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 638                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 639         }
 640         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 641                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 642         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 643                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 644                 devinfo->mbdata_completed = true;
 645                 wake_up(&devinfo->mbdata_resp_wait);
 646         }
 647 }
 648
 649
 650 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 651 {
 652         struct brcmf_pcie_shared_info *shared;
 653         struct brcmf_pcie_console *console;
 654         u32 addr;
 655
 656         shared = &devinfo->shared;
 657         console = &shared->console;
 658         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 659         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 660
 661         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 662         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 663         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 664         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 665
 666         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 667                   console->base_addr, console->buf_addr, console->bufsize);
 668 }
 669
 670
 671 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 672 {
 673         struct brcmf_pcie_console *console;
 674         u32 addr;
 675         u8 ch;
 676         u32 newidx;
 677
 678         if (!BRCMF_FWCON_ON())
 679                 return;
 680
 681         console = &devinfo->shared.console;
 682         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 683         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 684         while (newidx != console->read_idx) {
 685                 addr = console->buf_addr + console->read_idx;
 686                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 687                 console->read_idx++;
 688                 if (console->read_idx == console->bufsize)
 689                         console->read_idx = 0;
 690                 if (ch == '\r')
 691                         continue;
 692                 console->log_str[console->log_idx] = ch;
 693                 console->log_idx++;
 694                 if ((ch != '\n') &&
 695                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 696                         ch = '\n';
 697                         console->log_str[console->log_idx] = ch;
 698                         console->log_idx++;
 699                 }
 700                 if (ch == '\n') {
 701                         console->log_str[console->log_idx] = 0;
 702                         pr_debug("CONSOLE: %s", console->log_str);
 703                         console->log_idx = 0;
 704                 }
 705         }
 706 }
 707
 708
 709 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 710 {
 711         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
 712 }
 713
 714
 715 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 716 {
 717         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 718                                BRCMF_PCIE_MB_INT_D2H_DB |
 719                                BRCMF_PCIE_MB_INT_FN0_0 |
 720                                BRCMF_PCIE_MB_INT_FN0_1);
 721 }
 722
 723
 724 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
 725 {
 726         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 727
 728         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 729                 brcmf_pcie_intr_disable(devinfo);
 730                 brcmf_dbg(PCIE, "Enter\n");
 731                 return IRQ_WAKE_THREAD;
 732         }
 733         return IRQ_NONE;
 734 }
 735
 736
 737 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
 738 {
 739         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 740         u32 status;
 741
 742         devinfo->in_irq = true;
 743         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 744         brcmf_dbg(PCIE, "Enter %x\n", status);
 745         if (status) {
 746                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 747                                        status);
 748                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 749                               BRCMF_PCIE_MB_INT_FN0_1))
 750                         brcmf_pcie_handle_mb_data(devinfo);
 751                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 752                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 753                                 brcmf_proto_msgbuf_rx_trigger(
 754                                                         &devinfo->pdev->dev);
 755                 }
 756         }
 757         brcmf_pcie_bus_console_read(devinfo);
 758         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 759                 brcmf_pcie_intr_enable(devinfo);
 760         devinfo->in_irq = false;
 761         return IRQ_HANDLED;
 762 }
 763
 764
 765 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 766 {
 767         struct pci_dev *pdev;
 768
 769         pdev = devinfo->pdev;
 770
 771         brcmf_pcie_intr_disable(devinfo);
 772
 773         brcmf_dbg(PCIE, "Enter\n");
 774
 775         pci_enable_msi(pdev);
 776         if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
 777                                  brcmf_pcie_isr_thread, IRQF_SHARED,
 778                                  "brcmf_pcie_intr", devinfo)) {
 779                 pci_disable_msi(pdev);
 780                 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 781                 return -EIO;
 782         }
 783         devinfo->irq_allocated = true;
 784         return 0;
 785 }
 786
 787
 788 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 789 {
 790         struct pci_dev *pdev;
 791         u32 status;
 792         u32 count;
 793
 794         if (!devinfo->irq_allocated)
 795                 return;
 796
 797         pdev = devinfo->pdev;
 798
 799         brcmf_pcie_intr_disable(devinfo);
 800         free_irq(pdev->irq, devinfo);
 801         pci_disable_msi(pdev);
 802
 803         msleep(50);
 804         count = 0;
 805         while ((devinfo->in_irq) && (count < 20)) {
 806                 msleep(50);
 807                 count++;
 808         }
 809         if (devinfo->in_irq)
 810                 brcmf_err("Still in IRQ (processing) !!!\n");
 811
 812         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 813         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
 814
 815         devinfo->irq_allocated = false;
 816 }
 817
 818
 819 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 820 {
 821         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 822         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 823         struct brcmf_commonring *commonring = &ring->commonring;
 824
 825         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 826                 return -EIO;
 827
 828         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 829                   commonring->w_ptr, ring->id);
 830
 831         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 832
 833         return 0;
 834 }
 835
 836
 837 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 838 {
 839         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 840         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 841         struct brcmf_commonring *commonring = &ring->commonring;
 842
 843         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 844                 return -EIO;
 845
 846         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 847                   commonring->r_ptr, ring->id);
 848
 849         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 850
 851         return 0;
 852 }
 853
 854
 855 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 856 {
 857         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 858         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 859
 860         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 861                 return -EIO;
 862
 863         brcmf_dbg(PCIE, "RING !\n");
 864         /* Any arbitrary value will do, lets use 1 */
 865         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 866
 867         return 0;
 868 }
 869
 870
 871 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 872 {
 873         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 874         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 875         struct brcmf_commonring *commonring = &ring->commonring;
 876
 877         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 878                 return -EIO;
 879
 880         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
 881
 882         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 883                   commonring->w_ptr, ring->id);
 884
 885         return 0;
 886 }
 887
 888
 889 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 890 {
 891         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 892         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 893         struct brcmf_commonring *commonring = &ring->commonring;
 894
 895         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 896                 return -EIO;
 897
 898         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
 899
 900         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 901                   commonring->r_ptr, ring->id);
 902
 903         return 0;
 904 }
 905
 906
 907 static void *
 908 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
 909                                      u32 size, u32 tcm_dma_phys_addr,
 910                                      dma_addr_t *dma_handle)
 911 {
 912         void *ring;
 913         u64 address;
 914
 915         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
 916                                   GFP_KERNEL);
 917         if (!ring)
 918                 return NULL;
 919
 920         address = (u64)*dma_handle;
 921         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
 922                                address & 0xffffffff);
 923         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
 924
 925         memset(ring, 0, size);
 926
 927         return (ring);
 928 }
 929
 930
 931 static struct brcmf_pcie_ringbuf *
 932 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
 933                               u32 tcm_ring_phys_addr)
 934 {
 935         void *dma_buf;
 936         dma_addr_t dma_handle;
 937         struct brcmf_pcie_ringbuf *ring;
 938         u32 size;
 939         u32 addr;
 940
 941         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
 942         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
 943                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
 944                         &dma_handle);
 945         if (!dma_buf)
 946                 return NULL;
 947
 948         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
 949         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
 950         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
 951         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
 952
 953         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 954         if (!ring) {
 955                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
 956                                   dma_handle);
 957                 return NULL;
 958         }
 959         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
 960                                 brcmf_ring_itemsize[ring_id], dma_buf);
 961         ring->dma_handle = dma_handle;
 962         ring->devinfo = devinfo;
 963         brcmf_commonring_register_cb(&ring->commonring,
 964                                      brcmf_pcie_ring_mb_ring_bell,
 965                                      brcmf_pcie_ring_mb_update_rptr,
 966                                      brcmf_pcie_ring_mb_update_wptr,
 967                                      brcmf_pcie_ring_mb_write_rptr,
 968                                      brcmf_pcie_ring_mb_write_wptr, ring);
 969
 970         return (ring);
 971 }
 972
 973
 974 static void brcmf_pcie_release_ringbuffer(struct device *dev,
 975                                           struct brcmf_pcie_ringbuf *ring)
 976 {
 977         void *dma_buf;
 978         u32 size;
 979
 980         if (!ring)
 981                 return;
 982
 983         dma_buf = ring->commonring.buf_addr;
 984         if (dma_buf) {
 985                 size = ring->commonring.depth * ring->commonring.item_len;
 986                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
 987         }
 988         kfree(ring);
 989 }
 990
 991
 992 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
 993 {
 994         u32 i;
 995
 996         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
 997                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
 998                                               devinfo->shared.commonrings[i]);
 999                 devinfo->shared.commonrings[i] = NULL;
1000         }
1001         kfree(devinfo->shared.flowrings);
1002         devinfo->shared.flowrings = NULL;
1003         if (devinfo->idxbuf) {
1004                 dma_free_coherent(&devinfo->pdev->dev,
1005                                   devinfo->idxbuf_sz,
1006                                   devinfo->idxbuf,
1007                                   devinfo->idxbuf_dmahandle);
1008                 devinfo->idxbuf = NULL;
1009         }
1010 }
1011
1012
1013 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1014 {
1015         struct brcmf_pcie_ringbuf *ring;
1016         struct brcmf_pcie_ringbuf *rings;
1017         u32 ring_addr;
1018         u32 d2h_w_idx_ptr;
1019         u32 d2h_r_idx_ptr;
1020         u32 h2d_w_idx_ptr;
1021         u32 h2d_r_idx_ptr;
1022         u32 addr;
1023         u32 ring_mem_ptr;
1024         u32 i;
1025         u64 address;
1026         u32 bufsz;
1027         u16 max_sub_queues;
1028         u8 idx_offset;
1029
1030         ring_addr = devinfo->shared.ring_info_addr;
1031         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1032         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1033         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1034
1035         if (devinfo->dma_idx_sz != 0) {
1036                 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1037                         devinfo->dma_idx_sz * 2;
1038                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1039                                                      &devinfo->idxbuf_dmahandle,
1040                                                      GFP_KERNEL);
1041                 if (!devinfo->idxbuf)
1042                         devinfo->dma_idx_sz = 0;
1043         }
1044
1045         if (devinfo->dma_idx_sz == 0) {
1046                 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1047                 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1048                 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1049                 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1050                 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1051                 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1052                 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1053                 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1054                 idx_offset = sizeof(u32);
1055                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1056                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1057                 brcmf_dbg(PCIE, "Using TCM indices\n");
1058         } else {
1059                 memset(devinfo->idxbuf, 0, bufsz);
1060                 devinfo->idxbuf_sz = bufsz;
1061                 idx_offset = devinfo->dma_idx_sz;
1062                 devinfo->write_ptr = brcmf_pcie_write_idx;
1063                 devinfo->read_ptr = brcmf_pcie_read_idx;
1064
1065                 h2d_w_idx_ptr = 0;
1066                 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1067                 address = (u64)devinfo->idxbuf_dmahandle;
1068                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1069                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1070
1071                 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1072                 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1073                 address += max_sub_queues * idx_offset;
1074                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1075                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1076
1077                 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1078                 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1079                 address += max_sub_queues * idx_offset;
1080                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1081                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1082
1083                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1084                                 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1085                 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1086                 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1087                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1088                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1089                 brcmf_dbg(PCIE, "Using host memory indices\n");
1090         }
1091
1092         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1093         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1094
1095         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1096                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1097                 if (!ring)
1098                         goto fail;
1099                 ring->w_idx_addr = h2d_w_idx_ptr;
1100                 ring->r_idx_addr = h2d_r_idx_ptr;
1101                 ring->id = i;
1102                 devinfo->shared.commonrings[i] = ring;
1103
1104                 h2d_w_idx_ptr += idx_offset;
1105                 h2d_r_idx_ptr += idx_offset;
1106                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1107         }
1108
1109         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1110              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1111                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1112                 if (!ring)
1113                         goto fail;
1114                 ring->w_idx_addr = d2h_w_idx_ptr;
1115                 ring->r_idx_addr = d2h_r_idx_ptr;
1116                 ring->id = i;
1117                 devinfo->shared.commonrings[i] = ring;
1118
1119                 d2h_w_idx_ptr += idx_offset;
1120                 d2h_r_idx_ptr += idx_offset;
1121                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1122         }
1123
1124         devinfo->shared.nrof_flowrings =
1125                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1126         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1127                         GFP_KERNEL);
1128         if (!rings)
1129                 goto fail;
1130
1131         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1132                   devinfo->shared.nrof_flowrings);
1133
1134         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1135                 ring = &rings[i];
1136                 ring->devinfo = devinfo;
1137                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1138                 brcmf_commonring_register_cb(&ring->commonring,
1139                                              brcmf_pcie_ring_mb_ring_bell,
1140                                              brcmf_pcie_ring_mb_update_rptr,
1141                                              brcmf_pcie_ring_mb_update_wptr,
1142                                              brcmf_pcie_ring_mb_write_rptr,
1143                                              brcmf_pcie_ring_mb_write_wptr,
1144                                              ring);
1145                 ring->w_idx_addr = h2d_w_idx_ptr;
1146                 ring->r_idx_addr = h2d_r_idx_ptr;
1147                 h2d_w_idx_ptr += idx_offset;
1148                 h2d_r_idx_ptr += idx_offset;
1149         }
1150         devinfo->shared.flowrings = rings;
1151
1152         return 0;
1153
1154 fail:
1155         brcmf_err("Allocating ring buffers failed\n");
1156         brcmf_pcie_release_ringbuffers(devinfo);
1157         return -ENOMEM;
1158 }
1159
1160
1161 static void
1162 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1163 {
1164         if (devinfo->shared.scratch)
1165                 dma_free_coherent(&devinfo->pdev->dev,
1166                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1167                                   devinfo->shared.scratch,
1168                                   devinfo->shared.scratch_dmahandle);
1169         if (devinfo->shared.ringupd)
1170                 dma_free_coherent(&devinfo->pdev->dev,
1171                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1172                                   devinfo->shared.ringupd,
1173                                   devinfo->shared.ringupd_dmahandle);
1174 }
1175
1176 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1177 {
1178         u64 address;
1179         u32 addr;
1180
1181         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1182                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1183                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1184         if (!devinfo->shared.scratch)
1185                 goto fail;
1186
1187         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1188
1189         addr = devinfo->shared.tcm_base_address +
1190                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1191         address = (u64)devinfo->shared.scratch_dmahandle;
1192         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1193         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1194         addr = devinfo->shared.tcm_base_address +
1195                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1196         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1197
1198         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1199                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1200                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1201         if (!devinfo->shared.ringupd)
1202                 goto fail;
1203
1204         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1205
1206         addr = devinfo->shared.tcm_base_address +
1207                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1208         address = (u64)devinfo->shared.ringupd_dmahandle;
1209         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1210         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1211         addr = devinfo->shared.tcm_base_address +
1212                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1213         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1214         return 0;
1215
1216 fail:
1217         brcmf_err("Allocating scratch buffers failed\n");
1218         brcmf_pcie_release_scratchbuffers(devinfo);
1219         return -ENOMEM;
1220 }
1221
1222
1223 static void brcmf_pcie_down(struct device *dev)
1224 {
1225 }
1226
1227
1228 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1229 {
1230         return 0;
1231 }
1232
1233
1234 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1235                                 uint len)
1236 {
1237         return 0;
1238 }
1239
1240
1241 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1242                                 uint len)
1243 {
1244         return 0;
1245 }
1246
1247
1248 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1249 {
1250         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1251         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1252         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1253
1254         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1255         devinfo->wowl_enabled = enabled;
1256 }
1257
1258
1259 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1260 {
1261         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1262         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1263         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1264
1265         return devinfo->ci->ramsize - devinfo->ci->srsize;
1266 }
1267
1268
1269 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1270 {
1271         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1272         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1273         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1274
1275         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1276         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1277         return 0;
1278 }
1279
1280
1281 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1282         .txdata = brcmf_pcie_tx,
1283         .stop = brcmf_pcie_down,
1284         .txctl = brcmf_pcie_tx_ctlpkt,
1285         .rxctl = brcmf_pcie_rx_ctlpkt,
1286         .wowl_config = brcmf_pcie_wowl_config,
1287         .get_ramsize = brcmf_pcie_get_ramsize,
1288         .get_memdump = brcmf_pcie_get_memdump,
1289 };
1290
1291
1292 static void
1293 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1294                           u32 data_len)
1295 {
1296         __le32 *field;
1297         u32 newsize;
1298
1299         if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1300                 return;
1301
1302         field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1303         if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1304                 return;
1305         field++;
1306         newsize = le32_to_cpup(field);
1307
1308         brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1309                   newsize);
1310         devinfo->ci->ramsize = newsize;
1311 }
1312
1313
1314 static int
1315 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1316                                u32 sharedram_addr)
1317 {
1318         struct brcmf_pcie_shared_info *shared;
1319         u32 addr;
1320         u32 version;
1321
1322         shared = &devinfo->shared;
1323         shared->tcm_base_address = sharedram_addr;
1324
1325         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1326         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1327         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1328         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1329             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1330                 brcmf_err("Unsupported PCIE version %d\n", version);
1331                 return -EINVAL;
1332         }
1333
1334         /* check firmware support dma indicies */
1335         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1336                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1337                         devinfo->dma_idx_sz = sizeof(u16);
1338                 else
1339                         devinfo->dma_idx_sz = sizeof(u32);
1340         }
1341
1342         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1343         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1344         if (shared->max_rxbufpost == 0)
1345                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1346
1347         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1348         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1349
1350         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1351         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1352
1353         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1354         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1355
1356         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1357         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1358
1359         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1360                   shared->max_rxbufpost, shared->rx_dataoffset);
1361
1362         brcmf_pcie_bus_console_init(devinfo);
1363
1364         return 0;
1365 }
1366
1367
1368 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1369                                         const struct firmware *fw, void *nvram,
1370                                         u32 nvram_len)
1371 {
1372         u32 sharedram_addr;
1373         u32 sharedram_addr_written;
1374         u32 loop_counter;
1375         int err;
1376         u32 address;
1377         u32 resetintr;
1378
1379         brcmf_dbg(PCIE, "Halt ARM.\n");
1380         err = brcmf_pcie_enter_download_state(devinfo);
1381         if (err)
1382                 return err;
1383
1384         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1385         memcpy_toio(devinfo->tcm + devinfo->ci->rambase,
1386                     (void *)fw->data, fw->size);
1387
1388         resetintr = get_unaligned_le32(fw->data);
1389         release_firmware(fw);
1390
1391         /* reset last 4 bytes of RAM address. to be used for shared
1392          * area. This identifies when FW is running
1393          */
1394         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1395
1396         if (nvram) {
1397                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1398                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1399                           nvram_len;
1400                 memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
1401                 brcmf_fw_nvram_free(nvram);
1402         } else {
1403                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1404                           devinfo->nvram_name);
1405         }
1406
1407         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1408                                                        devinfo->ci->ramsize -
1409                                                        4);
1410         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1411         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1412         if (err)
1413                 return err;
1414
1415         brcmf_dbg(PCIE, "Wait for FW init\n");
1416         sharedram_addr = sharedram_addr_written;
1417         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1418         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1419                 msleep(50);
1420                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1421                                                        devinfo->ci->ramsize -
1422                                                        4);
1423                 loop_counter--;
1424         }
1425         if (sharedram_addr == sharedram_addr_written) {
1426                 brcmf_err("FW failed to initialize\n");
1427                 return -ENODEV;
1428         }
1429         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1430
1431         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1432 }
1433
1434
1435 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1436 {
1437         struct pci_dev *pdev;
1438         int err;
1439         phys_addr_t  bar0_addr, bar1_addr;
1440         ulong bar1_size;
1441
1442         pdev = devinfo->pdev;
1443
1444         err = pci_enable_device(pdev);
1445         if (err) {
1446                 brcmf_err("pci_enable_device failed err=%d\n", err);
1447                 return err;
1448         }
1449
1450         pci_set_master(pdev);
1451
1452         /* Bar-0 mapped address */
1453         bar0_addr = pci_resource_start(pdev, 0);
1454         /* Bar-1 mapped address */
1455         bar1_addr = pci_resource_start(pdev, 2);
1456         /* read Bar-1 mapped memory range */
1457         bar1_size = pci_resource_len(pdev, 2);
1458         if ((bar1_size == 0) || (bar1_addr == 0)) {
1459                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1460                           bar1_size, (unsigned long long)bar1_addr);
1461                 return -EINVAL;
1462         }
1463
1464         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1465         devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size);
1466
1467         if (!devinfo->regs || !devinfo->tcm) {
1468                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1469                           devinfo->tcm);
1470                 return -EINVAL;
1471         }
1472         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1473                   devinfo->regs, (unsigned long long)bar0_addr);
1474         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1475                   devinfo->tcm, (unsigned long long)bar1_addr,
1476                   (unsigned int)bar1_size);
1477
1478         return 0;
1479 }
1480
1481
1482 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1483 {
1484         if (devinfo->tcm)
1485                 iounmap(devinfo->tcm);
1486         if (devinfo->regs)
1487                 iounmap(devinfo->regs);
1488
1489         pci_disable_device(devinfo->pdev);
1490 }
1491
1492
1493 static int brcmf_pcie_attach_bus(struct brcmf_pciedev_info *devinfo)
1494 {
1495         int ret;
1496
1497         /* Attach to the common driver interface */
1498         ret = brcmf_attach(&devinfo->pdev->dev, devinfo->settings);
1499         if (ret) {
1500                 brcmf_err("brcmf_attach failed\n");
1501         } else {
1502                 ret = brcmf_bus_start(&devinfo->pdev->dev);
1503                 if (ret)
1504                         brcmf_err("dongle is not responding\n");
1505         }
1506
1507         return ret;
1508 }
1509
1510
1511 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1512 {
1513         u32 ret_addr;
1514
1515         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1516         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1517         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1518
1519         return ret_addr;
1520 }
1521
1522
1523 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1524 {
1525         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1526
1527         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1528         return brcmf_pcie_read_reg32(devinfo, addr);
1529 }
1530
1531
1532 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1533 {
1534         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1535
1536         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1537         brcmf_pcie_write_reg32(devinfo, addr, value);
1538 }
1539
1540
1541 static int brcmf_pcie_buscoreprep(void *ctx)
1542 {
1543         return brcmf_pcie_get_resource(ctx);
1544 }
1545
1546
1547 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1548 {
1549         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1550         u32 val;
1551
1552         devinfo->ci = chip;
1553         brcmf_pcie_reset_device(devinfo);
1554
1555         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1556         if (val != 0xffffffff)
1557                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1558                                        val);
1559
1560         return 0;
1561 }
1562
1563
1564 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1565                                         u32 rstvec)
1566 {
1567         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1568
1569         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1570 }
1571
1572
1573 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1574         .prepare = brcmf_pcie_buscoreprep,
1575         .reset = brcmf_pcie_buscore_reset,
1576         .activate = brcmf_pcie_buscore_activate,
1577         .read32 = brcmf_pcie_buscore_read32,
1578         .write32 = brcmf_pcie_buscore_write32,
1579 };
1580
1581 static void brcmf_pcie_setup(struct device *dev, int ret,
1582                              const struct firmware *fw,
1583                              void *nvram, u32 nvram_len)
1584 {
1585         struct brcmf_bus *bus;
1586         struct brcmf_pciedev *pcie_bus_dev;
1587         struct brcmf_pciedev_info *devinfo;
1588         struct brcmf_commonring **flowrings;
1589         u32 i;
1590
1591         /* check firmware loading result */
1592         if (ret)
1593                 goto fail;
1594
1595         bus = dev_get_drvdata(dev);
1596         pcie_bus_dev = bus->bus_priv.pcie;
1597         devinfo = pcie_bus_dev->devinfo;
1598         brcmf_pcie_attach(devinfo);
1599
1600         /* Some of the firmwares have the size of the memory of the device
1601          * defined inside the firmware. This is because part of the memory in
1602          * the device is shared and the devision is determined by FW. Parse
1603          * the firmware and adjust the chip memory size now.
1604          */
1605         brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
1606
1607         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1608         if (ret)
1609                 goto fail;
1610
1611         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1612
1613         ret = brcmf_pcie_init_ringbuffers(devinfo);
1614         if (ret)
1615                 goto fail;
1616
1617         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1618         if (ret)
1619                 goto fail;
1620
1621         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1622         ret = brcmf_pcie_request_irq(devinfo);
1623         if (ret)
1624                 goto fail;
1625
1626         /* hook the commonrings in the bus structure. */
1627         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1628                 bus->msgbuf->commonrings[i] =
1629                                 &devinfo->shared.commonrings[i]->commonring;
1630
1631         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
1632                             GFP_KERNEL);
1633         if (!flowrings)
1634                 goto fail;
1635
1636         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1637                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1638         bus->msgbuf->flowrings = flowrings;
1639
1640         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1641         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1642         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1643
1644         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1645
1646         brcmf_pcie_intr_enable(devinfo);
1647         if (brcmf_pcie_attach_bus(devinfo) == 0)
1648                 return;
1649
1650         brcmf_pcie_bus_console_read(devinfo);
1651
1652 fail:
1653         device_release_driver(dev);
1654 }
1655
1656 static int
1657 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1658 {
1659         int ret;
1660         struct brcmf_pciedev_info *devinfo;
1661         struct brcmf_pciedev *pcie_bus_dev;
1662         struct brcmf_bus *bus;
1663         u16 domain_nr;
1664         u16 bus_nr;
1665
1666         domain_nr = pci_domain_nr(pdev->bus) + 1;
1667         bus_nr = pdev->bus->number;
1668         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1669                   domain_nr, bus_nr);
1670
1671         ret = -ENOMEM;
1672         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1673         if (devinfo == NULL)
1674                 return ret;
1675
1676         devinfo->pdev = pdev;
1677         pcie_bus_dev = NULL;
1678         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1679         if (IS_ERR(devinfo->ci)) {
1680                 ret = PTR_ERR(devinfo->ci);
1681                 devinfo->ci = NULL;
1682                 goto fail;
1683         }
1684
1685         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1686         if (pcie_bus_dev == NULL) {
1687                 ret = -ENOMEM;
1688                 goto fail;
1689         }
1690
1691         devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
1692                                                    BRCMF_BUSTYPE_PCIE,
1693                                                    devinfo->ci->chip,
1694                                                    devinfo->ci->chiprev);
1695         if (!devinfo->settings) {
1696                 ret = -ENOMEM;
1697                 goto fail;
1698         }
1699
1700         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1701         if (!bus) {
1702                 ret = -ENOMEM;
1703                 goto fail;
1704         }
1705         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1706         if (!bus->msgbuf) {
1707                 ret = -ENOMEM;
1708                 kfree(bus);
1709                 goto fail;
1710         }
1711
1712         /* hook it all together. */
1713         pcie_bus_dev->devinfo = devinfo;
1714         pcie_bus_dev->bus = bus;
1715         bus->dev = &pdev->dev;
1716         bus->bus_priv.pcie = pcie_bus_dev;
1717         bus->ops = &brcmf_pcie_bus_ops;
1718         bus->proto_type = BRCMF_PROTO_MSGBUF;
1719         bus->chip = devinfo->coreid;
1720         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1721         dev_set_drvdata(&pdev->dev, bus);
1722
1723         ret = brcmf_fw_map_chip_to_name(devinfo->ci->chip, devinfo->ci->chiprev,
1724                                         brcmf_pcie_fwnames,
1725                                         ARRAY_SIZE(brcmf_pcie_fwnames),
1726                                         devinfo->fw_name, devinfo->nvram_name);
1727         if (ret)
1728                 goto fail_bus;
1729
1730         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1731                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1732                                           devinfo->fw_name, devinfo->nvram_name,
1733                                           brcmf_pcie_setup, domain_nr, bus_nr);
1734         if (ret == 0)
1735                 return 0;
1736 fail_bus:
1737         kfree(bus->msgbuf);
1738         kfree(bus);
1739 fail:
1740         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1741         brcmf_pcie_release_resource(devinfo);
1742         if (devinfo->ci)
1743                 brcmf_chip_detach(devinfo->ci);
1744         if (devinfo->settings)
1745                 brcmf_release_module_param(devinfo->settings);
1746         kfree(pcie_bus_dev);
1747         kfree(devinfo);
1748         return ret;
1749 }
1750
1751
1752 static void
1753 brcmf_pcie_remove(struct pci_dev *pdev)
1754 {
1755         struct brcmf_pciedev_info *devinfo;
1756         struct brcmf_bus *bus;
1757
1758         brcmf_dbg(PCIE, "Enter\n");
1759
1760         bus = dev_get_drvdata(&pdev->dev);
1761         if (bus == NULL)
1762                 return;
1763
1764         devinfo = bus->bus_priv.pcie->devinfo;
1765
1766         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1767         if (devinfo->ci)
1768                 brcmf_pcie_intr_disable(devinfo);
1769
1770         brcmf_detach(&pdev->dev);
1771
1772         kfree(bus->bus_priv.pcie);
1773         kfree(bus->msgbuf->flowrings);
1774         kfree(bus->msgbuf);
1775         kfree(bus);
1776
1777         brcmf_pcie_release_irq(devinfo);
1778         brcmf_pcie_release_scratchbuffers(devinfo);
1779         brcmf_pcie_release_ringbuffers(devinfo);
1780         brcmf_pcie_reset_device(devinfo);
1781         brcmf_pcie_release_resource(devinfo);
1782
1783         if (devinfo->ci)
1784                 brcmf_chip_detach(devinfo->ci);
1785         if (devinfo->settings)
1786                 brcmf_release_module_param(devinfo->settings);
1787
1788         kfree(devinfo);
1789         dev_set_drvdata(&pdev->dev, NULL);
1790 }
1791
1792
1793 #ifdef CONFIG_PM
1794
1795
1796 static int brcmf_pcie_pm_enter_D3(struct device *dev)
1797 {
1798         struct brcmf_pciedev_info *devinfo;
1799         struct brcmf_bus *bus;
1800
1801         brcmf_dbg(PCIE, "Enter\n");
1802
1803         bus = dev_get_drvdata(dev);
1804         devinfo = bus->bus_priv.pcie->devinfo;
1805
1806         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1807
1808         devinfo->mbdata_completed = false;
1809         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1810
1811         wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
1812                            BRCMF_PCIE_MBDATA_TIMEOUT);
1813         if (!devinfo->mbdata_completed) {
1814                 brcmf_err("Timeout on response for entering D3 substate\n");
1815                 return -EIO;
1816         }
1817
1818         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1819
1820         return 0;
1821 }
1822
1823
1824 static int brcmf_pcie_pm_leave_D3(struct device *dev)
1825 {
1826         struct brcmf_pciedev_info *devinfo;
1827         struct brcmf_bus *bus;
1828         struct pci_dev *pdev;
1829         int err;
1830
1831         brcmf_dbg(PCIE, "Enter\n");
1832
1833         bus = dev_get_drvdata(dev);
1834         devinfo = bus->bus_priv.pcie->devinfo;
1835         brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
1836
1837         /* Check if device is still up and running, if so we are ready */
1838         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1839                 brcmf_dbg(PCIE, "Try to wakeup device....\n");
1840                 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
1841                         goto cleanup;
1842                 brcmf_dbg(PCIE, "Hot resume, continue....\n");
1843                 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1844                 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1845                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1846                 brcmf_pcie_intr_enable(devinfo);
1847                 return 0;
1848         }
1849
1850 cleanup:
1851         brcmf_chip_detach(devinfo->ci);
1852         devinfo->ci = NULL;
1853         pdev = devinfo->pdev;
1854         brcmf_pcie_remove(pdev);
1855
1856         err = brcmf_pcie_probe(pdev, NULL);
1857         if (err)
1858                 brcmf_err("probe after resume failed, err=%d\n", err);
1859
1860         return err;
1861 }
1862
1863
1864 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
1865         .suspend = brcmf_pcie_pm_enter_D3,
1866         .resume = brcmf_pcie_pm_leave_D3,
1867         .freeze = brcmf_pcie_pm_enter_D3,
1868         .restore = brcmf_pcie_pm_leave_D3,
1869 };
1870
1871
1872 #endif /* CONFIG_PM */
1873
1874
1875 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1876         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1877 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev)  { \
1878         BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1879         subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1880
1881 static struct pci_device_id brcmf_pcie_devid_table[] = {
1882         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
1883         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1884         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1885         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1886         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
1887         BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
1888         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1889         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1890         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1891         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
1892         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
1893         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
1894         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
1895         BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365),
1896         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
1897         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
1898         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
1899         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
1900         { /* end: all zeroes */ }
1901 };
1902
1903
1904 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1905
1906
1907 static struct pci_driver brcmf_pciedrvr = {
1908         .node = {},
1909         .name = KBUILD_MODNAME,
1910         .id_table = brcmf_pcie_devid_table,
1911         .probe = brcmf_pcie_probe,
1912         .remove = brcmf_pcie_remove,
1913 #ifdef CONFIG_PM
1914         .driver.pm = &brcmf_pciedrvr_pm,
1915 #endif
1916 };
1917
1918
1919 void brcmf_pcie_register(void)
1920 {
1921         int err;
1922
1923         brcmf_dbg(PCIE, "Enter\n");
1924         err = pci_register_driver(&brcmf_pciedrvr);
1925         if (err)
1926                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1927 }
1928
1929
1930 void brcmf_pcie_exit(void)
1931 {
1932         brcmf_dbg(PCIE, "Enter\n");
1933         pci_unregister_driver(&brcmf_pciedrvr);
1934 }