drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <linux/io.h>
  26 #include <asm/unaligned.h>
  27
  28 #include <soc.h>
  29 #include <chipcommon.h>
  30 #include <brcmu_utils.h>
  31 #include <brcmu_wifi.h>
  32 #include <brcm_hw_ids.h>
  33
  34 #include "debug.h"
  35 #include "bus.h"
  36 #include "commonring.h"
  37 #include "msgbuf.h"
  38 #include "pcie.h"
  39 #include "firmware.h"
  40 #include "chip.h"
  41 #include "core.h"
  42 #include "common.h"
  43
  44
  45 enum brcmf_pcie_state {
  46         BRCMFMAC_PCIE_STATE_DOWN,
  47         BRCMFMAC_PCIE_STATE_UP
  48 };
  49
  50 BRCMF_FW_NVRAM_DEF(43602, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  51 BRCMF_FW_NVRAM_DEF(4350, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  52 BRCMF_FW_NVRAM_DEF(4350C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  53 BRCMF_FW_NVRAM_DEF(4356, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  54 BRCMF_FW_NVRAM_DEF(43570, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  55 BRCMF_FW_NVRAM_DEF(4358, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  56 BRCMF_FW_NVRAM_DEF(4359, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  57 BRCMF_FW_NVRAM_DEF(4365B, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  58 BRCMF_FW_NVRAM_DEF(4365C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  59 BRCMF_FW_NVRAM_DEF(4366B, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  60 BRCMF_FW_NVRAM_DEF(4366C, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  61 BRCMF_FW_NVRAM_DEF(4371, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
  62
  63 static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
  64         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
  65         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
  66         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
  67         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
  68         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
  69         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
  70         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
  71         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
  72         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
  73         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
  74         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
  75         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
  76         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
  77         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
  78         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
  79         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
  80 };
  81
  82 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  83
  84 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  85
  86 /* backplane addres space accessed by BAR0 */
  87 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  88 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  89 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  90
  91 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  92 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  93
  94 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  95 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  96
  97 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  98 #define BRCMF_PCIE_REG_INTMASK                  0x94
  99 #define BRCMF_PCIE_REG_SBMBX                    0x98
 100
 101 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
 102
 103 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
 104 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
 105 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
 106 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
 107 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
 108 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
 109
 110 #define BRCMF_PCIE2_INTA                        0x01
 111 #define BRCMF_PCIE2_INTB                        0x02
 112
 113 #define BRCMF_PCIE_INT_0                        0x01
 114 #define BRCMF_PCIE_INT_1                        0x02
 115 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 116                                                  BRCMF_PCIE_INT_1)
 117
 118 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 119 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 120 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 121 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 122 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 123 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 124 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 125 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 126 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 127 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 128
 129 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 130                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 131                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 132                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 133                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 134                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 135                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 136                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 137
 138 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 139 #define BRCMF_PCIE_MAX_SHARED_VERSION           6
 140 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 141 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 142 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 143
 144 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 145 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 146
 147 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 148 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 149 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 150 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 151 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 152 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 153 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 154 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 155 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 156 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 157 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 158
 159 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 160 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 161 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 162 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 163
 164 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 165 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 166 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 167 #define BRCMF_RING_MEM_SZ                       16
 168 #define BRCMF_RING_STATE_SZ                     8
 169
 170 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 171
 172 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 173 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 174 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 175
 176 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 177 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 178
 179 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 180 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 181 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 182
 183 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 184 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 185 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 186 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 187
 188 #define BRCMF_PCIE_MBDATA_TIMEOUT               msecs_to_jiffies(2000)
 189
 190 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 191 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 192 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 193 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 194 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 195 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 196 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 197 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 198 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 199 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 200 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 201 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 202 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 203
 204 /* Magic number at a magic location to find RAM size */
 205 #define BRCMF_RAMSIZE_MAGIC                     0x534d4152      /* SMAR */
 206 #define BRCMF_RAMSIZE_OFFSET                    0x6c
 207
 208
 209 struct brcmf_pcie_console {
 210         u32 base_addr;
 211         u32 buf_addr;
 212         u32 bufsize;
 213         u32 read_idx;
 214         u8 log_str[256];
 215         u8 log_idx;
 216 };
 217
 218 struct brcmf_pcie_shared_info {
 219         u32 tcm_base_address;
 220         u32 flags;
 221         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 222         struct brcmf_pcie_ringbuf *flowrings;
 223         u16 max_rxbufpost;
 224         u16 max_flowrings;
 225         u16 max_submissionrings;
 226         u16 max_completionrings;
 227         u32 rx_dataoffset;
 228         u32 htod_mb_data_addr;
 229         u32 dtoh_mb_data_addr;
 230         u32 ring_info_addr;
 231         struct brcmf_pcie_console console;
 232         void *scratch;
 233         dma_addr_t scratch_dmahandle;
 234         void *ringupd;
 235         dma_addr_t ringupd_dmahandle;
 236         u8 version;
 237 };
 238
 239 struct brcmf_pcie_core_info {
 240         u32 base;
 241         u32 wrapbase;
 242 };
 243
 244 struct brcmf_pciedev_info {
 245         enum brcmf_pcie_state state;
 246         bool in_irq;
 247         struct pci_dev *pdev;
 248         char fw_name[BRCMF_FW_NAME_LEN];
 249         char nvram_name[BRCMF_FW_NAME_LEN];
 250         void __iomem *regs;
 251         void __iomem *tcm;
 252         u32 ram_base;
 253         u32 ram_size;
 254         struct brcmf_chip *ci;
 255         u32 coreid;
 256         struct brcmf_pcie_shared_info shared;
 257         wait_queue_head_t mbdata_resp_wait;
 258         bool mbdata_completed;
 259         bool irq_allocated;
 260         bool wowl_enabled;
 261         u8 dma_idx_sz;
 262         void *idxbuf;
 263         u32 idxbuf_sz;
 264         dma_addr_t idxbuf_dmahandle;
 265         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 266         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 267                           u16 value);
 268         struct brcmf_mp_device *settings;
 269 };
 270
 271 struct brcmf_pcie_ringbuf {
 272         struct brcmf_commonring commonring;
 273         dma_addr_t dma_handle;
 274         u32 w_idx_addr;
 275         u32 r_idx_addr;
 276         struct brcmf_pciedev_info *devinfo;
 277         u8 id;
 278 };
 279
 280 /**
 281  * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
 282  *
 283  * @ringmem: dongle memory pointer to ring memory location
 284  * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
 285  * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
 286  * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
 287  * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
 288  * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
 289  * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
 290  * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
 291  * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
 292  * @max_flowrings: maximum number of tx flow rings supported.
 293  * @max_submissionrings: maximum number of submission rings(h2d) supported.
 294  * @max_completionrings: maximum number of completion rings(d2h) supported.
 295  */
 296 struct brcmf_pcie_dhi_ringinfo {
 297         __le32                  ringmem;
 298         __le32                  h2d_w_idx_ptr;
 299         __le32                  h2d_r_idx_ptr;
 300         __le32                  d2h_w_idx_ptr;
 301         __le32                  d2h_r_idx_ptr;
 302         struct msgbuf_buf_addr  h2d_w_idx_hostaddr;
 303         struct msgbuf_buf_addr  h2d_r_idx_hostaddr;
 304         struct msgbuf_buf_addr  d2h_w_idx_hostaddr;
 305         struct msgbuf_buf_addr  d2h_r_idx_hostaddr;
 306         __le16                  max_flowrings;
 307         __le16                  max_submissionrings;
 308         __le16                  max_completionrings;
 309 };
 310
 311 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 312         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 313         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 314         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 315         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 316         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 317 };
 318
 319 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 320         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 321         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 322         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 323         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 324         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 325 };
 326
 327
 328 static u32
 329 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 330 {
 331         void __iomem *address = devinfo->regs + reg_offset;
 332
 333         return (ioread32(address));
 334 }
 335
 336
 337 static void
 338 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 339                        u32 value)
 340 {
 341         void __iomem *address = devinfo->regs + reg_offset;
 342
 343         iowrite32(value, address);
 344 }
 345
 346
 347 static u8
 348 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 349 {
 350         void __iomem *address = devinfo->tcm + mem_offset;
 351
 352         return (ioread8(address));
 353 }
 354
 355
 356 static u16
 357 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 358 {
 359         void __iomem *address = devinfo->tcm + mem_offset;
 360
 361         return (ioread16(address));
 362 }
 363
 364
 365 static void
 366 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 367                        u16 value)
 368 {
 369         void __iomem *address = devinfo->tcm + mem_offset;
 370
 371         iowrite16(value, address);
 372 }
 373
 374
 375 static u16
 376 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 377 {
 378         u16 *address = devinfo->idxbuf + mem_offset;
 379
 380         return (*(address));
 381 }
 382
 383
 384 static void
 385 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 386                      u16 value)
 387 {
 388         u16 *address = devinfo->idxbuf + mem_offset;
 389
 390         *(address) = value;
 391 }
 392
 393
 394 static u32
 395 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 396 {
 397         void __iomem *address = devinfo->tcm + mem_offset;
 398
 399         return (ioread32(address));
 400 }
 401
 402
 403 static void
 404 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 405                        u32 value)
 406 {
 407         void __iomem *address = devinfo->tcm + mem_offset;
 408
 409         iowrite32(value, address);
 410 }
 411
 412
 413 static u32
 414 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 415 {
 416         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 417
 418         return (ioread32(addr));
 419 }
 420
 421
 422 static void
 423 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 424                        u32 value)
 425 {
 426         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 427
 428         iowrite32(value, addr);
 429 }
 430
 431
 432 static void
 433 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 434                           void *dstaddr, u32 len)
 435 {
 436         void __iomem *address = devinfo->tcm + mem_offset;
 437         __le32 *dst32;
 438         __le16 *dst16;
 439         u8 *dst8;
 440
 441         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 442                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 443                         dst8 = (u8 *)dstaddr;
 444                         while (len) {
 445                                 *dst8 = ioread8(address);
 446                                 address++;
 447                                 dst8++;
 448                                 len--;
 449                         }
 450                 } else {
 451                         len = len / 2;
 452                         dst16 = (__le16 *)dstaddr;
 453                         while (len) {
 454                                 *dst16 = cpu_to_le16(ioread16(address));
 455                                 address += 2;
 456                                 dst16++;
 457                                 len--;
 458                         }
 459                 }
 460         } else {
 461                 len = len / 4;
 462                 dst32 = (__le32 *)dstaddr;
 463                 while (len) {
 464                         *dst32 = cpu_to_le32(ioread32(address));
 465                         address += 4;
 466                         dst32++;
 467                         len--;
 468                 }
 469         }
 470 }
 471
 472
 473 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 474                 CHIPCREGOFFS(reg), value)
 475
 476
 477 static void
 478 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 479 {
 480         const struct pci_dev *pdev = devinfo->pdev;
 481         struct brcmf_core *core;
 482         u32 bar0_win;
 483
 484         core = brcmf_chip_get_core(devinfo->ci, coreid);
 485         if (core) {
 486                 bar0_win = core->base;
 487                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 488                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 489                                           &bar0_win) == 0) {
 490                         if (bar0_win != core->base) {
 491                                 bar0_win = core->base;
 492                                 pci_write_config_dword(pdev,
 493                                                        BRCMF_PCIE_BAR0_WINDOW,
 494                                                        bar0_win);
 495                         }
 496                 }
 497         } else {
 498                 brcmf_err("Unsupported core selected %x\n", coreid);
 499         }
 500 }
 501
 502
 503 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 504 {
 505         struct brcmf_core *core;
 506         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 507                              BRCMF_PCIE_CFGREG_PM_CSR,
 508                              BRCMF_PCIE_CFGREG_MSI_CAP,
 509                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 510                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 511                              BRCMF_PCIE_CFGREG_MSI_DATA,
 512                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 513                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 514                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 515                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 516                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 517         u32 i;
 518         u32 val;
 519         u32 lsc;
 520
 521         if (!devinfo->ci)
 522                 return;
 523
 524         /* Disable ASPM */
 525         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 526         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 527                               &lsc);
 528         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 529         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 530                                val);
 531
 532         /* Watchdog reset */
 533         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 534         WRITECC32(devinfo, watchdog, 4);
 535         msleep(100);
 536
 537         /* Restore ASPM */
 538         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 539         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 540                                lsc);
 541
 542         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 543         if (core->rev <= 13) {
 544                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 545                         brcmf_pcie_write_reg32(devinfo,
 546                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 547                                                cfg_offset[i]);
 548                         val = brcmf_pcie_read_reg32(devinfo,
 549                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 550                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 551                                   cfg_offset[i], val);
 552                         brcmf_pcie_write_reg32(devinfo,
 553                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 554                                                val);
 555                 }
 556         }
 557 }
 558
 559
 560 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 561 {
 562         u32 config;
 563
 564         /* BAR1 window may not be sized properly */
 565         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 566         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 567         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 568         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 569
 570         device_wakeup_enable(&devinfo->pdev->dev);
 571 }
 572
 573
 574 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 575 {
 576         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 577                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 578                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 579                                        5);
 580                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 581                                        0);
 582                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 583                                        7);
 584                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 585                                        0);
 586         }
 587         return 0;
 588 }
 589
 590
 591 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 592                                           u32 resetintr)
 593 {
 594         struct brcmf_core *core;
 595
 596         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 597                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 598                 brcmf_chip_resetcore(core, 0, 0, 0);
 599         }
 600
 601         if (!brcmf_chip_set_active(devinfo->ci, resetintr))
 602                 return -EIO;
 603         return 0;
 604 }
 605
 606
 607 static int
 608 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 609 {
 610         struct brcmf_pcie_shared_info *shared;
 611         u32 addr;
 612         u32 cur_htod_mb_data;
 613         u32 i;
 614
 615         shared = &devinfo->shared;
 616         addr = shared->htod_mb_data_addr;
 617         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 618
 619         if (cur_htod_mb_data != 0)
 620                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 621                           cur_htod_mb_data);
 622
 623         i = 0;
 624         while (cur_htod_mb_data != 0) {
 625                 msleep(10);
 626                 i++;
 627                 if (i > 100)
 628                         return -EIO;
 629                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 630         }
 631
 632         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 633         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 634         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 635
 636         return 0;
 637 }
 638
 639
 640 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 641 {
 642         struct brcmf_pcie_shared_info *shared;
 643         u32 addr;
 644         u32 dtoh_mb_data;
 645
 646         shared = &devinfo->shared;
 647         addr = shared->dtoh_mb_data_addr;
 648         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 649
 650         if (!dtoh_mb_data)
 651                 return;
 652
 653         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 654
 655         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 656         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 657                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 658                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 659                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 660         }
 661         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 662                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 663         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 664                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 665                 devinfo->mbdata_completed = true;
 666                 wake_up(&devinfo->mbdata_resp_wait);
 667         }
 668 }
 669
 670
 671 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 672 {
 673         struct brcmf_pcie_shared_info *shared;
 674         struct brcmf_pcie_console *console;
 675         u32 addr;
 676
 677         shared = &devinfo->shared;
 678         console = &shared->console;
 679         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 680         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 681
 682         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 683         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 684         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 685         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 686
 687         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 688                   console->base_addr, console->buf_addr, console->bufsize);
 689 }
 690
 691
 692 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 693 {
 694         struct brcmf_pcie_console *console;
 695         u32 addr;
 696         u8 ch;
 697         u32 newidx;
 698
 699         if (!BRCMF_FWCON_ON())
 700                 return;
 701
 702         console = &devinfo->shared.console;
 703         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 704         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 705         while (newidx != console->read_idx) {
 706                 addr = console->buf_addr + console->read_idx;
 707                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 708                 console->read_idx++;
 709                 if (console->read_idx == console->bufsize)
 710                         console->read_idx = 0;
 711                 if (ch == '\r')
 712                         continue;
 713                 console->log_str[console->log_idx] = ch;
 714                 console->log_idx++;
 715                 if ((ch != '\n') &&
 716                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 717                         ch = '\n';
 718                         console->log_str[console->log_idx] = ch;
 719                         console->log_idx++;
 720                 }
 721                 if (ch == '\n') {
 722                         console->log_str[console->log_idx] = 0;
 723                         pr_debug("CONSOLE: %s", console->log_str);
 724                         console->log_idx = 0;
 725                 }
 726         }
 727 }
 728
 729
 730 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 731 {
 732         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
 733 }
 734
 735
 736 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 737 {
 738         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 739                                BRCMF_PCIE_MB_INT_D2H_DB |
 740                                BRCMF_PCIE_MB_INT_FN0_0 |
 741                                BRCMF_PCIE_MB_INT_FN0_1);
 742 }
 743
 744
 745 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
 746 {
 747         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 748
 749         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 750                 brcmf_pcie_intr_disable(devinfo);
 751                 brcmf_dbg(PCIE, "Enter\n");
 752                 return IRQ_WAKE_THREAD;
 753         }
 754         return IRQ_NONE;
 755 }
 756
 757
 758 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
 759 {
 760         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 761         u32 status;
 762
 763         devinfo->in_irq = true;
 764         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 765         brcmf_dbg(PCIE, "Enter %x\n", status);
 766         if (status) {
 767                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 768                                        status);
 769                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 770                               BRCMF_PCIE_MB_INT_FN0_1))
 771                         brcmf_pcie_handle_mb_data(devinfo);
 772                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 773                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 774                                 brcmf_proto_msgbuf_rx_trigger(
 775                                                         &devinfo->pdev->dev);
 776                 }
 777         }
 778         brcmf_pcie_bus_console_read(devinfo);
 779         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 780                 brcmf_pcie_intr_enable(devinfo);
 781         devinfo->in_irq = false;
 782         return IRQ_HANDLED;
 783 }
 784
 785
 786 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 787 {
 788         struct pci_dev *pdev;
 789
 790         pdev = devinfo->pdev;
 791
 792         brcmf_pcie_intr_disable(devinfo);
 793
 794         brcmf_dbg(PCIE, "Enter\n");
 795
 796         pci_enable_msi(pdev);
 797         if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
 798                                  brcmf_pcie_isr_thread, IRQF_SHARED,
 799                                  "brcmf_pcie_intr", devinfo)) {
 800                 pci_disable_msi(pdev);
 801                 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 802                 return -EIO;
 803         }
 804         devinfo->irq_allocated = true;
 805         return 0;
 806 }
 807
 808
 809 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 810 {
 811         struct pci_dev *pdev;
 812         u32 status;
 813         u32 count;
 814
 815         if (!devinfo->irq_allocated)
 816                 return;
 817
 818         pdev = devinfo->pdev;
 819
 820         brcmf_pcie_intr_disable(devinfo);
 821         free_irq(pdev->irq, devinfo);
 822         pci_disable_msi(pdev);
 823
 824         msleep(50);
 825         count = 0;
 826         while ((devinfo->in_irq) && (count < 20)) {
 827                 msleep(50);
 828                 count++;
 829         }
 830         if (devinfo->in_irq)
 831                 brcmf_err("Still in IRQ (processing) !!!\n");
 832
 833         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 834         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
 835
 836         devinfo->irq_allocated = false;
 837 }
 838
 839
 840 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 841 {
 842         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 843         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 844         struct brcmf_commonring *commonring = &ring->commonring;
 845
 846         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 847                 return -EIO;
 848
 849         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 850                   commonring->w_ptr, ring->id);
 851
 852         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 853
 854         return 0;
 855 }
 856
 857
 858 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 859 {
 860         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 861         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 862         struct brcmf_commonring *commonring = &ring->commonring;
 863
 864         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 865                 return -EIO;
 866
 867         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 868                   commonring->r_ptr, ring->id);
 869
 870         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 871
 872         return 0;
 873 }
 874
 875
 876 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 877 {
 878         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 879         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 880
 881         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 882                 return -EIO;
 883
 884         brcmf_dbg(PCIE, "RING !\n");
 885         /* Any arbitrary value will do, lets use 1 */
 886         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 887
 888         return 0;
 889 }
 890
 891
 892 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 893 {
 894         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 895         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 896         struct brcmf_commonring *commonring = &ring->commonring;
 897
 898         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 899                 return -EIO;
 900
 901         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
 902
 903         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 904                   commonring->w_ptr, ring->id);
 905
 906         return 0;
 907 }
 908
 909
 910 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 911 {
 912         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 913         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 914         struct brcmf_commonring *commonring = &ring->commonring;
 915
 916         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 917                 return -EIO;
 918
 919         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
 920
 921         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 922                   commonring->r_ptr, ring->id);
 923
 924         return 0;
 925 }
 926
 927
 928 static void *
 929 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
 930                                      u32 size, u32 tcm_dma_phys_addr,
 931                                      dma_addr_t *dma_handle)
 932 {
 933         void *ring;
 934         u64 address;
 935
 936         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
 937                                   GFP_KERNEL);
 938         if (!ring)
 939                 return NULL;
 940
 941         address = (u64)*dma_handle;
 942         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
 943                                address & 0xffffffff);
 944         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
 945
 946         memset(ring, 0, size);
 947
 948         return (ring);
 949 }
 950
 951
 952 static struct brcmf_pcie_ringbuf *
 953 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
 954                               u32 tcm_ring_phys_addr)
 955 {
 956         void *dma_buf;
 957         dma_addr_t dma_handle;
 958         struct brcmf_pcie_ringbuf *ring;
 959         u32 size;
 960         u32 addr;
 961
 962         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
 963         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
 964                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
 965                         &dma_handle);
 966         if (!dma_buf)
 967                 return NULL;
 968
 969         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
 970         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
 971         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
 972         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
 973
 974         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 975         if (!ring) {
 976                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
 977                                   dma_handle);
 978                 return NULL;
 979         }
 980         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
 981                                 brcmf_ring_itemsize[ring_id], dma_buf);
 982         ring->dma_handle = dma_handle;
 983         ring->devinfo = devinfo;
 984         brcmf_commonring_register_cb(&ring->commonring,
 985                                      brcmf_pcie_ring_mb_ring_bell,
 986                                      brcmf_pcie_ring_mb_update_rptr,
 987                                      brcmf_pcie_ring_mb_update_wptr,
 988                                      brcmf_pcie_ring_mb_write_rptr,
 989                                      brcmf_pcie_ring_mb_write_wptr, ring);
 990
 991         return (ring);
 992 }
 993
 994
 995 static void brcmf_pcie_release_ringbuffer(struct device *dev,
 996                                           struct brcmf_pcie_ringbuf *ring)
 997 {
 998         void *dma_buf;
 999         u32 size;
1000
1001         if (!ring)
1002                 return;
1003
1004         dma_buf = ring->commonring.buf_addr;
1005         if (dma_buf) {
1006                 size = ring->commonring.depth * ring->commonring.item_len;
1007                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1008         }
1009         kfree(ring);
1010 }
1011
1012
1013 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1014 {
1015         u32 i;
1016
1017         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1018                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1019                                               devinfo->shared.commonrings[i]);
1020                 devinfo->shared.commonrings[i] = NULL;
1021         }
1022         kfree(devinfo->shared.flowrings);
1023         devinfo->shared.flowrings = NULL;
1024         if (devinfo->idxbuf) {
1025                 dma_free_coherent(&devinfo->pdev->dev,
1026                                   devinfo->idxbuf_sz,
1027                                   devinfo->idxbuf,
1028                                   devinfo->idxbuf_dmahandle);
1029                 devinfo->idxbuf = NULL;
1030         }
1031 }
1032
1033
1034 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1035 {
1036         struct brcmf_pcie_ringbuf *ring;
1037         struct brcmf_pcie_ringbuf *rings;
1038         u32 d2h_w_idx_ptr;
1039         u32 d2h_r_idx_ptr;
1040         u32 h2d_w_idx_ptr;
1041         u32 h2d_r_idx_ptr;
1042         u32 ring_mem_ptr;
1043         u32 i;
1044         u64 address;
1045         u32 bufsz;
1046         u8 idx_offset;
1047         struct brcmf_pcie_dhi_ringinfo ringinfo;
1048         u16 max_flowrings;
1049         u16 max_submissionrings;
1050         u16 max_completionrings;
1051
1052         memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1053                       sizeof(ringinfo));
1054         if (devinfo->shared.version >= 6) {
1055                 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1056                 max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1057                 max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1058         } else {
1059                 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1060                 max_flowrings = max_submissionrings -
1061                                 BRCMF_NROF_H2D_COMMON_MSGRINGS;
1062                 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1063         }
1064
1065         if (devinfo->dma_idx_sz != 0) {
1066                 bufsz = (max_submissionrings + max_completionrings) *
1067                         devinfo->dma_idx_sz * 2;
1068                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1069                                                      &devinfo->idxbuf_dmahandle,
1070                                                      GFP_KERNEL);
1071                 if (!devinfo->idxbuf)
1072                         devinfo->dma_idx_sz = 0;
1073         }
1074
1075         if (devinfo->dma_idx_sz == 0) {
1076                 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1077                 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1078                 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1079                 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1080                 idx_offset = sizeof(u32);
1081                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1082                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1083                 brcmf_dbg(PCIE, "Using TCM indices\n");
1084         } else {
1085                 memset(devinfo->idxbuf, 0, bufsz);
1086                 devinfo->idxbuf_sz = bufsz;
1087                 idx_offset = devinfo->dma_idx_sz;
1088                 devinfo->write_ptr = brcmf_pcie_write_idx;
1089                 devinfo->read_ptr = brcmf_pcie_read_idx;
1090
1091                 h2d_w_idx_ptr = 0;
1092                 address = (u64)devinfo->idxbuf_dmahandle;
1093                 ringinfo.h2d_w_idx_hostaddr.low_addr =
1094                         cpu_to_le32(address & 0xffffffff);
1095                 ringinfo.h2d_w_idx_hostaddr.high_addr =
1096                         cpu_to_le32(address >> 32);
1097
1098                 h2d_r_idx_ptr = h2d_w_idx_ptr +
1099                                 max_submissionrings * idx_offset;
1100                 address += max_submissionrings * idx_offset;
1101                 ringinfo.h2d_r_idx_hostaddr.low_addr =
1102                         cpu_to_le32(address & 0xffffffff);
1103                 ringinfo.h2d_r_idx_hostaddr.high_addr =
1104                         cpu_to_le32(address >> 32);
1105
1106                 d2h_w_idx_ptr = h2d_r_idx_ptr +
1107                                 max_submissionrings * idx_offset;
1108                 address += max_submissionrings * idx_offset;
1109                 ringinfo.d2h_w_idx_hostaddr.low_addr =
1110                         cpu_to_le32(address & 0xffffffff);
1111                 ringinfo.d2h_w_idx_hostaddr.high_addr =
1112                         cpu_to_le32(address >> 32);
1113
1114                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1115                                 max_completionrings * idx_offset;
1116                 address += max_completionrings * idx_offset;
1117                 ringinfo.d2h_r_idx_hostaddr.low_addr =
1118                         cpu_to_le32(address & 0xffffffff);
1119                 ringinfo.d2h_r_idx_hostaddr.high_addr =
1120                         cpu_to_le32(address >> 32);
1121
1122                 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1123                             &ringinfo, sizeof(ringinfo));
1124                 brcmf_dbg(PCIE, "Using host memory indices\n");
1125         }
1126
1127         ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1128
1129         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1130                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1131                 if (!ring)
1132                         goto fail;
1133                 ring->w_idx_addr = h2d_w_idx_ptr;
1134                 ring->r_idx_addr = h2d_r_idx_ptr;
1135                 ring->id = i;
1136                 devinfo->shared.commonrings[i] = ring;
1137
1138                 h2d_w_idx_ptr += idx_offset;
1139                 h2d_r_idx_ptr += idx_offset;
1140                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1141         }
1142
1143         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1144              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1145                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1146                 if (!ring)
1147                         goto fail;
1148                 ring->w_idx_addr = d2h_w_idx_ptr;
1149                 ring->r_idx_addr = d2h_r_idx_ptr;
1150                 ring->id = i;
1151                 devinfo->shared.commonrings[i] = ring;
1152
1153                 d2h_w_idx_ptr += idx_offset;
1154                 d2h_r_idx_ptr += idx_offset;
1155                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1156         }
1157
1158         devinfo->shared.max_flowrings = max_flowrings;
1159         devinfo->shared.max_submissionrings = max_submissionrings;
1160         devinfo->shared.max_completionrings = max_completionrings;
1161         rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1162         if (!rings)
1163                 goto fail;
1164
1165         brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1166
1167         for (i = 0; i < max_flowrings; i++) {
1168                 ring = &rings[i];
1169                 ring->devinfo = devinfo;
1170                 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1171                 brcmf_commonring_register_cb(&ring->commonring,
1172                                              brcmf_pcie_ring_mb_ring_bell,
1173                                              brcmf_pcie_ring_mb_update_rptr,
1174                                              brcmf_pcie_ring_mb_update_wptr,
1175                                              brcmf_pcie_ring_mb_write_rptr,
1176                                              brcmf_pcie_ring_mb_write_wptr,
1177                                              ring);
1178                 ring->w_idx_addr = h2d_w_idx_ptr;
1179                 ring->r_idx_addr = h2d_r_idx_ptr;
1180                 h2d_w_idx_ptr += idx_offset;
1181                 h2d_r_idx_ptr += idx_offset;
1182         }
1183         devinfo->shared.flowrings = rings;
1184
1185         return 0;
1186
1187 fail:
1188         brcmf_err("Allocating ring buffers failed\n");
1189         brcmf_pcie_release_ringbuffers(devinfo);
1190         return -ENOMEM;
1191 }
1192
1193
1194 static void
1195 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1196 {
1197         if (devinfo->shared.scratch)
1198                 dma_free_coherent(&devinfo->pdev->dev,
1199                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1200                                   devinfo->shared.scratch,
1201                                   devinfo->shared.scratch_dmahandle);
1202         if (devinfo->shared.ringupd)
1203                 dma_free_coherent(&devinfo->pdev->dev,
1204                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1205                                   devinfo->shared.ringupd,
1206                                   devinfo->shared.ringupd_dmahandle);
1207 }
1208
1209 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1210 {
1211         u64 address;
1212         u32 addr;
1213
1214         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1215                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1216                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1217         if (!devinfo->shared.scratch)
1218                 goto fail;
1219
1220         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1221
1222         addr = devinfo->shared.tcm_base_address +
1223                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1224         address = (u64)devinfo->shared.scratch_dmahandle;
1225         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1226         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1227         addr = devinfo->shared.tcm_base_address +
1228                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1229         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1230
1231         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1232                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1233                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1234         if (!devinfo->shared.ringupd)
1235                 goto fail;
1236
1237         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1238
1239         addr = devinfo->shared.tcm_base_address +
1240                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1241         address = (u64)devinfo->shared.ringupd_dmahandle;
1242         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1243         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1244         addr = devinfo->shared.tcm_base_address +
1245                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1246         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1247         return 0;
1248
1249 fail:
1250         brcmf_err("Allocating scratch buffers failed\n");
1251         brcmf_pcie_release_scratchbuffers(devinfo);
1252         return -ENOMEM;
1253 }
1254
1255
1256 static void brcmf_pcie_down(struct device *dev)
1257 {
1258 }
1259
1260
1261 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1262 {
1263         return 0;
1264 }
1265
1266
1267 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1268                                 uint len)
1269 {
1270         return 0;
1271 }
1272
1273
1274 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1275                                 uint len)
1276 {
1277         return 0;
1278 }
1279
1280
1281 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1282 {
1283         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1284         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1285         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1286
1287         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1288         devinfo->wowl_enabled = enabled;
1289 }
1290
1291
1292 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1293 {
1294         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1295         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1296         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1297
1298         return devinfo->ci->ramsize - devinfo->ci->srsize;
1299 }
1300
1301
1302 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1303 {
1304         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1305         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1306         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1307
1308         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1309         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1310         return 0;
1311 }
1312
1313
1314 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1315         .txdata = brcmf_pcie_tx,
1316         .stop = brcmf_pcie_down,
1317         .txctl = brcmf_pcie_tx_ctlpkt,
1318         .rxctl = brcmf_pcie_rx_ctlpkt,
1319         .wowl_config = brcmf_pcie_wowl_config,
1320         .get_ramsize = brcmf_pcie_get_ramsize,
1321         .get_memdump = brcmf_pcie_get_memdump,
1322 };
1323
1324
1325 static void
1326 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1327                           u32 data_len)
1328 {
1329         __le32 *field;
1330         u32 newsize;
1331
1332         if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1333                 return;
1334
1335         field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1336         if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1337                 return;
1338         field++;
1339         newsize = le32_to_cpup(field);
1340
1341         brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1342                   newsize);
1343         devinfo->ci->ramsize = newsize;
1344 }
1345
1346
1347 static int
1348 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1349                                u32 sharedram_addr)
1350 {
1351         struct brcmf_pcie_shared_info *shared;
1352         u32 addr;
1353
1354         shared = &devinfo->shared;
1355         shared->tcm_base_address = sharedram_addr;
1356
1357         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1358         shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1359         brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1360         if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1361             (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1362                 brcmf_err("Unsupported PCIE version %d\n", shared->version);
1363                 return -EINVAL;
1364         }
1365
1366         /* check firmware support dma indicies */
1367         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1368                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1369                         devinfo->dma_idx_sz = sizeof(u16);
1370                 else
1371                         devinfo->dma_idx_sz = sizeof(u32);
1372         }
1373
1374         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1375         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1376         if (shared->max_rxbufpost == 0)
1377                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1378
1379         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1380         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1381
1382         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1383         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1384
1385         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1386         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1387
1388         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1389         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1390
1391         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1392                   shared->max_rxbufpost, shared->rx_dataoffset);
1393
1394         brcmf_pcie_bus_console_init(devinfo);
1395
1396         return 0;
1397 }
1398
1399
1400 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1401                                         const struct firmware *fw, void *nvram,
1402                                         u32 nvram_len)
1403 {
1404         u32 sharedram_addr;
1405         u32 sharedram_addr_written;
1406         u32 loop_counter;
1407         int err;
1408         u32 address;
1409         u32 resetintr;
1410
1411         brcmf_dbg(PCIE, "Halt ARM.\n");
1412         err = brcmf_pcie_enter_download_state(devinfo);
1413         if (err)
1414                 return err;
1415
1416         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1417         memcpy_toio(devinfo->tcm + devinfo->ci->rambase,
1418                     (void *)fw->data, fw->size);
1419
1420         resetintr = get_unaligned_le32(fw->data);
1421         release_firmware(fw);
1422
1423         /* reset last 4 bytes of RAM address. to be used for shared
1424          * area. This identifies when FW is running
1425          */
1426         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1427
1428         if (nvram) {
1429                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1430                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1431                           nvram_len;
1432                 memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
1433                 brcmf_fw_nvram_free(nvram);
1434         } else {
1435                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1436                           devinfo->nvram_name);
1437         }
1438
1439         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1440                                                        devinfo->ci->ramsize -
1441                                                        4);
1442         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1443         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1444         if (err)
1445                 return err;
1446
1447         brcmf_dbg(PCIE, "Wait for FW init\n");
1448         sharedram_addr = sharedram_addr_written;
1449         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1450         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1451                 msleep(50);
1452                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1453                                                        devinfo->ci->ramsize -
1454                                                        4);
1455                 loop_counter--;
1456         }
1457         if (sharedram_addr == sharedram_addr_written) {
1458                 brcmf_err("FW failed to initialize\n");
1459                 return -ENODEV;
1460         }
1461         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1462
1463         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1464 }
1465
1466
1467 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1468 {
1469         struct pci_dev *pdev;
1470         int err;
1471         phys_addr_t  bar0_addr, bar1_addr;
1472         ulong bar1_size;
1473
1474         pdev = devinfo->pdev;
1475
1476         err = pci_enable_device(pdev);
1477         if (err) {
1478                 brcmf_err("pci_enable_device failed err=%d\n", err);
1479                 return err;
1480         }
1481
1482         pci_set_master(pdev);
1483
1484         /* Bar-0 mapped address */
1485         bar0_addr = pci_resource_start(pdev, 0);
1486         /* Bar-1 mapped address */
1487         bar1_addr = pci_resource_start(pdev, 2);
1488         /* read Bar-1 mapped memory range */
1489         bar1_size = pci_resource_len(pdev, 2);
1490         if ((bar1_size == 0) || (bar1_addr == 0)) {
1491                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1492                           bar1_size, (unsigned long long)bar1_addr);
1493                 return -EINVAL;
1494         }
1495
1496         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1497         devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size);
1498
1499         if (!devinfo->regs || !devinfo->tcm) {
1500                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1501                           devinfo->tcm);
1502                 return -EINVAL;
1503         }
1504         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1505                   devinfo->regs, (unsigned long long)bar0_addr);
1506         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1507                   devinfo->tcm, (unsigned long long)bar1_addr,
1508                   (unsigned int)bar1_size);
1509
1510         return 0;
1511 }
1512
1513
1514 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1515 {
1516         if (devinfo->tcm)
1517                 iounmap(devinfo->tcm);
1518         if (devinfo->regs)
1519                 iounmap(devinfo->regs);
1520
1521         pci_disable_device(devinfo->pdev);
1522 }
1523
1524
1525 static int brcmf_pcie_attach_bus(struct brcmf_pciedev_info *devinfo)
1526 {
1527         int ret;
1528
1529         /* Attach to the common driver interface */
1530         ret = brcmf_attach(&devinfo->pdev->dev, devinfo->settings);
1531         if (ret) {
1532                 brcmf_err("brcmf_attach failed\n");
1533         } else {
1534                 ret = brcmf_bus_started(&devinfo->pdev->dev);
1535                 if (ret)
1536                         brcmf_err("dongle is not responding\n");
1537         }
1538
1539         return ret;
1540 }
1541
1542
1543 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1544 {
1545         u32 ret_addr;
1546
1547         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1548         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1549         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1550
1551         return ret_addr;
1552 }
1553
1554
1555 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1556 {
1557         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1558
1559         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1560         return brcmf_pcie_read_reg32(devinfo, addr);
1561 }
1562
1563
1564 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1565 {
1566         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1567
1568         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1569         brcmf_pcie_write_reg32(devinfo, addr, value);
1570 }
1571
1572
1573 static int brcmf_pcie_buscoreprep(void *ctx)
1574 {
1575         return brcmf_pcie_get_resource(ctx);
1576 }
1577
1578
1579 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1580 {
1581         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1582         u32 val;
1583
1584         devinfo->ci = chip;
1585         brcmf_pcie_reset_device(devinfo);
1586
1587         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1588         if (val != 0xffffffff)
1589                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1590                                        val);
1591
1592         return 0;
1593 }
1594
1595
1596 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1597                                         u32 rstvec)
1598 {
1599         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1600
1601         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1602 }
1603
1604
1605 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1606         .prepare = brcmf_pcie_buscoreprep,
1607         .reset = brcmf_pcie_buscore_reset,
1608         .activate = brcmf_pcie_buscore_activate,
1609         .read32 = brcmf_pcie_buscore_read32,
1610         .write32 = brcmf_pcie_buscore_write32,
1611 };
1612
1613 static void brcmf_pcie_setup(struct device *dev, int ret,
1614                              const struct firmware *fw,
1615                              void *nvram, u32 nvram_len)
1616 {
1617         struct brcmf_bus *bus;
1618         struct brcmf_pciedev *pcie_bus_dev;
1619         struct brcmf_pciedev_info *devinfo;
1620         struct brcmf_commonring **flowrings;
1621         u32 i;
1622
1623         /* check firmware loading result */
1624         if (ret)
1625                 goto fail;
1626
1627         bus = dev_get_drvdata(dev);
1628         pcie_bus_dev = bus->bus_priv.pcie;
1629         devinfo = pcie_bus_dev->devinfo;
1630         brcmf_pcie_attach(devinfo);
1631
1632         /* Some of the firmwares have the size of the memory of the device
1633          * defined inside the firmware. This is because part of the memory in
1634          * the device is shared and the devision is determined by FW. Parse
1635          * the firmware and adjust the chip memory size now.
1636          */
1637         brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
1638
1639         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1640         if (ret)
1641                 goto fail;
1642
1643         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1644
1645         ret = brcmf_pcie_init_ringbuffers(devinfo);
1646         if (ret)
1647                 goto fail;
1648
1649         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1650         if (ret)
1651                 goto fail;
1652
1653         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1654         ret = brcmf_pcie_request_irq(devinfo);
1655         if (ret)
1656                 goto fail;
1657
1658         /* hook the commonrings in the bus structure. */
1659         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1660                 bus->msgbuf->commonrings[i] =
1661                                 &devinfo->shared.commonrings[i]->commonring;
1662
1663         flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
1664                             GFP_KERNEL);
1665         if (!flowrings)
1666                 goto fail;
1667
1668         for (i = 0; i < devinfo->shared.max_flowrings; i++)
1669                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1670         bus->msgbuf->flowrings = flowrings;
1671
1672         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1673         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1674         bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
1675
1676         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1677
1678         brcmf_pcie_intr_enable(devinfo);
1679         if (brcmf_pcie_attach_bus(devinfo) == 0)
1680                 return;
1681
1682         brcmf_pcie_bus_console_read(devinfo);
1683
1684 fail:
1685         device_release_driver(dev);
1686 }
1687
1688 static int
1689 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1690 {
1691         int ret;
1692         struct brcmf_pciedev_info *devinfo;
1693         struct brcmf_pciedev *pcie_bus_dev;
1694         struct brcmf_bus *bus;
1695         u16 domain_nr;
1696         u16 bus_nr;
1697
1698         domain_nr = pci_domain_nr(pdev->bus) + 1;
1699         bus_nr = pdev->bus->number;
1700         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1701                   domain_nr, bus_nr);
1702
1703         ret = -ENOMEM;
1704         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1705         if (devinfo == NULL)
1706                 return ret;
1707
1708         devinfo->pdev = pdev;
1709         pcie_bus_dev = NULL;
1710         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1711         if (IS_ERR(devinfo->ci)) {
1712                 ret = PTR_ERR(devinfo->ci);
1713                 devinfo->ci = NULL;
1714                 goto fail;
1715         }
1716
1717         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1718         if (pcie_bus_dev == NULL) {
1719                 ret = -ENOMEM;
1720                 goto fail;
1721         }
1722
1723         devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
1724                                                    BRCMF_BUSTYPE_PCIE,
1725                                                    devinfo->ci->chip,
1726                                                    devinfo->ci->chiprev);
1727         if (!devinfo->settings) {
1728                 ret = -ENOMEM;
1729                 goto fail;
1730         }
1731
1732         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1733         if (!bus) {
1734                 ret = -ENOMEM;
1735                 goto fail;
1736         }
1737         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1738         if (!bus->msgbuf) {
1739                 ret = -ENOMEM;
1740                 kfree(bus);
1741                 goto fail;
1742         }
1743
1744         /* hook it all together. */
1745         pcie_bus_dev->devinfo = devinfo;
1746         pcie_bus_dev->bus = bus;
1747         bus->dev = &pdev->dev;
1748         bus->bus_priv.pcie = pcie_bus_dev;
1749         bus->ops = &brcmf_pcie_bus_ops;
1750         bus->proto_type = BRCMF_PROTO_MSGBUF;
1751         bus->chip = devinfo->coreid;
1752         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1753         dev_set_drvdata(&pdev->dev, bus);
1754
1755         ret = brcmf_fw_map_chip_to_name(devinfo->ci->chip, devinfo->ci->chiprev,
1756                                         brcmf_pcie_fwnames,
1757                                         ARRAY_SIZE(brcmf_pcie_fwnames),
1758                                         devinfo->fw_name, devinfo->nvram_name);
1759         if (ret)
1760                 goto fail_bus;
1761
1762         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1763                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1764                                           devinfo->fw_name, devinfo->nvram_name,
1765                                           brcmf_pcie_setup, domain_nr, bus_nr);
1766         if (ret == 0)
1767                 return 0;
1768 fail_bus:
1769         kfree(bus->msgbuf);
1770         kfree(bus);
1771 fail:
1772         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1773         brcmf_pcie_release_resource(devinfo);
1774         if (devinfo->ci)
1775                 brcmf_chip_detach(devinfo->ci);
1776         if (devinfo->settings)
1777                 brcmf_release_module_param(devinfo->settings);
1778         kfree(pcie_bus_dev);
1779         kfree(devinfo);
1780         return ret;
1781 }
1782
1783
1784 static void
1785 brcmf_pcie_remove(struct pci_dev *pdev)
1786 {
1787         struct brcmf_pciedev_info *devinfo;
1788         struct brcmf_bus *bus;
1789
1790         brcmf_dbg(PCIE, "Enter\n");
1791
1792         bus = dev_get_drvdata(&pdev->dev);
1793         if (bus == NULL)
1794                 return;
1795
1796         devinfo = bus->bus_priv.pcie->devinfo;
1797
1798         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1799         if (devinfo->ci)
1800                 brcmf_pcie_intr_disable(devinfo);
1801
1802         brcmf_detach(&pdev->dev);
1803
1804         kfree(bus->bus_priv.pcie);
1805         kfree(bus->msgbuf->flowrings);
1806         kfree(bus->msgbuf);
1807         kfree(bus);
1808
1809         brcmf_pcie_release_irq(devinfo);
1810         brcmf_pcie_release_scratchbuffers(devinfo);
1811         brcmf_pcie_release_ringbuffers(devinfo);
1812         brcmf_pcie_reset_device(devinfo);
1813         brcmf_pcie_release_resource(devinfo);
1814
1815         if (devinfo->ci)
1816                 brcmf_chip_detach(devinfo->ci);
1817         if (devinfo->settings)
1818                 brcmf_release_module_param(devinfo->settings);
1819
1820         kfree(devinfo);
1821         dev_set_drvdata(&pdev->dev, NULL);
1822 }
1823
1824
1825 #ifdef CONFIG_PM
1826
1827
1828 static int brcmf_pcie_pm_enter_D3(struct device *dev)
1829 {
1830         struct brcmf_pciedev_info *devinfo;
1831         struct brcmf_bus *bus;
1832
1833         brcmf_dbg(PCIE, "Enter\n");
1834
1835         bus = dev_get_drvdata(dev);
1836         devinfo = bus->bus_priv.pcie->devinfo;
1837
1838         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1839
1840         devinfo->mbdata_completed = false;
1841         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1842
1843         wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
1844                            BRCMF_PCIE_MBDATA_TIMEOUT);
1845         if (!devinfo->mbdata_completed) {
1846                 brcmf_err("Timeout on response for entering D3 substate\n");
1847                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1848                 return -EIO;
1849         }
1850
1851         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1852
1853         return 0;
1854 }
1855
1856
1857 static int brcmf_pcie_pm_leave_D3(struct device *dev)
1858 {
1859         struct brcmf_pciedev_info *devinfo;
1860         struct brcmf_bus *bus;
1861         struct pci_dev *pdev;
1862         int err;
1863
1864         brcmf_dbg(PCIE, "Enter\n");
1865
1866         bus = dev_get_drvdata(dev);
1867         devinfo = bus->bus_priv.pcie->devinfo;
1868         brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
1869
1870         /* Check if device is still up and running, if so we are ready */
1871         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1872                 brcmf_dbg(PCIE, "Try to wakeup device....\n");
1873                 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
1874                         goto cleanup;
1875                 brcmf_dbg(PCIE, "Hot resume, continue....\n");
1876                 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1877                 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1878                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1879                 brcmf_pcie_intr_enable(devinfo);
1880                 return 0;
1881         }
1882
1883 cleanup:
1884         brcmf_chip_detach(devinfo->ci);
1885         devinfo->ci = NULL;
1886         pdev = devinfo->pdev;
1887         brcmf_pcie_remove(pdev);
1888
1889         err = brcmf_pcie_probe(pdev, NULL);
1890         if (err)
1891                 brcmf_err("probe after resume failed, err=%d\n", err);
1892
1893         return err;
1894 }
1895
1896
1897 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
1898         .suspend = brcmf_pcie_pm_enter_D3,
1899         .resume = brcmf_pcie_pm_leave_D3,
1900         .freeze = brcmf_pcie_pm_enter_D3,
1901         .restore = brcmf_pcie_pm_leave_D3,
1902 };
1903
1904
1905 #endif /* CONFIG_PM */
1906
1907
1908 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1909         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1910 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev)  { \
1911         BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1912         subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1913
1914 static const struct pci_device_id brcmf_pcie_devid_table[] = {
1915         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
1916         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1917         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1918         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1919         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
1920         BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
1921         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1922         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1923         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1924         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
1925         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
1926         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
1927         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
1928         BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365),
1929         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
1930         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
1931         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
1932         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
1933         { /* end: all zeroes */ }
1934 };
1935
1936
1937 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1938
1939
1940 static struct pci_driver brcmf_pciedrvr = {
1941         .node = {},
1942         .name = KBUILD_MODNAME,
1943         .id_table = brcmf_pcie_devid_table,
1944         .probe = brcmf_pcie_probe,
1945         .remove = brcmf_pcie_remove,
1946 #ifdef CONFIG_PM
1947         .driver.pm = &brcmf_pciedrvr_pm,
1948 #endif
1949 };
1950
1951
1952 void brcmf_pcie_register(void)
1953 {
1954         int err;
1955
1956         brcmf_dbg(PCIE, "Enter\n");
1957         err = pci_register_driver(&brcmf_pciedrvr);
1958         if (err)
1959                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1960 }
1961
1962
1963 void brcmf_pcie_exit(void)
1964 {
1965         brcmf_dbg(PCIE, "Enter\n");
1966         pci_unregister_driver(&brcmf_pciedrvr);
1967 }