drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <linux/io.h>
  26 #include <asm/unaligned.h>
  27
  28 #include <soc.h>
  29 #include <chipcommon.h>
  30 #include <brcmu_utils.h>
  31 #include <brcmu_wifi.h>
  32 #include <brcm_hw_ids.h>
  33
  34 #include "debug.h"
  35 #include "bus.h"
  36 #include "commonring.h"
  37 #include "msgbuf.h"
  38 #include "pcie.h"
  39 #include "firmware.h"
  40 #include "chip.h"
  41 #include "core.h"
  42 #include "common.h"
  43
  44
  45 enum brcmf_pcie_state {
  46         BRCMFMAC_PCIE_STATE_DOWN,
  47         BRCMFMAC_PCIE_STATE_UP
  48 };
  49
  50 BRCMF_FW_DEF(43602, "/*(DEBLOBBED)*/");
  51 BRCMF_FW_DEF(4350, "/*(DEBLOBBED)*/");
  52 BRCMF_FW_DEF(4350C, "/*(DEBLOBBED)*/");
  53 BRCMF_FW_DEF(4356, "/*(DEBLOBBED)*/");
  54 BRCMF_FW_DEF(43570, "/*(DEBLOBBED)*/");
  55 BRCMF_FW_DEF(4358, "/*(DEBLOBBED)*/");
  56 BRCMF_FW_DEF(4359, "/*(DEBLOBBED)*/");
  57 BRCMF_FW_DEF(4365B, "/*(DEBLOBBED)*/");
  58 BRCMF_FW_DEF(4365C, "/*(DEBLOBBED)*/");
  59 BRCMF_FW_DEF(4366B, "/*(DEBLOBBED)*/");
  60 BRCMF_FW_DEF(4366C, "/*(DEBLOBBED)*/");
  61 BRCMF_FW_DEF(4371, "/*(DEBLOBBED)*/");
  62
  63 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
  64         BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
  65         BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
  66         BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
  67         BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
  68         BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
  69         BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
  70         BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
  71         BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
  72         BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
  73         BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
  74         BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
  75         BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
  76         BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
  77         BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
  78         BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
  79         BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
  80         BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
  81 };
  82
  83 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  84
  85 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  86
  87 /* backplane addres space accessed by BAR0 */
  88 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  89 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  90 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  91
  92 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  93 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  94
  95 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  96 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  97
  98 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  99 #define BRCMF_PCIE_REG_INTMASK                  0x94
 100 #define BRCMF_PCIE_REG_SBMBX                    0x98
 101
 102 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
 103
 104 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
 105 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
 106 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
 107 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
 108 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
 109 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0       0x140
 110 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1       0x144
 111
 112 #define BRCMF_PCIE2_INTA                        0x01
 113 #define BRCMF_PCIE2_INTB                        0x02
 114
 115 #define BRCMF_PCIE_INT_0                        0x01
 116 #define BRCMF_PCIE_INT_1                        0x02
 117 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 118                                                  BRCMF_PCIE_INT_1)
 119
 120 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 121 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 122 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 123 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 124 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 125 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 126 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 127 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 128 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 129 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 130
 131 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 132                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 133                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 134                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 135                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 136                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 137                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 138                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 139
 140 #define BRCMF_PCIE_SHARED_VERSION_7             7
 141 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 142 #define BRCMF_PCIE_MAX_SHARED_VERSION           BRCMF_PCIE_SHARED_VERSION_7
 143 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 144 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 145 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 146 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1           0x10000000
 147
 148 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 149 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 150
 151 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 152 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 153 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 154 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 155 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 156 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 157 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 158 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 159 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 160 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 161 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 162
 163 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 164 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 165 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 166 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 167
 168 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 169 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 170 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 171 #define BRCMF_RING_MEM_SZ                       16
 172 #define BRCMF_RING_STATE_SZ                     8
 173
 174 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 175
 176 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 177 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 178 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 179
 180 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 181 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 182
 183 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 184 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 185 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 186 #define BRCMF_D2H_DEV_FWHALT                    0x10000000
 187
 188 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 189 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 190 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 191 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 192
 193 #define BRCMF_PCIE_MBDATA_TIMEOUT               msecs_to_jiffies(2000)
 194
 195 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 196 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 197 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 198 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 199 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 200 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 201 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 202 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 203 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 204 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 205 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 206 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 207 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 208
 209 /* Magic number at a magic location to find RAM size */
 210 #define BRCMF_RAMSIZE_MAGIC                     0x534d4152      /* SMAR */
 211 #define BRCMF_RAMSIZE_OFFSET                    0x6c
 212
 213
 214 struct brcmf_pcie_console {
 215         u32 base_addr;
 216         u32 buf_addr;
 217         u32 bufsize;
 218         u32 read_idx;
 219         u8 log_str[256];
 220         u8 log_idx;
 221 };
 222
 223 struct brcmf_pcie_shared_info {
 224         u32 tcm_base_address;
 225         u32 flags;
 226         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 227         struct brcmf_pcie_ringbuf *flowrings;
 228         u16 max_rxbufpost;
 229         u16 max_flowrings;
 230         u16 max_submissionrings;
 231         u16 max_completionrings;
 232         u32 rx_dataoffset;
 233         u32 htod_mb_data_addr;
 234         u32 dtoh_mb_data_addr;
 235         u32 ring_info_addr;
 236         struct brcmf_pcie_console console;
 237         void *scratch;
 238         dma_addr_t scratch_dmahandle;
 239         void *ringupd;
 240         dma_addr_t ringupd_dmahandle;
 241         u8 version;
 242 };
 243
 244 struct brcmf_pcie_core_info {
 245         u32 base;
 246         u32 wrapbase;
 247 };
 248
 249 struct brcmf_pciedev_info {
 250         enum brcmf_pcie_state state;
 251         bool in_irq;
 252         struct pci_dev *pdev;
 253         char fw_name[BRCMF_FW_NAME_LEN];
 254         char nvram_name[BRCMF_FW_NAME_LEN];
 255         void __iomem *regs;
 256         void __iomem *tcm;
 257         u32 ram_base;
 258         u32 ram_size;
 259         struct brcmf_chip *ci;
 260         u32 coreid;
 261         struct brcmf_pcie_shared_info shared;
 262         wait_queue_head_t mbdata_resp_wait;
 263         bool mbdata_completed;
 264         bool irq_allocated;
 265         bool wowl_enabled;
 266         u8 dma_idx_sz;
 267         void *idxbuf;
 268         u32 idxbuf_sz;
 269         dma_addr_t idxbuf_dmahandle;
 270         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 271         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 272                           u16 value);
 273         struct brcmf_mp_device *settings;
 274 };
 275
 276 struct brcmf_pcie_ringbuf {
 277         struct brcmf_commonring commonring;
 278         dma_addr_t dma_handle;
 279         u32 w_idx_addr;
 280         u32 r_idx_addr;
 281         struct brcmf_pciedev_info *devinfo;
 282         u8 id;
 283 };
 284
 285 /**
 286  * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
 287  *
 288  * @ringmem: dongle memory pointer to ring memory location
 289  * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
 290  * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
 291  * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
 292  * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
 293  * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
 294  * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
 295  * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
 296  * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
 297  * @max_flowrings: maximum number of tx flow rings supported.
 298  * @max_submissionrings: maximum number of submission rings(h2d) supported.
 299  * @max_completionrings: maximum number of completion rings(d2h) supported.
 300  */
 301 struct brcmf_pcie_dhi_ringinfo {
 302         __le32                  ringmem;
 303         __le32                  h2d_w_idx_ptr;
 304         __le32                  h2d_r_idx_ptr;
 305         __le32                  d2h_w_idx_ptr;
 306         __le32                  d2h_r_idx_ptr;
 307         struct msgbuf_buf_addr  h2d_w_idx_hostaddr;
 308         struct msgbuf_buf_addr  h2d_r_idx_hostaddr;
 309         struct msgbuf_buf_addr  d2h_w_idx_hostaddr;
 310         struct msgbuf_buf_addr  d2h_r_idx_hostaddr;
 311         __le16                  max_flowrings;
 312         __le16                  max_submissionrings;
 313         __le16                  max_completionrings;
 314 };
 315
 316 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 317         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 318         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 319         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 320         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 321         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 322 };
 323
 324 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
 325         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 326         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 327         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 328         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
 329         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
 330 };
 331
 332 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 333         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 334         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 335         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 336         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 337         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 338 };
 339
 340
 341 static u32
 342 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 343 {
 344         void __iomem *address = devinfo->regs + reg_offset;
 345
 346         return (ioread32(address));
 347 }
 348
 349
 350 static void
 351 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 352                        u32 value)
 353 {
 354         void __iomem *address = devinfo->regs + reg_offset;
 355
 356         iowrite32(value, address);
 357 }
 358
 359
 360 static u8
 361 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 362 {
 363         void __iomem *address = devinfo->tcm + mem_offset;
 364
 365         return (ioread8(address));
 366 }
 367
 368
 369 static u16
 370 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 371 {
 372         void __iomem *address = devinfo->tcm + mem_offset;
 373
 374         return (ioread16(address));
 375 }
 376
 377
 378 static void
 379 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 380                        u16 value)
 381 {
 382         void __iomem *address = devinfo->tcm + mem_offset;
 383
 384         iowrite16(value, address);
 385 }
 386
 387
 388 static u16
 389 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 390 {
 391         u16 *address = devinfo->idxbuf + mem_offset;
 392
 393         return (*(address));
 394 }
 395
 396
 397 static void
 398 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 399                      u16 value)
 400 {
 401         u16 *address = devinfo->idxbuf + mem_offset;
 402
 403         *(address) = value;
 404 }
 405
 406
 407 static u32
 408 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 409 {
 410         void __iomem *address = devinfo->tcm + mem_offset;
 411
 412         return (ioread32(address));
 413 }
 414
 415
 416 static void
 417 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 418                        u32 value)
 419 {
 420         void __iomem *address = devinfo->tcm + mem_offset;
 421
 422         iowrite32(value, address);
 423 }
 424
 425
 426 static u32
 427 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 428 {
 429         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 430
 431         return (ioread32(addr));
 432 }
 433
 434
 435 static void
 436 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 437                        u32 value)
 438 {
 439         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 440
 441         iowrite32(value, addr);
 442 }
 443
 444
 445 static void
 446 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 447                           void *dstaddr, u32 len)
 448 {
 449         void __iomem *address = devinfo->tcm + mem_offset;
 450         __le32 *dst32;
 451         __le16 *dst16;
 452         u8 *dst8;
 453
 454         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 455                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 456                         dst8 = (u8 *)dstaddr;
 457                         while (len) {
 458                                 *dst8 = ioread8(address);
 459                                 address++;
 460                                 dst8++;
 461                                 len--;
 462                         }
 463                 } else {
 464                         len = len / 2;
 465                         dst16 = (__le16 *)dstaddr;
 466                         while (len) {
 467                                 *dst16 = cpu_to_le16(ioread16(address));
 468                                 address += 2;
 469                                 dst16++;
 470                                 len--;
 471                         }
 472                 }
 473         } else {
 474                 len = len / 4;
 475                 dst32 = (__le32 *)dstaddr;
 476                 while (len) {
 477                         *dst32 = cpu_to_le32(ioread32(address));
 478                         address += 4;
 479                         dst32++;
 480                         len--;
 481                 }
 482         }
 483 }
 484
 485
 486 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 487                 CHIPCREGOFFS(reg), value)
 488
 489
 490 static void
 491 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 492 {
 493         const struct pci_dev *pdev = devinfo->pdev;
 494         struct brcmf_core *core;
 495         u32 bar0_win;
 496
 497         core = brcmf_chip_get_core(devinfo->ci, coreid);
 498         if (core) {
 499                 bar0_win = core->base;
 500                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 501                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 502                                           &bar0_win) == 0) {
 503                         if (bar0_win != core->base) {
 504                                 bar0_win = core->base;
 505                                 pci_write_config_dword(pdev,
 506                                                        BRCMF_PCIE_BAR0_WINDOW,
 507                                                        bar0_win);
 508                         }
 509                 }
 510         } else {
 511                 brcmf_err("Unsupported core selected %x\n", coreid);
 512         }
 513 }
 514
 515
 516 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 517 {
 518         struct brcmf_core *core;
 519         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 520                              BRCMF_PCIE_CFGREG_PM_CSR,
 521                              BRCMF_PCIE_CFGREG_MSI_CAP,
 522                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 523                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 524                              BRCMF_PCIE_CFGREG_MSI_DATA,
 525                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 526                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 527                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 528                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 529                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 530         u32 i;
 531         u32 val;
 532         u32 lsc;
 533
 534         if (!devinfo->ci)
 535                 return;
 536
 537         /* Disable ASPM */
 538         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 539         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 540                               &lsc);
 541         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 542         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 543                                val);
 544
 545         /* Watchdog reset */
 546         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 547         WRITECC32(devinfo, watchdog, 4);
 548         msleep(100);
 549
 550         /* Restore ASPM */
 551         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 552         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 553                                lsc);
 554
 555         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 556         if (core->rev <= 13) {
 557                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 558                         brcmf_pcie_write_reg32(devinfo,
 559                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 560                                                cfg_offset[i]);
 561                         val = brcmf_pcie_read_reg32(devinfo,
 562                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 563                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 564                                   cfg_offset[i], val);
 565                         brcmf_pcie_write_reg32(devinfo,
 566                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 567                                                val);
 568                 }
 569         }
 570 }
 571
 572
 573 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 574 {
 575         u32 config;
 576
 577         /* BAR1 window may not be sized properly */
 578         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 579         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 580         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 581         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 582
 583         device_wakeup_enable(&devinfo->pdev->dev);
 584 }
 585
 586
 587 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 588 {
 589         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 590                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 591                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 592                                        5);
 593                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 594                                        0);
 595                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 596                                        7);
 597                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 598                                        0);
 599         }
 600         return 0;
 601 }
 602
 603
 604 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 605                                           u32 resetintr)
 606 {
 607         struct brcmf_core *core;
 608
 609         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 610                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 611                 brcmf_chip_resetcore(core, 0, 0, 0);
 612         }
 613
 614         if (!brcmf_chip_set_active(devinfo->ci, resetintr))
 615                 return -EIO;
 616         return 0;
 617 }
 618
 619
 620 static int
 621 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 622 {
 623         struct brcmf_pcie_shared_info *shared;
 624         u32 addr;
 625         u32 cur_htod_mb_data;
 626         u32 i;
 627
 628         shared = &devinfo->shared;
 629         addr = shared->htod_mb_data_addr;
 630         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 631
 632         if (cur_htod_mb_data != 0)
 633                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 634                           cur_htod_mb_data);
 635
 636         i = 0;
 637         while (cur_htod_mb_data != 0) {
 638                 msleep(10);
 639                 i++;
 640                 if (i > 100)
 641                         return -EIO;
 642                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 643         }
 644
 645         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 646         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 647         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 648
 649         return 0;
 650 }
 651
 652
 653 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 654 {
 655         struct brcmf_pcie_shared_info *shared;
 656         u32 addr;
 657         u32 dtoh_mb_data;
 658
 659         shared = &devinfo->shared;
 660         addr = shared->dtoh_mb_data_addr;
 661         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 662
 663         if (!dtoh_mb_data)
 664                 return;
 665
 666         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 667
 668         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 669         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 670                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 671                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 672                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 673         }
 674         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 675                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 676         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 677                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 678                 devinfo->mbdata_completed = true;
 679                 wake_up(&devinfo->mbdata_resp_wait);
 680         }
 681         if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) {
 682                 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
 683                 brcmf_dev_coredump(&devinfo->pdev->dev);
 684         }
 685 }
 686
 687
 688 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 689 {
 690         struct brcmf_pcie_shared_info *shared;
 691         struct brcmf_pcie_console *console;
 692         u32 addr;
 693
 694         shared = &devinfo->shared;
 695         console = &shared->console;
 696         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 697         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 698
 699         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 700         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 701         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 702         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 703
 704         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 705                   console->base_addr, console->buf_addr, console->bufsize);
 706 }
 707
 708
 709 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 710 {
 711         struct brcmf_pcie_console *console;
 712         u32 addr;
 713         u8 ch;
 714         u32 newidx;
 715
 716         if (!BRCMF_FWCON_ON())
 717                 return;
 718
 719         console = &devinfo->shared.console;
 720         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 721         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 722         while (newidx != console->read_idx) {
 723                 addr = console->buf_addr + console->read_idx;
 724                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 725                 console->read_idx++;
 726                 if (console->read_idx == console->bufsize)
 727                         console->read_idx = 0;
 728                 if (ch == '\r')
 729                         continue;
 730                 console->log_str[console->log_idx] = ch;
 731                 console->log_idx++;
 732                 if ((ch != '\n') &&
 733                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 734                         ch = '\n';
 735                         console->log_str[console->log_idx] = ch;
 736                         console->log_idx++;
 737                 }
 738                 if (ch == '\n') {
 739                         console->log_str[console->log_idx] = 0;
 740                         pr_debug("CONSOLE: %s", console->log_str);
 741                         console->log_idx = 0;
 742                 }
 743         }
 744 }
 745
 746
 747 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 748 {
 749         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
 750 }
 751
 752
 753 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 754 {
 755         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 756                                BRCMF_PCIE_MB_INT_D2H_DB |
 757                                BRCMF_PCIE_MB_INT_FN0_0 |
 758                                BRCMF_PCIE_MB_INT_FN0_1);
 759 }
 760
 761 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
 762 {
 763         if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
 764                 brcmf_pcie_write_reg32(devinfo,
 765                                        BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 1);
 766 }
 767
 768 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
 769 {
 770         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 771
 772         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 773                 brcmf_pcie_intr_disable(devinfo);
 774                 brcmf_dbg(PCIE, "Enter\n");
 775                 return IRQ_WAKE_THREAD;
 776         }
 777         return IRQ_NONE;
 778 }
 779
 780
 781 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
 782 {
 783         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 784         u32 status;
 785
 786         devinfo->in_irq = true;
 787         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 788         brcmf_dbg(PCIE, "Enter %x\n", status);
 789         if (status) {
 790                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 791                                        status);
 792                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 793                               BRCMF_PCIE_MB_INT_FN0_1))
 794                         brcmf_pcie_handle_mb_data(devinfo);
 795                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 796                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 797                                 brcmf_proto_msgbuf_rx_trigger(
 798                                                         &devinfo->pdev->dev);
 799                 }
 800         }
 801         brcmf_pcie_bus_console_read(devinfo);
 802         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 803                 brcmf_pcie_intr_enable(devinfo);
 804         devinfo->in_irq = false;
 805         return IRQ_HANDLED;
 806 }
 807
 808
 809 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 810 {
 811         struct pci_dev *pdev;
 812
 813         pdev = devinfo->pdev;
 814
 815         brcmf_pcie_intr_disable(devinfo);
 816
 817         brcmf_dbg(PCIE, "Enter\n");
 818
 819         pci_enable_msi(pdev);
 820         if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
 821                                  brcmf_pcie_isr_thread, IRQF_SHARED,
 822                                  "brcmf_pcie_intr", devinfo)) {
 823                 pci_disable_msi(pdev);
 824                 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 825                 return -EIO;
 826         }
 827         devinfo->irq_allocated = true;
 828         return 0;
 829 }
 830
 831
 832 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 833 {
 834         struct pci_dev *pdev;
 835         u32 status;
 836         u32 count;
 837
 838         if (!devinfo->irq_allocated)
 839                 return;
 840
 841         pdev = devinfo->pdev;
 842
 843         brcmf_pcie_intr_disable(devinfo);
 844         free_irq(pdev->irq, devinfo);
 845         pci_disable_msi(pdev);
 846
 847         msleep(50);
 848         count = 0;
 849         while ((devinfo->in_irq) && (count < 20)) {
 850                 msleep(50);
 851                 count++;
 852         }
 853         if (devinfo->in_irq)
 854                 brcmf_err("Still in IRQ (processing) !!!\n");
 855
 856         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 857         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
 858
 859         devinfo->irq_allocated = false;
 860 }
 861
 862
 863 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 864 {
 865         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 866         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 867         struct brcmf_commonring *commonring = &ring->commonring;
 868
 869         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 870                 return -EIO;
 871
 872         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 873                   commonring->w_ptr, ring->id);
 874
 875         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 876
 877         return 0;
 878 }
 879
 880
 881 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 882 {
 883         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 884         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 885         struct brcmf_commonring *commonring = &ring->commonring;
 886
 887         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 888                 return -EIO;
 889
 890         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 891                   commonring->r_ptr, ring->id);
 892
 893         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 894
 895         return 0;
 896 }
 897
 898
 899 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 900 {
 901         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 902         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 903
 904         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 905                 return -EIO;
 906
 907         brcmf_dbg(PCIE, "RING !\n");
 908         /* Any arbitrary value will do, lets use 1 */
 909         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 1);
 910
 911         return 0;
 912 }
 913
 914
 915 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 916 {
 917         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 918         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 919         struct brcmf_commonring *commonring = &ring->commonring;
 920
 921         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 922                 return -EIO;
 923
 924         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
 925
 926         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 927                   commonring->w_ptr, ring->id);
 928
 929         return 0;
 930 }
 931
 932
 933 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 934 {
 935         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 936         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 937         struct brcmf_commonring *commonring = &ring->commonring;
 938
 939         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 940                 return -EIO;
 941
 942         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
 943
 944         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 945                   commonring->r_ptr, ring->id);
 946
 947         return 0;
 948 }
 949
 950
 951 static void *
 952 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
 953                                      u32 size, u32 tcm_dma_phys_addr,
 954                                      dma_addr_t *dma_handle)
 955 {
 956         void *ring;
 957         u64 address;
 958
 959         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
 960                                   GFP_KERNEL);
 961         if (!ring)
 962                 return NULL;
 963
 964         address = (u64)*dma_handle;
 965         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
 966                                address & 0xffffffff);
 967         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
 968
 969         memset(ring, 0, size);
 970
 971         return (ring);
 972 }
 973
 974
 975 static struct brcmf_pcie_ringbuf *
 976 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
 977                               u32 tcm_ring_phys_addr)
 978 {
 979         void *dma_buf;
 980         dma_addr_t dma_handle;
 981         struct brcmf_pcie_ringbuf *ring;
 982         u32 size;
 983         u32 addr;
 984         const u32 *ring_itemsize_array;
 985
 986         if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7)
 987                 ring_itemsize_array = brcmf_ring_itemsize_pre_v7;
 988         else
 989                 ring_itemsize_array = brcmf_ring_itemsize;
 990
 991         size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id];
 992         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
 993                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
 994                         &dma_handle);
 995         if (!dma_buf)
 996                 return NULL;
 997
 998         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
 999         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1000         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1001         brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]);
1002
1003         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1004         if (!ring) {
1005                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1006                                   dma_handle);
1007                 return NULL;
1008         }
1009         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1010                                 ring_itemsize_array[ring_id], dma_buf);
1011         ring->dma_handle = dma_handle;
1012         ring->devinfo = devinfo;
1013         brcmf_commonring_register_cb(&ring->commonring,
1014                                      brcmf_pcie_ring_mb_ring_bell,
1015                                      brcmf_pcie_ring_mb_update_rptr,
1016                                      brcmf_pcie_ring_mb_update_wptr,
1017                                      brcmf_pcie_ring_mb_write_rptr,
1018                                      brcmf_pcie_ring_mb_write_wptr, ring);
1019
1020         return (ring);
1021 }
1022
1023
1024 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1025                                           struct brcmf_pcie_ringbuf *ring)
1026 {
1027         void *dma_buf;
1028         u32 size;
1029
1030         if (!ring)
1031                 return;
1032
1033         dma_buf = ring->commonring.buf_addr;
1034         if (dma_buf) {
1035                 size = ring->commonring.depth * ring->commonring.item_len;
1036                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1037         }
1038         kfree(ring);
1039 }
1040
1041
1042 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1043 {
1044         u32 i;
1045
1046         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1047                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1048                                               devinfo->shared.commonrings[i]);
1049                 devinfo->shared.commonrings[i] = NULL;
1050         }
1051         kfree(devinfo->shared.flowrings);
1052         devinfo->shared.flowrings = NULL;
1053         if (devinfo->idxbuf) {
1054                 dma_free_coherent(&devinfo->pdev->dev,
1055                                   devinfo->idxbuf_sz,
1056                                   devinfo->idxbuf,
1057                                   devinfo->idxbuf_dmahandle);
1058                 devinfo->idxbuf = NULL;
1059         }
1060 }
1061
1062
1063 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1064 {
1065         struct brcmf_pcie_ringbuf *ring;
1066         struct brcmf_pcie_ringbuf *rings;
1067         u32 d2h_w_idx_ptr;
1068         u32 d2h_r_idx_ptr;
1069         u32 h2d_w_idx_ptr;
1070         u32 h2d_r_idx_ptr;
1071         u32 ring_mem_ptr;
1072         u32 i;
1073         u64 address;
1074         u32 bufsz;
1075         u8 idx_offset;
1076         struct brcmf_pcie_dhi_ringinfo ringinfo;
1077         u16 max_flowrings;
1078         u16 max_submissionrings;
1079         u16 max_completionrings;
1080
1081         memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1082                       sizeof(ringinfo));
1083         if (devinfo->shared.version >= 6) {
1084                 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1085                 max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1086                 max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1087         } else {
1088                 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1089                 max_flowrings = max_submissionrings -
1090                                 BRCMF_NROF_H2D_COMMON_MSGRINGS;
1091                 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1092         }
1093
1094         if (devinfo->dma_idx_sz != 0) {
1095                 bufsz = (max_submissionrings + max_completionrings) *
1096                         devinfo->dma_idx_sz * 2;
1097                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1098                                                      &devinfo->idxbuf_dmahandle,
1099                                                      GFP_KERNEL);
1100                 if (!devinfo->idxbuf)
1101                         devinfo->dma_idx_sz = 0;
1102         }
1103
1104         if (devinfo->dma_idx_sz == 0) {
1105                 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1106                 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1107                 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1108                 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1109                 idx_offset = sizeof(u32);
1110                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1111                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1112                 brcmf_dbg(PCIE, "Using TCM indices\n");
1113         } else {
1114                 memset(devinfo->idxbuf, 0, bufsz);
1115                 devinfo->idxbuf_sz = bufsz;
1116                 idx_offset = devinfo->dma_idx_sz;
1117                 devinfo->write_ptr = brcmf_pcie_write_idx;
1118                 devinfo->read_ptr = brcmf_pcie_read_idx;
1119
1120                 h2d_w_idx_ptr = 0;
1121                 address = (u64)devinfo->idxbuf_dmahandle;
1122                 ringinfo.h2d_w_idx_hostaddr.low_addr =
1123                         cpu_to_le32(address & 0xffffffff);
1124                 ringinfo.h2d_w_idx_hostaddr.high_addr =
1125                         cpu_to_le32(address >> 32);
1126
1127                 h2d_r_idx_ptr = h2d_w_idx_ptr +
1128                                 max_submissionrings * idx_offset;
1129                 address += max_submissionrings * idx_offset;
1130                 ringinfo.h2d_r_idx_hostaddr.low_addr =
1131                         cpu_to_le32(address & 0xffffffff);
1132                 ringinfo.h2d_r_idx_hostaddr.high_addr =
1133                         cpu_to_le32(address >> 32);
1134
1135                 d2h_w_idx_ptr = h2d_r_idx_ptr +
1136                                 max_submissionrings * idx_offset;
1137                 address += max_submissionrings * idx_offset;
1138                 ringinfo.d2h_w_idx_hostaddr.low_addr =
1139                         cpu_to_le32(address & 0xffffffff);
1140                 ringinfo.d2h_w_idx_hostaddr.high_addr =
1141                         cpu_to_le32(address >> 32);
1142
1143                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1144                                 max_completionrings * idx_offset;
1145                 address += max_completionrings * idx_offset;
1146                 ringinfo.d2h_r_idx_hostaddr.low_addr =
1147                         cpu_to_le32(address & 0xffffffff);
1148                 ringinfo.d2h_r_idx_hostaddr.high_addr =
1149                         cpu_to_le32(address >> 32);
1150
1151                 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1152                             &ringinfo, sizeof(ringinfo));
1153                 brcmf_dbg(PCIE, "Using host memory indices\n");
1154         }
1155
1156         ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1157
1158         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1159                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1160                 if (!ring)
1161                         goto fail;
1162                 ring->w_idx_addr = h2d_w_idx_ptr;
1163                 ring->r_idx_addr = h2d_r_idx_ptr;
1164                 ring->id = i;
1165                 devinfo->shared.commonrings[i] = ring;
1166
1167                 h2d_w_idx_ptr += idx_offset;
1168                 h2d_r_idx_ptr += idx_offset;
1169                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1170         }
1171
1172         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1173              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1174                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1175                 if (!ring)
1176                         goto fail;
1177                 ring->w_idx_addr = d2h_w_idx_ptr;
1178                 ring->r_idx_addr = d2h_r_idx_ptr;
1179                 ring->id = i;
1180                 devinfo->shared.commonrings[i] = ring;
1181
1182                 d2h_w_idx_ptr += idx_offset;
1183                 d2h_r_idx_ptr += idx_offset;
1184                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1185         }
1186
1187         devinfo->shared.max_flowrings = max_flowrings;
1188         devinfo->shared.max_submissionrings = max_submissionrings;
1189         devinfo->shared.max_completionrings = max_completionrings;
1190         rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1191         if (!rings)
1192                 goto fail;
1193
1194         brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1195
1196         for (i = 0; i < max_flowrings; i++) {
1197                 ring = &rings[i];
1198                 ring->devinfo = devinfo;
1199                 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1200                 brcmf_commonring_register_cb(&ring->commonring,
1201                                              brcmf_pcie_ring_mb_ring_bell,
1202                                              brcmf_pcie_ring_mb_update_rptr,
1203                                              brcmf_pcie_ring_mb_update_wptr,
1204                                              brcmf_pcie_ring_mb_write_rptr,
1205                                              brcmf_pcie_ring_mb_write_wptr,
1206                                              ring);
1207                 ring->w_idx_addr = h2d_w_idx_ptr;
1208                 ring->r_idx_addr = h2d_r_idx_ptr;
1209                 h2d_w_idx_ptr += idx_offset;
1210                 h2d_r_idx_ptr += idx_offset;
1211         }
1212         devinfo->shared.flowrings = rings;
1213
1214         return 0;
1215
1216 fail:
1217         brcmf_err("Allocating ring buffers failed\n");
1218         brcmf_pcie_release_ringbuffers(devinfo);
1219         return -ENOMEM;
1220 }
1221
1222
1223 static void
1224 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1225 {
1226         if (devinfo->shared.scratch)
1227                 dma_free_coherent(&devinfo->pdev->dev,
1228                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1229                                   devinfo->shared.scratch,
1230                                   devinfo->shared.scratch_dmahandle);
1231         if (devinfo->shared.ringupd)
1232                 dma_free_coherent(&devinfo->pdev->dev,
1233                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1234                                   devinfo->shared.ringupd,
1235                                   devinfo->shared.ringupd_dmahandle);
1236 }
1237
1238 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1239 {
1240         u64 address;
1241         u32 addr;
1242
1243         devinfo->shared.scratch =
1244                 dma_zalloc_coherent(&devinfo->pdev->dev,
1245                                         BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1246                                         &devinfo->shared.scratch_dmahandle,
1247                                         GFP_KERNEL);
1248         if (!devinfo->shared.scratch)
1249                 goto fail;
1250
1251         addr = devinfo->shared.tcm_base_address +
1252                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1253         address = (u64)devinfo->shared.scratch_dmahandle;
1254         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1255         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1256         addr = devinfo->shared.tcm_base_address +
1257                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1258         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1259
1260         devinfo->shared.ringupd =
1261                 dma_zalloc_coherent(&devinfo->pdev->dev,
1262                                         BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1263                                         &devinfo->shared.ringupd_dmahandle,
1264                                         GFP_KERNEL);
1265         if (!devinfo->shared.ringupd)
1266                 goto fail;
1267
1268         addr = devinfo->shared.tcm_base_address +
1269                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1270         address = (u64)devinfo->shared.ringupd_dmahandle;
1271         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1272         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1273         addr = devinfo->shared.tcm_base_address +
1274                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1275         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1276         return 0;
1277
1278 fail:
1279         brcmf_err("Allocating scratch buffers failed\n");
1280         brcmf_pcie_release_scratchbuffers(devinfo);
1281         return -ENOMEM;
1282 }
1283
1284
1285 static void brcmf_pcie_down(struct device *dev)
1286 {
1287 }
1288
1289
1290 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1291 {
1292         return 0;
1293 }
1294
1295
1296 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1297                                 uint len)
1298 {
1299         return 0;
1300 }
1301
1302
1303 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1304                                 uint len)
1305 {
1306         return 0;
1307 }
1308
1309
1310 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1311 {
1312         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1313         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1314         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1315
1316         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1317         devinfo->wowl_enabled = enabled;
1318 }
1319
1320
1321 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1322 {
1323         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1324         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1325         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1326
1327         return devinfo->ci->ramsize - devinfo->ci->srsize;
1328 }
1329
1330
1331 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1332 {
1333         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1334         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1335         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1336
1337         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1338         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1339         return 0;
1340 }
1341
1342 static
1343 int brcmf_pcie_get_fwname(struct device *dev, const char *ext, u8 *fw_name)
1344 {
1345         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1346         struct brcmf_fw_request *fwreq;
1347         struct brcmf_fw_name fwnames[] = {
1348                 { ext, fw_name },
1349         };
1350
1351         fwreq = brcmf_fw_alloc_request(bus_if->chip, bus_if->chiprev,
1352                                        brcmf_pcie_fwnames,
1353                                        ARRAY_SIZE(brcmf_pcie_fwnames),
1354                                        fwnames, ARRAY_SIZE(fwnames));
1355         if (!fwreq)
1356                 return -ENOMEM;
1357
1358         kfree(fwreq);
1359         return 0;
1360 }
1361
1362 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1363         .txdata = brcmf_pcie_tx,
1364         .stop = brcmf_pcie_down,
1365         .txctl = brcmf_pcie_tx_ctlpkt,
1366         .rxctl = brcmf_pcie_rx_ctlpkt,
1367         .wowl_config = brcmf_pcie_wowl_config,
1368         .get_ramsize = brcmf_pcie_get_ramsize,
1369         .get_memdump = brcmf_pcie_get_memdump,
1370         .get_fwname = brcmf_pcie_get_fwname,
1371 };
1372
1373
1374 static void
1375 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1376                           u32 data_len)
1377 {
1378         __le32 *field;
1379         u32 newsize;
1380
1381         if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1382                 return;
1383
1384         field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1385         if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1386                 return;
1387         field++;
1388         newsize = le32_to_cpup(field);
1389
1390         brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1391                   newsize);
1392         devinfo->ci->ramsize = newsize;
1393 }
1394
1395
1396 static int
1397 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1398                                u32 sharedram_addr)
1399 {
1400         struct brcmf_pcie_shared_info *shared;
1401         u32 addr;
1402
1403         shared = &devinfo->shared;
1404         shared->tcm_base_address = sharedram_addr;
1405
1406         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1407         shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1408         brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1409         if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1410             (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1411                 brcmf_err("Unsupported PCIE version %d\n", shared->version);
1412                 return -EINVAL;
1413         }
1414
1415         /* check firmware support dma indicies */
1416         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1417                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1418                         devinfo->dma_idx_sz = sizeof(u16);
1419                 else
1420                         devinfo->dma_idx_sz = sizeof(u32);
1421         }
1422
1423         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1424         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1425         if (shared->max_rxbufpost == 0)
1426                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1427
1428         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1429         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1430
1431         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1432         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1433
1434         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1435         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1436
1437         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1438         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1439
1440         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1441                   shared->max_rxbufpost, shared->rx_dataoffset);
1442
1443         brcmf_pcie_bus_console_init(devinfo);
1444
1445         return 0;
1446 }
1447
1448
1449 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1450                                         const struct firmware *fw, void *nvram,
1451                                         u32 nvram_len)
1452 {
1453         u32 sharedram_addr;
1454         u32 sharedram_addr_written;
1455         u32 loop_counter;
1456         int err;
1457         u32 address;
1458         u32 resetintr;
1459
1460         brcmf_dbg(PCIE, "Halt ARM.\n");
1461         err = brcmf_pcie_enter_download_state(devinfo);
1462         if (err)
1463                 return err;
1464
1465         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1466         memcpy_toio(devinfo->tcm + devinfo->ci->rambase,
1467                     (void *)fw->data, fw->size);
1468
1469         resetintr = get_unaligned_le32(fw->data);
1470         release_firmware(fw);
1471
1472         /* reset last 4 bytes of RAM address. to be used for shared
1473          * area. This identifies when FW is running
1474          */
1475         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1476
1477         if (nvram) {
1478                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1479                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1480                           nvram_len;
1481                 memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
1482                 brcmf_fw_nvram_free(nvram);
1483         } else {
1484                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1485                           devinfo->nvram_name);
1486         }
1487
1488         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1489                                                        devinfo->ci->ramsize -
1490                                                        4);
1491         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1492         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1493         if (err)
1494                 return err;
1495
1496         brcmf_dbg(PCIE, "Wait for FW init\n");
1497         sharedram_addr = sharedram_addr_written;
1498         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1499         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1500                 msleep(50);
1501                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1502                                                        devinfo->ci->ramsize -
1503                                                        4);
1504                 loop_counter--;
1505         }
1506         if (sharedram_addr == sharedram_addr_written) {
1507                 brcmf_err("FW failed to initialize\n");
1508                 return -ENODEV;
1509         }
1510         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1511
1512         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1513 }
1514
1515
1516 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1517 {
1518         struct pci_dev *pdev;
1519         int err;
1520         phys_addr_t  bar0_addr, bar1_addr;
1521         ulong bar1_size;
1522
1523         pdev = devinfo->pdev;
1524
1525         err = pci_enable_device(pdev);
1526         if (err) {
1527                 brcmf_err("pci_enable_device failed err=%d\n", err);
1528                 return err;
1529         }
1530
1531         pci_set_master(pdev);
1532
1533         /* Bar-0 mapped address */
1534         bar0_addr = pci_resource_start(pdev, 0);
1535         /* Bar-1 mapped address */
1536         bar1_addr = pci_resource_start(pdev, 2);
1537         /* read Bar-1 mapped memory range */
1538         bar1_size = pci_resource_len(pdev, 2);
1539         if ((bar1_size == 0) || (bar1_addr == 0)) {
1540                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1541                           bar1_size, (unsigned long long)bar1_addr);
1542                 return -EINVAL;
1543         }
1544
1545         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1546         devinfo->tcm = ioremap_nocache(bar1_addr, bar1_size);
1547
1548         if (!devinfo->regs || !devinfo->tcm) {
1549                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1550                           devinfo->tcm);
1551                 return -EINVAL;
1552         }
1553         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1554                   devinfo->regs, (unsigned long long)bar0_addr);
1555         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1556                   devinfo->tcm, (unsigned long long)bar1_addr,
1557                   (unsigned int)bar1_size);
1558
1559         return 0;
1560 }
1561
1562
1563 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1564 {
1565         if (devinfo->tcm)
1566                 iounmap(devinfo->tcm);
1567         if (devinfo->regs)
1568                 iounmap(devinfo->regs);
1569
1570         pci_disable_device(devinfo->pdev);
1571 }
1572
1573
1574 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1575 {
1576         u32 ret_addr;
1577
1578         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1579         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1580         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1581
1582         return ret_addr;
1583 }
1584
1585
1586 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1587 {
1588         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1589
1590         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1591         return brcmf_pcie_read_reg32(devinfo, addr);
1592 }
1593
1594
1595 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1596 {
1597         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1598
1599         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1600         brcmf_pcie_write_reg32(devinfo, addr, value);
1601 }
1602
1603
1604 static int brcmf_pcie_buscoreprep(void *ctx)
1605 {
1606         return brcmf_pcie_get_resource(ctx);
1607 }
1608
1609
1610 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1611 {
1612         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1613         u32 val;
1614
1615         devinfo->ci = chip;
1616         brcmf_pcie_reset_device(devinfo);
1617
1618         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1619         if (val != 0xffffffff)
1620                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1621                                        val);
1622
1623         return 0;
1624 }
1625
1626
1627 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1628                                         u32 rstvec)
1629 {
1630         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1631
1632         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1633 }
1634
1635
1636 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1637         .prepare = brcmf_pcie_buscoreprep,
1638         .reset = brcmf_pcie_buscore_reset,
1639         .activate = brcmf_pcie_buscore_activate,
1640         .read32 = brcmf_pcie_buscore_read32,
1641         .write32 = brcmf_pcie_buscore_write32,
1642 };
1643
1644 #define BRCMF_PCIE_FW_CODE      0
1645 #define BRCMF_PCIE_FW_NVRAM     1
1646
1647 static void brcmf_pcie_setup(struct device *dev, int ret,
1648                              struct brcmf_fw_request *fwreq)
1649 {
1650         const struct firmware *fw;
1651         void *nvram;
1652         struct brcmf_bus *bus;
1653         struct brcmf_pciedev *pcie_bus_dev;
1654         struct brcmf_pciedev_info *devinfo;
1655         struct brcmf_commonring **flowrings;
1656         u32 i, nvram_len;
1657
1658         /* check firmware loading result */
1659         if (ret)
1660                 goto fail;
1661
1662         bus = dev_get_drvdata(dev);
1663         pcie_bus_dev = bus->bus_priv.pcie;
1664         devinfo = pcie_bus_dev->devinfo;
1665         brcmf_pcie_attach(devinfo);
1666
1667         fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary;
1668         nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data;
1669         nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len;
1670         kfree(fwreq);
1671
1672         /* Some of the firmwares have the size of the memory of the device
1673          * defined inside the firmware. This is because part of the memory in
1674          * the device is shared and the devision is determined by FW. Parse
1675          * the firmware and adjust the chip memory size now.
1676          */
1677         brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
1678
1679         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1680         if (ret)
1681                 goto fail;
1682
1683         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1684
1685         ret = brcmf_pcie_init_ringbuffers(devinfo);
1686         if (ret)
1687                 goto fail;
1688
1689         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1690         if (ret)
1691                 goto fail;
1692
1693         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1694         ret = brcmf_pcie_request_irq(devinfo);
1695         if (ret)
1696                 goto fail;
1697
1698         /* hook the commonrings in the bus structure. */
1699         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1700                 bus->msgbuf->commonrings[i] =
1701                                 &devinfo->shared.commonrings[i]->commonring;
1702
1703         flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
1704                             GFP_KERNEL);
1705         if (!flowrings)
1706                 goto fail;
1707
1708         for (i = 0; i < devinfo->shared.max_flowrings; i++)
1709                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1710         bus->msgbuf->flowrings = flowrings;
1711
1712         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1713         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1714         bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
1715
1716         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1717
1718         brcmf_pcie_intr_enable(devinfo);
1719         brcmf_pcie_hostready(devinfo);
1720         if (brcmf_attach(&devinfo->pdev->dev, devinfo->settings) == 0)
1721                 return;
1722
1723         brcmf_pcie_bus_console_read(devinfo);
1724
1725 fail:
1726         device_release_driver(dev);
1727 }
1728
1729 static struct brcmf_fw_request *
1730 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo)
1731 {
1732         struct brcmf_fw_request *fwreq;
1733         struct brcmf_fw_name fwnames[] = {
1734                 { ".bin", devinfo->fw_name },
1735                 { ".txt", devinfo->nvram_name },
1736         };
1737
1738         fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev,
1739                                        brcmf_pcie_fwnames,
1740                                        ARRAY_SIZE(brcmf_pcie_fwnames),
1741                                        fwnames, ARRAY_SIZE(fwnames));
1742         if (!fwreq)
1743                 return NULL;
1744
1745         fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
1746         fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
1747         fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL;
1748         /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */
1749         fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1;
1750         fwreq->bus_nr = devinfo->pdev->bus->number;
1751
1752         return fwreq;
1753 }
1754
1755 static int
1756 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1757 {
1758         int ret;
1759         struct brcmf_fw_request *fwreq;
1760         struct brcmf_pciedev_info *devinfo;
1761         struct brcmf_pciedev *pcie_bus_dev;
1762         struct brcmf_bus *bus;
1763
1764         brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
1765
1766         ret = -ENOMEM;
1767         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1768         if (devinfo == NULL)
1769                 return ret;
1770
1771         devinfo->pdev = pdev;
1772         pcie_bus_dev = NULL;
1773         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1774         if (IS_ERR(devinfo->ci)) {
1775                 ret = PTR_ERR(devinfo->ci);
1776                 devinfo->ci = NULL;
1777                 goto fail;
1778         }
1779
1780         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1781         if (pcie_bus_dev == NULL) {
1782                 ret = -ENOMEM;
1783                 goto fail;
1784         }
1785
1786         devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
1787                                                    BRCMF_BUSTYPE_PCIE,
1788                                                    devinfo->ci->chip,
1789                                                    devinfo->ci->chiprev);
1790         if (!devinfo->settings) {
1791                 ret = -ENOMEM;
1792                 goto fail;
1793         }
1794
1795         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1796         if (!bus) {
1797                 ret = -ENOMEM;
1798                 goto fail;
1799         }
1800         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1801         if (!bus->msgbuf) {
1802                 ret = -ENOMEM;
1803                 kfree(bus);
1804                 goto fail;
1805         }
1806
1807         /* hook it all together. */
1808         pcie_bus_dev->devinfo = devinfo;
1809         pcie_bus_dev->bus = bus;
1810         bus->dev = &pdev->dev;
1811         bus->bus_priv.pcie = pcie_bus_dev;
1812         bus->ops = &brcmf_pcie_bus_ops;
1813         bus->proto_type = BRCMF_PROTO_MSGBUF;
1814         bus->chip = devinfo->coreid;
1815         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1816         dev_set_drvdata(&pdev->dev, bus);
1817
1818         fwreq = brcmf_pcie_prepare_fw_request(devinfo);
1819         if (!fwreq) {
1820                 ret = -ENOMEM;
1821                 goto fail_bus;
1822         }
1823
1824         ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup);
1825         if (ret < 0) {
1826                 kfree(fwreq);
1827                 goto fail_bus;
1828         }
1829         return 0;
1830
1831 fail_bus:
1832         kfree(bus->msgbuf);
1833         kfree(bus);
1834 fail:
1835         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1836         brcmf_pcie_release_resource(devinfo);
1837         if (devinfo->ci)
1838                 brcmf_chip_detach(devinfo->ci);
1839         if (devinfo->settings)
1840                 brcmf_release_module_param(devinfo->settings);
1841         kfree(pcie_bus_dev);
1842         kfree(devinfo);
1843         return ret;
1844 }
1845
1846
1847 static void
1848 brcmf_pcie_remove(struct pci_dev *pdev)
1849 {
1850         struct brcmf_pciedev_info *devinfo;
1851         struct brcmf_bus *bus;
1852
1853         brcmf_dbg(PCIE, "Enter\n");
1854
1855         bus = dev_get_drvdata(&pdev->dev);
1856         if (bus == NULL)
1857                 return;
1858
1859         devinfo = bus->bus_priv.pcie->devinfo;
1860
1861         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1862         if (devinfo->ci)
1863                 brcmf_pcie_intr_disable(devinfo);
1864
1865         brcmf_detach(&pdev->dev);
1866
1867         kfree(bus->bus_priv.pcie);
1868         kfree(bus->msgbuf->flowrings);
1869         kfree(bus->msgbuf);
1870         kfree(bus);
1871
1872         brcmf_pcie_release_irq(devinfo);
1873         brcmf_pcie_release_scratchbuffers(devinfo);
1874         brcmf_pcie_release_ringbuffers(devinfo);
1875         brcmf_pcie_reset_device(devinfo);
1876         brcmf_pcie_release_resource(devinfo);
1877
1878         if (devinfo->ci)
1879                 brcmf_chip_detach(devinfo->ci);
1880         if (devinfo->settings)
1881                 brcmf_release_module_param(devinfo->settings);
1882
1883         kfree(devinfo);
1884         dev_set_drvdata(&pdev->dev, NULL);
1885 }
1886
1887
1888 #ifdef CONFIG_PM
1889
1890
1891 static int brcmf_pcie_pm_enter_D3(struct device *dev)
1892 {
1893         struct brcmf_pciedev_info *devinfo;
1894         struct brcmf_bus *bus;
1895
1896         brcmf_dbg(PCIE, "Enter\n");
1897
1898         bus = dev_get_drvdata(dev);
1899         devinfo = bus->bus_priv.pcie->devinfo;
1900
1901         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1902
1903         devinfo->mbdata_completed = false;
1904         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1905
1906         wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
1907                            BRCMF_PCIE_MBDATA_TIMEOUT);
1908         if (!devinfo->mbdata_completed) {
1909                 brcmf_err("Timeout on response for entering D3 substate\n");
1910                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1911                 return -EIO;
1912         }
1913
1914         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1915
1916         return 0;
1917 }
1918
1919
1920 static int brcmf_pcie_pm_leave_D3(struct device *dev)
1921 {
1922         struct brcmf_pciedev_info *devinfo;
1923         struct brcmf_bus *bus;
1924         struct pci_dev *pdev;
1925         int err;
1926
1927         brcmf_dbg(PCIE, "Enter\n");
1928
1929         bus = dev_get_drvdata(dev);
1930         devinfo = bus->bus_priv.pcie->devinfo;
1931         brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
1932
1933         /* Check if device is still up and running, if so we are ready */
1934         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1935                 brcmf_dbg(PCIE, "Try to wakeup device....\n");
1936                 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
1937                         goto cleanup;
1938                 brcmf_dbg(PCIE, "Hot resume, continue....\n");
1939                 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1940                 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1941                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1942                 brcmf_pcie_intr_enable(devinfo);
1943                 brcmf_pcie_hostready(devinfo);
1944                 return 0;
1945         }
1946
1947 cleanup:
1948         brcmf_chip_detach(devinfo->ci);
1949         devinfo->ci = NULL;
1950         pdev = devinfo->pdev;
1951         brcmf_pcie_remove(pdev);
1952
1953         err = brcmf_pcie_probe(pdev, NULL);
1954         if (err)
1955                 brcmf_err("probe after resume failed, err=%d\n", err);
1956
1957         return err;
1958 }
1959
1960
1961 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
1962         .suspend = brcmf_pcie_pm_enter_D3,
1963         .resume = brcmf_pcie_pm_leave_D3,
1964         .freeze = brcmf_pcie_pm_enter_D3,
1965         .restore = brcmf_pcie_pm_leave_D3,
1966 };
1967
1968
1969 #endif /* CONFIG_PM */
1970
1971
1972 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1973         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1974 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev)  { \
1975         BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1976         subvend, subdev, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1977
1978 static const struct pci_device_id brcmf_pcie_devid_table[] = {
1979         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
1980         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1981         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1982         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1983         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
1984         BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
1985         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1986         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1987         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1988         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
1989         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
1990         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
1991         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
1992         BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365),
1993         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
1994         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
1995         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
1996         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
1997         { /* end: all zeroes */ }
1998 };
1999
2000
2001 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2002
2003
2004 static struct pci_driver brcmf_pciedrvr = {
2005         .node = {},
2006         .name = KBUILD_MODNAME,
2007         .id_table = brcmf_pcie_devid_table,
2008         .probe = brcmf_pcie_probe,
2009         .remove = brcmf_pcie_remove,
2010 #ifdef CONFIG_PM
2011         .driver.pm = &brcmf_pciedrvr_pm,
2012 #endif
2013         .driver.coredump = brcmf_dev_coredump,
2014 };
2015
2016
2017 void brcmf_pcie_register(void)
2018 {
2019         int err;
2020
2021         brcmf_dbg(PCIE, "Enter\n");
2022         err = pci_register_driver(&brcmf_pciedrvr);
2023         if (err)
2024                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2025 }
2026
2027
2028 void brcmf_pcie_exit(void)
2029 {
2030         brcmf_dbg(PCIE, "Enter\n");
2031         pci_unregister_driver(&brcmf_pciedrvr);
2032 }