2 * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/etherdevice.h>
18 #include <linux/moduleparam.h>
19 #include <linux/prefetch.h>
20 #include <linux/types.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
25 #include "txrx_edma.h"
29 #define WIL_EDMA_MAX_DATA_OFFSET (2)
30 /* RX buffer size must be aligned to 4 bytes */
31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048)
33 static void wil_tx_desc_unmap_edma(struct device *dev,
34 union wil_tx_desc *desc,
37 struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc;
38 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma);
39 u16 dmalen = le16_to_cpu(d->dma.length);
41 switch (ctx->mapped_as) {
42 case wil_mapped_as_single:
43 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE);
45 case wil_mapped_as_page:
46 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE);
53 static int wil_find_free_sring(struct wil6210_priv *wil)
57 for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) {
58 if (!wil->srings[i].va)
65 static void wil_sring_free(struct wil6210_priv *wil,
66 struct wil_status_ring *sring)
68 struct device *dev = wil_to_dev(wil);
71 if (!sring || !sring->va)
74 sz = sring->elem_size * sring->size;
76 wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n",
77 sz, sring->va, &sring->pa);
79 dma_free_coherent(dev, sz, (void *)sring->va, sring->pa);
84 static int wil_sring_alloc(struct wil6210_priv *wil,
85 struct wil_status_ring *sring)
87 struct device *dev = wil_to_dev(wil);
88 size_t sz = sring->elem_size * sring->size;
90 wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz);
93 wil_err(wil, "Cannot allocate a zero size status ring\n");
99 /* Status messages are allocated and initialized to 0. This is necessary
100 * since DR bit should be initialized to 0.
102 sring->va = dma_zalloc_coherent(dev, sz, &sring->pa, GFP_KERNEL);
106 wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va,
112 static int wil_tx_init_edma(struct wil6210_priv *wil)
114 int ring_id = wil_find_free_sring(wil);
115 struct wil_status_ring *sring;
117 u16 status_ring_size;
119 if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
120 wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
121 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT;
123 status_ring_size = 1 << wil->tx_status_ring_order;
125 wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n",
126 status_ring_size, ring_id);
131 /* Allocate Tx status ring. Tx descriptor rings will be
132 * allocated on WMI connect event
134 sring = &wil->srings[ring_id];
136 sring->is_rx = false;
137 sring->size = status_ring_size;
138 sring->elem_size = sizeof(struct wil_ring_tx_status);
139 rc = wil_sring_alloc(wil, sring);
143 rc = wil_wmi_tx_sring_cfg(wil, ring_id);
147 sring->desc_rdy_pol = 1;
148 wil->tx_sring_idx = ring_id;
152 wil_sring_free(wil, sring);
157 * Allocate one skb for Rx descriptor RING
159 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil,
160 struct wil_ring *ring, u32 i)
162 struct device *dev = wil_to_dev(wil);
163 unsigned int sz = ALIGN(wil->rx_buf_len, 4);
166 struct list_head *active = &wil->rx_buff_mgmt.active;
167 struct list_head *free = &wil->rx_buff_mgmt.free;
168 struct wil_rx_buff *rx_buff;
169 struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr;
171 struct wil_rx_enhanced_desc dd, *d = ⅆ
172 struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *)
173 &ring->va[i].rx.enhanced;
175 if (unlikely(list_empty(free))) {
176 wil->rx_buff_mgmt.free_list_empty_cnt++;
180 skb = dev_alloc_skb(sz);
187 * Make sure that the network stack calculates checksum for packets
188 * which failed the HW checksum calculation
190 skb->ip_summed = CHECKSUM_NONE;
192 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE);
193 if (unlikely(dma_mapping_error(dev, pa))) {
198 /* Get the buffer ID - the index of the rx buffer in the buff_arr */
199 rx_buff = list_first_entry(free, struct wil_rx_buff, list);
200 buff_id = rx_buff->id;
202 /* Move a buffer from the free list to the active list */
203 list_move(&rx_buff->list, active);
205 buff_arr[buff_id].skb = skb;
207 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa);
208 d->dma.length = cpu_to_le16(sz);
209 d->mac.buff_id = cpu_to_le16(buff_id);
212 /* Save the physical address in skb->cb for later use in dma_unmap */
213 memcpy(skb->cb, &pa, sizeof(pa));
219 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg)
221 memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)),
225 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring)
227 sring->swhead = (sring->swhead + 1) % sring->size;
228 if (sring->swhead == 0)
229 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol;
232 static int wil_rx_refill_edma(struct wil6210_priv *wil)
234 struct wil_ring *ring = &wil->ring_rx;
237 ring->swtail = *ring->edma_rx_swtail.va;
239 for (; next_head = wil_ring_next_head(ring),
240 (next_head != ring->swtail);
241 ring->swhead = next_head) {
242 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead);
245 wil_dbg_txrx(wil, "No free buffer ID found\n");
247 wil_err_ratelimited(wil,
248 "Error %d in refill desc[%d]\n",
254 /* make sure all writes to descriptors (shared memory) are done before
255 * committing them to HW
259 wil_w(wil, ring->hwtail, ring->swhead);
264 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil,
265 struct wil_ring *ring)
267 struct device *dev = wil_to_dev(wil);
268 struct list_head *active = &wil->rx_buff_mgmt.active;
271 if (!wil->rx_buff_mgmt.buff_arr)
274 while (!list_empty(active)) {
275 struct wil_rx_buff *rx_buff =
276 list_first_entry(active, struct wil_rx_buff, list);
277 struct sk_buff *skb = rx_buff->skb;
279 if (unlikely(!skb)) {
280 wil_err(wil, "No Rx skb at buff_id %d\n", rx_buff->id);
283 memcpy(&pa, skb->cb, sizeof(pa));
284 dma_unmap_single(dev, pa, wil->rx_buf_len,
289 /* Move the buffer from the active to the free list */
290 list_move(&rx_buff->list, &wil->rx_buff_mgmt.free);
294 static void wil_free_rx_buff_arr(struct wil6210_priv *wil)
296 struct wil_ring *ring = &wil->ring_rx;
298 if (!wil->rx_buff_mgmt.buff_arr)
301 /* Move all the buffers to the free list in case active list is
302 * not empty in order to release all SKBs before deleting the array
304 wil_move_all_rx_buff_to_free_list(wil, ring);
306 kfree(wil->rx_buff_mgmt.buff_arr);
307 wil->rx_buff_mgmt.buff_arr = NULL;
310 static int wil_init_rx_buff_arr(struct wil6210_priv *wil,
313 struct wil_rx_buff *buff_arr;
314 struct list_head *active = &wil->rx_buff_mgmt.active;
315 struct list_head *free = &wil->rx_buff_mgmt.free;
318 wil->rx_buff_mgmt.buff_arr = kcalloc(size, sizeof(struct wil_rx_buff),
320 if (!wil->rx_buff_mgmt.buff_arr)
324 INIT_LIST_HEAD(active);
325 INIT_LIST_HEAD(free);
327 /* Linkify the list */
328 buff_arr = wil->rx_buff_mgmt.buff_arr;
329 for (i = 0; i < size; i++) {
330 list_add(&buff_arr[i].list, free);
334 wil->rx_buff_mgmt.size = size;
339 static int wil_init_rx_sring(struct wil6210_priv *wil,
340 u16 status_ring_size,
344 struct wil_status_ring *sring = &wil->srings[ring_id];
347 wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", sring->size,
350 memset(&sring->rx_data, 0, sizeof(sring->rx_data));
353 sring->size = status_ring_size;
354 sring->elem_size = elem_size;
355 rc = wil_sring_alloc(wil, sring);
359 rc = wil_wmi_rx_sring_add(wil, ring_id);
363 sring->desc_rdy_pol = 1;
367 wil_sring_free(wil, sring);
371 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil,
372 struct wil_ring *ring)
374 struct device *dev = wil_to_dev(wil);
375 size_t sz = ring->size * sizeof(ring->va[0]);
377 wil_dbg_misc(wil, "alloc_desc_ring:\n");
379 BUILD_BUG_ON(sizeof(ring->va[0]) != 32);
383 ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL);
387 ring->va = dma_zalloc_coherent(dev, sz, &ring->pa, GFP_KERNEL);
392 sz = sizeof(*ring->edma_rx_swtail.va);
393 ring->edma_rx_swtail.va =
394 dma_zalloc_coherent(dev, sz, &ring->edma_rx_swtail.pa,
396 if (!ring->edma_rx_swtail.va)
400 wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n",
401 ring->is_rx ? "RX" : "TX",
402 ring->size, ring->va, &ring->pa, ring->ctx);
406 dma_free_coherent(dev, ring->size * sizeof(ring->va[0]),
407 (void *)ring->va, ring->pa);
416 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring)
418 struct device *dev = wil_to_dev(wil);
425 sz = ring->size * sizeof(ring->va[0]);
427 lockdep_assert_held(&wil->mutex);
429 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n",
430 ring->size, ring->va,
431 &ring->pa, ring->ctx);
433 wil_move_all_rx_buff_to_free_list(wil, ring);
438 ring_index = ring - wil->ring_tx;
440 wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n",
441 ring_index, ring->size, ring->va,
442 &ring->pa, ring->ctx);
444 while (!wil_ring_is_empty(ring)) {
447 struct wil_tx_enhanced_desc dd, *d = ⅆ
448 struct wil_tx_enhanced_desc *_d =
449 (struct wil_tx_enhanced_desc *)
450 &ring->va[ring->swtail].tx.enhanced;
452 ctx = &ring->ctx[ring->swtail];
455 "ctx(%d) was already completed\n",
457 ring->swtail = wil_ring_next_tail(ring);
461 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx);
463 dev_kfree_skb_any(ctx->skb);
464 ring->swtail = wil_ring_next_tail(ring);
468 dma_free_coherent(dev, sz, (void *)ring->va, ring->pa);
475 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size,
478 struct wil_ring *ring = &wil->ring_rx;
481 wil_dbg_misc(wil, "init RX desc ring\n");
483 ring->size = desc_ring_size;
485 rc = wil_ring_alloc_desc_ring(wil, ring);
489 rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id);
495 wil_ring_free_edma(wil, ring);
499 static void wil_get_reorder_params_edma(struct wil6210_priv *wil,
500 struct sk_buff *skb, int *tid,
501 int *cid, int *mid, u16 *seq,
502 int *mcast, int *retry)
504 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
506 *tid = wil_rx_status_get_tid(s);
507 *cid = wil_rx_status_get_cid(s);
508 *mid = wil_rx_status_get_mid(s);
509 *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s));
510 *mcast = wil_rx_status_get_mcast(s);
511 *retry = wil_rx_status_get_retry(s);
514 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid,
517 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
519 *cid = wil_rx_status_get_cid(s);
520 *security = wil_rx_status_get_security(s);
523 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil,
526 struct wil_rx_status_extended *st;
527 int cid, tid, key_id, mc;
528 struct wil_sta_info *s;
529 struct wil_tid_crypto_rx *c;
530 struct wil_tid_crypto_rx_single *cc;
533 /* In HW reorder, HW is responsible for crypto check */
534 if (wil->use_rx_hw_reordering)
537 st = wil_skb_rxstatus(skb);
539 cid = wil_rx_status_get_cid(st);
540 tid = wil_rx_status_get_tid(st);
541 key_id = wil_rx_status_get_key_id(st);
542 mc = wil_rx_status_get_mcast(st);
544 c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid];
545 cc = &c->key_id[key_id];
546 pn = (u8 *)&st->ext.pn_15_0;
549 wil_err_ratelimited(wil,
550 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n",
551 cid, tid, mc, key_id);
555 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) {
556 wil_err_ratelimited(wil,
557 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n",
558 cid, tid, mc, key_id, pn, cc->pn);
561 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN);
566 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil)
568 struct wil_status_ring *sring;
569 struct wil_rx_status_extended msg1;
574 for (i = 0; i < wil->num_rx_status_rings; i++) {
575 sring = &wil->srings[i];
579 wil_get_next_rx_status_msg(sring, msg);
580 dr_bit = wil_rx_status_get_desc_rdy_bit(msg);
582 /* Check if there are unhandled RX status messages */
583 if (dr_bit == sring->desc_rdy_pol)
590 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil)
592 wil->rx_buf_len = rx_large_buf ?
593 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT;
596 static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order)
598 u16 status_ring_size, desc_ring_size = 1 << desc_ring_order;
599 struct wil_ring *ring = &wil->ring_rx;
601 size_t elem_size = wil->use_compressed_rx_status ?
602 sizeof(struct wil_rx_status_compressed) :
603 sizeof(struct wil_rx_status_extended);
605 u16 max_rx_pl_per_desc;
607 /* In SW reorder one must use extended status messages */
608 if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) {
610 "compressed RX status cannot be used with SW reorder\n");
613 if (wil->rx_status_ring_order <= desc_ring_order)
614 /* make sure sring is larger than desc ring */
615 wil->rx_status_ring_order = desc_ring_order + 1;
616 if (wil->rx_buff_id_count <= desc_ring_size)
617 /* make sure we will not run out of buff_ids */
618 wil->rx_buff_id_count = desc_ring_size + 512;
619 if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
620 wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
621 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT;
623 status_ring_size = 1 << wil->rx_status_ring_order;
626 "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n",
627 desc_ring_size, status_ring_size, elem_size);
629 wil_rx_buf_len_init_edma(wil);
631 max_rx_pl_per_desc = ALIGN(wil->rx_buf_len, 4);
633 /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */
634 if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1)
635 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1;
637 wil_dbg_misc(wil, "rx_init: allocate %d status rings\n",
638 wil->num_rx_status_rings);
640 rc = wil_wmi_cfg_def_rx_offload(wil, max_rx_pl_per_desc);
644 /* Allocate status ring */
645 for (i = 0; i < wil->num_rx_status_rings; i++) {
646 int sring_id = wil_find_free_sring(wil);
650 goto err_free_status;
652 rc = wil_init_rx_sring(wil, status_ring_size, elem_size,
655 goto err_free_status;
658 /* Allocate descriptor ring */
659 rc = wil_init_rx_desc_ring(wil, desc_ring_size,
660 WIL_DEFAULT_RX_STATUS_RING_ID);
662 goto err_free_status;
664 if (wil->rx_buff_id_count >= status_ring_size) {
666 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n",
667 wil->rx_buff_id_count, status_ring_size,
668 status_ring_size - 1);
669 wil->rx_buff_id_count = status_ring_size - 1;
672 /* Allocate Rx buffer array */
673 rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count);
677 /* Fill descriptor ring with credits */
678 rc = wil_rx_refill_edma(wil);
680 goto err_free_rx_buff_arr;
683 err_free_rx_buff_arr:
684 wil_free_rx_buff_arr(wil);
686 wil_ring_free_edma(wil, ring);
688 for (i = 0; i < wil->num_rx_status_rings; i++)
689 wil_sring_free(wil, &wil->srings[i]);
694 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id,
695 int size, int cid, int tid)
697 struct wil6210_priv *wil = vif_to_wil(vif);
699 struct wil_ring *ring = &wil->ring_tx[ring_id];
700 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
702 lockdep_assert_held(&wil->mutex);
705 "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n",
706 ring_id, cid, tid, wil->tx_sring_idx);
708 wil_tx_data_init(txdata);
710 rc = wil_ring_alloc_desc_ring(wil, ring);
714 wil->ring2cid_tid[ring_id][0] = cid;
715 wil->ring2cid_tid[ring_id][1] = tid;
717 txdata->dot1x_open = true;
719 rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid);
721 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n");
725 if (txdata->dot1x_open && agg_wsize >= 0)
726 wil_addba_tx_request(wil, ring_id, agg_wsize);
730 spin_lock_bh(&txdata->lock);
731 txdata->dot1x_open = false;
733 spin_unlock_bh(&txdata->lock);
734 wil_ring_free_edma(wil, ring);
735 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID;
736 wil->ring2cid_tid[ring_id][1] = 0;
742 /* This function is used only for RX SW reorder */
743 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid,
744 struct sk_buff *skb, struct wil_net_stats *stats)
751 struct wil6210_vif *vif;
753 ftype = wil_rx_status_get_frame_type(wil, msg);
754 if (ftype == IEEE80211_FTYPE_DATA)
757 fc1 = wil_rx_status_get_fc1(wil, msg);
758 mid = wil_rx_status_get_mid(msg);
759 tid = wil_rx_status_get_tid(msg);
760 seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg));
761 vif = wil->vifs[mid];
763 if (unlikely(!vif)) {
764 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid);
769 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
770 fc1, mid, cid, tid, seq);
772 stats->rx_non_data_frame++;
773 if (wil_is_back_req(fc1)) {
775 "BAR: MID %d CID %d TID %d Seq 0x%03x\n",
777 wil_rx_bar(wil, vif, cid, tid, seq);
779 u32 sz = wil->use_compressed_rx_status ?
780 sizeof(struct wil_rx_status_compressed) :
781 sizeof(struct wil_rx_status_extended);
783 /* print again all info. One can enable only this
784 * without overhead for printing every Rx frame
787 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
788 fc1, mid, cid, tid, seq);
789 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
790 (const void *)msg, sz, false);
791 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
792 skb->data, skb_headlen(skb), false);
798 static int wil_rx_error_check_edma(struct wil6210_priv *wil,
800 struct wil_net_stats *stats)
806 void *msg = wil_skb_rxstatus(skb);
808 error = wil_rx_status_get_error(msg);
810 skb->ip_summed = CHECKSUM_UNNECESSARY;
814 l2_rx_status = wil_rx_status_get_l2_rx_status(msg);
815 if (l2_rx_status != 0) {
816 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n",
818 /* Due to HW issue, KEY error will trigger a MIC error */
819 if (l2_rx_status == WIL_RX_EDMA_ERROR_MIC) {
820 wil_err_ratelimited(wil,
821 "L2 MIC/KEY error, dropping packet\n");
822 stats->rx_mic_error++;
824 if (l2_rx_status == WIL_RX_EDMA_ERROR_KEY) {
825 wil_err_ratelimited(wil,
826 "L2 KEY error, dropping packet\n");
827 stats->rx_key_error++;
829 if (l2_rx_status == WIL_RX_EDMA_ERROR_REPLAY) {
830 wil_err_ratelimited(wil,
831 "L2 REPLAY error, dropping packet\n");
834 if (l2_rx_status == WIL_RX_EDMA_ERROR_AMSDU) {
835 wil_err_ratelimited(wil,
836 "L2 AMSDU error, dropping packet\n");
837 stats->rx_amsdu_error++;
842 l3_rx_status = wil_rx_status_get_l3_rx_status(msg);
843 l4_rx_status = wil_rx_status_get_l4_rx_status(msg);
844 if (!l3_rx_status && !l4_rx_status)
845 skb->ip_summed = CHECKSUM_UNNECESSARY;
846 /* If HW reports bad checksum, let IP stack re-check it
847 * For example, HW don't understand Microsoft IP stack that
848 * mis-calculates TCP checksum - if it should be 0x0,
849 * it writes 0xffff in violation of RFC 1624
852 stats->rx_csum_err++;
857 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil,
858 struct wil_status_ring *sring)
860 struct device *dev = wil_to_dev(wil);
861 struct wil_rx_status_extended msg1;
866 struct wil_ring_rx_data *rxdata = &sring->rx_data;
867 unsigned int sz = ALIGN(wil->rx_buf_len, 4);
868 struct wil_net_stats *stats = NULL;
871 bool eop, headstolen;
875 struct wil_rx_status_extended *s;
876 u16 sring_idx = sring - wil->srings;
878 BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb));
881 wil_get_next_rx_status_msg(sring, msg);
882 dr_bit = wil_rx_status_get_desc_rdy_bit(msg);
884 /* Completed handling all the ready status messages */
885 if (dr_bit != sring->desc_rdy_pol)
888 /* Extract the buffer ID from the status message */
889 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg));
890 if (unlikely(!wil_val_in_range(buff_id, 0, wil->rx_buff_mgmt.size))) {
891 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n",
892 buff_id, sring->swhead);
893 wil_sring_advance_swhead(sring);
897 wil_sring_advance_swhead(sring);
899 /* Extract the SKB from the rx_buff management array */
900 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb;
901 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL;
903 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id);
904 /* Move the buffer from the active list to the free list */
905 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list,
906 &wil->rx_buff_mgmt.free);
910 memcpy(&pa, skb->cb, sizeof(pa));
911 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE);
912 dmalen = le16_to_cpu(wil_rx_status_get_length(msg));
914 trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id,
916 wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n",
917 buff_id, sring_idx, dmalen);
918 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
919 (const void *)msg, wil->use_compressed_rx_status ?
920 sizeof(struct wil_rx_status_compressed) :
921 sizeof(struct wil_rx_status_extended), false);
923 /* Move the buffer from the active list to the free list */
924 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list,
925 &wil->rx_buff_mgmt.free);
927 eop = wil_rx_status_get_eop(msg);
929 cid = wil_rx_status_get_cid(msg);
930 if (unlikely(!wil_val_in_range(cid, 0, WIL6210_MAX_CID))) {
931 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n",
933 rxdata->skipping = true;
936 stats = &wil->sta[cid].stats;
938 if (unlikely(skb->len < ETH_HLEN)) {
939 wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len);
940 stats->rx_short_frame++;
941 rxdata->skipping = true;
945 if (unlikely(dmalen > sz)) {
946 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen);
947 stats->rx_large_frame++;
948 rxdata->skipping = true;
952 /* skipping indicates if a certain SKB should be dropped.
953 * It is set in case there is an error on the current SKB or in case
954 * of RX chaining: as long as we manage to merge the SKBs it will
955 * be false. once we have a bad SKB or we don't manage to merge SKBs
956 * it will be set to the !EOP value of the current SKB.
957 * This guarantees that all the following SKBs until EOP will also
960 if (unlikely(rxdata->skipping)) {
963 kfree_skb(rxdata->skb);
966 rxdata->skipping = !eop;
970 skb_trim(skb, dmalen);
977 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen,
979 kfree_skb_partial(skb, headstolen);
981 wil_err(wil, "failed to merge skbs!\n");
983 kfree_skb(rxdata->skb);
985 rxdata->skipping = !eop;
993 /* reaching here rxdata->skb always contains a full packet */
996 rxdata->skipping = false;
999 stats->last_mcs_rx = wil_rx_status_get_mcs(msg);
1000 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs))
1001 stats->rx_per_mcs[stats->last_mcs_rx]++;
1004 if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status &&
1005 wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) {
1010 /* Compensate for the HW data alignment according to the status
1013 data_offset = wil_rx_status_get_data_offset(msg);
1014 if (data_offset == 0xFF ||
1015 data_offset > WIL_EDMA_MAX_DATA_OFFSET) {
1016 wil_err(wil, "Unexpected data offset %d\n", data_offset);
1021 skb_pull(skb, data_offset);
1023 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
1024 skb->data, skb_headlen(skb), false);
1026 /* Has to be done after dma_unmap_single as skb->cb is also
1027 * used for holding the pa
1029 s = wil_skb_rxstatus(skb);
1030 memcpy(s, msg, sring->elem_size);
1035 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota)
1037 struct net_device *ndev;
1038 struct wil_ring *ring = &wil->ring_rx;
1039 struct wil_status_ring *sring;
1040 struct sk_buff *skb;
1043 if (unlikely(!ring->va)) {
1044 wil_err(wil, "Rx IRQ while Rx not yet initialized\n");
1047 wil_dbg_txrx(wil, "rx_handle\n");
1049 for (i = 0; i < wil->num_rx_status_rings; i++) {
1050 sring = &wil->srings[i];
1051 if (unlikely(!sring->va)) {
1053 "Rx IRQ while Rx status ring %d not yet initialized\n",
1058 while ((*quota > 0) &&
1060 wil_sring_reap_rx_edma(wil, sring)))) {
1062 if (wil->use_rx_hw_reordering) {
1063 void *msg = wil_skb_rxstatus(skb);
1064 int mid = wil_rx_status_get_mid(msg);
1065 struct wil6210_vif *vif = wil->vifs[mid];
1067 if (unlikely(!vif)) {
1069 "RX desc invalid mid %d",
1074 ndev = vif_to_ndev(vif);
1075 wil_netif_rx_any(skb, ndev);
1077 wil_rx_reorder(wil, skb);
1081 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size);
1084 wil_rx_refill_edma(wil);
1087 static int wil_tx_desc_map_edma(union wil_tx_desc *desc,
1092 struct wil_tx_enhanced_desc *d =
1093 (struct wil_tx_enhanced_desc *)&desc->enhanced;
1095 memset(d, 0, sizeof(struct wil_tx_enhanced_desc));
1097 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa);
1099 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/
1100 d->dma.length = cpu_to_le16((u16)len);
1101 d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS);
1102 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi;
1105 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) |
1106 (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS);
1112 wil_get_next_tx_status_msg(struct wil_status_ring *sring,
1113 struct wil_ring_tx_status *msg)
1115 struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *)
1116 (sring->va + (sring->elem_size * sring->swhead));
1122 * Clean up transmitted skb's from the Tx descriptor RING.
1123 * Return number of descriptors cleared.
1125 int wil_tx_sring_handler(struct wil6210_priv *wil,
1126 struct wil_status_ring *sring)
1128 struct net_device *ndev;
1129 struct device *dev = wil_to_dev(wil);
1130 struct wil_ring *ring = NULL;
1131 struct wil_ring_tx_data *txdata;
1132 /* Total number of completed descriptors in all descriptor rings */
1135 struct wil_net_stats *stats = NULL;
1136 struct wil_tx_enhanced_desc *_d;
1137 unsigned int ring_id;
1138 unsigned int num_descs;
1140 u8 dr_bit; /* Descriptor Ready bit */
1141 struct wil_ring_tx_status msg;
1142 struct wil6210_vif *vif;
1143 int used_before_complete;
1146 wil_get_next_tx_status_msg(sring, &msg);
1147 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS;
1149 /* Process completion messages while DR bit has the expected polarity */
1150 while (dr_bit == sring->desc_rdy_pol) {
1151 num_descs = msg.num_descriptors;
1153 wil_err(wil, "invalid num_descs 0\n");
1157 /* Find the corresponding descriptor ring */
1158 ring_id = msg.ring_id;
1160 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) {
1161 wil_err(wil, "invalid ring id %d\n", ring_id);
1164 ring = &wil->ring_tx[ring_id];
1165 if (unlikely(!ring->va)) {
1166 wil_err(wil, "Tx irq[%d]: ring not initialized\n",
1170 txdata = &wil->ring_tx_data[ring_id];
1171 if (unlikely(!txdata->enabled)) {
1172 wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id);
1175 vif = wil->vifs[txdata->mid];
1176 if (unlikely(!vif)) {
1177 wil_dbg_txrx(wil, "invalid MID %d for ring %d\n",
1178 txdata->mid, ring_id);
1182 ndev = vif_to_ndev(vif);
1184 cid = wil->ring2cid_tid[ring_id][0];
1185 if (cid < WIL6210_MAX_CID)
1186 stats = &wil->sta[cid].stats;
1189 "tx_status: completed desc_ring (%d), num_descs (%d)\n",
1190 ring_id, num_descs);
1192 used_before_complete = wil_ring_used_tx(ring);
1194 for (i = 0 ; i < num_descs; ++i) {
1195 struct wil_ctx *ctx = &ring->ctx[ring->swtail];
1196 struct wil_tx_enhanced_desc dd, *d = ⅆ
1198 struct sk_buff *skb = ctx->skb;
1200 _d = (struct wil_tx_enhanced_desc *)
1201 &ring->va[ring->swtail].tx.enhanced;
1204 dmalen = le16_to_cpu(d->dma.length);
1205 trace_wil6210_tx_status(&msg, ring->swtail, dmalen);
1207 "TxC[%2d][%3d] : %d bytes, status 0x%02x\n",
1208 ring_id, ring->swtail, dmalen,
1210 wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4,
1211 (const void *)&msg, sizeof(msg),
1214 wil_tx_desc_unmap_edma(dev,
1215 (union wil_tx_desc *)d,
1219 if (likely(msg.status == 0)) {
1220 ndev->stats.tx_packets++;
1221 ndev->stats.tx_bytes += skb->len;
1223 stats->tx_packets++;
1224 stats->tx_bytes += skb->len;
1226 wil_tx_latency_calc(wil, skb,
1230 ndev->stats.tx_errors++;
1234 wil_consume_skb(skb, msg.status == 0);
1236 memset(ctx, 0, sizeof(*ctx));
1237 /* Make sure the ctx is zeroed before updating the tail
1238 * to prevent a case where wil_tx_ring will see
1239 * this descriptor as used and handle it before ctx zero
1244 ring->swtail = wil_ring_next_tail(ring);
1249 /* performance monitoring */
1250 used_new = wil_ring_used_tx(ring);
1251 if (wil_val_in_range(wil->ring_idle_trsh,
1252 used_new, used_before_complete)) {
1253 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n",
1254 ring_id, used_before_complete, used_new);
1255 txdata->last_idle = get_cycles();
1259 wil_sring_advance_swhead(sring);
1261 wil_get_next_tx_status_msg(sring, &msg);
1262 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS;
1265 /* shall we wake net queues? */
1267 wil_update_net_queues(wil, vif, NULL, false);
1269 /* Update the HW tail ptr (RD ptr) */
1270 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size);
1276 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding
1277 * @skb is used to obtain the protocol and headers length.
1278 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data,
1279 * 2 - middle, 3 - last descriptor.
1281 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d,
1282 int tso_desc_type, bool is_ipv4,
1284 int skb_net_hdr_len,
1287 /* Number of descriptors */
1289 /* Maximum Segment Size */
1290 d->mac.tso_mss |= cpu_to_le16(mss >> 2);
1291 /* L4 header len: TCP header length */
1292 d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK;
1293 /* EOP, TSO desc type, Segmentation enable,
1294 * Insert IPv4 and TCP / UDP Checksum
1296 d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) |
1297 tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS |
1298 BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) |
1299 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) |
1300 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS);
1301 /* Calculate pseudo-header */
1302 d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) |
1303 BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS);
1304 /* IP Header Length */
1305 d->dma.ip_length |= skb_net_hdr_len;
1306 /* MAC header length and IP address family*/
1307 d->dma.b11 |= ETH_HLEN |
1308 is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS;
1311 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr,
1312 int len, uint i, int tso_desc_type,
1313 skb_frag_t *frag, struct wil_ring *ring,
1314 struct sk_buff *skb, bool is_ipv4,
1315 int tcp_hdr_len, int skb_net_hdr_len,
1316 int mss, int *descs_used)
1318 struct device *dev = wil_to_dev(wil);
1319 struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *)
1320 &ring->va[i].tx.enhanced;
1321 struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem;
1322 int ring_index = ring - wil->ring_tx;
1329 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE);
1330 ring->ctx[i].mapped_as = wil_mapped_as_single;
1332 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE);
1333 ring->ctx[i].mapped_as = wil_mapped_as_page;
1335 if (unlikely(dma_mapping_error(dev, pa))) {
1336 wil_err(wil, "TSO: Skb DMA map error\n");
1340 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa,
1342 wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4,
1344 skb_net_hdr_len, mss);
1346 /* hold reference to skb
1347 * to prevent skb release before accounting
1348 * in case of immediate "tx done"
1350 if (tso_desc_type == wil_tso_type_lst)
1351 ring->ctx[i].skb = skb_get(skb);
1353 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4,
1354 (const void *)d, sizeof(*d), false);
1362 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil,
1363 struct wil6210_vif *vif,
1364 struct wil_ring *ring,
1365 struct sk_buff *skb)
1367 int ring_index = ring - wil->ring_tx;
1368 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index];
1369 int nr_frags = skb_shinfo(skb)->nr_frags;
1370 int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */
1371 int used, avail = wil_ring_avail_tx(ring);
1372 int f, hdrlen, headlen;
1375 u32 swhead = ring->swhead;
1376 int descs_used = 0; /* total number of used descriptors */
1379 int skb_net_hdr_len;
1380 int mss = skb_shinfo(skb)->gso_size;
1382 wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len,
1385 if (unlikely(!txdata->enabled))
1388 if (unlikely(avail < min_desc_required)) {
1389 wil_err_ratelimited(wil,
1390 "TSO: Tx ring[%2d] full. No space for %d fragments\n",
1391 ring_index, min_desc_required);
1395 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4);
1407 if (skb->ip_summed != CHECKSUM_PARTIAL)
1410 /* tcp header length and skb network header length are fixed for all
1411 * packet's descriptors - read them once here
1413 tcp_hdr_len = tcp_hdrlen(skb);
1414 skb_net_hdr_len = skb_network_header_len(skb);
1416 /* First descriptor must contain the header only
1417 * Header Length = MAC header len + IP header len + TCP header len
1419 hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len;
1420 wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n",
1422 rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead,
1423 wil_tso_type_hdr, NULL, ring, skb,
1424 is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1429 /* Second descriptor contains the head */
1430 headlen = skb_headlen(skb) - hdrlen;
1431 wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen);
1432 rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen,
1433 (swhead + descs_used) % ring->size,
1434 (nr_frags != 0) ? wil_tso_type_first :
1435 wil_tso_type_lst, NULL, ring, skb,
1436 is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1441 /* Rest of the descriptors are from the SKB fragments */
1442 for (f = 0; f < nr_frags; f++) {
1443 skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1444 int len = frag->size;
1446 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f,
1449 rc = wil_tx_tso_gen_desc(wil, NULL, len,
1450 (swhead + descs_used) % ring->size,
1451 (f != nr_frags - 1) ?
1452 wil_tso_type_mid : wil_tso_type_lst,
1453 frag, ring, skb, is_ipv4,
1454 tcp_hdr_len, skb_net_hdr_len,
1460 /* performance monitoring */
1461 used = wil_ring_used_tx(ring);
1462 if (wil_val_in_range(wil->ring_idle_trsh,
1463 used, used + descs_used)) {
1464 txdata->idle += get_cycles() - txdata->last_idle;
1465 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n",
1466 ring_index, used, used + descs_used);
1469 /* advance swhead */
1470 wil_ring_advance_head(ring, descs_used);
1471 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead);
1473 /* make sure all writes to descriptors (shared memory) are done before
1474 * committing them to HW
1478 if (wil->tx_latency)
1479 *(ktime_t *)&skb->cb = ktime_get();
1481 memset(skb->cb, 0, sizeof(ktime_t));
1483 wil_w(wil, ring->hwtail, ring->swhead);
1488 while (descs_used > 0) {
1489 struct device *dev = wil_to_dev(wil);
1490 struct wil_ctx *ctx;
1491 int i = (swhead + descs_used - 1) % ring->size;
1492 struct wil_tx_enhanced_desc dd, *d = ⅆ
1493 struct wil_tx_enhanced_desc *_desc =
1494 (struct wil_tx_enhanced_desc *)
1495 &ring->va[i].tx.enhanced;
1498 ctx = &ring->ctx[i];
1499 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx);
1500 memset(ctx, 0, sizeof(*ctx));
1506 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id,
1509 struct wil6210_priv *wil = vif_to_wil(vif);
1510 struct wil_ring *ring = &wil->ring_tx[ring_id];
1512 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
1514 wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n",
1515 ring_id, wil->tx_sring_idx);
1517 lockdep_assert_held(&wil->mutex);
1519 wil_tx_data_init(txdata);
1521 ring->is_rx = false;
1522 rc = wil_ring_alloc_desc_ring(wil, ring);
1526 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */
1527 wil->ring2cid_tid[ring_id][1] = 0; /* TID */
1529 txdata->dot1x_open = true;
1531 rc = wil_wmi_bcast_desc_ring_add(vif, ring_id);
1538 spin_lock_bh(&txdata->lock);
1539 txdata->enabled = 0;
1540 txdata->dot1x_open = false;
1541 spin_unlock_bh(&txdata->lock);
1542 wil_ring_free_edma(wil, ring);
1548 static void wil_tx_fini_edma(struct wil6210_priv *wil)
1550 struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx];
1552 wil_dbg_misc(wil, "free TX sring\n");
1554 wil_sring_free(wil, sring);
1557 static void wil_rx_data_free(struct wil_status_ring *sring)
1562 kfree_skb(sring->rx_data.skb);
1563 sring->rx_data.skb = NULL;
1566 static void wil_rx_fini_edma(struct wil6210_priv *wil)
1568 struct wil_ring *ring = &wil->ring_rx;
1571 wil_dbg_misc(wil, "rx_fini_edma\n");
1573 wil_ring_free_edma(wil, ring);
1575 for (i = 0; i < wil->num_rx_status_rings; i++) {
1576 wil_rx_data_free(&wil->srings[i]);
1577 wil_sring_free(wil, &wil->srings[i]);
1580 wil_free_rx_buff_arr(wil);
1583 void wil_init_txrx_ops_edma(struct wil6210_priv *wil)
1585 wil->txrx_ops.configure_interrupt_moderation =
1586 wil_configure_interrupt_moderation_edma;
1588 wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma;
1589 wil->txrx_ops.ring_fini_tx = wil_ring_free_edma;
1590 wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma;
1591 wil->txrx_ops.tx_init = wil_tx_init_edma;
1592 wil->txrx_ops.tx_fini = wil_tx_fini_edma;
1593 wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma;
1594 wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma;
1595 wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma;
1597 wil->txrx_ops.rx_init = wil_rx_init_edma;
1598 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma;
1599 wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma;
1600 wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma;
1601 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma;
1602 wil->txrx_ops.rx_error_check = wil_rx_error_check_edma;
1603 wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma;
1604 wil->txrx_ops.rx_fini = wil_rx_fini_edma;