2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/interrupt.h>
24 * Theory of operation:
26 * There is ISR pseudo-cause register,
27 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
28 * Its bits represents OR'ed bits from 3 real ISR registers:
31 * Registers may be configured to either "write 1 to clear" or
32 * "clear on read" mode
34 * When handling interrupt, one have to mask/unmask interrupts for the
35 * real ISR registers, or hardware may malfunction.
39 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
40 #define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL)
41 #define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \
42 BIT_DMA_EP_RX_ICR_RX_HTRSH)
43 #define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \
44 (~(BIT_DMA_EP_RX_ICR_RX_HTRSH)))
45 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
46 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
47 #define WIL6210_IMC_TX_EDMA BIT_TX_STATUS_IRQ
48 #define WIL6210_IMC_RX_EDMA BIT_RX_STATUS_IRQ
49 #define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \
52 #define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \
53 BIT_DMA_EP_MISC_ICR_HALP)
54 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
55 BIT_DMA_PSEUDO_CAUSE_TX | \
56 BIT_DMA_PSEUDO_CAUSE_MISC))
58 #if defined(CONFIG_WIL6210_ISR_COR)
59 /* configure to Clear-On-Read mode */
60 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
61 #define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL)
63 static inline void wil_icr_clear(u32 x, void __iomem *addr)
66 #else /* defined(CONFIG_WIL6210_ISR_COR) */
67 /* configure to Write-1-to-Clear mode */
68 #define WIL_ICR_ICC_VALUE (0UL)
69 #define WIL_ICR_ICC_MISC_VALUE (0UL)
71 static inline void wil_icr_clear(u32 x, void __iomem *addr)
75 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
77 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
81 wil_icr_clear(x, addr);
86 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
88 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
92 static void wil6210_mask_irq_tx_edma(struct wil6210_priv *wil)
94 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS),
98 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
100 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
101 WIL6210_IRQ_DISABLE);
104 static void wil6210_mask_irq_rx_edma(struct wil6210_priv *wil)
106 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS),
107 WIL6210_IRQ_DISABLE);
110 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
112 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",
113 mask_halp ? "true" : "false");
115 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
116 mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP);
119 void wil6210_mask_halp(struct wil6210_priv *wil)
121 wil_dbg_irq(wil, "mask_halp\n");
123 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
124 BIT_DMA_EP_MISC_ICR_HALP);
127 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
129 wil_dbg_irq(wil, "mask_irq_pseudo\n");
131 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
133 clear_bit(wil_status_irqen, wil->status);
136 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
138 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
142 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil)
144 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC),
145 WIL6210_IMC_TX_EDMA);
148 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
150 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0;
152 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
153 unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH);
156 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil)
158 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC),
159 WIL6210_IMC_RX_EDMA);
162 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
164 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",
165 unmask_halp ? "true" : "false");
167 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
168 unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP);
171 static void wil6210_unmask_halp(struct wil6210_priv *wil)
173 wil_dbg_irq(wil, "unmask_halp\n");
175 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
176 BIT_DMA_EP_MISC_ICR_HALP);
179 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
181 wil_dbg_irq(wil, "unmask_irq_pseudo\n");
183 set_bit(wil_status_irqen, wil->status);
185 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
188 void wil_mask_irq(struct wil6210_priv *wil)
190 wil_dbg_irq(wil, "mask_irq\n");
192 wil6210_mask_irq_tx(wil);
193 wil6210_mask_irq_tx_edma(wil);
194 wil6210_mask_irq_rx(wil);
195 wil6210_mask_irq_rx_edma(wil);
196 wil6210_mask_irq_misc(wil, true);
197 wil6210_mask_irq_pseudo(wil);
200 void wil_unmask_irq(struct wil6210_priv *wil)
202 wil_dbg_irq(wil, "unmask_irq\n");
204 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
206 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
208 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
209 WIL_ICR_ICC_MISC_VALUE);
210 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC),
212 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC),
215 wil6210_unmask_irq_pseudo(wil);
216 if (wil->use_enhanced_dma_hw) {
217 wil6210_unmask_irq_tx_edma(wil);
218 wil6210_unmask_irq_rx_edma(wil);
220 wil6210_unmask_irq_tx(wil);
221 wil6210_unmask_irq_rx(wil);
223 wil6210_unmask_irq_misc(wil, true);
226 void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil)
230 wil_s(wil, RGF_INT_GEN_IDLE_TIME_LIMIT, WIL_EDMA_IDLE_TIME_LIMIT_USEC);
232 wil_s(wil, RGF_INT_GEN_TIME_UNIT_LIMIT, WIL_EDMA_TIME_UNIT_CLK_CYCLES);
234 /* Update RX and TX moderation */
235 moderation = wil->rx_max_burst_duration |
236 (WIL_EDMA_AGG_WATERMARK << WIL_EDMA_AGG_WATERMARK_POS);
237 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation);
238 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation);
240 /* Treat special events as regular
241 * (set bit 0 to 0x1 and clear bits 1-8)
243 wil_c(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1FE);
244 wil_s(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1);
247 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
249 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr;
251 wil_dbg_irq(wil, "configure_interrupt_moderation\n");
253 /* disable interrupt moderation for monitor
254 * to get better timestamp precision
256 if (wdev->iftype == NL80211_IFTYPE_MONITOR)
259 /* Disable and clear tx counter before (re)configuration */
260 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
261 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
262 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
263 wil->tx_max_burst_duration);
264 /* Configure TX max burst duration timer to use usec units */
265 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
266 BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);
268 /* Disable and clear tx idle counter before (re)configuration */
269 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
270 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
271 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
272 wil->tx_interframe_timeout);
273 /* Configure TX max burst duration timer to use usec units */
274 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
275 BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);
277 /* Disable and clear rx counter before (re)configuration */
278 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
279 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
280 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
281 wil->rx_max_burst_duration);
282 /* Configure TX max burst duration timer to use usec units */
283 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
284 BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);
286 /* Disable and clear rx idle counter before (re)configuration */
287 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
288 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
289 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
290 wil->rx_interframe_timeout);
291 /* Configure TX max burst duration timer to use usec units */
292 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
293 BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
296 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
298 struct wil6210_priv *wil = cookie;
300 bool need_unmask = true;
302 wil6210_mask_irq_rx(wil);
304 isr = wil_ioread32_and_clear(wil->csr +
305 HOSTADDR(RGF_DMA_EP_RX_ICR) +
306 offsetof(struct RGF_ICR, ICR));
308 trace_wil6210_irq_rx(isr);
309 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
311 if (unlikely(!isr)) {
312 wil_err_ratelimited(wil, "spurious IRQ: RX\n");
313 wil6210_unmask_irq_rx(wil);
317 /* RX_DONE and RX_HTRSH interrupts are the same if interrupt
318 * moderation is not used. Interrupt moderation may cause RX
319 * buffer overflow while RX_DONE is delayed. The required
320 * action is always the same - should empty the accumulated
321 * packets from the RX ring.
323 if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE |
324 BIT_DMA_EP_RX_ICR_RX_HTRSH))) {
325 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
328 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE |
329 BIT_DMA_EP_RX_ICR_RX_HTRSH);
330 if (likely(test_bit(wil_status_fwready, wil->status))) {
331 if (likely(test_bit(wil_status_napi_en, wil->status))) {
332 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
334 napi_schedule(&wil->napi_rx);
338 "Got Rx interrupt while stopping interface\n");
341 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n");
346 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
348 /* Rx IRQ will be enabled when NAPI processing finished */
350 atomic_inc(&wil->isr_count_rx);
352 if (unlikely(need_unmask))
353 wil6210_unmask_irq_rx(wil);
358 static irqreturn_t wil6210_irq_rx_edma(int irq, void *cookie)
360 struct wil6210_priv *wil = cookie;
362 bool need_unmask = true;
364 wil6210_mask_irq_rx_edma(wil);
366 isr = wil_ioread32_and_clear(wil->csr +
367 HOSTADDR(RGF_INT_GEN_RX_ICR) +
368 offsetof(struct RGF_ICR, ICR));
370 trace_wil6210_irq_rx(isr);
371 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
373 if (unlikely(!isr)) {
374 wil_err(wil, "spurious IRQ: RX\n");
375 wil6210_unmask_irq_rx_edma(wil);
379 if (likely(isr & BIT_RX_STATUS_IRQ)) {
380 wil_dbg_irq(wil, "RX status ring\n");
381 isr &= ~BIT_RX_STATUS_IRQ;
382 if (likely(test_bit(wil_status_fwready, wil->status))) {
383 if (likely(test_bit(wil_status_napi_en, wil->status))) {
384 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
386 napi_schedule(&wil->napi_rx);
389 "Got Rx interrupt while stopping interface\n");
392 wil_err(wil, "Got Rx interrupt while in reset\n");
397 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
399 /* Rx IRQ will be enabled when NAPI processing finished */
401 atomic_inc(&wil->isr_count_rx);
403 if (unlikely(need_unmask))
404 wil6210_unmask_irq_rx_edma(wil);
409 static irqreturn_t wil6210_irq_tx_edma(int irq, void *cookie)
411 struct wil6210_priv *wil = cookie;
413 bool need_unmask = true;
415 wil6210_mask_irq_tx_edma(wil);
417 isr = wil_ioread32_and_clear(wil->csr +
418 HOSTADDR(RGF_INT_GEN_TX_ICR) +
419 offsetof(struct RGF_ICR, ICR));
421 trace_wil6210_irq_tx(isr);
422 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
424 if (unlikely(!isr)) {
425 wil_err(wil, "spurious IRQ: TX\n");
426 wil6210_unmask_irq_tx_edma(wil);
430 if (likely(isr & BIT_TX_STATUS_IRQ)) {
431 wil_dbg_irq(wil, "TX status ring\n");
432 isr &= ~BIT_TX_STATUS_IRQ;
433 if (likely(test_bit(wil_status_fwready, wil->status))) {
434 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
436 napi_schedule(&wil->napi_tx);
438 wil_err(wil, "Got Tx status ring IRQ while in reset\n");
443 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
445 /* Tx IRQ will be enabled when NAPI processing finished */
447 atomic_inc(&wil->isr_count_tx);
449 if (unlikely(need_unmask))
450 wil6210_unmask_irq_tx_edma(wil);
455 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
457 struct wil6210_priv *wil = cookie;
459 bool need_unmask = true;
461 wil6210_mask_irq_tx(wil);
463 isr = wil_ioread32_and_clear(wil->csr +
464 HOSTADDR(RGF_DMA_EP_TX_ICR) +
465 offsetof(struct RGF_ICR, ICR));
467 trace_wil6210_irq_tx(isr);
468 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
470 if (unlikely(!isr)) {
471 wil_err_ratelimited(wil, "spurious IRQ: TX\n");
472 wil6210_unmask_irq_tx(wil);
476 if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) {
477 wil_dbg_irq(wil, "TX done\n");
478 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
479 /* clear also all VRING interrupts */
480 isr &= ~(BIT(25) - 1UL);
481 if (likely(test_bit(wil_status_fwready, wil->status))) {
482 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
484 napi_schedule(&wil->napi_tx);
486 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n");
491 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n",
494 /* Tx IRQ will be enabled when NAPI processing finished */
496 atomic_inc(&wil->isr_count_tx);
498 if (unlikely(need_unmask))
499 wil6210_unmask_irq_tx(wil);
504 static void wil_notify_fw_error(struct wil6210_priv *wil)
506 struct device *dev = &wil->main_ndev->dev;
508 [0] = "SOURCE=wil6210",
509 [1] = "EVENT=FW_ERROR",
512 wil_err(wil, "Notify about firmware error\n");
513 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
516 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
518 /* make shadow copy of registers that should not change on run time */
519 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
520 sizeof(struct wil6210_mbox_ctl));
521 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
522 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
525 static bool wil_validate_mbox_regs(struct wil6210_priv *wil)
527 size_t min_size = sizeof(struct wil6210_mbox_hdr) +
528 sizeof(struct wmi_cmd_hdr);
530 if (wil->mbox_ctl.rx.entry_size < min_size) {
531 wil_err(wil, "rx mbox entry too small (%d)\n",
532 wil->mbox_ctl.rx.entry_size);
535 if (wil->mbox_ctl.tx.entry_size < min_size) {
536 wil_err(wil, "tx mbox entry too small (%d)\n",
537 wil->mbox_ctl.tx.entry_size);
544 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
546 struct wil6210_priv *wil = cookie;
549 wil6210_mask_irq_misc(wil, false);
551 isr = wil_ioread32_and_clear(wil->csr +
552 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
553 offsetof(struct RGF_ICR, ICR));
555 trace_wil6210_irq_misc(isr);
556 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
559 wil_err(wil, "spurious IRQ: MISC\n");
560 wil6210_unmask_irq_misc(wil, false);
564 if (isr & ISR_MISC_FW_ERROR) {
565 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr);
566 u32 ucode_assert_code =
567 wil_r(wil, wil->rgf_ucode_assert_code_addr);
570 "Firmware error detected, assert codes FW 0x%08x, UCODE 0x%08x\n",
571 fw_assert_code, ucode_assert_code);
572 clear_bit(wil_status_fwready, wil->status);
574 * do not clear @isr here - we do 2-nd part in thread
575 * there, user space get notified, and it should be done
576 * in non-atomic context
580 if (isr & ISR_MISC_FW_READY) {
581 wil_dbg_irq(wil, "IRQ: FW ready\n");
582 wil_cache_mbox_regs(wil);
583 if (wil_validate_mbox_regs(wil))
584 set_bit(wil_status_mbox_ready, wil->status);
586 * Actual FW ready indicated by the
587 * WMI_FW_READY_EVENTID
589 isr &= ~ISR_MISC_FW_READY;
592 if (isr & BIT_DMA_EP_MISC_ICR_HALP) {
593 isr &= ~BIT_DMA_EP_MISC_ICR_HALP;
594 if (wil->halp.handle_icr) {
595 /* no need to handle HALP ICRs until next vote */
596 wil->halp.handle_icr = false;
597 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");
598 wil6210_mask_halp(wil);
599 complete(&wil->halp.comp);
606 return IRQ_WAKE_THREAD;
608 wil6210_unmask_irq_misc(wil, false);
613 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
615 struct wil6210_priv *wil = cookie;
616 u32 isr = wil->isr_misc;
618 trace_wil6210_irq_misc_thread(isr);
619 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
621 if (isr & ISR_MISC_FW_ERROR) {
622 wil->recovery_state = fw_recovery_pending;
623 wil_fw_core_dump(wil);
624 wil_notify_fw_error(wil);
625 isr &= ~ISR_MISC_FW_ERROR;
626 if (wil->platform_ops.notify) {
627 wil_err(wil, "notify platform driver about FW crash");
628 wil->platform_ops.notify(wil->platform_handle,
629 WIL_PLATFORM_EVT_FW_CRASH);
631 wil_fw_error_recovery(wil);
634 if (isr & ISR_MISC_MBOX_EVT) {
635 wil_dbg_irq(wil, "MBOX event\n");
637 isr &= ~ISR_MISC_MBOX_EVT;
641 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
645 wil6210_unmask_irq_misc(wil, false);
647 /* in non-triple MSI case, this is done inside wil6210_thread_irq
648 * because it has to be done after unmasking the pseudo.
650 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) {
651 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
652 wil->suspend_resp_comp = true;
653 wake_up_interruptible(&wil->wq);
662 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
664 struct wil6210_priv *wil = cookie;
666 wil_dbg_irq(wil, "Thread IRQ\n");
667 /* Discover real IRQ cause */
669 wil6210_irq_misc_thread(irq, cookie);
671 wil6210_unmask_irq_pseudo(wil);
673 if (wil->suspend_resp_rcvd) {
674 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
675 wil->suspend_resp_comp = true;
676 wake_up_interruptible(&wil->wq);
683 * There is subtle bug in hardware that causes IRQ to raise when it should be
684 * masked. It is quite rare and hard to debug.
686 * Catch irq issue if it happens and print all I can.
688 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
690 u32 icm_rx, icr_rx, imv_rx;
691 u32 icm_tx, icr_tx, imv_tx;
692 u32 icm_misc, icr_misc, imv_misc;
694 if (!test_bit(wil_status_irqen, wil->status)) {
695 if (wil->use_enhanced_dma_hw) {
696 icm_rx = wil_ioread32_and_clear(wil->csr +
697 HOSTADDR(RGF_INT_GEN_RX_ICR) +
698 offsetof(struct RGF_ICR, ICM));
699 icr_rx = wil_ioread32_and_clear(wil->csr +
700 HOSTADDR(RGF_INT_GEN_RX_ICR) +
701 offsetof(struct RGF_ICR, ICR));
702 imv_rx = wil_r(wil, RGF_INT_GEN_RX_ICR +
703 offsetof(struct RGF_ICR, IMV));
704 icm_tx = wil_ioread32_and_clear(wil->csr +
705 HOSTADDR(RGF_INT_GEN_TX_ICR) +
706 offsetof(struct RGF_ICR, ICM));
707 icr_tx = wil_ioread32_and_clear(wil->csr +
708 HOSTADDR(RGF_INT_GEN_TX_ICR) +
709 offsetof(struct RGF_ICR, ICR));
710 imv_tx = wil_r(wil, RGF_INT_GEN_TX_ICR +
711 offsetof(struct RGF_ICR, IMV));
713 icm_rx = wil_ioread32_and_clear(wil->csr +
714 HOSTADDR(RGF_DMA_EP_RX_ICR) +
715 offsetof(struct RGF_ICR, ICM));
716 icr_rx = wil_ioread32_and_clear(wil->csr +
717 HOSTADDR(RGF_DMA_EP_RX_ICR) +
718 offsetof(struct RGF_ICR, ICR));
719 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
720 offsetof(struct RGF_ICR, IMV));
721 icm_tx = wil_ioread32_and_clear(wil->csr +
722 HOSTADDR(RGF_DMA_EP_TX_ICR) +
723 offsetof(struct RGF_ICR, ICM));
724 icr_tx = wil_ioread32_and_clear(wil->csr +
725 HOSTADDR(RGF_DMA_EP_TX_ICR) +
726 offsetof(struct RGF_ICR, ICR));
727 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
728 offsetof(struct RGF_ICR, IMV));
730 icm_misc = wil_ioread32_and_clear(wil->csr +
731 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
732 offsetof(struct RGF_ICR, ICM));
733 icr_misc = wil_ioread32_and_clear(wil->csr +
734 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
735 offsetof(struct RGF_ICR, ICR));
736 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
737 offsetof(struct RGF_ICR, IMV));
739 /* HALP interrupt can be unmasked when misc interrupts are
742 if (icr_misc & BIT_DMA_EP_MISC_ICR_HALP)
745 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
746 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
747 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
748 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
750 icm_rx, icr_rx, imv_rx,
751 icm_tx, icr_tx, imv_tx,
752 icm_misc, icr_misc, imv_misc);
760 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
762 irqreturn_t rc = IRQ_HANDLED;
763 struct wil6210_priv *wil = cookie;
764 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
767 * pseudo_cause is Clear-On-Read, no need to ACK
769 if (unlikely((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff)))
773 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause)))
776 trace_wil6210_irq_pseudo(pseudo_cause);
777 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
779 wil6210_mask_irq_pseudo(wil);
781 /* Discover real IRQ cause
782 * There are 2 possible phases for every IRQ:
783 * - hard IRQ handler called right here
784 * - threaded handler called later
786 * Hard IRQ handler reads and clears ISR.
788 * If threaded handler requested, hard IRQ handler
789 * returns IRQ_WAKE_THREAD and saves ISR register value
790 * for the threaded handler use.
792 * voting for wake thread - need at least 1 vote
794 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
795 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
796 rc = IRQ_WAKE_THREAD;
798 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
799 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
800 rc = IRQ_WAKE_THREAD;
802 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
803 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
804 rc = IRQ_WAKE_THREAD;
806 /* if thread is requested, it will unmask IRQ */
807 if (rc != IRQ_WAKE_THREAD)
808 wil6210_unmask_irq_pseudo(wil);
813 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
817 /* IRQ's are in the following order:
822 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED,
823 WIL_NAME "_tx", wil);
827 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED,
828 WIL_NAME "_rx", wil);
832 rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
833 wil6210_irq_misc_thread,
834 IRQF_SHARED, WIL_NAME "_misc", wil);
840 free_irq(irq + 1, wil);
847 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
848 static inline void wil_clear32(void __iomem *addr)
855 void wil6210_clear_irq(struct wil6210_priv *wil)
857 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
858 offsetof(struct RGF_ICR, ICR));
859 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
860 offsetof(struct RGF_ICR, ICR));
861 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) +
862 offsetof(struct RGF_ICR, ICR));
863 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) +
864 offsetof(struct RGF_ICR, ICR));
865 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
866 offsetof(struct RGF_ICR, ICR));
867 wmb(); /* make sure write completed */
870 void wil6210_set_halp(struct wil6210_priv *wil)
872 wil_dbg_irq(wil, "set_halp\n");
874 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
875 BIT_DMA_EP_MISC_ICR_HALP);
878 void wil6210_clear_halp(struct wil6210_priv *wil)
880 wil_dbg_irq(wil, "clear_halp\n");
882 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
883 BIT_DMA_EP_MISC_ICR_HALP);
884 wil6210_unmask_halp(wil);
887 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
891 wil_dbg_misc(wil, "init_irq: %s, n_msi=%d\n",
892 wil->n_msi ? "MSI" : "INTx", wil->n_msi);
894 if (wil->use_enhanced_dma_hw) {
895 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma;
896 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma;
898 wil->txrx_ops.irq_tx = wil6210_irq_tx;
899 wil->txrx_ops.irq_rx = wil6210_irq_rx;
903 rc = wil6210_request_3msi(wil, irq);
905 rc = request_threaded_irq(irq, wil6210_hardirq,
907 wil->n_msi ? 0 : IRQF_SHARED,
912 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
914 wil_dbg_misc(wil, "fini_irq:\n");
918 if (wil->n_msi == 3) {
919 free_irq(irq + 1, wil);
920 free_irq(irq + 2, wil);