2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/interrupt.h>
23 * Theory of operation:
25 * There is ISR pseudo-cause register,
26 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
27 * Its bits represents OR'ed bits from 3 real ISR registers:
30 * Registers may be configured to either "write 1 to clear" or
31 * "clear on read" mode
33 * When handling interrupt, one have to mask/unmask interrupts for the
34 * real ISR registers, or hardware may malfunction.
38 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
39 #define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL)
40 #define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \
41 BIT_DMA_EP_RX_ICR_RX_HTRSH)
42 #define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \
43 (~(BIT_DMA_EP_RX_ICR_RX_HTRSH)))
44 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
45 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
46 #define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \
49 #define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \
50 BIT_DMA_EP_MISC_ICR_HALP)
51 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
52 BIT_DMA_PSEUDO_CAUSE_TX | \
53 BIT_DMA_PSEUDO_CAUSE_MISC))
55 #if defined(CONFIG_WIL6210_ISR_COR)
56 /* configure to Clear-On-Read mode */
57 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
58 #define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL)
60 static inline void wil_icr_clear(u32 x, void __iomem *addr)
63 #else /* defined(CONFIG_WIL6210_ISR_COR) */
64 /* configure to Write-1-to-Clear mode */
65 #define WIL_ICR_ICC_VALUE (0UL)
66 #define WIL_ICR_ICC_MISC_VALUE (0UL)
68 static inline void wil_icr_clear(u32 x, void __iomem *addr)
72 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
74 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
78 wil_icr_clear(x, addr);
83 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
85 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
89 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
91 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
95 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
97 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",
98 mask_halp ? "true" : "false");
100 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
101 mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP);
104 void wil6210_mask_halp(struct wil6210_priv *wil)
106 wil_dbg_irq(wil, "mask_halp\n");
108 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
109 BIT_DMA_EP_MISC_ICR_HALP);
112 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
114 wil_dbg_irq(wil, "mask_irq_pseudo\n");
116 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
118 clear_bit(wil_status_irqen, wil->status);
121 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
123 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
127 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
129 bool unmask_rx_htrsh = test_bit(wil_status_fwconnected, wil->status);
131 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
132 unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH);
135 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
137 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",
138 unmask_halp ? "true" : "false");
140 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
141 unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP);
144 static void wil6210_unmask_halp(struct wil6210_priv *wil)
146 wil_dbg_irq(wil, "unmask_halp\n");
148 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
149 BIT_DMA_EP_MISC_ICR_HALP);
152 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
154 wil_dbg_irq(wil, "unmask_irq_pseudo\n");
156 set_bit(wil_status_irqen, wil->status);
158 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
161 void wil_mask_irq(struct wil6210_priv *wil)
163 wil_dbg_irq(wil, "mask_irq\n");
165 wil6210_mask_irq_tx(wil);
166 wil6210_mask_irq_rx(wil);
167 wil6210_mask_irq_misc(wil, true);
168 wil6210_mask_irq_pseudo(wil);
171 void wil_unmask_irq(struct wil6210_priv *wil)
173 wil_dbg_irq(wil, "unmask_irq\n");
175 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
177 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
179 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
180 WIL_ICR_ICC_MISC_VALUE);
182 wil6210_unmask_irq_pseudo(wil);
183 wil6210_unmask_irq_tx(wil);
184 wil6210_unmask_irq_rx(wil);
185 wil6210_unmask_irq_misc(wil, true);
188 void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
190 wil_dbg_irq(wil, "configure_interrupt_moderation\n");
192 /* disable interrupt moderation for monitor
193 * to get better timestamp precision
195 if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR)
198 /* Disable and clear tx counter before (re)configuration */
199 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
200 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
201 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
202 wil->tx_max_burst_duration);
203 /* Configure TX max burst duration timer to use usec units */
204 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
205 BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);
207 /* Disable and clear tx idle counter before (re)configuration */
208 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
209 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
210 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
211 wil->tx_interframe_timeout);
212 /* Configure TX max burst duration timer to use usec units */
213 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
214 BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);
216 /* Disable and clear rx counter before (re)configuration */
217 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
218 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
219 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
220 wil->rx_max_burst_duration);
221 /* Configure TX max burst duration timer to use usec units */
222 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
223 BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);
225 /* Disable and clear rx idle counter before (re)configuration */
226 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
227 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
228 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
229 wil->rx_interframe_timeout);
230 /* Configure TX max burst duration timer to use usec units */
231 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
232 BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
235 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
237 struct wil6210_priv *wil = cookie;
238 u32 isr = wil_ioread32_and_clear(wil->csr +
239 HOSTADDR(RGF_DMA_EP_RX_ICR) +
240 offsetof(struct RGF_ICR, ICR));
241 bool need_unmask = true;
243 trace_wil6210_irq_rx(isr);
244 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
246 if (unlikely(!isr)) {
247 wil_err_ratelimited(wil, "spurious IRQ: RX\n");
251 wil6210_mask_irq_rx(wil);
253 /* RX_DONE and RX_HTRSH interrupts are the same if interrupt
254 * moderation is not used. Interrupt moderation may cause RX
255 * buffer overflow while RX_DONE is delayed. The required
256 * action is always the same - should empty the accumulated
257 * packets from the RX ring.
259 if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE |
260 BIT_DMA_EP_RX_ICR_RX_HTRSH))) {
261 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
264 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE |
265 BIT_DMA_EP_RX_ICR_RX_HTRSH);
266 if (likely(test_bit(wil_status_fwready, wil->status))) {
267 if (likely(test_bit(wil_status_napi_en, wil->status))) {
268 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
270 napi_schedule(&wil->napi_rx);
274 "Got Rx interrupt while stopping interface\n");
277 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n");
282 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
284 /* Rx IRQ will be enabled when NAPI processing finished */
286 atomic_inc(&wil->isr_count_rx);
288 if (unlikely(need_unmask))
289 wil6210_unmask_irq_rx(wil);
294 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
296 struct wil6210_priv *wil = cookie;
297 u32 isr = wil_ioread32_and_clear(wil->csr +
298 HOSTADDR(RGF_DMA_EP_TX_ICR) +
299 offsetof(struct RGF_ICR, ICR));
300 bool need_unmask = true;
302 trace_wil6210_irq_tx(isr);
303 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
305 if (unlikely(!isr)) {
306 wil_err_ratelimited(wil, "spurious IRQ: TX\n");
310 wil6210_mask_irq_tx(wil);
312 if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) {
313 wil_dbg_irq(wil, "TX done\n");
314 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
315 /* clear also all VRING interrupts */
316 isr &= ~(BIT(25) - 1UL);
317 if (likely(test_bit(wil_status_fwready, wil->status))) {
318 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
320 napi_schedule(&wil->napi_tx);
322 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n");
327 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n",
330 /* Tx IRQ will be enabled when NAPI processing finished */
332 atomic_inc(&wil->isr_count_tx);
334 if (unlikely(need_unmask))
335 wil6210_unmask_irq_tx(wil);
340 static void wil_notify_fw_error(struct wil6210_priv *wil)
342 struct device *dev = &wil_to_ndev(wil)->dev;
344 [0] = "SOURCE=wil6210",
345 [1] = "EVENT=FW_ERROR",
348 wil_err(wil, "Notify about firmware error\n");
349 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
352 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
354 /* make shadow copy of registers that should not change on run time */
355 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
356 sizeof(struct wil6210_mbox_ctl));
357 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
358 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
361 static bool wil_validate_mbox_regs(struct wil6210_priv *wil)
363 size_t min_size = sizeof(struct wil6210_mbox_hdr) +
364 sizeof(struct wmi_cmd_hdr);
366 if (wil->mbox_ctl.rx.entry_size < min_size) {
367 wil_err(wil, "rx mbox entry too small (%d)\n",
368 wil->mbox_ctl.rx.entry_size);
371 if (wil->mbox_ctl.tx.entry_size < min_size) {
372 wil_err(wil, "tx mbox entry too small (%d)\n",
373 wil->mbox_ctl.tx.entry_size);
380 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
382 struct wil6210_priv *wil = cookie;
383 u32 isr = wil_ioread32_and_clear(wil->csr +
384 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
385 offsetof(struct RGF_ICR, ICR));
387 trace_wil6210_irq_misc(isr);
388 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
391 wil_err(wil, "spurious IRQ: MISC\n");
395 wil6210_mask_irq_misc(wil, false);
397 if (isr & ISR_MISC_FW_ERROR) {
398 u32 fw_assert_code = wil_r(wil, RGF_FW_ASSERT_CODE);
399 u32 ucode_assert_code = wil_r(wil, RGF_UCODE_ASSERT_CODE);
402 "Firmware error detected, assert codes FW 0x%08x, UCODE 0x%08x\n",
403 fw_assert_code, ucode_assert_code);
404 clear_bit(wil_status_fwready, wil->status);
406 * do not clear @isr here - we do 2-nd part in thread
407 * there, user space get notified, and it should be done
408 * in non-atomic context
412 if (isr & ISR_MISC_FW_READY) {
413 wil_dbg_irq(wil, "IRQ: FW ready\n");
414 wil_cache_mbox_regs(wil);
415 if (wil_validate_mbox_regs(wil))
416 set_bit(wil_status_mbox_ready, wil->status);
418 * Actual FW ready indicated by the
419 * WMI_FW_READY_EVENTID
421 isr &= ~ISR_MISC_FW_READY;
424 if (isr & BIT_DMA_EP_MISC_ICR_HALP) {
425 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");
426 wil6210_mask_halp(wil);
427 isr &= ~BIT_DMA_EP_MISC_ICR_HALP;
428 complete(&wil->halp.comp);
434 return IRQ_WAKE_THREAD;
436 wil6210_unmask_irq_misc(wil, false);
441 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
443 struct wil6210_priv *wil = cookie;
444 u32 isr = wil->isr_misc;
446 trace_wil6210_irq_misc_thread(isr);
447 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
449 if (isr & ISR_MISC_FW_ERROR) {
450 wil->recovery_state = fw_recovery_pending;
451 wil_fw_core_dump(wil);
452 wil_notify_fw_error(wil);
453 isr &= ~ISR_MISC_FW_ERROR;
454 if (wil->platform_ops.notify) {
455 wil_err(wil, "notify platform driver about FW crash");
456 wil->platform_ops.notify(wil->platform_handle,
457 WIL_PLATFORM_EVT_FW_CRASH);
459 wil_fw_error_recovery(wil);
462 if (isr & ISR_MISC_MBOX_EVT) {
463 wil_dbg_irq(wil, "MBOX event\n");
465 isr &= ~ISR_MISC_MBOX_EVT;
469 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
473 wil6210_unmask_irq_misc(wil, false);
481 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
483 struct wil6210_priv *wil = cookie;
485 wil_dbg_irq(wil, "Thread IRQ\n");
486 /* Discover real IRQ cause */
488 wil6210_irq_misc_thread(irq, cookie);
490 wil6210_unmask_irq_pseudo(wil);
492 if (wil->suspend_resp_rcvd) {
493 wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
494 wil->suspend_resp_comp = true;
495 wake_up_interruptible(&wil->wq);
502 * There is subtle bug in hardware that causes IRQ to raise when it should be
503 * masked. It is quite rare and hard to debug.
505 * Catch irq issue if it happens and print all I can.
507 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
509 if (!test_bit(wil_status_irqen, wil->status)) {
510 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
511 HOSTADDR(RGF_DMA_EP_RX_ICR) +
512 offsetof(struct RGF_ICR, ICM));
513 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
514 HOSTADDR(RGF_DMA_EP_RX_ICR) +
515 offsetof(struct RGF_ICR, ICR));
516 u32 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
517 offsetof(struct RGF_ICR, IMV));
518 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
519 HOSTADDR(RGF_DMA_EP_TX_ICR) +
520 offsetof(struct RGF_ICR, ICM));
521 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
522 HOSTADDR(RGF_DMA_EP_TX_ICR) +
523 offsetof(struct RGF_ICR, ICR));
524 u32 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
525 offsetof(struct RGF_ICR, IMV));
526 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
527 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
528 offsetof(struct RGF_ICR, ICM));
529 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
530 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
531 offsetof(struct RGF_ICR, ICR));
532 u32 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
533 offsetof(struct RGF_ICR, IMV));
535 /* HALP interrupt can be unmasked when misc interrupts are
538 if (icr_misc & BIT_DMA_EP_MISC_ICR_HALP)
541 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
542 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
543 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
544 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
546 icm_rx, icr_rx, imv_rx,
547 icm_tx, icr_tx, imv_tx,
548 icm_misc, icr_misc, imv_misc);
556 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
558 irqreturn_t rc = IRQ_HANDLED;
559 struct wil6210_priv *wil = cookie;
560 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
563 * pseudo_cause is Clear-On-Read, no need to ACK
565 if (unlikely((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff)))
568 /* FIXME: IRQ mask debug */
569 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause)))
572 trace_wil6210_irq_pseudo(pseudo_cause);
573 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
575 wil6210_mask_irq_pseudo(wil);
577 /* Discover real IRQ cause
578 * There are 2 possible phases for every IRQ:
579 * - hard IRQ handler called right here
580 * - threaded handler called later
582 * Hard IRQ handler reads and clears ISR.
584 * If threaded handler requested, hard IRQ handler
585 * returns IRQ_WAKE_THREAD and saves ISR register value
586 * for the threaded handler use.
588 * voting for wake thread - need at least 1 vote
590 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
591 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
592 rc = IRQ_WAKE_THREAD;
594 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
595 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
596 rc = IRQ_WAKE_THREAD;
598 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
599 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
600 rc = IRQ_WAKE_THREAD;
602 /* if thread is requested, it will unmask IRQ */
603 if (rc != IRQ_WAKE_THREAD)
604 wil6210_unmask_irq_pseudo(wil);
609 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
610 static inline void wil_clear32(void __iomem *addr)
617 void wil6210_clear_irq(struct wil6210_priv *wil)
619 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
620 offsetof(struct RGF_ICR, ICR));
621 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
622 offsetof(struct RGF_ICR, ICR));
623 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
624 offsetof(struct RGF_ICR, ICR));
625 wmb(); /* make sure write completed */
628 void wil6210_set_halp(struct wil6210_priv *wil)
630 wil_dbg_irq(wil, "set_halp\n");
632 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
633 BIT_DMA_EP_MISC_ICR_HALP);
636 void wil6210_clear_halp(struct wil6210_priv *wil)
638 wil_dbg_irq(wil, "clear_halp\n");
640 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
641 BIT_DMA_EP_MISC_ICR_HALP);
642 wil6210_unmask_halp(wil);
645 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi)
649 wil_dbg_misc(wil, "init_irq: %s\n", use_msi ? "MSI" : "INTx");
651 rc = request_threaded_irq(irq, wil6210_hardirq,
653 use_msi ? 0 : IRQF_SHARED,
658 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
660 wil_dbg_misc(wil, "fini_irq:\n");