2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq,
54 struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 struct ath_txq *txq, struct list_head *bf_q,
57 struct ieee80211_sta *sta,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
84 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
85 struct ieee80211_sta *sta = info->status.status_driver_data[0];
87 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
88 IEEE80211_TX_STATUS_EOSP)) {
89 ieee80211_tx_status(hw, skb);
94 ieee80211_tx_status_noskb(hw, sta, info);
99 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
100 __acquires(&txq->axq_lock)
102 spin_lock_bh(&txq->axq_lock);
105 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
106 __releases(&txq->axq_lock)
108 spin_unlock_bh(&txq->axq_lock);
111 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
112 __releases(&txq->axq_lock)
114 struct ieee80211_hw *hw = sc->hw;
115 struct sk_buff_head q;
118 __skb_queue_head_init(&q);
119 skb_queue_splice_init(&txq->complete_q, &q);
120 spin_unlock_bh(&txq->axq_lock);
122 while ((skb = __skb_dequeue(&q)))
123 ath_tx_status(hw, skb);
126 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq,
127 struct ath_atx_tid *tid)
129 struct list_head *list;
130 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
131 struct ath_chanctx *ctx = avp->chanctx;
136 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
137 if (list_empty(&tid->list))
138 list_add_tail(&tid->list, list);
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
149 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
154 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
155 seqno << IEEE80211_SEQ_SEQ_SHIFT);
158 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
161 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
162 ARRAY_SIZE(bf->rates));
165 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
168 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
169 struct ath_frame_info *fi = get_frame_info(skb);
175 txq = sc->tx.txq_map[q];
176 if (WARN_ON(--txq->pending_frames < 0))
177 txq->pending_frames = 0;
180 txq->pending_frames < sc->tx.txq_max_pending[q]) {
181 if (ath9k_is_chanctx_enabled())
182 ieee80211_wake_queue(sc->hw, info->hw_queue);
184 ieee80211_wake_queue(sc->hw, q);
185 txq->stopped = false;
189 static struct ath_atx_tid *
190 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
192 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
193 return ATH_AN_2_TID(an, tidno);
196 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
198 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
201 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
205 skb = __skb_dequeue(&tid->retry_q);
207 skb = __skb_dequeue(&tid->buf_q);
213 * ath_tx_tid_change_state:
214 * - clears a-mpdu flag of previous session
215 * - force sequence number allocation to fix next BlockAck Window
218 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
220 struct ath_txq *txq = tid->txq;
221 struct ieee80211_tx_info *tx_info;
222 struct sk_buff *skb, *tskb;
224 struct ath_frame_info *fi;
226 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
227 fi = get_frame_info(skb);
230 tx_info = IEEE80211_SKB_CB(skb);
231 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
236 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
238 __skb_unlink(skb, &tid->buf_q);
239 ath_txq_skb_done(sc, txq, skb);
240 ieee80211_free_txskb(sc->hw, skb);
247 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
249 struct ath_txq *txq = tid->txq;
252 struct list_head bf_head;
253 struct ath_tx_status ts;
254 struct ath_frame_info *fi;
255 bool sendbar = false;
257 INIT_LIST_HEAD(&bf_head);
259 memset(&ts, 0, sizeof(ts));
261 while ((skb = __skb_dequeue(&tid->retry_q))) {
262 fi = get_frame_info(skb);
265 ath_txq_skb_done(sc, txq, skb);
266 ieee80211_free_txskb(sc->hw, skb);
270 if (fi->baw_tracked) {
271 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
275 list_add_tail(&bf->list, &bf_head);
276 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
280 ath_txq_unlock(sc, txq);
281 ath_send_bar(tid, tid->seq_start);
282 ath_txq_lock(sc, txq);
286 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
291 index = ATH_BA_INDEX(tid->seq_start, seqno);
292 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
294 __clear_bit(cindex, tid->tx_buf);
296 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
297 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
298 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
299 if (tid->bar_index >= 0)
304 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
307 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
308 u16 seqno = bf->bf_state.seqno;
311 index = ATH_BA_INDEX(tid->seq_start, seqno);
312 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
313 __set_bit(cindex, tid->tx_buf);
316 if (index >= ((tid->baw_tail - tid->baw_head) &
317 (ATH_TID_MAX_BUFS - 1))) {
318 tid->baw_tail = cindex;
319 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
323 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
324 struct ath_atx_tid *tid)
329 struct list_head bf_head;
330 struct ath_tx_status ts;
331 struct ath_frame_info *fi;
333 memset(&ts, 0, sizeof(ts));
334 INIT_LIST_HEAD(&bf_head);
336 while ((skb = ath_tid_dequeue(tid))) {
337 fi = get_frame_info(skb);
341 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
345 list_add_tail(&bf->list, &bf_head);
346 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
350 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
351 struct sk_buff *skb, int count)
353 struct ath_frame_info *fi = get_frame_info(skb);
354 struct ath_buf *bf = fi->bf;
355 struct ieee80211_hdr *hdr;
356 int prev = fi->retries;
358 TX_STAT_INC(txq->axq_qnum, a_retries);
359 fi->retries += count;
364 hdr = (struct ieee80211_hdr *)skb->data;
365 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
366 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
367 sizeof(*hdr), DMA_TO_DEVICE);
370 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
372 struct ath_buf *bf = NULL;
374 spin_lock_bh(&sc->tx.txbuflock);
376 if (unlikely(list_empty(&sc->tx.txbuf))) {
377 spin_unlock_bh(&sc->tx.txbuflock);
381 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
384 spin_unlock_bh(&sc->tx.txbuflock);
389 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
391 spin_lock_bh(&sc->tx.txbuflock);
392 list_add_tail(&bf->list, &sc->tx.txbuf);
393 spin_unlock_bh(&sc->tx.txbuflock);
396 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
400 tbf = ath_tx_get_buffer(sc);
404 ATH_TXBUF_RESET(tbf);
406 tbf->bf_mpdu = bf->bf_mpdu;
407 tbf->bf_buf_addr = bf->bf_buf_addr;
408 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
409 tbf->bf_state = bf->bf_state;
410 tbf->bf_state.stale = false;
415 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
416 struct ath_tx_status *ts, int txok,
417 int *nframes, int *nbad)
419 struct ath_frame_info *fi;
421 u32 ba[WME_BA_BMP_SIZE >> 5];
428 isaggr = bf_isaggr(bf);
430 seq_st = ts->ts_seqnum;
431 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
435 fi = get_frame_info(bf->bf_mpdu);
436 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
439 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
447 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
448 struct ath_buf *bf, struct list_head *bf_q,
449 struct ieee80211_sta *sta,
450 struct ath_atx_tid *tid,
451 struct ath_tx_status *ts, int txok)
453 struct ath_node *an = NULL;
455 struct ieee80211_hdr *hdr;
456 struct ieee80211_tx_info *tx_info;
457 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
458 struct list_head bf_head;
459 struct sk_buff_head bf_pending;
460 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
461 u32 ba[WME_BA_BMP_SIZE >> 5];
462 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
463 bool rc_update = true, isba;
464 struct ieee80211_tx_rate rates[4];
465 struct ath_frame_info *fi;
467 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
472 hdr = (struct ieee80211_hdr *)skb->data;
474 tx_info = IEEE80211_SKB_CB(skb);
476 memcpy(rates, bf->rates, sizeof(rates));
478 retries = ts->ts_longretry + 1;
479 for (i = 0; i < ts->ts_rateindex; i++)
480 retries += rates[i].count;
483 INIT_LIST_HEAD(&bf_head);
485 bf_next = bf->bf_next;
487 if (!bf->bf_state.stale || bf_next != NULL)
488 list_move_tail(&bf->list, &bf_head);
490 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
497 an = (struct ath_node *)sta->drv_priv;
498 seq_first = tid->seq_start;
499 isba = ts->ts_flags & ATH9K_TX_BA;
502 * The hardware occasionally sends a tx status for the wrong TID.
503 * In this case, the BA status cannot be considered valid and all
504 * subframes need to be retransmitted
506 * Only BlockAcks have a TID and therefore normal Acks cannot be
509 if (isba && tid->tidno != ts->tid)
512 isaggr = bf_isaggr(bf);
513 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
515 if (isaggr && txok) {
516 if (ts->ts_flags & ATH9K_TX_BA) {
517 seq_st = ts->ts_seqnum;
518 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
521 * AR5416 can become deaf/mute when BA
522 * issue happens. Chip needs to be reset.
523 * But AP code may have sychronization issues
524 * when perform internal reset in this routine.
525 * Only enable reset in STA mode for now.
527 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
532 __skb_queue_head_init(&bf_pending);
534 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
536 u16 seqno = bf->bf_state.seqno;
538 txfail = txpending = sendbar = 0;
539 bf_next = bf->bf_next;
542 tx_info = IEEE80211_SKB_CB(skb);
543 fi = get_frame_info(skb);
545 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
548 * Outside of the current BlockAck window,
549 * maybe part of a previous session
552 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
553 /* transmit completion, subframe is
554 * acked by block ack */
556 } else if (!isaggr && txok) {
557 /* transmit completion */
561 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
562 if (txok || !an->sleeping)
563 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
570 bar_index = max_t(int, bar_index,
571 ATH_BA_INDEX(seq_first, seqno));
575 * Make sure the last desc is reclaimed if it
576 * not a holding desc.
578 INIT_LIST_HEAD(&bf_head);
579 if (bf_next != NULL || !bf_last->bf_state.stale)
580 list_move_tail(&bf->list, &bf_head);
584 * complete the acked-ones/xretried ones; update
587 ath_tx_update_baw(sc, tid, seqno);
589 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
590 memcpy(tx_info->control.rates, rates, sizeof(rates));
591 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
593 if (bf == bf->bf_lastbf)
594 ath_dynack_sample_tx_ts(sc->sc_ah,
599 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
602 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
603 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
604 ieee80211_sta_eosp(sta);
606 /* retry the un-acked ones */
607 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
610 tbf = ath_clone_txbuf(sc, bf_last);
612 * Update tx baw and complete the
613 * frame with failed status if we
617 ath_tx_update_baw(sc, tid, seqno);
619 ath_tx_complete_buf(sc, bf, txq,
622 bar_index = max_t(int, bar_index,
623 ATH_BA_INDEX(seq_first, seqno));
631 * Put this buffer to the temporary pending
632 * queue to retain ordering
634 __skb_queue_tail(&bf_pending, skb);
640 /* prepend un-acked frames to the beginning of the pending frame queue */
641 if (!skb_queue_empty(&bf_pending)) {
643 ieee80211_sta_set_buffered(sta, tid->tidno, true);
645 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
647 ath_tx_queue_tid(sc, txq, tid);
649 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
650 tid->clear_ps_filter = true;
654 if (bar_index >= 0) {
655 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
657 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
658 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
660 ath_txq_unlock(sc, txq);
661 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
662 ath_txq_lock(sc, txq);
666 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
669 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
671 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
672 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
675 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
676 struct ath_tx_status *ts, struct ath_buf *bf,
677 struct list_head *bf_head)
679 struct ieee80211_hw *hw = sc->hw;
680 struct ieee80211_tx_info *info;
681 struct ieee80211_sta *sta;
682 struct ieee80211_hdr *hdr;
683 struct ath_atx_tid *tid = NULL;
686 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
687 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
688 txq->axq_tx_inprogress = false;
691 if (bf_is_ampdu_not_probing(bf))
692 txq->axq_ampdu_depth--;
694 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
697 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
698 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
700 struct ath_node *an = (struct ath_node *)sta->drv_priv;
701 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
702 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
703 tid->clear_ps_filter = true;
706 if (!bf_isampdu(bf)) {
708 info = IEEE80211_SKB_CB(bf->bf_mpdu);
709 memcpy(info->control.rates, bf->rates,
710 sizeof(info->control.rates));
711 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
712 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
715 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
717 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
720 ath_txq_schedule(sc, txq);
723 static bool ath_lookup_legacy(struct ath_buf *bf)
726 struct ieee80211_tx_info *tx_info;
727 struct ieee80211_tx_rate *rates;
731 tx_info = IEEE80211_SKB_CB(skb);
732 rates = tx_info->control.rates;
734 for (i = 0; i < 4; i++) {
735 if (!rates[i].count || rates[i].idx < 0)
738 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
745 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
746 struct ath_atx_tid *tid)
749 struct ieee80211_tx_info *tx_info;
750 struct ieee80211_tx_rate *rates;
751 u32 max_4ms_framelen, frmlen;
752 u16 aggr_limit, bt_aggr_limit, legacy = 0;
753 int q = tid->txq->mac80211_qnum;
757 tx_info = IEEE80211_SKB_CB(skb);
761 * Find the lowest frame length among the rate series that will have a
762 * 4ms (or TXOP limited) transmit duration.
764 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
766 for (i = 0; i < 4; i++) {
772 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
777 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
782 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
785 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
786 max_4ms_framelen = min(max_4ms_framelen, frmlen);
790 * limit aggregate size by the minimum rate if rate selected is
791 * not a probe rate, if rate selected is a probe rate then
792 * avoid aggregation of this packet.
794 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
797 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
800 * Override the default aggregation limit for BTCOEX.
802 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
804 aggr_limit = bt_aggr_limit;
806 if (tid->an->maxampdu)
807 aggr_limit = min(aggr_limit, tid->an->maxampdu);
813 * Returns the number of delimiters to be added to
814 * meet the minimum required mpdudensity.
816 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
817 struct ath_buf *bf, u16 frmlen,
820 #define FIRST_DESC_NDELIMS 60
821 u32 nsymbits, nsymbols;
824 int width, streams, half_gi, ndelim, mindelim;
825 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
827 /* Select standard number of delimiters based on frame length alone */
828 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
831 * If encryption enabled, hardware requires some more padding between
833 * TODO - this could be improved to be dependent on the rate.
834 * The hardware can keep up at lower rates, but not higher rates
836 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
837 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
838 ndelim += ATH_AGGR_ENCRYPTDELIM;
841 * Add delimiter when using RTS/CTS with aggregation
842 * and non enterprise AR9003 card
844 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
845 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
846 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
849 * Convert desired mpdu density from microeconds to bytes based
850 * on highest rate in rate series (i.e. first rate) to determine
851 * required minimum length for subframe. Take into account
852 * whether high rate is 20 or 40Mhz and half or full GI.
854 * If there is no mpdu density restriction, no further calculation
858 if (tid->an->mpdudensity == 0)
861 rix = bf->rates[0].idx;
862 flags = bf->rates[0].flags;
863 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
864 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
867 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
869 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
874 streams = HT_RC_2_STREAMS(rix);
875 nsymbits = bits_per_symbol[rix % 8][width] * streams;
876 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
878 if (frmlen < minlen) {
879 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
880 ndelim = max(mindelim, ndelim);
886 static struct ath_buf *
887 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
888 struct ath_atx_tid *tid, struct sk_buff_head **q)
890 struct ieee80211_tx_info *tx_info;
891 struct ath_frame_info *fi;
898 if (skb_queue_empty(*q))
905 fi = get_frame_info(skb);
908 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
910 bf->bf_state.stale = false;
913 __skb_unlink(skb, *q);
914 ath_txq_skb_done(sc, txq, skb);
915 ieee80211_free_txskb(sc->hw, skb);
922 tx_info = IEEE80211_SKB_CB(skb);
923 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
926 * No aggregation session is running, but there may be frames
927 * from a previous session or a failed attempt in the queue.
928 * Send them out as normal data frames
931 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
933 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
934 bf->bf_state.bf_type = 0;
938 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
939 seqno = bf->bf_state.seqno;
941 /* do not step over block-ack window */
942 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
945 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
946 struct ath_tx_status ts = {};
947 struct list_head bf_head;
949 INIT_LIST_HEAD(&bf_head);
950 list_add(&bf->list, &bf_head);
951 __skb_unlink(skb, *q);
952 ath_tx_update_baw(sc, tid, seqno);
953 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
964 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
965 struct ath_atx_tid *tid, struct list_head *bf_q,
966 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
969 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
970 struct ath_buf *bf = bf_first, *bf_prev = NULL;
971 int nframes = 0, ndelim;
972 u16 aggr_limit = 0, al = 0, bpad = 0,
973 al_delta, h_baw = tid->baw_size / 2;
974 struct ieee80211_tx_info *tx_info;
975 struct ath_frame_info *fi;
980 aggr_limit = ath_lookup_rate(sc, bf, tid);
984 fi = get_frame_info(skb);
986 /* do not exceed aggregation limit */
987 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
989 if (aggr_limit < al + bpad + al_delta ||
990 ath_lookup_legacy(bf) || nframes >= h_baw)
993 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
994 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
995 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
999 /* add padding for previous frame to aggregation length */
1000 al += bpad + al_delta;
1003 * Get the delimiters needed to meet the MPDU
1004 * density for this node.
1006 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1008 bpad = PADBYTES(al_delta) + (ndelim << 2);
1013 /* link buffers of this frame to the aggregate */
1014 if (!fi->baw_tracked)
1015 ath_tx_addto_baw(sc, tid, bf);
1016 bf->bf_state.ndelim = ndelim;
1018 __skb_unlink(skb, tid_q);
1019 list_add_tail(&bf->list, bf_q);
1021 bf_prev->bf_next = bf;
1025 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1030 } while (ath_tid_has_buffered(tid));
1033 bf->bf_lastbf = bf_prev;
1035 if (bf == bf_prev) {
1036 al = get_frame_info(bf->bf_mpdu)->framelen;
1037 bf->bf_state.bf_type = BUF_AMPDU;
1039 TX_STAT_INC(txq->axq_qnum, a_aggr);
1050 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1051 * width - 0 for 20 MHz, 1 for 40 MHz
1052 * half_gi - to use 4us v/s 3.6 us for symbol time
1054 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1055 int width, int half_gi, bool shortPreamble)
1057 u32 nbits, nsymbits, duration, nsymbols;
1060 /* find number of symbols: PLCP + data */
1061 streams = HT_RC_2_STREAMS(rix);
1062 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1063 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1064 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1067 duration = SYMBOL_TIME(nsymbols);
1069 duration = SYMBOL_TIME_HALFGI(nsymbols);
1071 /* addup duration for legacy/ht training and signal fields */
1072 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1077 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1079 int streams = HT_RC_2_STREAMS(mcs);
1083 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1084 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1085 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1086 bits -= OFDM_PLCP_BITS;
1094 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1096 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1099 /* 4ms is the default (and maximum) duration */
1100 if (!txop || txop > 4096)
1103 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1104 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1105 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1106 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1107 for (mcs = 0; mcs < 32; mcs++) {
1108 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1109 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1110 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1111 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1115 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1116 u8 rateidx, bool is_40, bool is_cck)
1119 struct sk_buff *skb;
1120 struct ath_frame_info *fi;
1121 struct ieee80211_tx_info *info;
1122 struct ath_hw *ah = sc->sc_ah;
1124 if (sc->tx99_state || !ah->tpc_enabled)
1125 return MAX_RATE_POWER;
1128 fi = get_frame_info(skb);
1129 info = IEEE80211_SKB_CB(skb);
1131 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1132 int txpower = fi->tx_power;
1136 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1138 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1140 struct modal_eep_header *pmodal;
1142 is_2ghz = info->band == NL80211_BAND_2GHZ;
1143 pmodal = &eep->modalHeader[is_2ghz];
1144 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1146 power_ht40delta = 2;
1148 txpower += power_ht40delta;
1151 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1153 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1154 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1157 power_offset = ah->eep_ops->get_eeprom(ah,
1158 EEP_PWR_TABLE_OFFSET);
1159 txpower -= 2 * power_offset;
1162 if (OLC_FOR_AR9280_20_LATER && is_cck)
1165 txpower = max(txpower, 0);
1166 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1168 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1169 * max_power is set to 0, frames are transmitted at max
1172 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1174 } else if (!bf->bf_state.bfs_paprd) {
1175 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1176 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1179 max_power = min_t(u8, ah->tx_power[rateidx],
1182 max_power = ah->paprd_training_power;
1188 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1189 struct ath_tx_info *info, int len, bool rts)
1191 struct ath_hw *ah = sc->sc_ah;
1192 struct ath_common *common = ath9k_hw_common(ah);
1193 struct sk_buff *skb;
1194 struct ieee80211_tx_info *tx_info;
1195 struct ieee80211_tx_rate *rates;
1196 const struct ieee80211_rate *rate;
1197 struct ieee80211_hdr *hdr;
1198 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1199 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1204 tx_info = IEEE80211_SKB_CB(skb);
1206 hdr = (struct ieee80211_hdr *)skb->data;
1208 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1209 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1210 info->rtscts_rate = fi->rtscts_rate;
1212 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1213 bool is_40, is_sgi, is_sp, is_cck;
1216 if (!rates[i].count || (rates[i].idx < 0))
1220 info->rates[i].Tries = rates[i].count;
1223 * Handle RTS threshold for unaggregated HT frames.
1225 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1226 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1227 unlikely(rts_thresh != (u32) -1)) {
1228 if (!rts_thresh || (len > rts_thresh))
1232 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1233 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1234 info->flags |= ATH9K_TXDESC_RTSENA;
1235 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1236 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1237 info->flags |= ATH9K_TXDESC_CTSENA;
1240 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1241 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1242 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1243 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1245 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1246 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1247 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1249 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1251 info->rates[i].Rate = rix | 0x80;
1252 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1253 ah->txchainmask, info->rates[i].Rate);
1254 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1255 is_40, is_sgi, is_sp);
1256 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1257 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1258 if (rix >= 8 && fi->dyn_smps) {
1259 info->rates[i].RateFlags |=
1260 ATH9K_RATESERIES_RTS_CTS;
1261 info->flags |= ATH9K_TXDESC_CTSENA;
1264 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1270 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1271 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1272 !(rate->flags & IEEE80211_RATE_ERP_G))
1273 phy = WLAN_RC_PHY_CCK;
1275 phy = WLAN_RC_PHY_OFDM;
1277 info->rates[i].Rate = rate->hw_value;
1278 if (rate->hw_value_short) {
1279 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1280 info->rates[i].Rate |= rate->hw_value_short;
1285 if (bf->bf_state.bfs_paprd)
1286 info->rates[i].ChSel = ah->txchainmask;
1288 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1289 ah->txchainmask, info->rates[i].Rate);
1291 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1292 phy, rate->bitrate * 100, len, rix, is_sp);
1294 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1295 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1299 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1300 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1301 info->flags &= ~ATH9K_TXDESC_RTSENA;
1303 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1304 if (info->flags & ATH9K_TXDESC_RTSENA)
1305 info->flags &= ~ATH9K_TXDESC_CTSENA;
1308 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1310 struct ieee80211_hdr *hdr;
1311 enum ath9k_pkt_type htype;
1314 hdr = (struct ieee80211_hdr *)skb->data;
1315 fc = hdr->frame_control;
1317 if (ieee80211_is_beacon(fc))
1318 htype = ATH9K_PKT_TYPE_BEACON;
1319 else if (ieee80211_is_probe_resp(fc))
1320 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1321 else if (ieee80211_is_atim(fc))
1322 htype = ATH9K_PKT_TYPE_ATIM;
1323 else if (ieee80211_is_pspoll(fc))
1324 htype = ATH9K_PKT_TYPE_PSPOLL;
1326 htype = ATH9K_PKT_TYPE_NORMAL;
1331 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1332 struct ath_txq *txq, int len)
1334 struct ath_hw *ah = sc->sc_ah;
1335 struct ath_buf *bf_first = NULL;
1336 struct ath_tx_info info;
1337 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1340 memset(&info, 0, sizeof(info));
1341 info.is_first = true;
1342 info.is_last = true;
1343 info.qcu = txq->axq_qnum;
1346 struct sk_buff *skb = bf->bf_mpdu;
1347 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1348 struct ath_frame_info *fi = get_frame_info(skb);
1349 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1351 info.type = get_hw_packet_type(skb);
1353 info.link = bf->bf_next->bf_daddr;
1355 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1360 if (!sc->tx99_state)
1361 info.flags = ATH9K_TXDESC_INTREQ;
1362 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1363 txq == sc->tx.uapsdq)
1364 info.flags |= ATH9K_TXDESC_CLRDMASK;
1366 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1367 info.flags |= ATH9K_TXDESC_NOACK;
1368 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1369 info.flags |= ATH9K_TXDESC_LDPC;
1371 if (bf->bf_state.bfs_paprd)
1372 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1373 ATH9K_TXDESC_PAPRD_S;
1376 * mac80211 doesn't handle RTS threshold for HT because
1377 * the decision has to be taken based on AMPDU length
1378 * and aggregation is done entirely inside ath9k.
1379 * Set the RTS/CTS flag for the first subframe based
1382 if (aggr && (bf == bf_first) &&
1383 unlikely(rts_thresh != (u32) -1)) {
1385 * "len" is the size of the entire AMPDU.
1387 if (!rts_thresh || (len > rts_thresh))
1394 ath_buf_set_rate(sc, bf, &info, len, rts);
1397 info.buf_addr[0] = bf->bf_buf_addr;
1398 info.buf_len[0] = skb->len;
1399 info.pkt_len = fi->framelen;
1400 info.keyix = fi->keyix;
1401 info.keytype = fi->keytype;
1405 info.aggr = AGGR_BUF_FIRST;
1406 else if (bf == bf_first->bf_lastbf)
1407 info.aggr = AGGR_BUF_LAST;
1409 info.aggr = AGGR_BUF_MIDDLE;
1411 info.ndelim = bf->bf_state.ndelim;
1412 info.aggr_len = len;
1415 if (bf == bf_first->bf_lastbf)
1418 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1424 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1425 struct ath_atx_tid *tid, struct list_head *bf_q,
1426 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1428 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1429 struct sk_buff *skb;
1433 struct ieee80211_tx_info *tx_info;
1437 __skb_unlink(skb, tid_q);
1438 list_add_tail(&bf->list, bf_q);
1440 bf_prev->bf_next = bf;
1446 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1450 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1451 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1454 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1458 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1459 struct ath_atx_tid *tid, bool *stop)
1462 struct ieee80211_tx_info *tx_info;
1463 struct sk_buff_head *tid_q;
1464 struct list_head bf_q;
1466 bool aggr, last = true;
1468 if (!ath_tid_has_buffered(tid))
1471 INIT_LIST_HEAD(&bf_q);
1473 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1477 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1478 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1479 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1480 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1485 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1487 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1490 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1492 if (list_empty(&bf_q))
1495 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1496 tid->clear_ps_filter = false;
1497 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1500 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1501 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1505 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1508 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1509 struct ath_atx_tid *txtid;
1510 struct ath_txq *txq;
1511 struct ath_node *an;
1514 ath_dbg(common, XMIT, "%s called\n", __func__);
1516 an = (struct ath_node *)sta->drv_priv;
1517 txtid = ATH_AN_2_TID(an, tid);
1520 ath_txq_lock(sc, txq);
1522 /* update ampdu factor/density, they may have changed. This may happen
1523 * in HT IBSS when a beacon with HT-info is received after the station
1524 * has already been added.
1526 if (sta->ht_cap.ht_supported) {
1527 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1528 sta->ht_cap.ampdu_factor)) - 1;
1529 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1530 an->mpdudensity = density;
1533 /* force sequence number allocation for pending frames */
1534 ath_tx_tid_change_state(sc, txtid);
1536 txtid->active = true;
1537 *ssn = txtid->seq_start = txtid->seq_next;
1538 txtid->bar_index = -1;
1540 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1541 txtid->baw_head = txtid->baw_tail = 0;
1543 ath_txq_unlock_complete(sc, txq);
1548 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1550 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1551 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1552 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1553 struct ath_txq *txq = txtid->txq;
1555 ath_dbg(common, XMIT, "%s called\n", __func__);
1557 ath_txq_lock(sc, txq);
1558 txtid->active = false;
1559 ath_tx_flush_tid(sc, txtid);
1560 ath_tx_tid_change_state(sc, txtid);
1561 ath_txq_unlock_complete(sc, txq);
1564 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1565 struct ath_node *an)
1567 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1568 struct ath_atx_tid *tid;
1569 struct ath_txq *txq;
1573 ath_dbg(common, XMIT, "%s called\n", __func__);
1575 for (tidno = 0, tid = &an->tid[tidno];
1576 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1580 ath_txq_lock(sc, txq);
1582 if (list_empty(&tid->list)) {
1583 ath_txq_unlock(sc, txq);
1587 buffered = ath_tid_has_buffered(tid);
1589 list_del_init(&tid->list);
1591 ath_txq_unlock(sc, txq);
1593 ieee80211_sta_set_buffered(sta, tidno, buffered);
1597 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1599 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1600 struct ath_atx_tid *tid;
1601 struct ath_txq *txq;
1604 ath_dbg(common, XMIT, "%s called\n", __func__);
1606 for (tidno = 0, tid = &an->tid[tidno];
1607 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1611 ath_txq_lock(sc, txq);
1612 tid->clear_ps_filter = true;
1614 if (ath_tid_has_buffered(tid)) {
1615 ath_tx_queue_tid(sc, txq, tid);
1616 ath_txq_schedule(sc, txq);
1619 ath_txq_unlock_complete(sc, txq);
1623 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1626 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1627 struct ath_atx_tid *tid;
1628 struct ath_node *an;
1629 struct ath_txq *txq;
1631 ath_dbg(common, XMIT, "%s called\n", __func__);
1633 an = (struct ath_node *)sta->drv_priv;
1634 tid = ATH_AN_2_TID(an, tidno);
1637 ath_txq_lock(sc, txq);
1639 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1641 if (ath_tid_has_buffered(tid)) {
1642 ath_tx_queue_tid(sc, txq, tid);
1643 ath_txq_schedule(sc, txq);
1646 ath_txq_unlock_complete(sc, txq);
1649 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1650 struct ieee80211_sta *sta,
1651 u16 tids, int nframes,
1652 enum ieee80211_frame_release_type reason,
1655 struct ath_softc *sc = hw->priv;
1656 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1657 struct ath_txq *txq = sc->tx.uapsdq;
1658 struct ieee80211_tx_info *info;
1659 struct list_head bf_q;
1660 struct ath_buf *bf_tail = NULL, *bf;
1661 struct sk_buff_head *tid_q;
1665 INIT_LIST_HEAD(&bf_q);
1666 for (i = 0; tids && nframes; i++, tids >>= 1) {
1667 struct ath_atx_tid *tid;
1672 tid = ATH_AN_2_TID(an, i);
1674 ath_txq_lock(sc, tid->txq);
1675 while (nframes > 0) {
1676 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1680 __skb_unlink(bf->bf_mpdu, tid_q);
1681 list_add_tail(&bf->list, &bf_q);
1682 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1683 if (bf_isampdu(bf)) {
1684 ath_tx_addto_baw(sc, tid, bf);
1685 bf->bf_state.bf_type &= ~BUF_AGGR;
1688 bf_tail->bf_next = bf;
1693 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1695 if (an->sta && !ath_tid_has_buffered(tid))
1696 ieee80211_sta_set_buffered(an->sta, i, false);
1698 ath_txq_unlock_complete(sc, tid->txq);
1701 if (list_empty(&bf_q))
1704 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1705 info->flags |= IEEE80211_TX_STATUS_EOSP;
1707 bf = list_first_entry(&bf_q, struct ath_buf, list);
1708 ath_txq_lock(sc, txq);
1709 ath_tx_fill_desc(sc, bf, txq, 0);
1710 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1711 ath_txq_unlock(sc, txq);
1714 /********************/
1715 /* Queue Management */
1716 /********************/
1718 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1720 struct ath_hw *ah = sc->sc_ah;
1721 struct ath9k_tx_queue_info qi;
1722 static const int subtype_txq_to_hwq[] = {
1723 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1724 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1725 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1726 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1730 memset(&qi, 0, sizeof(qi));
1731 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1732 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1733 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1734 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1735 qi.tqi_physCompBuf = 0;
1738 * Enable interrupts only for EOL and DESC conditions.
1739 * We mark tx descriptors to receive a DESC interrupt
1740 * when a tx queue gets deep; otherwise waiting for the
1741 * EOL to reap descriptors. Note that this is done to
1742 * reduce interrupt load and this only defers reaping
1743 * descriptors, never transmitting frames. Aside from
1744 * reducing interrupts this also permits more concurrency.
1745 * The only potential downside is if the tx queue backs
1746 * up in which case the top half of the kernel may backup
1747 * due to a lack of tx descriptors.
1749 * The UAPSD queue is an exception, since we take a desc-
1750 * based intr on the EOSP frames.
1752 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1753 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1755 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1756 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1758 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1759 TXQ_FLAG_TXDESCINT_ENABLE;
1761 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1762 if (axq_qnum == -1) {
1764 * NB: don't print a message, this happens
1765 * normally on parts with too few tx queues
1769 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1770 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1772 txq->axq_qnum = axq_qnum;
1773 txq->mac80211_qnum = -1;
1774 txq->axq_link = NULL;
1775 __skb_queue_head_init(&txq->complete_q);
1776 INIT_LIST_HEAD(&txq->axq_q);
1777 spin_lock_init(&txq->axq_lock);
1779 txq->axq_ampdu_depth = 0;
1780 txq->axq_tx_inprogress = false;
1781 sc->tx.txqsetup |= 1<<axq_qnum;
1783 txq->txq_headidx = txq->txq_tailidx = 0;
1784 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1785 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1787 return &sc->tx.txq[axq_qnum];
1790 int ath_txq_update(struct ath_softc *sc, int qnum,
1791 struct ath9k_tx_queue_info *qinfo)
1793 struct ath_hw *ah = sc->sc_ah;
1795 struct ath9k_tx_queue_info qi;
1797 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1799 ath9k_hw_get_txq_props(ah, qnum, &qi);
1800 qi.tqi_aifs = qinfo->tqi_aifs;
1801 qi.tqi_cwmin = qinfo->tqi_cwmin;
1802 qi.tqi_cwmax = qinfo->tqi_cwmax;
1803 qi.tqi_burstTime = qinfo->tqi_burstTime;
1804 qi.tqi_readyTime = qinfo->tqi_readyTime;
1806 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1807 ath_err(ath9k_hw_common(sc->sc_ah),
1808 "Unable to update hardware queue %u!\n", qnum);
1811 ath9k_hw_resettxqueue(ah, qnum);
1817 int ath_cabq_update(struct ath_softc *sc)
1819 struct ath9k_tx_queue_info qi;
1820 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1821 int qnum = sc->beacon.cabq->axq_qnum;
1823 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1825 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1826 ATH_CABQ_READY_TIME) / 100;
1827 ath_txq_update(sc, qnum, &qi);
1832 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1833 struct list_head *list)
1835 struct ath_buf *bf, *lastbf;
1836 struct list_head bf_head;
1837 struct ath_tx_status ts;
1839 memset(&ts, 0, sizeof(ts));
1840 ts.ts_status = ATH9K_TX_FLUSH;
1841 INIT_LIST_HEAD(&bf_head);
1843 while (!list_empty(list)) {
1844 bf = list_first_entry(list, struct ath_buf, list);
1846 if (bf->bf_state.stale) {
1847 list_del(&bf->list);
1849 ath_tx_return_buffer(sc, bf);
1853 lastbf = bf->bf_lastbf;
1854 list_cut_position(&bf_head, list, &lastbf->list);
1855 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1860 * Drain a given TX queue (could be Beacon or Data)
1862 * This assumes output has been stopped and
1863 * we do not need to block ath_tx_tasklet.
1865 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1868 ath_txq_lock(sc, txq);
1870 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1871 int idx = txq->txq_tailidx;
1873 while (!list_empty(&txq->txq_fifo[idx])) {
1874 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1876 INCR(idx, ATH_TXFIFO_DEPTH);
1878 txq->txq_tailidx = idx;
1881 txq->axq_link = NULL;
1882 txq->axq_tx_inprogress = false;
1883 ath_drain_txq_list(sc, txq, &txq->axq_q);
1885 ath_txq_unlock_complete(sc, txq);
1889 bool ath_drain_all_txq(struct ath_softc *sc)
1891 struct ath_hw *ah = sc->sc_ah;
1892 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1893 struct ath_txq *txq;
1897 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1900 ath9k_hw_abort_tx_dma(ah);
1902 /* Check if any queue remains active */
1903 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1904 if (!ATH_TXQ_SETUP(sc, i))
1907 if (!sc->tx.txq[i].axq_depth)
1910 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1915 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1916 ath_dbg(common, RESET,
1917 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1920 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1921 if (!ATH_TXQ_SETUP(sc, i))
1925 * The caller will resume queues with ieee80211_wake_queues.
1926 * Mark the queue as not stopped to prevent ath_tx_complete
1927 * from waking the queue too early.
1929 txq = &sc->tx.txq[i];
1930 txq->stopped = false;
1931 ath_draintxq(sc, txq);
1937 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1939 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1940 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1943 /* For each acq entry, for each tid, try to schedule packets
1944 * for transmit until ampdu_depth has reached min Q depth.
1946 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1948 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1949 struct ath_atx_tid *tid, *last_tid;
1950 struct list_head *tid_list;
1953 if (txq->mac80211_qnum < 0)
1956 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1959 spin_lock_bh(&sc->chan_lock);
1960 tid_list = &sc->cur_chan->acq[txq->mac80211_qnum];
1962 if (list_empty(tid_list)) {
1963 spin_unlock_bh(&sc->chan_lock);
1969 last_tid = list_entry(tid_list->prev, struct ath_atx_tid, list);
1970 while (!list_empty(tid_list)) {
1973 if (sc->cur_chan->stopped)
1976 tid = list_first_entry(tid_list, struct ath_atx_tid, list);
1977 list_del_init(&tid->list);
1979 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1983 * add tid to round-robin queue if more frames
1984 * are pending for the tid
1986 if (ath_tid_has_buffered(tid))
1987 ath_tx_queue_tid(sc, txq, tid);
1992 if (tid == last_tid) {
1997 last_tid = list_entry(tid_list->prev,
1998 struct ath_atx_tid, list);
2003 spin_unlock_bh(&sc->chan_lock);
2006 void ath_txq_schedule_all(struct ath_softc *sc)
2008 struct ath_txq *txq;
2011 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2012 txq = sc->tx.txq_map[i];
2014 spin_lock_bh(&txq->axq_lock);
2015 ath_txq_schedule(sc, txq);
2016 spin_unlock_bh(&txq->axq_lock);
2025 * Insert a chain of ath_buf (descriptors) on a txq and
2026 * assume the descriptors are already chained together by caller.
2028 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2029 struct list_head *head, bool internal)
2031 struct ath_hw *ah = sc->sc_ah;
2032 struct ath_common *common = ath9k_hw_common(ah);
2033 struct ath_buf *bf, *bf_last;
2034 bool puttxbuf = false;
2038 * Insert the frame on the outbound list and
2039 * pass it on to the hardware.
2042 if (list_empty(head))
2045 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2046 bf = list_first_entry(head, struct ath_buf, list);
2047 bf_last = list_entry(head->prev, struct ath_buf, list);
2049 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2050 txq->axq_qnum, txq->axq_depth);
2052 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2053 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2054 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2057 list_splice_tail_init(head, &txq->axq_q);
2059 if (txq->axq_link) {
2060 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2061 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2062 txq->axq_qnum, txq->axq_link,
2063 ito64(bf->bf_daddr), bf->bf_desc);
2067 txq->axq_link = bf_last->bf_desc;
2071 TX_STAT_INC(txq->axq_qnum, puttxbuf);
2072 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2073 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2074 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2077 if (!edma || sc->tx99_state) {
2078 TX_STAT_INC(txq->axq_qnum, txstart);
2079 ath9k_hw_txstart(ah, txq->axq_qnum);
2085 if (bf_is_ampdu_not_probing(bf))
2086 txq->axq_ampdu_depth++;
2088 bf_last = bf->bf_lastbf;
2089 bf = bf_last->bf_next;
2090 bf_last->bf_next = NULL;
2095 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2096 struct ath_atx_tid *tid, struct sk_buff *skb)
2098 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2099 struct ath_frame_info *fi = get_frame_info(skb);
2100 struct list_head bf_head;
2101 struct ath_buf *bf = fi->bf;
2103 INIT_LIST_HEAD(&bf_head);
2104 list_add_tail(&bf->list, &bf_head);
2105 bf->bf_state.bf_type = 0;
2106 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2107 bf->bf_state.bf_type = BUF_AMPDU;
2108 ath_tx_addto_baw(sc, tid, bf);
2113 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2114 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2115 TX_STAT_INC(txq->axq_qnum, queued);
2118 static void setup_frame_info(struct ieee80211_hw *hw,
2119 struct ieee80211_sta *sta,
2120 struct sk_buff *skb,
2123 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2124 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2125 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2126 const struct ieee80211_rate *rate;
2127 struct ath_frame_info *fi = get_frame_info(skb);
2128 struct ath_node *an = NULL;
2129 enum ath9k_key_type keytype;
2130 bool short_preamble = false;
2134 * We check if Short Preamble is needed for the CTS rate by
2135 * checking the BSS's global flag.
2136 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2138 if (tx_info->control.vif &&
2139 tx_info->control.vif->bss_conf.use_short_preamble)
2140 short_preamble = true;
2142 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2143 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2146 an = (struct ath_node *) sta->drv_priv;
2148 if (tx_info->control.vif) {
2149 struct ieee80211_vif *vif = tx_info->control.vif;
2151 txpower = 2 * vif->bss_conf.txpower;
2153 struct ath_softc *sc = hw->priv;
2155 txpower = sc->cur_chan->cur_txpower;
2158 memset(fi, 0, sizeof(*fi));
2161 fi->keyix = hw_key->hw_key_idx;
2162 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2163 fi->keyix = an->ps_key;
2165 fi->keyix = ATH9K_TXKEYIX_INVALID;
2166 fi->dyn_smps = sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC;
2167 fi->keytype = keytype;
2168 fi->framelen = framelen;
2169 fi->tx_power = txpower;
2173 fi->rtscts_rate = rate->hw_value;
2175 fi->rtscts_rate |= rate->hw_value_short;
2178 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2180 struct ath_hw *ah = sc->sc_ah;
2181 struct ath9k_channel *curchan = ah->curchan;
2183 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2184 (chainmask == 0x7) && (rate < 0x90))
2186 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2194 * Assign a descriptor (and sequence number if necessary,
2195 * and map buffer for DMA. Frees skb on error
2197 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2198 struct ath_txq *txq,
2199 struct ath_atx_tid *tid,
2200 struct sk_buff *skb)
2202 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2203 struct ath_frame_info *fi = get_frame_info(skb);
2204 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2209 bf = ath_tx_get_buffer(sc);
2211 ath_dbg(common, XMIT, "TX buffers are full\n");
2215 ATH_TXBUF_RESET(bf);
2217 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2218 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2219 seqno = tid->seq_next;
2220 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2223 hdr->seq_ctrl |= cpu_to_le16(fragno);
2225 if (!ieee80211_has_morefrags(hdr->frame_control))
2226 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2228 bf->bf_state.seqno = seqno;
2233 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2234 skb->len, DMA_TO_DEVICE);
2235 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2237 bf->bf_buf_addr = 0;
2238 ath_err(ath9k_hw_common(sc->sc_ah),
2239 "dma_mapping_error() on TX\n");
2240 ath_tx_return_buffer(sc, bf);
2249 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2251 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2252 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2253 struct ieee80211_vif *vif = info->control.vif;
2254 struct ath_vif *avp;
2256 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2262 avp = (struct ath_vif *)vif->drv_priv;
2264 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2265 avp->seq_no += 0x10;
2267 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2268 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2271 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2272 struct ath_tx_control *txctl)
2274 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2275 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2276 struct ieee80211_sta *sta = txctl->sta;
2277 struct ieee80211_vif *vif = info->control.vif;
2278 struct ath_vif *avp;
2279 struct ath_softc *sc = hw->priv;
2280 int frmlen = skb->len + FCS_LEN;
2281 int padpos, padsize;
2283 /* NOTE: sta can be NULL according to net/mac80211.h */
2285 txctl->an = (struct ath_node *)sta->drv_priv;
2286 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2287 avp = (void *)vif->drv_priv;
2288 txctl->an = &avp->mcast_node;
2291 if (info->control.hw_key)
2292 frmlen += info->control.hw_key->icv_len;
2294 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2296 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2297 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2298 !ieee80211_is_data(hdr->frame_control))
2299 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2301 /* Add the padding after the header if this is not already done */
2302 padpos = ieee80211_hdrlen(hdr->frame_control);
2303 padsize = padpos & 3;
2304 if (padsize && skb->len > padpos) {
2305 if (skb_headroom(skb) < padsize)
2308 skb_push(skb, padsize);
2309 memmove(skb->data, skb->data + padsize, padpos);
2312 setup_frame_info(hw, sta, skb, frmlen);
2317 /* Upon failure caller should free skb */
2318 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2319 struct ath_tx_control *txctl)
2321 struct ieee80211_hdr *hdr;
2322 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2323 struct ieee80211_sta *sta = txctl->sta;
2324 struct ieee80211_vif *vif = info->control.vif;
2325 struct ath_frame_info *fi = get_frame_info(skb);
2326 struct ath_vif *avp = NULL;
2327 struct ath_softc *sc = hw->priv;
2328 struct ath_txq *txq = txctl->txq;
2329 struct ath_atx_tid *tid = NULL;
2331 bool queue, skip_uapsd = false, ps_resp;
2335 avp = (void *)vif->drv_priv;
2337 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
2338 txctl->force_channel = true;
2340 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2342 ret = ath_tx_prepare(hw, skb, txctl);
2346 hdr = (struct ieee80211_hdr *) skb->data;
2348 * At this point, the vif, hw_key and sta pointers in the tx control
2349 * info are no longer valid (overwritten by the ath_frame_info data.
2352 q = skb_get_queue_mapping(skb);
2354 ath_txq_lock(sc, txq);
2355 if (txq == sc->tx.txq_map[q]) {
2357 if (++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2359 if (ath9k_is_chanctx_enabled())
2360 ieee80211_stop_queue(sc->hw, info->hw_queue);
2362 ieee80211_stop_queue(sc->hw, q);
2363 txq->stopped = true;
2367 queue = ieee80211_is_data_present(hdr->frame_control);
2369 /* If chanctx, queue all null frames while NOA could be there */
2370 if (ath9k_is_chanctx_enabled() &&
2371 ieee80211_is_nullfunc(hdr->frame_control) &&
2372 !txctl->force_channel)
2375 /* Force queueing of all frames that belong to a virtual interface on
2376 * a different channel context, to ensure that they are sent on the
2379 if (((avp && avp->chanctx != sc->cur_chan) ||
2380 sc->cur_chan->stopped) && !txctl->force_channel) {
2382 txctl->an = &avp->mcast_node;
2387 if (txctl->an && queue)
2388 tid = ath_get_skb_tid(sc, txctl->an, skb);
2390 if (!skip_uapsd && ps_resp) {
2391 ath_txq_unlock(sc, txq);
2392 txq = sc->tx.uapsdq;
2393 ath_txq_lock(sc, txq);
2394 } else if (txctl->an && queue) {
2395 WARN_ON(tid->txq != txctl->txq);
2397 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2398 tid->clear_ps_filter = true;
2401 * Add this frame to software queue for scheduling later
2404 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2405 __skb_queue_tail(&tid->buf_q, skb);
2406 if (!txctl->an->sleeping)
2407 ath_tx_queue_tid(sc, txq, tid);
2409 ath_txq_schedule(sc, txq);
2413 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2415 ath_txq_skb_done(sc, txq, skb);
2417 dev_kfree_skb_any(skb);
2419 ieee80211_free_txskb(sc->hw, skb);
2423 bf->bf_state.bfs_paprd = txctl->paprd;
2426 bf->bf_state.bfs_paprd_timestamp = jiffies;
2428 ath_set_rates(vif, sta, bf);
2429 ath_tx_send_normal(sc, txq, tid, skb);
2432 ath_txq_unlock(sc, txq);
2437 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2438 struct sk_buff *skb)
2440 struct ath_softc *sc = hw->priv;
2441 struct ath_tx_control txctl = {
2442 .txq = sc->beacon.cabq
2444 struct ath_tx_info info = {};
2445 struct ieee80211_hdr *hdr;
2446 struct ath_buf *bf_tail = NULL;
2453 sc->cur_chan->beacon.beacon_interval * 1000 *
2454 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2457 struct ath_frame_info *fi = get_frame_info(skb);
2459 if (ath_tx_prepare(hw, skb, &txctl))
2462 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2467 ath_set_rates(vif, NULL, bf);
2468 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2469 duration += info.rates[0].PktDuration;
2471 bf_tail->bf_next = bf;
2473 list_add_tail(&bf->list, &bf_q);
2477 if (duration > max_duration)
2480 skb = ieee80211_get_buffered_bc(hw, vif);
2484 ieee80211_free_txskb(hw, skb);
2486 if (list_empty(&bf_q))
2489 bf = list_first_entry(&bf_q, struct ath_buf, list);
2490 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2492 if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) {
2493 hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA);
2494 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2495 sizeof(*hdr), DMA_TO_DEVICE);
2498 ath_txq_lock(sc, txctl.txq);
2499 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2500 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2501 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2502 ath_txq_unlock(sc, txctl.txq);
2509 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2510 int tx_flags, struct ath_txq *txq,
2511 struct ieee80211_sta *sta)
2513 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2514 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2515 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2516 int padpos, padsize;
2517 unsigned long flags;
2519 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2521 if (sc->sc_ah->caldata)
2522 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2524 if (!(tx_flags & ATH_TX_ERROR)) {
2525 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2526 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2528 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2531 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2532 padpos = ieee80211_hdrlen(hdr->frame_control);
2533 padsize = padpos & 3;
2534 if (padsize && skb->len>padpos+padsize) {
2536 * Remove MAC header padding before giving the frame back to
2539 memmove(skb->data + padsize, skb->data, padpos);
2540 skb_pull(skb, padsize);
2544 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2545 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2546 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2548 "Going back to sleep after having received TX status (0x%lx)\n",
2549 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2551 PS_WAIT_FOR_PSPOLL_DATA |
2552 PS_WAIT_FOR_TX_ACK));
2554 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2556 ath_txq_skb_done(sc, txq, skb);
2557 tx_info->status.status_driver_data[0] = sta;
2558 __skb_queue_tail(&txq->complete_q, skb);
2561 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2562 struct ath_txq *txq, struct list_head *bf_q,
2563 struct ieee80211_sta *sta,
2564 struct ath_tx_status *ts, int txok)
2566 struct sk_buff *skb = bf->bf_mpdu;
2567 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2568 unsigned long flags;
2572 tx_flags |= ATH_TX_ERROR;
2574 if (ts->ts_status & ATH9K_TXERR_FILT)
2575 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2577 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2578 bf->bf_buf_addr = 0;
2580 goto skip_tx_complete;
2582 if (bf->bf_state.bfs_paprd) {
2583 if (time_after(jiffies,
2584 bf->bf_state.bfs_paprd_timestamp +
2585 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2586 dev_kfree_skb_any(skb);
2588 complete(&sc->paprd_complete);
2590 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2591 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2594 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2595 * accidentally reference it later.
2600 * Return the list of ath_buf of this mpdu to free queue
2602 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2603 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2604 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2607 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2608 struct ath_tx_status *ts, int nframes, int nbad,
2611 struct sk_buff *skb = bf->bf_mpdu;
2612 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2613 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2614 struct ieee80211_hw *hw = sc->hw;
2615 struct ath_hw *ah = sc->sc_ah;
2619 tx_info->status.ack_signal = ts->ts_rssi;
2621 tx_rateindex = ts->ts_rateindex;
2622 WARN_ON(tx_rateindex >= hw->max_rates);
2624 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2625 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2627 BUG_ON(nbad > nframes);
2629 tx_info->status.ampdu_len = nframes;
2630 tx_info->status.ampdu_ack_len = nframes - nbad;
2632 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2633 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2635 * If an underrun error is seen assume it as an excessive
2636 * retry only if max frame trigger level has been reached
2637 * (2 KB for single stream, and 4 KB for dual stream).
2638 * Adjust the long retry as if the frame was tried
2639 * hw->max_rate_tries times to affect how rate control updates
2640 * PER for the failed rate.
2641 * In case of congestion on the bus penalizing this type of
2642 * underruns should help hardware actually transmit new frames
2643 * successfully by eventually preferring slower rates.
2644 * This itself should also alleviate congestion on the bus.
2646 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2647 ATH9K_TX_DELIM_UNDERRUN)) &&
2648 ieee80211_is_data(hdr->frame_control) &&
2649 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2650 tx_info->status.rates[tx_rateindex].count =
2654 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2655 tx_info->status.rates[i].count = 0;
2656 tx_info->status.rates[i].idx = -1;
2659 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2662 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2664 struct ath_hw *ah = sc->sc_ah;
2665 struct ath_common *common = ath9k_hw_common(ah);
2666 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2667 struct list_head bf_head;
2668 struct ath_desc *ds;
2669 struct ath_tx_status ts;
2672 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2673 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2676 ath_txq_lock(sc, txq);
2678 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2681 if (list_empty(&txq->axq_q)) {
2682 txq->axq_link = NULL;
2683 ath_txq_schedule(sc, txq);
2686 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2689 * There is a race condition that a BH gets scheduled
2690 * after sw writes TxE and before hw re-load the last
2691 * descriptor to get the newly chained one.
2692 * Software must keep the last DONE descriptor as a
2693 * holding descriptor - software does so by marking
2694 * it with the STALE flag.
2697 if (bf->bf_state.stale) {
2699 if (list_is_last(&bf_held->list, &txq->axq_q))
2702 bf = list_entry(bf_held->list.next, struct ath_buf,
2706 lastbf = bf->bf_lastbf;
2707 ds = lastbf->bf_desc;
2709 memset(&ts, 0, sizeof(ts));
2710 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2711 if (status == -EINPROGRESS)
2714 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2717 * Remove ath_buf's of the same transmit unit from txq,
2718 * however leave the last descriptor back as the holding
2719 * descriptor for hw.
2721 lastbf->bf_state.stale = true;
2722 INIT_LIST_HEAD(&bf_head);
2723 if (!list_is_singular(&lastbf->list))
2724 list_cut_position(&bf_head,
2725 &txq->axq_q, lastbf->list.prev);
2728 list_del(&bf_held->list);
2729 ath_tx_return_buffer(sc, bf_held);
2732 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2734 ath_txq_unlock_complete(sc, txq);
2737 void ath_tx_tasklet(struct ath_softc *sc)
2739 struct ath_hw *ah = sc->sc_ah;
2740 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2744 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2745 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2746 ath_tx_processq(sc, &sc->tx.txq[i]);
2751 void ath_tx_edma_tasklet(struct ath_softc *sc)
2753 struct ath_tx_status ts;
2754 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2755 struct ath_hw *ah = sc->sc_ah;
2756 struct ath_txq *txq;
2757 struct ath_buf *bf, *lastbf;
2758 struct list_head bf_head;
2759 struct list_head *fifo_list;
2764 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2767 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2768 if (status == -EINPROGRESS)
2770 if (status == -EIO) {
2771 ath_dbg(common, XMIT, "Error processing tx status\n");
2775 /* Process beacon completions separately */
2776 if (ts.qid == sc->beacon.beaconq) {
2777 sc->beacon.tx_processed = true;
2778 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2780 if (ath9k_is_chanctx_enabled()) {
2781 ath_chanctx_event(sc, NULL,
2782 ATH_CHANCTX_EVENT_BEACON_SENT);
2785 ath9k_csa_update(sc);
2789 txq = &sc->tx.txq[ts.qid];
2791 ath_txq_lock(sc, txq);
2793 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2795 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2796 if (list_empty(fifo_list)) {
2797 ath_txq_unlock(sc, txq);
2801 bf = list_first_entry(fifo_list, struct ath_buf, list);
2802 if (bf->bf_state.stale) {
2803 list_del(&bf->list);
2804 ath_tx_return_buffer(sc, bf);
2805 bf = list_first_entry(fifo_list, struct ath_buf, list);
2808 lastbf = bf->bf_lastbf;
2810 INIT_LIST_HEAD(&bf_head);
2811 if (list_is_last(&lastbf->list, fifo_list)) {
2812 list_splice_tail_init(fifo_list, &bf_head);
2813 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2815 if (!list_empty(&txq->axq_q)) {
2816 struct list_head bf_q;
2818 INIT_LIST_HEAD(&bf_q);
2819 txq->axq_link = NULL;
2820 list_splice_tail_init(&txq->axq_q, &bf_q);
2821 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2824 lastbf->bf_state.stale = true;
2826 list_cut_position(&bf_head, fifo_list,
2830 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2831 ath_txq_unlock_complete(sc, txq);
2840 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2842 struct ath_descdma *dd = &sc->txsdma;
2843 u8 txs_len = sc->sc_ah->caps.txs_len;
2845 dd->dd_desc_len = size * txs_len;
2846 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2847 &dd->dd_desc_paddr, GFP_KERNEL);
2854 static int ath_tx_edma_init(struct ath_softc *sc)
2858 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2860 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2861 sc->txsdma.dd_desc_paddr,
2862 ATH_TXSTATUS_RING_SIZE);
2867 int ath_tx_init(struct ath_softc *sc, int nbufs)
2869 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2872 spin_lock_init(&sc->tx.txbuflock);
2874 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2878 "Failed to allocate tx descriptors: %d\n", error);
2882 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2883 "beacon", ATH_BCBUF, 1, 1);
2886 "Failed to allocate beacon descriptors: %d\n", error);
2890 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2892 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2893 error = ath_tx_edma_init(sc);
2898 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2900 struct ath_atx_tid *tid;
2903 for (tidno = 0, tid = &an->tid[tidno];
2904 tidno < IEEE80211_NUM_TIDS;
2908 tid->seq_start = tid->seq_next = 0;
2909 tid->baw_size = WME_MAX_BA;
2910 tid->baw_head = tid->baw_tail = 0;
2911 tid->active = false;
2912 tid->clear_ps_filter = true;
2913 __skb_queue_head_init(&tid->buf_q);
2914 __skb_queue_head_init(&tid->retry_q);
2915 INIT_LIST_HEAD(&tid->list);
2916 acno = TID_TO_WME_AC(tidno);
2917 tid->txq = sc->tx.txq_map[acno];
2921 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2923 struct ath_atx_tid *tid;
2924 struct ath_txq *txq;
2927 for (tidno = 0, tid = &an->tid[tidno];
2928 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2932 ath_txq_lock(sc, txq);
2934 if (!list_empty(&tid->list))
2935 list_del_init(&tid->list);
2937 ath_tid_drain(sc, txq, tid);
2938 tid->active = false;
2940 ath_txq_unlock(sc, txq);
2944 #ifdef CONFIG_ATH9K_TX99
2946 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2947 struct ath_tx_control *txctl)
2949 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2950 struct ath_frame_info *fi = get_frame_info(skb);
2951 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2953 int padpos, padsize;
2955 padpos = ieee80211_hdrlen(hdr->frame_control);
2956 padsize = padpos & 3;
2958 if (padsize && skb->len > padpos) {
2959 if (skb_headroom(skb) < padsize) {
2960 ath_dbg(common, XMIT,
2961 "tx99 padding failed\n");
2965 skb_push(skb, padsize);
2966 memmove(skb->data, skb->data + padsize, padpos);
2969 fi->keyix = ATH9K_TXKEYIX_INVALID;
2970 fi->framelen = skb->len + FCS_LEN;
2971 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2973 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2975 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2979 ath_set_rates(sc->tx99_vif, NULL, bf);
2981 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2982 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2984 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2989 #endif /* CONFIG_ATH9K_TX99 */