drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/delay.h>
  19 #include "ath9k.h"
  20 #include "btcoex.h"
  21
  22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23 {
  24         /*
  25          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26          *   0 for no restriction
  27          *   1 for 1/4 us
  28          *   2 for 1/2 us
  29          *   3 for 1 us
  30          *   4 for 2 us
  31          *   5 for 4 us
  32          *   6 for 8 us
  33          *   7 for 16 us
  34          */
  35         switch (mpdudensity) {
  36         case 0:
  37                 return 0;
  38         case 1:
  39         case 2:
  40         case 3:
  41                 /* Our lower layer calculations limit our precision to
  42                    1 microsecond */
  43                 return 1;
  44         case 4:
  45                 return 2;
  46         case 5:
  47                 return 4;
  48         case 6:
  49                 return 8;
  50         case 7:
  51                 return 16;
  52         default:
  53                 return 0;
  54         }
  55 }
  56
  57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
  58                                      bool sw_pending)
  59 {
  60         bool pending = false;
  61
  62         spin_lock_bh(&txq->axq_lock);
  63
  64         if (txq->axq_depth) {
  65                 pending = true;
  66                 goto out;
  67         }
  68
  69         if (!sw_pending)
  70                 goto out;
  71
  72         if (txq->mac80211_qnum >= 0) {
  73                 struct ath_acq *acq;
  74
  75                 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
  76                 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
  77                         pending = true;
  78         }
  79 out:
  80         spin_unlock_bh(&txq->axq_lock);
  81         return pending;
  82 }
  83
  84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  85 {
  86         unsigned long flags;
  87         bool ret;
  88
  89         spin_lock_irqsave(&sc->sc_pm_lock, flags);
  90         ret = ath9k_hw_setpower(sc->sc_ah, mode);
  91         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  92
  93         return ret;
  94 }
  95
  96 void ath_ps_full_sleep(struct timer_list *t)
  97 {
  98         struct ath_softc *sc = from_timer(sc, t, sleep_timer);
  99         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 100         unsigned long flags;
 101         bool reset;
 102
 103         spin_lock_irqsave(&common->cc_lock, flags);
 104         ath_hw_cycle_counters_update(common);
 105         spin_unlock_irqrestore(&common->cc_lock, flags);
 106
 107         ath9k_hw_setrxabort(sc->sc_ah, 1);
 108         ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
 109
 110         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 111 }
 112
 113 void ath9k_ps_wakeup(struct ath_softc *sc)
 114 {
 115         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 116         unsigned long flags;
 117         enum ath9k_power_mode power_mode;
 118
 119         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 120         if (++sc->ps_usecount != 1)
 121                 goto unlock;
 122
 123         del_timer_sync(&sc->sleep_timer);
 124         power_mode = sc->sc_ah->power_mode;
 125         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 126
 127         /*
 128          * While the hardware is asleep, the cycle counters contain no
 129          * useful data. Better clear them now so that they don't mess up
 130          * survey data results.
 131          */
 132         if (power_mode != ATH9K_PM_AWAKE) {
 133                 spin_lock(&common->cc_lock);
 134                 ath_hw_cycle_counters_update(common);
 135                 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
 136                 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
 137                 spin_unlock(&common->cc_lock);
 138         }
 139
 140  unlock:
 141         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 142 }
 143
 144 void ath9k_ps_restore(struct ath_softc *sc)
 145 {
 146         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 147         enum ath9k_power_mode mode;
 148         unsigned long flags;
 149
 150         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 151         if (--sc->ps_usecount != 0)
 152                 goto unlock;
 153
 154         if (sc->ps_idle) {
 155                 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
 156                 goto unlock;
 157         }
 158
 159         if (sc->ps_enabled &&
 160                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
 161                                      PS_WAIT_FOR_CAB |
 162                                      PS_WAIT_FOR_PSPOLL_DATA |
 163                                      PS_WAIT_FOR_TX_ACK |
 164                                      PS_WAIT_FOR_ANI))) {
 165                 mode = ATH9K_PM_NETWORK_SLEEP;
 166                 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
 167                         ath9k_btcoex_stop_gen_timer(sc);
 168         } else {
 169                 goto unlock;
 170         }
 171
 172         spin_lock(&common->cc_lock);
 173         ath_hw_cycle_counters_update(common);
 174         spin_unlock(&common->cc_lock);
 175
 176         ath9k_hw_setpower(sc->sc_ah, mode);
 177
 178  unlock:
 179         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 180 }
 181
 182 static void __ath_cancel_work(struct ath_softc *sc)
 183 {
 184         cancel_work_sync(&sc->paprd_work);
 185         cancel_delayed_work_sync(&sc->hw_check_work);
 186         cancel_delayed_work_sync(&sc->hw_pll_work);
 187
 188 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 189         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
 190                 cancel_work_sync(&sc->mci_work);
 191 #endif
 192 }
 193
 194 void ath_cancel_work(struct ath_softc *sc)
 195 {
 196         __ath_cancel_work(sc);
 197         cancel_work_sync(&sc->hw_reset_work);
 198 }
 199
 200 void ath_restart_work(struct ath_softc *sc)
 201 {
 202         ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
 203                                      ATH_HW_CHECK_POLL_INT);
 204
 205         if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
 206                 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
 207                                      msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
 208
 209         ath_start_ani(sc);
 210 }
 211
 212 static bool ath_prepare_reset(struct ath_softc *sc)
 213 {
 214         struct ath_hw *ah = sc->sc_ah;
 215         bool ret = true;
 216
 217         ieee80211_stop_queues(sc->hw);
 218         ath_stop_ani(sc);
 219         ath9k_hw_disable_interrupts(ah);
 220
 221         if (AR_SREV_9300_20_OR_LATER(ah)) {
 222                 ret &= ath_stoprecv(sc);
 223                 ret &= ath_drain_all_txq(sc);
 224         } else {
 225                 ret &= ath_drain_all_txq(sc);
 226                 ret &= ath_stoprecv(sc);
 227         }
 228
 229         return ret;
 230 }
 231
 232 static bool ath_complete_reset(struct ath_softc *sc, bool start)
 233 {
 234         struct ath_hw *ah = sc->sc_ah;
 235         struct ath_common *common = ath9k_hw_common(ah);
 236         unsigned long flags;
 237
 238         ath9k_calculate_summary_state(sc, sc->cur_chan);
 239         ath_startrecv(sc);
 240         ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
 241                                sc->cur_chan->txpower,
 242                                &sc->cur_chan->cur_txpower);
 243         clear_bit(ATH_OP_HW_RESET, &common->op_flags);
 244
 245         if (!sc->cur_chan->offchannel && start) {
 246                 /* restore per chanctx TSF timer */
 247                 if (sc->cur_chan->tsf_val) {
 248                         u32 offset;
 249
 250                         offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
 251                                                          NULL);
 252                         ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
 253                 }
 254
 255
 256                 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
 257                         goto work;
 258
 259                 if (ah->opmode == NL80211_IFTYPE_STATION &&
 260                     test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
 261                         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 262                         sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
 263                         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 264                 } else {
 265                         ath9k_set_beacon(sc);
 266                 }
 267         work:
 268                 ath_restart_work(sc);
 269                 ath_txq_schedule_all(sc);
 270         }
 271
 272         sc->gtt_cnt = 0;
 273
 274         ath9k_hw_set_interrupts(ah);
 275         ath9k_hw_enable_interrupts(ah);
 276         ieee80211_wake_queues(sc->hw);
 277         ath9k_p2p_ps_timer(sc);
 278
 279         return true;
 280 }
 281
 282 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
 283 {
 284         struct ath_hw *ah = sc->sc_ah;
 285         struct ath_common *common = ath9k_hw_common(ah);
 286         struct ath9k_hw_cal_data *caldata = NULL;
 287         bool fastcc = true;
 288         int r;
 289
 290         __ath_cancel_work(sc);
 291
 292         disable_irq(sc->irq);
 293         tasklet_disable(&sc->intr_tq);
 294         tasklet_disable(&sc->bcon_tasklet);
 295         spin_lock_bh(&sc->sc_pcu_lock);
 296
 297         if (!sc->cur_chan->offchannel) {
 298                 fastcc = false;
 299                 caldata = &sc->cur_chan->caldata;
 300         }
 301
 302         if (!hchan) {
 303                 fastcc = false;
 304                 hchan = ah->curchan;
 305         }
 306
 307         if (!hchan) {
 308                 fastcc = false;
 309                 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
 310         }
 311
 312         if (!ath_prepare_reset(sc))
 313                 fastcc = false;
 314
 315         if (ath9k_is_chanctx_enabled())
 316                 fastcc = false;
 317
 318         spin_lock_bh(&sc->chan_lock);
 319         sc->cur_chandef = sc->cur_chan->chandef;
 320         spin_unlock_bh(&sc->chan_lock);
 321
 322         ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
 323                 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
 324
 325         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
 326         if (r) {
 327                 ath_err(common,
 328                         "Unable to reset channel, reset status %d\n", r);
 329
 330                 ath9k_hw_enable_interrupts(ah);
 331                 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
 332
 333                 goto out;
 334         }
 335
 336         if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
 337             sc->cur_chan->offchannel)
 338                 ath9k_mci_set_txpower(sc, true, false);
 339
 340         if (!ath_complete_reset(sc, true))
 341                 r = -EIO;
 342
 343 out:
 344         enable_irq(sc->irq);
 345         spin_unlock_bh(&sc->sc_pcu_lock);
 346         tasklet_enable(&sc->bcon_tasklet);
 347         tasklet_enable(&sc->intr_tq);
 348
 349         return r;
 350 }
 351
 352 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
 353                             struct ieee80211_vif *vif)
 354 {
 355         struct ath_node *an;
 356         an = (struct ath_node *)sta->drv_priv;
 357
 358         an->sc = sc;
 359         an->sta = sta;
 360         an->vif = vif;
 361         memset(&an->key_idx, 0, sizeof(an->key_idx));
 362
 363         ath_tx_node_init(sc, an);
 364
 365         ath_dynack_node_init(sc->sc_ah, an);
 366 }
 367
 368 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 369 {
 370         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 371         ath_tx_node_cleanup(sc, an);
 372
 373         ath_dynack_node_deinit(sc->sc_ah, an);
 374 }
 375
 376 void ath9k_tasklet(unsigned long data)
 377 {
 378         struct ath_softc *sc = (struct ath_softc *)data;
 379         struct ath_hw *ah = sc->sc_ah;
 380         struct ath_common *common = ath9k_hw_common(ah);
 381         enum ath_reset_type type;
 382         unsigned long flags;
 383         u32 status;
 384         u32 rxmask;
 385
 386         spin_lock_irqsave(&sc->intr_lock, flags);
 387         status = sc->intrstatus;
 388         sc->intrstatus = 0;
 389         spin_unlock_irqrestore(&sc->intr_lock, flags);
 390
 391         ath9k_ps_wakeup(sc);
 392         spin_lock(&sc->sc_pcu_lock);
 393
 394         if (status & ATH9K_INT_FATAL) {
 395                 type = RESET_TYPE_FATAL_INT;
 396                 ath9k_queue_reset(sc, type);
 397                 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
 398                 goto out;
 399         }
 400
 401         if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 402             (status & ATH9K_INT_BB_WATCHDOG)) {
 403                 spin_lock_irqsave(&common->cc_lock, flags);
 404                 ath_hw_cycle_counters_update(common);
 405                 ar9003_hw_bb_watchdog_dbg_info(ah);
 406                 spin_unlock_irqrestore(&common->cc_lock, flags);
 407
 408                 if (ar9003_hw_bb_watchdog_check(ah)) {
 409                         type = RESET_TYPE_BB_WATCHDOG;
 410                         ath9k_queue_reset(sc, type);
 411
 412                         ath_dbg(common, RESET,
 413                                 "BB_WATCHDOG: Skipping interrupts\n");
 414                         goto out;
 415                 }
 416         }
 417
 418         if (status & ATH9K_INT_GTT) {
 419                 sc->gtt_cnt++;
 420
 421                 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
 422                         type = RESET_TYPE_TX_GTT;
 423                         ath9k_queue_reset(sc, type);
 424                         ath_dbg(common, RESET,
 425                                 "GTT: Skipping interrupts\n");
 426                         goto out;
 427                 }
 428         }
 429
 430         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 431         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 432                 /*
 433                  * TSF sync does not look correct; remain awake to sync with
 434                  * the next Beacon.
 435                  */
 436                 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
 437                 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
 438         }
 439         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 440
 441         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 442                 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
 443                           ATH9K_INT_RXORN);
 444         else
 445                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 446
 447         if (status & rxmask) {
 448                 /* Check for high priority Rx first */
 449                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 450                     (status & ATH9K_INT_RXHP))
 451                         ath_rx_tasklet(sc, 0, true);
 452
 453                 ath_rx_tasklet(sc, 0, false);
 454         }
 455
 456         if (status & ATH9K_INT_TX) {
 457                 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 458                         /*
 459                          * For EDMA chips, TX completion is enabled for the
 460                          * beacon queue, so if a beacon has been transmitted
 461                          * successfully after a GTT interrupt, the GTT counter
 462                          * gets reset to zero here.
 463                          */
 464                         sc->gtt_cnt = 0;
 465
 466                         ath_tx_edma_tasklet(sc);
 467                 } else {
 468                         ath_tx_tasklet(sc);
 469                 }
 470
 471                 wake_up(&sc->tx_wait);
 472         }
 473
 474         if (status & ATH9K_INT_GENTIMER)
 475                 ath_gen_timer_isr(sc->sc_ah);
 476
 477         ath9k_btcoex_handle_interrupt(sc, status);
 478
 479         /* re-enable hardware interrupt */
 480         ath9k_hw_resume_interrupts(ah);
 481 out:
 482         spin_unlock(&sc->sc_pcu_lock);
 483         ath9k_ps_restore(sc);
 484 }
 485
 486 irqreturn_t ath_isr(int irq, void *dev)
 487 {
 488 #define SCHED_INTR (                            \
 489                 ATH9K_INT_FATAL |               \
 490                 ATH9K_INT_BB_WATCHDOG |         \
 491                 ATH9K_INT_RXORN |               \
 492                 ATH9K_INT_RXEOL |               \
 493                 ATH9K_INT_RX |                  \
 494                 ATH9K_INT_RXLP |                \
 495                 ATH9K_INT_RXHP |                \
 496                 ATH9K_INT_TX |                  \
 497                 ATH9K_INT_BMISS |               \
 498                 ATH9K_INT_CST |                 \
 499                 ATH9K_INT_GTT |                 \
 500                 ATH9K_INT_TSFOOR |              \
 501                 ATH9K_INT_GENTIMER |            \
 502                 ATH9K_INT_MCI)
 503
 504         struct ath_softc *sc = dev;
 505         struct ath_hw *ah = sc->sc_ah;
 506         struct ath_common *common = ath9k_hw_common(ah);
 507         enum ath9k_int status;
 508         u32 sync_cause = 0;
 509         bool sched = false;
 510
 511         /*
 512          * The hardware is not ready/present, don't
 513          * touch anything. Note this can happen early
 514          * on if the IRQ is shared.
 515          */
 516         if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
 517                 return IRQ_NONE;
 518
 519         /* shared irq, not for us */
 520         if (!ath9k_hw_intrpend(ah))
 521                 return IRQ_NONE;
 522
 523         /*
 524          * Figure out the reason(s) for the interrupt.  Note
 525          * that the hal returns a pseudo-ISR that may include
 526          * bits we haven't explicitly enabled so we mask the
 527          * value to insure we only process bits we requested.
 528          */
 529         ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
 530         ath9k_debug_sync_cause(sc, sync_cause);
 531         status &= ah->imask;    /* discard unasked-for bits */
 532
 533         if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
 534                 return IRQ_HANDLED;
 535
 536         /*
 537          * If there are no status bits set, then this interrupt was not
 538          * for me (should have been caught above).
 539          */
 540         if (!status)
 541                 return IRQ_NONE;
 542
 543         /* Cache the status */
 544         spin_lock(&sc->intr_lock);
 545         sc->intrstatus |= status;
 546         spin_unlock(&sc->intr_lock);
 547
 548         if (status & SCHED_INTR)
 549                 sched = true;
 550
 551         /*
 552          * If a FATAL interrupt is received, we have to reset the chip
 553          * immediately.
 554          */
 555         if (status & ATH9K_INT_FATAL)
 556                 goto chip_reset;
 557
 558         if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 559             (status & ATH9K_INT_BB_WATCHDOG))
 560                 goto chip_reset;
 561
 562         if (status & ATH9K_INT_SWBA)
 563                 tasklet_schedule(&sc->bcon_tasklet);
 564
 565         if (status & ATH9K_INT_TXURN)
 566                 ath9k_hw_updatetxtriglevel(ah, true);
 567
 568         if (status & ATH9K_INT_RXEOL) {
 569                 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 570                 ath9k_hw_set_interrupts(ah);
 571         }
 572
 573         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 574                 if (status & ATH9K_INT_TIM_TIMER) {
 575                         if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
 576                                 goto chip_reset;
 577                         /* Clear RxAbort bit so that we can
 578                          * receive frames */
 579                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 580                         spin_lock(&sc->sc_pm_lock);
 581                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 582                         sc->ps_flags |= PS_WAIT_FOR_BEACON;
 583                         spin_unlock(&sc->sc_pm_lock);
 584                 }
 585
 586 chip_reset:
 587
 588         ath_debug_stat_interrupt(sc, status);
 589
 590         if (sched) {
 591                 /* turn off every interrupt */
 592                 ath9k_hw_kill_interrupts(ah);
 593                 tasklet_schedule(&sc->intr_tq);
 594         }
 595
 596         return IRQ_HANDLED;
 597
 598 #undef SCHED_INTR
 599 }
 600
 601 /*
 602  * This function is called when a HW reset cannot be deferred
 603  * and has to be immediate.
 604  */
 605 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
 606 {
 607         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 608         int r;
 609
 610         ath9k_hw_kill_interrupts(sc->sc_ah);
 611         set_bit(ATH_OP_HW_RESET, &common->op_flags);
 612
 613         ath9k_ps_wakeup(sc);
 614         r = ath_reset_internal(sc, hchan);
 615         ath9k_ps_restore(sc);
 616
 617         return r;
 618 }
 619
 620 /*
 621  * When a HW reset can be deferred, it is added to the
 622  * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
 623  * queueing.
 624  */
 625 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
 626 {
 627         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 628 #ifdef CONFIG_ATH9K_DEBUGFS
 629         RESET_STAT_INC(sc, type);
 630 #endif
 631         ath9k_hw_kill_interrupts(sc->sc_ah);
 632         set_bit(ATH_OP_HW_RESET, &common->op_flags);
 633         ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
 634 }
 635
 636 void ath_reset_work(struct work_struct *work)
 637 {
 638         struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
 639
 640         ath9k_ps_wakeup(sc);
 641         ath_reset_internal(sc, NULL);
 642         ath9k_ps_restore(sc);
 643 }
 644
 645 /**********************/
 646 /* mac80211 callbacks */
 647 /**********************/
 648
 649 static int ath9k_start(struct ieee80211_hw *hw)
 650 {
 651         struct ath_softc *sc = hw->priv;
 652         struct ath_hw *ah = sc->sc_ah;
 653         struct ath_common *common = ath9k_hw_common(ah);
 654         struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
 655         struct ath_chanctx *ctx = sc->cur_chan;
 656         struct ath9k_channel *init_channel;
 657         int r;
 658
 659         ath_dbg(common, CONFIG,
 660                 "Starting driver with initial channel: %d MHz\n",
 661                 curchan->center_freq);
 662
 663         ath9k_ps_wakeup(sc);
 664         mutex_lock(&sc->mutex);
 665
 666         init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
 667         sc->cur_chandef = hw->conf.chandef;
 668
 669         /* Reset SERDES registers */
 670         ath9k_hw_configpcipowersave(ah, false);
 671
 672         /*
 673          * The basic interface to setting the hardware in a good
 674          * state is ``reset''.  On return the hardware is known to
 675          * be powered up and with interrupts disabled.  This must
 676          * be followed by initialization of the appropriate bits
 677          * and then setup of the interrupt mask.
 678          */
 679         spin_lock_bh(&sc->sc_pcu_lock);
 680
 681         atomic_set(&ah->intr_ref_cnt, -1);
 682
 683         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
 684         if (r) {
 685                 ath_err(common,
 686                         "Unable to reset hardware; reset status %d (freq %u MHz)\n",
 687                         r, curchan->center_freq);
 688                 ah->reset_power_on = false;
 689         }
 690
 691         /* Setup our intr mask. */
 692         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
 693                     ATH9K_INT_RXORN | ATH9K_INT_FATAL |
 694                     ATH9K_INT_GLOBAL;
 695
 696         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 697                 ah->imask |= ATH9K_INT_RXHP |
 698                              ATH9K_INT_RXLP;
 699         else
 700                 ah->imask |= ATH9K_INT_RX;
 701
 702         if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
 703                 ah->imask |= ATH9K_INT_BB_WATCHDOG;
 704
 705         /*
 706          * Enable GTT interrupts only for AR9003/AR9004 chips
 707          * for now.
 708          */
 709         if (AR_SREV_9300_20_OR_LATER(ah))
 710                 ah->imask |= ATH9K_INT_GTT;
 711
 712         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
 713                 ah->imask |= ATH9K_INT_CST;
 714
 715         ath_mci_enable(sc);
 716
 717         clear_bit(ATH_OP_INVALID, &common->op_flags);
 718         sc->sc_ah->is_monitoring = false;
 719
 720         if (!ath_complete_reset(sc, false))
 721                 ah->reset_power_on = false;
 722
 723         if (ah->led_pin >= 0) {
 724                 ath9k_hw_set_gpio(ah, ah->led_pin,
 725                                   (ah->config.led_active_high) ? 1 : 0);
 726                 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
 727                                           AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 728         }
 729
 730         /*
 731          * Reset key cache to sane defaults (all entries cleared) instead of
 732          * semi-random values after suspend/resume.
 733          */
 734         ath9k_cmn_init_crypto(sc->sc_ah);
 735
 736         ath9k_hw_reset_tsf(ah);
 737
 738         spin_unlock_bh(&sc->sc_pcu_lock);
 739
 740         ath9k_rng_start(sc);
 741
 742         mutex_unlock(&sc->mutex);
 743
 744         ath9k_ps_restore(sc);
 745
 746         return 0;
 747 }
 748
 749 static void ath9k_tx(struct ieee80211_hw *hw,
 750                      struct ieee80211_tx_control *control,
 751                      struct sk_buff *skb)
 752 {
 753         struct ath_softc *sc = hw->priv;
 754         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 755         struct ath_tx_control txctl;
 756         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 757         unsigned long flags;
 758
 759         if (sc->ps_enabled) {
 760                 /*
 761                  * mac80211 does not set PM field for normal data frames, so we
 762                  * need to update that based on the current PS mode.
 763                  */
 764                 if (ieee80211_is_data(hdr->frame_control) &&
 765                     !ieee80211_is_nullfunc(hdr->frame_control) &&
 766                     !ieee80211_has_pm(hdr->frame_control)) {
 767                         ath_dbg(common, PS,
 768                                 "Add PM=1 for a TX frame while in PS mode\n");
 769                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
 770                 }
 771         }
 772
 773         if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
 774                 /*
 775                  * We are using PS-Poll and mac80211 can request TX while in
 776                  * power save mode. Need to wake up hardware for the TX to be
 777                  * completed and if needed, also for RX of buffered frames.
 778                  */
 779                 ath9k_ps_wakeup(sc);
 780                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
 781                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 782                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 783                 if (ieee80211_is_pspoll(hdr->frame_control)) {
 784                         ath_dbg(common, PS,
 785                                 "Sending PS-Poll to pick a buffered frame\n");
 786                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
 787                 } else {
 788                         ath_dbg(common, PS, "Wake up to complete TX\n");
 789                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
 790                 }
 791                 /*
 792                  * The actual restore operation will happen only after
 793                  * the ps_flags bit is cleared. We are just dropping
 794                  * the ps_usecount here.
 795                  */
 796                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 797                 ath9k_ps_restore(sc);
 798         }
 799
 800         /*
 801          * Cannot tx while the hardware is in full sleep, it first needs a full
 802          * chip reset to recover from that
 803          */
 804         if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
 805                 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
 806                 goto exit;
 807         }
 808
 809         memset(&txctl, 0, sizeof(struct ath_tx_control));
 810         txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
 811         txctl.sta = control->sta;
 812
 813         ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
 814
 815         if (ath_tx_start(hw, skb, &txctl) != 0) {
 816                 ath_dbg(common, XMIT, "TX failed\n");
 817                 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
 818                 goto exit;
 819         }
 820
 821         return;
 822 exit:
 823         ieee80211_free_txskb(hw, skb);
 824 }
 825
 826 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
 827 {
 828         struct ath_buf *bf;
 829         struct ieee80211_tx_info *txinfo;
 830         struct ath_frame_info *fi;
 831
 832         list_for_each_entry(bf, txq_list, list) {
 833                 if (bf->bf_state.stale || !bf->bf_mpdu)
 834                         continue;
 835
 836                 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
 837                 fi = (struct ath_frame_info *)&txinfo->rate_driver_data[0];
 838                 if (fi->keyix == keyix)
 839                         return true;
 840         }
 841
 842         return false;
 843 }
 844
 845 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
 846 {
 847         struct ath_hw *ah = sc->sc_ah;
 848         int i;
 849         struct ath_txq *txq;
 850         bool key_in_use = false;
 851
 852         for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
 853                 if (!ATH_TXQ_SETUP(sc, i))
 854                         continue;
 855                 txq = &sc->tx.txq[i];
 856                 if (!txq->axq_depth)
 857                         continue;
 858                 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
 859                         continue;
 860
 861                 ath_txq_lock(sc, txq);
 862                 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
 863                 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 864                         int idx = txq->txq_tailidx;
 865
 866                         while (!key_in_use &&
 867                                !list_empty(&txq->txq_fifo[idx])) {
 868                                 key_in_use = ath9k_txq_list_has_key(
 869                                         &txq->txq_fifo[idx], keyix);
 870                                 INCR(idx, ATH_TXFIFO_DEPTH);
 871                         }
 872                 }
 873                 ath_txq_unlock(sc, txq);
 874         }
 875
 876         return key_in_use;
 877 }
 878
 879 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
 880 {
 881         struct ath_hw *ah = sc->sc_ah;
 882         struct ath_common *common = ath9k_hw_common(ah);
 883
 884         if (!test_bit(keyix, ah->pending_del_keymap) ||
 885             ath9k_txq_has_key(sc, keyix))
 886                 return;
 887
 888         /* No more TXQ frames point to this key cache entry, so delete it. */
 889         clear_bit(keyix, ah->pending_del_keymap);
 890         ath_key_delete(common, keyix);
 891 }
 892
 893 static void ath9k_stop(struct ieee80211_hw *hw)
 894 {
 895         struct ath_softc *sc = hw->priv;
 896         struct ath_hw *ah = sc->sc_ah;
 897         struct ath_common *common = ath9k_hw_common(ah);
 898         bool prev_idle;
 899         int i;
 900
 901         ath9k_deinit_channel_context(sc);
 902
 903         mutex_lock(&sc->mutex);
 904
 905         ath9k_rng_stop(sc);
 906
 907         ath_cancel_work(sc);
 908
 909         if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
 910                 ath_dbg(common, ANY, "Device not present\n");
 911                 mutex_unlock(&sc->mutex);
 912                 return;
 913         }
 914
 915         /* Ensure HW is awake when we try to shut it down. */
 916         ath9k_ps_wakeup(sc);
 917
 918         spin_lock_bh(&sc->sc_pcu_lock);
 919
 920         /* prevent tasklets to enable interrupts once we disable them */
 921         ah->imask &= ~ATH9K_INT_GLOBAL;
 922
 923         /* make sure h/w will not generate any interrupt
 924          * before setting the invalid flag. */
 925         ath9k_hw_disable_interrupts(ah);
 926
 927         spin_unlock_bh(&sc->sc_pcu_lock);
 928
 929         /* we can now sync irq and kill any running tasklets, since we already
 930          * disabled interrupts and not holding a spin lock */
 931         synchronize_irq(sc->irq);
 932         tasklet_kill(&sc->intr_tq);
 933         tasklet_kill(&sc->bcon_tasklet);
 934
 935         prev_idle = sc->ps_idle;
 936         sc->ps_idle = true;
 937
 938         spin_lock_bh(&sc->sc_pcu_lock);
 939
 940         if (ah->led_pin >= 0) {
 941                 ath9k_hw_set_gpio(ah, ah->led_pin,
 942                                   (ah->config.led_active_high) ? 0 : 1);
 943                 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
 944         }
 945
 946         ath_prepare_reset(sc);
 947
 948         if (sc->rx.frag) {
 949                 dev_kfree_skb_any(sc->rx.frag);
 950                 sc->rx.frag = NULL;
 951         }
 952
 953         if (!ah->curchan)
 954                 ah->curchan = ath9k_cmn_get_channel(hw, ah,
 955                                                     &sc->cur_chan->chandef);
 956
 957         ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 958
 959         set_bit(ATH_OP_INVALID, &common->op_flags);
 960
 961         ath9k_hw_phy_disable(ah);
 962
 963         ath9k_hw_configpcipowersave(ah, true);
 964
 965         spin_unlock_bh(&sc->sc_pcu_lock);
 966
 967         for (i = 0; i < ATH_KEYMAX; i++)
 968                 ath9k_pending_key_del(sc, i);
 969
 970         /* Clear key cache entries explicitly to get rid of any potentially
 971          * remaining keys.
 972          */
 973         ath9k_cmn_init_crypto(sc->sc_ah);
 974
 975         ath9k_ps_restore(sc);
 976
 977         sc->ps_idle = prev_idle;
 978
 979         mutex_unlock(&sc->mutex);
 980
 981         ath_dbg(common, CONFIG, "Driver halt\n");
 982 }
 983
 984 static bool ath9k_uses_beacons(int type)
 985 {
 986         switch (type) {
 987         case NL80211_IFTYPE_AP:
 988         case NL80211_IFTYPE_ADHOC:
 989         case NL80211_IFTYPE_MESH_POINT:
 990                 return true;
 991         default:
 992                 return false;
 993         }
 994 }
 995
 996 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
 997                                       struct ieee80211_vif *vif)
 998 {
 999         /* Use the first (configured) interface, but prefering AP interfaces. */
1000         if (!iter_data->primary_beacon_vif) {
1001                 iter_data->primary_beacon_vif = vif;
1002         } else {
1003                 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1004                     vif->type == NL80211_IFTYPE_AP)
1005                         iter_data->primary_beacon_vif = vif;
1006         }
1007
1008         iter_data->beacons = true;
1009         iter_data->nbcnvifs += 1;
1010 }
1011
1012 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1013                            u8 *mac, struct ieee80211_vif *vif)
1014 {
1015         struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1016         int i;
1017
1018         if (iter_data->has_hw_macaddr) {
1019                 for (i = 0; i < ETH_ALEN; i++)
1020                         iter_data->mask[i] &=
1021                                 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1022         } else {
1023                 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1024                 iter_data->has_hw_macaddr = true;
1025         }
1026
1027         if (!vif->bss_conf.use_short_slot)
1028                 iter_data->slottime = 20;
1029
1030         switch (vif->type) {
1031         case NL80211_IFTYPE_AP:
1032                 iter_data->naps++;
1033                 if (vif->bss_conf.enable_beacon)
1034                         ath9k_vif_iter_set_beacon(iter_data, vif);
1035                 break;
1036         case NL80211_IFTYPE_STATION:
1037                 iter_data->nstations++;
1038                 if (avp->assoc && !iter_data->primary_sta)
1039                         iter_data->primary_sta = vif;
1040                 break;
1041         case NL80211_IFTYPE_OCB:
1042                 iter_data->nocbs++;
1043                 break;
1044         case NL80211_IFTYPE_ADHOC:
1045                 iter_data->nadhocs++;
1046                 if (vif->bss_conf.enable_beacon)
1047                         ath9k_vif_iter_set_beacon(iter_data, vif);
1048                 break;
1049         case NL80211_IFTYPE_MESH_POINT:
1050                 iter_data->nmeshes++;
1051                 if (vif->bss_conf.enable_beacon)
1052                         ath9k_vif_iter_set_beacon(iter_data, vif);
1053                 break;
1054         case NL80211_IFTYPE_WDS:
1055                 iter_data->nwds++;
1056                 break;
1057         default:
1058                 break;
1059         }
1060 }
1061
1062 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1063                                     struct ath_chanctx *ctx,
1064                                     struct ath9k_vif_iter_data *iter_data)
1065 {
1066         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1067         struct ath_vif *avp;
1068         int i;
1069
1070         if (!ath9k_is_chanctx_enabled())
1071                 return;
1072
1073         list_for_each_entry(avp, &ctx->vifs, list) {
1074                 if (ctx->nvifs_assigned != 1)
1075                         continue;
1076
1077                 if (!iter_data->has_hw_macaddr)
1078                         continue;
1079
1080                 ether_addr_copy(common->curbssid, avp->bssid);
1081
1082                 /* perm_addr will be used as the p2p device address. */
1083                 for (i = 0; i < ETH_ALEN; i++)
1084                         iter_data->mask[i] &=
1085                                 ~(iter_data->hw_macaddr[i] ^
1086                                   sc->hw->wiphy->perm_addr[i]);
1087         }
1088 }
1089
1090 /* Called with sc->mutex held. */
1091 void ath9k_calculate_iter_data(struct ath_softc *sc,
1092                                struct ath_chanctx *ctx,
1093                                struct ath9k_vif_iter_data *iter_data)
1094 {
1095         struct ath_vif *avp;
1096
1097         /*
1098          * The hardware will use primary station addr together with the
1099          * BSSID mask when matching addresses.
1100          */
1101         memset(iter_data, 0, sizeof(*iter_data));
1102         eth_broadcast_addr(iter_data->mask);
1103         iter_data->slottime = 9;
1104
1105         list_for_each_entry(avp, &ctx->vifs, list)
1106                 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1107
1108         ath9k_update_bssid_mask(sc, ctx, iter_data);
1109 }
1110
1111 static void ath9k_set_assoc_state(struct ath_softc *sc,
1112                                   struct ieee80211_vif *vif, bool changed)
1113 {
1114         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1115         struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1116         unsigned long flags;
1117
1118         set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1119
1120         ether_addr_copy(common->curbssid, avp->bssid);
1121         common->curaid = avp->aid;
1122         ath9k_hw_write_associd(sc->sc_ah);
1123
1124         if (changed) {
1125                 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1126                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1127
1128                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1129                 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1130                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1131         }
1132
1133         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1134                 ath9k_mci_update_wlan_channels(sc, false);
1135
1136         ath_dbg(common, CONFIG,
1137                 "Primary Station interface: %pM, BSSID: %pM\n",
1138                 vif->addr, common->curbssid);
1139 }
1140
1141 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1142 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1143 {
1144         struct ath_hw *ah = sc->sc_ah;
1145         struct ath_common *common = ath9k_hw_common(ah);
1146         struct ieee80211_vif *vif = NULL;
1147
1148         ath9k_ps_wakeup(sc);
1149
1150         if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1151                 vif = sc->offchannel.scan_vif;
1152         else
1153                 vif = sc->offchannel.roc_vif;
1154
1155         if (WARN_ON(!vif))
1156                 goto exit;
1157
1158         eth_zero_addr(common->curbssid);
1159         eth_broadcast_addr(common->bssidmask);
1160         memcpy(common->macaddr, vif->addr, ETH_ALEN);
1161         common->curaid = 0;
1162         ah->opmode = vif->type;
1163         ah->imask &= ~ATH9K_INT_SWBA;
1164         ah->imask &= ~ATH9K_INT_TSFOOR;
1165         ah->slottime = 9;
1166
1167         ath_hw_setbssidmask(common);
1168         ath9k_hw_setopmode(ah);
1169         ath9k_hw_write_associd(sc->sc_ah);
1170         ath9k_hw_set_interrupts(ah);
1171         ath9k_hw_init_global_settings(ah);
1172
1173 exit:
1174         ath9k_ps_restore(sc);
1175 }
1176 #endif
1177
1178 /* Called with sc->mutex held. */
1179 void ath9k_calculate_summary_state(struct ath_softc *sc,
1180                                    struct ath_chanctx *ctx)
1181 {
1182         struct ath_hw *ah = sc->sc_ah;
1183         struct ath_common *common = ath9k_hw_common(ah);
1184         struct ath9k_vif_iter_data iter_data;
1185
1186         ath_chanctx_check_active(sc, ctx);
1187
1188         if (ctx != sc->cur_chan)
1189                 return;
1190
1191 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1192         if (ctx == &sc->offchannel.chan)
1193                 return ath9k_set_offchannel_state(sc);
1194 #endif
1195
1196         ath9k_ps_wakeup(sc);
1197         ath9k_calculate_iter_data(sc, ctx, &iter_data);
1198
1199         if (iter_data.has_hw_macaddr)
1200                 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1201
1202         memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1203         ath_hw_setbssidmask(common);
1204
1205         if (iter_data.naps > 0) {
1206                 ath9k_hw_set_tsfadjust(ah, true);
1207                 ah->opmode = NL80211_IFTYPE_AP;
1208         } else {
1209                 ath9k_hw_set_tsfadjust(ah, false);
1210                 if (iter_data.beacons)
1211                         ath9k_beacon_ensure_primary_slot(sc);
1212
1213                 if (iter_data.nmeshes)
1214                         ah->opmode = NL80211_IFTYPE_MESH_POINT;
1215                 else if (iter_data.nocbs)
1216                         ah->opmode = NL80211_IFTYPE_OCB;
1217                 else if (iter_data.nwds)
1218                         ah->opmode = NL80211_IFTYPE_AP;
1219                 else if (iter_data.nadhocs)
1220                         ah->opmode = NL80211_IFTYPE_ADHOC;
1221                 else
1222                         ah->opmode = NL80211_IFTYPE_STATION;
1223         }
1224
1225         ath9k_hw_setopmode(ah);
1226
1227         ctx->switch_after_beacon = false;
1228         if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1229                 ah->imask |= ATH9K_INT_TSFOOR;
1230         else {
1231                 ah->imask &= ~ATH9K_INT_TSFOOR;
1232                 if (iter_data.naps == 1 && iter_data.beacons)
1233                         ctx->switch_after_beacon = true;
1234         }
1235
1236         if (ah->opmode == NL80211_IFTYPE_STATION) {
1237                 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1238
1239                 if (iter_data.primary_sta) {
1240                         iter_data.primary_beacon_vif = iter_data.primary_sta;
1241                         iter_data.beacons = true;
1242                         ath9k_set_assoc_state(sc, iter_data.primary_sta,
1243                                               changed);
1244                         ctx->primary_sta = iter_data.primary_sta;
1245                 } else {
1246                         ctx->primary_sta = NULL;
1247                         eth_zero_addr(common->curbssid);
1248                         common->curaid = 0;
1249                         ath9k_hw_write_associd(sc->sc_ah);
1250                         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1251                                 ath9k_mci_update_wlan_channels(sc, true);
1252                 }
1253         }
1254         sc->nbcnvifs = iter_data.nbcnvifs;
1255         ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1256                             iter_data.beacons);
1257         ath9k_hw_set_interrupts(ah);
1258
1259         if (ah->slottime != iter_data.slottime) {
1260                 ah->slottime = iter_data.slottime;
1261                 ath9k_hw_init_global_settings(ah);
1262         }
1263
1264         if (iter_data.primary_sta)
1265                 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1266         else
1267                 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1268
1269         ath_dbg(common, CONFIG,
1270                 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1271                 common->macaddr, common->curbssid, common->bssidmask);
1272
1273         ath9k_ps_restore(sc);
1274 }
1275
1276 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1277 {
1278         int *power = data;
1279
1280         if (*power < vif->bss_conf.txpower)
1281                 *power = vif->bss_conf.txpower;
1282 }
1283
1284 /* Called with sc->mutex held. */
1285 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1286 {
1287         int power;
1288         struct ath_hw *ah = sc->sc_ah;
1289         struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1290
1291         ath9k_ps_wakeup(sc);
1292         if (ah->tpc_enabled) {
1293                 power = (vif) ? vif->bss_conf.txpower : -1;
1294                 ieee80211_iterate_active_interfaces_atomic(
1295                                 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1296                                 ath9k_tpc_vif_iter, &power);
1297                 if (power == -1)
1298                         power = sc->hw->conf.power_level;
1299         } else {
1300                 power = sc->hw->conf.power_level;
1301         }
1302         sc->cur_chan->txpower = 2 * power;
1303         ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1304         sc->cur_chan->cur_txpower = reg->max_power_level;
1305         ath9k_ps_restore(sc);
1306 }
1307
1308 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1309                                    struct ieee80211_vif *vif)
1310 {
1311         int i;
1312
1313         if (!ath9k_is_chanctx_enabled())
1314                 return;
1315
1316         for (i = 0; i < IEEE80211_NUM_ACS; i++)
1317                 vif->hw_queue[i] = i;
1318
1319         if (vif->type == NL80211_IFTYPE_AP ||
1320             vif->type == NL80211_IFTYPE_MESH_POINT)
1321                 vif->cab_queue = hw->queues - 2;
1322         else
1323                 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1324 }
1325
1326 static int ath9k_add_interface(struct ieee80211_hw *hw,
1327                                struct ieee80211_vif *vif)
1328 {
1329         struct ath_softc *sc = hw->priv;
1330         struct ath_hw *ah = sc->sc_ah;
1331         struct ath_common *common = ath9k_hw_common(ah);
1332         struct ath_vif *avp = (void *)vif->drv_priv;
1333         struct ath_node *an = &avp->mcast_node;
1334
1335         mutex_lock(&sc->mutex);
1336         if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1337                 if (sc->cur_chan->nvifs >= 1) {
1338                         mutex_unlock(&sc->mutex);
1339                         return -EOPNOTSUPP;
1340                 }
1341                 sc->tx99_vif = vif;
1342         }
1343
1344         ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1345         sc->cur_chan->nvifs++;
1346
1347         if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1348                 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1349
1350         if (ath9k_uses_beacons(vif->type))
1351                 ath9k_beacon_assign_slot(sc, vif);
1352
1353         avp->vif = vif;
1354         if (!ath9k_is_chanctx_enabled()) {
1355                 avp->chanctx = sc->cur_chan;
1356                 list_add_tail(&avp->list, &avp->chanctx->vifs);
1357         }
1358
1359         ath9k_calculate_summary_state(sc, avp->chanctx);
1360
1361         ath9k_assign_hw_queues(hw, vif);
1362
1363         ath9k_set_txpower(sc, vif);
1364
1365         an->sc = sc;
1366         an->sta = NULL;
1367         an->vif = vif;
1368         an->no_ps_filter = true;
1369         ath_tx_node_init(sc, an);
1370
1371         mutex_unlock(&sc->mutex);
1372         return 0;
1373 }
1374
1375 static int ath9k_change_interface(struct ieee80211_hw *hw,
1376                                   struct ieee80211_vif *vif,
1377                                   enum nl80211_iftype new_type,
1378                                   bool p2p)
1379 {
1380         struct ath_softc *sc = hw->priv;
1381         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1382         struct ath_vif *avp = (void *)vif->drv_priv;
1383
1384         mutex_lock(&sc->mutex);
1385
1386         if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1387                 mutex_unlock(&sc->mutex);
1388                 return -EOPNOTSUPP;
1389         }
1390
1391         ath_dbg(common, CONFIG, "Change Interface\n");
1392
1393         if (ath9k_uses_beacons(vif->type))
1394                 ath9k_beacon_remove_slot(sc, vif);
1395
1396         vif->type = new_type;
1397         vif->p2p = p2p;
1398
1399         if (ath9k_uses_beacons(vif->type))
1400                 ath9k_beacon_assign_slot(sc, vif);
1401
1402         ath9k_assign_hw_queues(hw, vif);
1403         ath9k_calculate_summary_state(sc, avp->chanctx);
1404
1405         ath9k_set_txpower(sc, vif);
1406
1407         mutex_unlock(&sc->mutex);
1408         return 0;
1409 }
1410
1411 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1412                                    struct ieee80211_vif *vif)
1413 {
1414         struct ath_softc *sc = hw->priv;
1415         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1416         struct ath_vif *avp = (void *)vif->drv_priv;
1417
1418         ath_dbg(common, CONFIG, "Detach Interface\n");
1419
1420         mutex_lock(&sc->mutex);
1421
1422         ath9k_p2p_remove_vif(sc, vif);
1423
1424         sc->cur_chan->nvifs--;
1425         sc->tx99_vif = NULL;
1426         if (!ath9k_is_chanctx_enabled())
1427                 list_del(&avp->list);
1428
1429         if (ath9k_uses_beacons(vif->type))
1430                 ath9k_beacon_remove_slot(sc, vif);
1431
1432         ath_tx_node_cleanup(sc, &avp->mcast_node);
1433
1434         ath9k_calculate_summary_state(sc, avp->chanctx);
1435
1436         ath9k_set_txpower(sc, NULL);
1437
1438         mutex_unlock(&sc->mutex);
1439 }
1440
1441 static void ath9k_enable_ps(struct ath_softc *sc)
1442 {
1443         struct ath_hw *ah = sc->sc_ah;
1444         struct ath_common *common = ath9k_hw_common(ah);
1445
1446         if (IS_ENABLED(CONFIG_ATH9K_TX99))
1447                 return;
1448
1449         sc->ps_enabled = true;
1450         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1451                 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1452                         ah->imask |= ATH9K_INT_TIM_TIMER;
1453                         ath9k_hw_set_interrupts(ah);
1454                 }
1455                 ath9k_hw_setrxabort(ah, 1);
1456         }
1457         ath_dbg(common, PS, "PowerSave enabled\n");
1458 }
1459
1460 static void ath9k_disable_ps(struct ath_softc *sc)
1461 {
1462         struct ath_hw *ah = sc->sc_ah;
1463         struct ath_common *common = ath9k_hw_common(ah);
1464
1465         if (IS_ENABLED(CONFIG_ATH9K_TX99))
1466                 return;
1467
1468         sc->ps_enabled = false;
1469         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1470         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1471                 ath9k_hw_setrxabort(ah, 0);
1472                 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1473                                   PS_WAIT_FOR_CAB |
1474                                   PS_WAIT_FOR_PSPOLL_DATA |
1475                                   PS_WAIT_FOR_TX_ACK);
1476                 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1477                         ah->imask &= ~ATH9K_INT_TIM_TIMER;
1478                         ath9k_hw_set_interrupts(ah);
1479                 }
1480         }
1481         ath_dbg(common, PS, "PowerSave disabled\n");
1482 }
1483
1484 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1485 {
1486         struct ath_softc *sc = hw->priv;
1487         struct ath_hw *ah = sc->sc_ah;
1488         struct ath_common *common = ath9k_hw_common(ah);
1489         struct ieee80211_conf *conf = &hw->conf;
1490         struct ath_chanctx *ctx = sc->cur_chan;
1491
1492         ath9k_ps_wakeup(sc);
1493         mutex_lock(&sc->mutex);
1494
1495         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1496                 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1497                 if (sc->ps_idle) {
1498                         ath_cancel_work(sc);
1499                         ath9k_stop_btcoex(sc);
1500                 } else {
1501                         ath9k_start_btcoex(sc);
1502                         /*
1503                          * The chip needs a reset to properly wake up from
1504                          * full sleep
1505                          */
1506                         ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1507                 }
1508         }
1509
1510         /*
1511          * We just prepare to enable PS. We have to wait until our AP has
1512          * ACK'd our null data frame to disable RX otherwise we'll ignore
1513          * those ACKs and end up retransmitting the same null data frames.
1514          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1515          */
1516         if (changed & IEEE80211_CONF_CHANGE_PS) {
1517                 unsigned long flags;
1518                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1519                 if (conf->flags & IEEE80211_CONF_PS)
1520                         ath9k_enable_ps(sc);
1521                 else
1522                         ath9k_disable_ps(sc);
1523                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1524         }
1525
1526         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1527                 if (conf->flags & IEEE80211_CONF_MONITOR) {
1528                         ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1529                         sc->sc_ah->is_monitoring = true;
1530                 } else {
1531                         ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1532                         sc->sc_ah->is_monitoring = false;
1533                 }
1534         }
1535
1536         if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1537                 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1538                 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1539         }
1540
1541         if (changed & IEEE80211_CONF_CHANGE_POWER)
1542                 ath9k_set_txpower(sc, NULL);
1543
1544         mutex_unlock(&sc->mutex);
1545         ath9k_ps_restore(sc);
1546
1547         return 0;
1548 }
1549
1550 #define SUPPORTED_FILTERS                       \
1551         (FIF_ALLMULTI |                         \
1552         FIF_CONTROL |                           \
1553         FIF_PSPOLL |                            \
1554         FIF_OTHER_BSS |                         \
1555         FIF_BCN_PRBRESP_PROMISC |               \
1556         FIF_PROBE_REQ |                         \
1557         FIF_FCSFAIL)
1558
1559 /* FIXME: sc->sc_full_reset ? */
1560 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1561                                    unsigned int changed_flags,
1562                                    unsigned int *total_flags,
1563                                    u64 multicast)
1564 {
1565         struct ath_softc *sc = hw->priv;
1566         struct ath_chanctx *ctx;
1567         u32 rfilt;
1568
1569         changed_flags &= SUPPORTED_FILTERS;
1570         *total_flags &= SUPPORTED_FILTERS;
1571
1572         spin_lock_bh(&sc->chan_lock);
1573         ath_for_each_chanctx(sc, ctx)
1574                 ctx->rxfilter = *total_flags;
1575 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1576         sc->offchannel.chan.rxfilter = *total_flags;
1577 #endif
1578         spin_unlock_bh(&sc->chan_lock);
1579
1580         ath9k_ps_wakeup(sc);
1581         rfilt = ath_calcrxfilter(sc);
1582         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1583         ath9k_ps_restore(sc);
1584
1585         ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1586                 rfilt);
1587 }
1588
1589 static int ath9k_sta_add(struct ieee80211_hw *hw,
1590                          struct ieee80211_vif *vif,
1591                          struct ieee80211_sta *sta)
1592 {
1593         struct ath_softc *sc = hw->priv;
1594         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1595         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1596         struct ieee80211_key_conf ps_key = { };
1597         int key;
1598
1599         ath_node_attach(sc, sta, vif);
1600
1601         if (vif->type != NL80211_IFTYPE_AP &&
1602             vif->type != NL80211_IFTYPE_AP_VLAN)
1603                 return 0;
1604
1605         key = ath_key_config(common, vif, sta, &ps_key);
1606         if (key > 0) {
1607                 an->ps_key = key;
1608                 an->key_idx[0] = key;
1609         }
1610
1611         return 0;
1612 }
1613
1614 static void ath9k_del_ps_key(struct ath_softc *sc,
1615                              struct ieee80211_vif *vif,
1616                              struct ieee80211_sta *sta)
1617 {
1618         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1619         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1620
1621         if (!an->ps_key)
1622             return;
1623
1624         ath_key_delete(common, an->ps_key);
1625         an->ps_key = 0;
1626         an->key_idx[0] = 0;
1627 }
1628
1629 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1630                             struct ieee80211_vif *vif,
1631                             struct ieee80211_sta *sta)
1632 {
1633         struct ath_softc *sc = hw->priv;
1634
1635         ath9k_del_ps_key(sc, vif, sta);
1636         ath_node_detach(sc, sta);
1637
1638         return 0;
1639 }
1640
1641 static int ath9k_sta_state(struct ieee80211_hw *hw,
1642                            struct ieee80211_vif *vif,
1643                            struct ieee80211_sta *sta,
1644                            enum ieee80211_sta_state old_state,
1645                            enum ieee80211_sta_state new_state)
1646 {
1647         struct ath_softc *sc = hw->priv;
1648         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1649         int ret = 0;
1650
1651         if (old_state == IEEE80211_STA_NOTEXIST &&
1652             new_state == IEEE80211_STA_NONE) {
1653                 ret = ath9k_sta_add(hw, vif, sta);
1654                 ath_dbg(common, CONFIG,
1655                         "Add station: %pM\n", sta->addr);
1656         } else if (old_state == IEEE80211_STA_NONE &&
1657                    new_state == IEEE80211_STA_NOTEXIST) {
1658                 ret = ath9k_sta_remove(hw, vif, sta);
1659                 ath_dbg(common, CONFIG,
1660                         "Remove station: %pM\n", sta->addr);
1661         }
1662
1663         if (ath9k_is_chanctx_enabled()) {
1664                 if (vif->type == NL80211_IFTYPE_STATION) {
1665                         if (old_state == IEEE80211_STA_ASSOC &&
1666                             new_state == IEEE80211_STA_AUTHORIZED)
1667                                 ath_chanctx_event(sc, vif,
1668                                                   ATH_CHANCTX_EVENT_AUTHORIZED);
1669                 }
1670         }
1671
1672         return ret;
1673 }
1674
1675 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1676                                     struct ath_node *an,
1677                                     bool set)
1678 {
1679         int i;
1680
1681         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1682                 if (!an->key_idx[i])
1683                         continue;
1684                 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1685         }
1686 }
1687
1688 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1689                          struct ieee80211_vif *vif,
1690                          enum sta_notify_cmd cmd,
1691                          struct ieee80211_sta *sta)
1692 {
1693         struct ath_softc *sc = hw->priv;
1694         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1695
1696         switch (cmd) {
1697         case STA_NOTIFY_SLEEP:
1698                 an->sleeping = true;
1699                 ath_tx_aggr_sleep(sta, sc, an);
1700                 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1701                 break;
1702         case STA_NOTIFY_AWAKE:
1703                 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1704                 an->sleeping = false;
1705                 ath_tx_aggr_wakeup(sc, an);
1706                 break;
1707         }
1708 }
1709
1710 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1711                          struct ieee80211_vif *vif, u16 queue,
1712                          const struct ieee80211_tx_queue_params *params)
1713 {
1714         struct ath_softc *sc = hw->priv;
1715         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1716         struct ath_txq *txq;
1717         struct ath9k_tx_queue_info qi;
1718         int ret = 0;
1719
1720         if (queue >= IEEE80211_NUM_ACS)
1721                 return 0;
1722
1723         txq = sc->tx.txq_map[queue];
1724
1725         ath9k_ps_wakeup(sc);
1726         mutex_lock(&sc->mutex);
1727
1728         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1729
1730         qi.tqi_aifs = params->aifs;
1731         qi.tqi_cwmin = params->cw_min;
1732         qi.tqi_cwmax = params->cw_max;
1733         qi.tqi_burstTime = params->txop * 32;
1734
1735         ath_dbg(common, CONFIG,
1736                 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1737                 queue, txq->axq_qnum, params->aifs, params->cw_min,
1738                 params->cw_max, params->txop);
1739
1740         ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1741         ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1742         if (ret)
1743                 ath_err(common, "TXQ Update failed\n");
1744
1745         mutex_unlock(&sc->mutex);
1746         ath9k_ps_restore(sc);
1747
1748         return ret;
1749 }
1750
1751 static int ath9k_set_key(struct ieee80211_hw *hw,
1752                          enum set_key_cmd cmd,
1753                          struct ieee80211_vif *vif,
1754                          struct ieee80211_sta *sta,
1755                          struct ieee80211_key_conf *key)
1756 {
1757         struct ath_softc *sc = hw->priv;
1758         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1759         struct ath_node *an = NULL;
1760         int ret = 0, i;
1761
1762         if (ath9k_modparam_nohwcrypt)
1763                 return -ENOSPC;
1764
1765         if ((vif->type == NL80211_IFTYPE_ADHOC ||
1766              vif->type == NL80211_IFTYPE_MESH_POINT) &&
1767             (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1768              key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1769             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1770                 /*
1771                  * For now, disable hw crypto for the RSN IBSS group keys. This
1772                  * could be optimized in the future to use a modified key cache
1773                  * design to support per-STA RX GTK, but until that gets
1774                  * implemented, use of software crypto for group addressed
1775                  * frames is a acceptable to allow RSN IBSS to be used.
1776                  */
1777                 return -EOPNOTSUPP;
1778         }
1779
1780         mutex_lock(&sc->mutex);
1781         ath9k_ps_wakeup(sc);
1782         ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1783         if (sta)
1784                 an = (struct ath_node *)sta->drv_priv;
1785
1786         /* Delete pending key cache entries if no more frames are pointing to
1787          * them in TXQs.
1788          */
1789         for (i = 0; i < ATH_KEYMAX; i++)
1790                 ath9k_pending_key_del(sc, i);
1791
1792         switch (cmd) {
1793         case SET_KEY:
1794                 if (sta)
1795                         ath9k_del_ps_key(sc, vif, sta);
1796
1797                 key->hw_key_idx = 0;
1798                 ret = ath_key_config(common, vif, sta, key);
1799                 if (ret >= 0) {
1800                         key->hw_key_idx = ret;
1801                         /* push IV and Michael MIC generation to stack */
1802                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1803                         if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1804                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1805                         if (sc->sc_ah->sw_mgmt_crypto_tx &&
1806                             key->cipher == WLAN_CIPHER_SUITE_CCMP)
1807                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1808                         ret = 0;
1809                 }
1810                 if (an && key->hw_key_idx) {
1811                         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1812                                 if (an->key_idx[i])
1813                                         continue;
1814                                 an->key_idx[i] = key->hw_key_idx;
1815                                 break;
1816                         }
1817                         WARN_ON(i == ARRAY_SIZE(an->key_idx));
1818                 }
1819                 break;
1820         case DISABLE_KEY:
1821                 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1822                         /* Delay key cache entry deletion until there are no
1823                          * remaining TXQ frames pointing to this entry.
1824                          */
1825                         set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1826                         ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1827                 } else {
1828                         ath_key_delete(common, key->hw_key_idx);
1829                 }
1830                 if (an) {
1831                         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1832                                 if (an->key_idx[i] != key->hw_key_idx)
1833                                         continue;
1834                                 an->key_idx[i] = 0;
1835                                 break;
1836                         }
1837                 }
1838                 key->hw_key_idx = 0;
1839                 break;
1840         default:
1841                 ret = -EINVAL;
1842         }
1843
1844         ath9k_ps_restore(sc);
1845         mutex_unlock(&sc->mutex);
1846
1847         return ret;
1848 }
1849
1850 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1851                                    struct ieee80211_vif *vif,
1852                                    struct ieee80211_bss_conf *bss_conf,
1853                                    u32 changed)
1854 {
1855 #define CHECK_ANI                               \
1856         (BSS_CHANGED_ASSOC |                    \
1857          BSS_CHANGED_IBSS |                     \
1858          BSS_CHANGED_BEACON_ENABLED)
1859
1860         struct ath_softc *sc = hw->priv;
1861         struct ath_hw *ah = sc->sc_ah;
1862         struct ath_common *common = ath9k_hw_common(ah);
1863         struct ath_vif *avp = (void *)vif->drv_priv;
1864         int slottime;
1865
1866         ath9k_ps_wakeup(sc);
1867         mutex_lock(&sc->mutex);
1868
1869         if (changed & BSS_CHANGED_ASSOC) {
1870                 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1871                         bss_conf->bssid, bss_conf->assoc);
1872
1873                 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1874                 avp->aid = bss_conf->aid;
1875                 avp->assoc = bss_conf->assoc;
1876
1877                 ath9k_calculate_summary_state(sc, avp->chanctx);
1878         }
1879
1880         if ((changed & BSS_CHANGED_IBSS) ||
1881               (changed & BSS_CHANGED_OCB)) {
1882                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1883                 common->curaid = bss_conf->aid;
1884                 ath9k_hw_write_associd(sc->sc_ah);
1885         }
1886
1887         if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1888             (changed & BSS_CHANGED_BEACON_INT) ||
1889             (changed & BSS_CHANGED_BEACON_INFO)) {
1890                 ath9k_calculate_summary_state(sc, avp->chanctx);
1891         }
1892
1893         if ((avp->chanctx == sc->cur_chan) &&
1894             (changed & BSS_CHANGED_ERP_SLOT)) {
1895                 if (bss_conf->use_short_slot)
1896                         slottime = 9;
1897                 else
1898                         slottime = 20;
1899
1900                 if (vif->type == NL80211_IFTYPE_AP) {
1901                         /*
1902                          * Defer update, so that connected stations can adjust
1903                          * their settings at the same time.
1904                          * See beacon.c for more details
1905                          */
1906                         sc->beacon.slottime = slottime;
1907                         sc->beacon.updateslot = UPDATE;
1908                 } else {
1909                         ah->slottime = slottime;
1910                         ath9k_hw_init_global_settings(ah);
1911                 }
1912         }
1913
1914         if (changed & BSS_CHANGED_P2P_PS)
1915                 ath9k_p2p_bss_info_changed(sc, vif);
1916
1917         if (changed & CHECK_ANI)
1918                 ath_check_ani(sc);
1919
1920         if (changed & BSS_CHANGED_TXPOWER) {
1921                 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1922                         vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1923                 ath9k_set_txpower(sc, vif);
1924         }
1925
1926         mutex_unlock(&sc->mutex);
1927         ath9k_ps_restore(sc);
1928
1929 #undef CHECK_ANI
1930 }
1931
1932 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1933 {
1934         struct ath_softc *sc = hw->priv;
1935         struct ath_vif *avp = (void *)vif->drv_priv;
1936         u64 tsf;
1937
1938         mutex_lock(&sc->mutex);
1939         ath9k_ps_wakeup(sc);
1940         /* Get current TSF either from HW or kernel time. */
1941         if (sc->cur_chan == avp->chanctx) {
1942                 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1943         } else {
1944                 tsf = sc->cur_chan->tsf_val +
1945                       ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1946         }
1947         tsf += le64_to_cpu(avp->tsf_adjust);
1948         ath9k_ps_restore(sc);
1949         mutex_unlock(&sc->mutex);
1950
1951         return tsf;
1952 }
1953
1954 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1955                           struct ieee80211_vif *vif,
1956                           u64 tsf)
1957 {
1958         struct ath_softc *sc = hw->priv;
1959         struct ath_vif *avp = (void *)vif->drv_priv;
1960
1961         mutex_lock(&sc->mutex);
1962         ath9k_ps_wakeup(sc);
1963         tsf -= le64_to_cpu(avp->tsf_adjust);
1964         ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1965         if (sc->cur_chan == avp->chanctx)
1966                 ath9k_hw_settsf64(sc->sc_ah, tsf);
1967         avp->chanctx->tsf_val = tsf;
1968         ath9k_ps_restore(sc);
1969         mutex_unlock(&sc->mutex);
1970 }
1971
1972 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1973 {
1974         struct ath_softc *sc = hw->priv;
1975         struct ath_vif *avp = (void *)vif->drv_priv;
1976
1977         mutex_lock(&sc->mutex);
1978
1979         ath9k_ps_wakeup(sc);
1980         ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1981         if (sc->cur_chan == avp->chanctx)
1982                 ath9k_hw_reset_tsf(sc->sc_ah);
1983         avp->chanctx->tsf_val = 0;
1984         ath9k_ps_restore(sc);
1985
1986         mutex_unlock(&sc->mutex);
1987 }
1988
1989 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1990                               struct ieee80211_vif *vif,
1991                               struct ieee80211_ampdu_params *params)
1992 {
1993         struct ath_softc *sc = hw->priv;
1994         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1995         bool flush = false;
1996         int ret = 0;
1997         struct ieee80211_sta *sta = params->sta;
1998         struct ath_node *an = (struct ath_node *)sta->drv_priv;
1999         enum ieee80211_ampdu_mlme_action action = params->action;
2000         u16 tid = params->tid;
2001         u16 *ssn = &params->ssn;
2002         struct ath_atx_tid *atid;
2003
2004         mutex_lock(&sc->mutex);
2005
2006         switch (action) {
2007         case IEEE80211_AMPDU_RX_START:
2008                 break;
2009         case IEEE80211_AMPDU_RX_STOP:
2010                 break;
2011         case IEEE80211_AMPDU_TX_START:
2012                 if (ath9k_is_chanctx_enabled()) {
2013                         if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2014                                 ret = -EBUSY;
2015                                 break;
2016                         }
2017                 }
2018                 ath9k_ps_wakeup(sc);
2019                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2020                 if (!ret)
2021                         ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2022                 ath9k_ps_restore(sc);
2023                 break;
2024         case IEEE80211_AMPDU_TX_STOP_FLUSH:
2025         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2026                 flush = true;
2027                 /* fall through */
2028         case IEEE80211_AMPDU_TX_STOP_CONT:
2029                 ath9k_ps_wakeup(sc);
2030                 ath_tx_aggr_stop(sc, sta, tid);
2031                 if (!flush)
2032                         ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2033                 ath9k_ps_restore(sc);
2034                 break;
2035         case IEEE80211_AMPDU_TX_OPERATIONAL:
2036                 atid = ath_node_to_tid(an, tid);
2037                 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2038                                 sta->ht_cap.ampdu_factor;
2039                 break;
2040         default:
2041                 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2042         }
2043
2044         mutex_unlock(&sc->mutex);
2045
2046         return ret;
2047 }
2048
2049 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2050                              struct survey_info *survey)
2051 {
2052         struct ath_softc *sc = hw->priv;
2053         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2054         struct ieee80211_supported_band *sband;
2055         struct ieee80211_channel *chan;
2056         unsigned long flags;
2057         int pos;
2058
2059         if (IS_ENABLED(CONFIG_ATH9K_TX99))
2060                 return -EOPNOTSUPP;
2061
2062         spin_lock_irqsave(&common->cc_lock, flags);
2063         if (idx == 0)
2064                 ath_update_survey_stats(sc);
2065
2066         sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2067         if (sband && idx >= sband->n_channels) {
2068                 idx -= sband->n_channels;
2069                 sband = NULL;
2070         }
2071
2072         if (!sband)
2073                 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2074
2075         if (!sband || idx >= sband->n_channels) {
2076                 spin_unlock_irqrestore(&common->cc_lock, flags);
2077                 return -ENOENT;
2078         }
2079
2080         chan = &sband->channels[idx];
2081         pos = chan->hw_value;
2082         memcpy(survey, &sc->survey[pos], sizeof(*survey));
2083         survey->channel = chan;
2084         spin_unlock_irqrestore(&common->cc_lock, flags);
2085
2086         return 0;
2087 }
2088
2089 static void ath9k_enable_dynack(struct ath_softc *sc)
2090 {
2091 #ifdef CONFIG_ATH9K_DYNACK
2092         u32 rfilt;
2093         struct ath_hw *ah = sc->sc_ah;
2094
2095         ath_dynack_reset(ah);
2096
2097         ah->dynack.enabled = true;
2098         rfilt = ath_calcrxfilter(sc);
2099         ath9k_hw_setrxfilter(ah, rfilt);
2100 #endif
2101 }
2102
2103 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2104                                      s16 coverage_class)
2105 {
2106         struct ath_softc *sc = hw->priv;
2107         struct ath_hw *ah = sc->sc_ah;
2108
2109         if (IS_ENABLED(CONFIG_ATH9K_TX99))
2110                 return;
2111
2112         mutex_lock(&sc->mutex);
2113
2114         if (coverage_class >= 0) {
2115                 ah->coverage_class = coverage_class;
2116                 if (ah->dynack.enabled) {
2117                         u32 rfilt;
2118
2119                         ah->dynack.enabled = false;
2120                         rfilt = ath_calcrxfilter(sc);
2121                         ath9k_hw_setrxfilter(ah, rfilt);
2122                 }
2123                 ath9k_ps_wakeup(sc);
2124                 ath9k_hw_init_global_settings(ah);
2125                 ath9k_ps_restore(sc);
2126         } else if (!ah->dynack.enabled) {
2127                 ath9k_enable_dynack(sc);
2128         }
2129
2130         mutex_unlock(&sc->mutex);
2131 }
2132
2133 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2134                                  bool sw_pending)
2135 {
2136         int i, npend = 0;
2137
2138         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2139                 if (!ATH_TXQ_SETUP(sc, i))
2140                         continue;
2141
2142                 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2143                                                  sw_pending);
2144                 if (npend)
2145                         break;
2146         }
2147
2148         return !!npend;
2149 }
2150
2151 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2152                         u32 queues, bool drop)
2153 {
2154         struct ath_softc *sc = hw->priv;
2155         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2156
2157         if (ath9k_is_chanctx_enabled()) {
2158                 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2159                         goto flush;
2160
2161                 /*
2162                  * If MCC is active, extend the flush timeout
2163                  * and wait for the HW/SW queues to become
2164                  * empty. This needs to be done outside the
2165                  * sc->mutex lock to allow the channel scheduler
2166                  * to switch channel contexts.
2167                  *
2168                  * The vif queues have been stopped in mac80211,
2169                  * so there won't be any incoming frames.
2170                  */
2171                 __ath9k_flush(hw, queues, drop, true, true);
2172                 return;
2173         }
2174 flush:
2175         mutex_lock(&sc->mutex);
2176         __ath9k_flush(hw, queues, drop, true, false);
2177         mutex_unlock(&sc->mutex);
2178 }
2179
2180 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2181                    bool sw_pending, bool timeout_override)
2182 {
2183         struct ath_softc *sc = hw->priv;
2184         struct ath_hw *ah = sc->sc_ah;
2185         struct ath_common *common = ath9k_hw_common(ah);
2186         int timeout;
2187         bool drain_txq;
2188
2189         cancel_delayed_work_sync(&sc->hw_check_work);
2190
2191         if (ah->ah_flags & AH_UNPLUGGED) {
2192                 ath_dbg(common, ANY, "Device has been unplugged!\n");
2193                 return;
2194         }
2195
2196         if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2197                 ath_dbg(common, ANY, "Device not present\n");
2198                 return;
2199         }
2200
2201         spin_lock_bh(&sc->chan_lock);
2202         if (timeout_override)
2203                 timeout = HZ / 5;
2204         else
2205                 timeout = sc->cur_chan->flush_timeout;
2206         spin_unlock_bh(&sc->chan_lock);
2207
2208         ath_dbg(common, CHAN_CTX,
2209                 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2210
2211         if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2212                                timeout) > 0)
2213                 drop = false;
2214
2215         if (drop) {
2216                 ath9k_ps_wakeup(sc);
2217                 spin_lock_bh(&sc->sc_pcu_lock);
2218                 drain_txq = ath_drain_all_txq(sc);
2219                 spin_unlock_bh(&sc->sc_pcu_lock);
2220
2221                 if (!drain_txq)
2222                         ath_reset(sc, NULL);
2223
2224                 ath9k_ps_restore(sc);
2225         }
2226
2227         ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2228                                      ATH_HW_CHECK_POLL_INT);
2229 }
2230
2231 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2232 {
2233         struct ath_softc *sc = hw->priv;
2234
2235         return ath9k_has_tx_pending(sc, true);
2236 }
2237
2238 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2239 {
2240         struct ath_softc *sc = hw->priv;
2241         struct ath_hw *ah = sc->sc_ah;
2242         struct ieee80211_vif *vif;
2243         struct ath_vif *avp;
2244         struct ath_buf *bf;
2245         struct ath_tx_status ts;
2246         bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2247         int status;
2248
2249         vif = sc->beacon.bslot[0];
2250         if (!vif)
2251                 return 0;
2252
2253         if (!vif->bss_conf.enable_beacon)
2254                 return 0;
2255
2256         avp = (void *)vif->drv_priv;
2257
2258         if (!sc->beacon.tx_processed && !edma) {
2259                 tasklet_disable(&sc->bcon_tasklet);
2260
2261                 bf = avp->av_bcbuf;
2262                 if (!bf || !bf->bf_mpdu)
2263                         goto skip;
2264
2265                 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2266                 if (status == -EINPROGRESS)
2267                         goto skip;
2268
2269                 sc->beacon.tx_processed = true;
2270                 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2271
2272 skip:
2273                 tasklet_enable(&sc->bcon_tasklet);
2274         }
2275
2276         return sc->beacon.tx_last;
2277 }
2278
2279 static int ath9k_get_stats(struct ieee80211_hw *hw,
2280                            struct ieee80211_low_level_stats *stats)
2281 {
2282         struct ath_softc *sc = hw->priv;
2283         struct ath_hw *ah = sc->sc_ah;
2284         struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2285
2286         stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2287         stats->dot11RTSFailureCount = mib_stats->rts_bad;
2288         stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2289         stats->dot11RTSSuccessCount = mib_stats->rts_good;
2290         return 0;
2291 }
2292
2293 static u32 fill_chainmask(u32 cap, u32 new)
2294 {
2295         u32 filled = 0;
2296         int i;
2297
2298         for (i = 0; cap && new; i++, cap >>= 1) {
2299                 if (!(cap & BIT(0)))
2300                         continue;
2301
2302                 if (new & BIT(0))
2303                         filled |= BIT(i);
2304
2305                 new >>= 1;
2306         }
2307
2308         return filled;
2309 }
2310
2311 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2312 {
2313         if (AR_SREV_9300_20_OR_LATER(ah))
2314                 return true;
2315
2316         switch (val & 0x7) {
2317         case 0x1:
2318         case 0x3:
2319         case 0x7:
2320                 return true;
2321         case 0x2:
2322                 return (ah->caps.rx_chainmask == 1);
2323         default:
2324                 return false;
2325         }
2326 }
2327
2328 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2329 {
2330         struct ath_softc *sc = hw->priv;
2331         struct ath_hw *ah = sc->sc_ah;
2332
2333         if (ah->caps.rx_chainmask != 1)
2334                 rx_ant |= tx_ant;
2335
2336         if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2337                 return -EINVAL;
2338
2339         sc->ant_rx = rx_ant;
2340         sc->ant_tx = tx_ant;
2341
2342         if (ah->caps.rx_chainmask == 1)
2343                 return 0;
2344
2345         /* AR9100 runs into calibration issues if not all rx chains are enabled */
2346         if (AR_SREV_9100(ah))
2347                 ah->rxchainmask = 0x7;
2348         else
2349                 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2350
2351         ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2352         ath9k_cmn_reload_chainmask(ah);
2353
2354         return 0;
2355 }
2356
2357 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2358 {
2359         struct ath_softc *sc = hw->priv;
2360
2361         *tx_ant = sc->ant_tx;
2362         *rx_ant = sc->ant_rx;
2363         return 0;
2364 }
2365
2366 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2367                                 struct ieee80211_vif *vif,
2368                                 const u8 *mac_addr)
2369 {
2370         struct ath_softc *sc = hw->priv;
2371         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2372         set_bit(ATH_OP_SCANNING, &common->op_flags);
2373 }
2374
2375 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2376                                    struct ieee80211_vif *vif)
2377 {
2378         struct ath_softc *sc = hw->priv;
2379         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2380         clear_bit(ATH_OP_SCANNING, &common->op_flags);
2381 }
2382
2383 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2384
2385 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2386 {
2387         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2388
2389         if (sc->offchannel.roc_vif) {
2390                 ath_dbg(common, CHAN_CTX,
2391                         "%s: Aborting RoC\n", __func__);
2392
2393                 del_timer_sync(&sc->offchannel.timer);
2394                 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2395                         ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2396         }
2397
2398         if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2399                 ath_dbg(common, CHAN_CTX,
2400                         "%s: Aborting HW scan\n", __func__);
2401
2402                 del_timer_sync(&sc->offchannel.timer);
2403                 ath_scan_complete(sc, true);
2404         }
2405 }
2406
2407 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2408                          struct ieee80211_scan_request *hw_req)
2409 {
2410         struct cfg80211_scan_request *req = &hw_req->req;
2411         struct ath_softc *sc = hw->priv;
2412         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2413         int ret = 0;
2414
2415         mutex_lock(&sc->mutex);
2416
2417         if (WARN_ON(sc->offchannel.scan_req)) {
2418                 ret = -EBUSY;
2419                 goto out;
2420         }
2421
2422         ath9k_ps_wakeup(sc);
2423         set_bit(ATH_OP_SCANNING, &common->op_flags);
2424         sc->offchannel.scan_vif = vif;
2425         sc->offchannel.scan_req = req;
2426         sc->offchannel.scan_idx = 0;
2427
2428         ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2429                 vif->addr);
2430
2431         if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2432                 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2433                 ath_offchannel_next(sc);
2434         }
2435
2436 out:
2437         mutex_unlock(&sc->mutex);
2438
2439         return ret;
2440 }
2441
2442 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2443                                  struct ieee80211_vif *vif)
2444 {
2445         struct ath_softc *sc = hw->priv;
2446         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2447
2448         ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2449
2450         mutex_lock(&sc->mutex);
2451         del_timer_sync(&sc->offchannel.timer);
2452         ath_scan_complete(sc, true);
2453         mutex_unlock(&sc->mutex);
2454 }
2455
2456 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2457                                    struct ieee80211_vif *vif,
2458                                    struct ieee80211_channel *chan, int duration,
2459                                    enum ieee80211_roc_type type)
2460 {
2461         struct ath_softc *sc = hw->priv;
2462         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2463         int ret = 0;
2464
2465         mutex_lock(&sc->mutex);
2466
2467         if (WARN_ON(sc->offchannel.roc_vif)) {
2468                 ret = -EBUSY;
2469                 goto out;
2470         }
2471
2472         ath9k_ps_wakeup(sc);
2473         sc->offchannel.roc_vif = vif;
2474         sc->offchannel.roc_chan = chan;
2475         sc->offchannel.roc_duration = duration;
2476
2477         ath_dbg(common, CHAN_CTX,
2478                 "RoC request on vif: %pM, type: %d duration: %d\n",
2479                 vif->addr, type, duration);
2480
2481         if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2482                 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2483                 ath_offchannel_next(sc);
2484         }
2485
2486 out:
2487         mutex_unlock(&sc->mutex);
2488
2489         return ret;
2490 }
2491
2492 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2493 {
2494         struct ath_softc *sc = hw->priv;
2495         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2496
2497         mutex_lock(&sc->mutex);
2498
2499         ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2500         del_timer_sync(&sc->offchannel.timer);
2501
2502         if (sc->offchannel.roc_vif) {
2503                 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2504                         ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2505         }
2506
2507         mutex_unlock(&sc->mutex);
2508
2509         return 0;
2510 }
2511
2512 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2513                              struct ieee80211_chanctx_conf *conf)
2514 {
2515         struct ath_softc *sc = hw->priv;
2516         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2517         struct ath_chanctx *ctx, **ptr;
2518         int pos;
2519
2520         mutex_lock(&sc->mutex);
2521
2522         ath_for_each_chanctx(sc, ctx) {
2523                 if (ctx->assigned)
2524                         continue;
2525
2526                 ptr = (void *) conf->drv_priv;
2527                 *ptr = ctx;
2528                 ctx->assigned = true;
2529                 pos = ctx - &sc->chanctx[0];
2530                 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2531
2532                 ath_dbg(common, CHAN_CTX,
2533                         "Add channel context: %d MHz\n",
2534                         conf->def.chan->center_freq);
2535
2536                 ath_chanctx_set_channel(sc, ctx, &conf->def);
2537
2538                 mutex_unlock(&sc->mutex);
2539                 return 0;
2540         }
2541
2542         mutex_unlock(&sc->mutex);
2543         return -ENOSPC;
2544 }
2545
2546
2547 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2548                                  struct ieee80211_chanctx_conf *conf)
2549 {
2550         struct ath_softc *sc = hw->priv;
2551         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2552         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2553
2554         mutex_lock(&sc->mutex);
2555
2556         ath_dbg(common, CHAN_CTX,
2557                 "Remove channel context: %d MHz\n",
2558                 conf->def.chan->center_freq);
2559
2560         ctx->assigned = false;
2561         ctx->hw_queue_base = 0;
2562         ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2563
2564         mutex_unlock(&sc->mutex);
2565 }
2566
2567 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2568                                  struct ieee80211_chanctx_conf *conf,
2569                                  u32 changed)
2570 {
2571         struct ath_softc *sc = hw->priv;
2572         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2573         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2574
2575         mutex_lock(&sc->mutex);
2576         ath_dbg(common, CHAN_CTX,
2577                 "Change channel context: %d MHz\n",
2578                 conf->def.chan->center_freq);
2579         ath_chanctx_set_channel(sc, ctx, &conf->def);
2580         mutex_unlock(&sc->mutex);
2581 }
2582
2583 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2584                                     struct ieee80211_vif *vif,
2585                                     struct ieee80211_chanctx_conf *conf)
2586 {
2587         struct ath_softc *sc = hw->priv;
2588         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2589         struct ath_vif *avp = (void *)vif->drv_priv;
2590         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2591         int i;
2592
2593         ath9k_cancel_pending_offchannel(sc);
2594
2595         mutex_lock(&sc->mutex);
2596
2597         ath_dbg(common, CHAN_CTX,
2598                 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2599                 vif->addr, vif->type, vif->p2p,
2600                 conf->def.chan->center_freq);
2601
2602         avp->chanctx = ctx;
2603         ctx->nvifs_assigned++;
2604         list_add_tail(&avp->list, &ctx->vifs);
2605         ath9k_calculate_summary_state(sc, ctx);
2606         for (i = 0; i < IEEE80211_NUM_ACS; i++)
2607                 vif->hw_queue[i] = ctx->hw_queue_base + i;
2608
2609         mutex_unlock(&sc->mutex);
2610
2611         return 0;
2612 }
2613
2614 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2615                                        struct ieee80211_vif *vif,
2616                                        struct ieee80211_chanctx_conf *conf)
2617 {
2618         struct ath_softc *sc = hw->priv;
2619         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2620         struct ath_vif *avp = (void *)vif->drv_priv;
2621         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2622         int ac;
2623
2624         ath9k_cancel_pending_offchannel(sc);
2625
2626         mutex_lock(&sc->mutex);
2627
2628         ath_dbg(common, CHAN_CTX,
2629                 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2630                 vif->addr, vif->type, vif->p2p,
2631                 conf->def.chan->center_freq);
2632
2633         avp->chanctx = NULL;
2634         ctx->nvifs_assigned--;
2635         list_del(&avp->list);
2636         ath9k_calculate_summary_state(sc, ctx);
2637         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2638                 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2639
2640         mutex_unlock(&sc->mutex);
2641 }
2642
2643 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2644                                  struct ieee80211_vif *vif,
2645                                  u16 duration)
2646 {
2647         struct ath_softc *sc = hw->priv;
2648         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2649         struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2650         struct ath_beacon_config *cur_conf;
2651         struct ath_chanctx *go_ctx;
2652         unsigned long timeout;
2653         bool changed = false;
2654         u32 beacon_int;
2655
2656         if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2657                 return;
2658
2659         if (!avp->chanctx)
2660                 return;
2661
2662         mutex_lock(&sc->mutex);
2663
2664         spin_lock_bh(&sc->chan_lock);
2665         if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2666                 changed = true;
2667         spin_unlock_bh(&sc->chan_lock);
2668
2669         if (!changed)
2670                 goto out;
2671
2672         ath9k_cancel_pending_offchannel(sc);
2673
2674         go_ctx = ath_is_go_chanctx_present(sc);
2675
2676         if (go_ctx) {
2677                 /*
2678                  * Wait till the GO interface gets a chance
2679                  * to send out an NoA.
2680                  */
2681                 spin_lock_bh(&sc->chan_lock);
2682                 sc->sched.mgd_prepare_tx = true;
2683                 cur_conf = &go_ctx->beacon;
2684                 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2685                 spin_unlock_bh(&sc->chan_lock);
2686
2687                 timeout = usecs_to_jiffies(beacon_int * 2);
2688                 init_completion(&sc->go_beacon);
2689
2690                 mutex_unlock(&sc->mutex);
2691
2692                 if (wait_for_completion_timeout(&sc->go_beacon,
2693                                                 timeout) == 0) {
2694                         ath_dbg(common, CHAN_CTX,
2695                                 "Failed to send new NoA\n");
2696
2697                         spin_lock_bh(&sc->chan_lock);
2698                         sc->sched.mgd_prepare_tx = false;
2699                         spin_unlock_bh(&sc->chan_lock);
2700                 }
2701
2702                 mutex_lock(&sc->mutex);
2703         }
2704
2705         ath_dbg(common, CHAN_CTX,
2706                 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2707                 __func__, vif->addr);
2708
2709         spin_lock_bh(&sc->chan_lock);
2710         sc->next_chan = avp->chanctx;
2711         sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2712         spin_unlock_bh(&sc->chan_lock);
2713
2714         ath_chanctx_set_next(sc, true);
2715 out:
2716         mutex_unlock(&sc->mutex);
2717 }
2718
2719 void ath9k_fill_chanctx_ops(void)
2720 {
2721         if (!ath9k_is_chanctx_enabled())
2722                 return;
2723
2724         ath9k_ops.hw_scan                  = ath9k_hw_scan;
2725         ath9k_ops.cancel_hw_scan           = ath9k_cancel_hw_scan;
2726         ath9k_ops.remain_on_channel        = ath9k_remain_on_channel;
2727         ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2728         ath9k_ops.add_chanctx              = ath9k_add_chanctx;
2729         ath9k_ops.remove_chanctx           = ath9k_remove_chanctx;
2730         ath9k_ops.change_chanctx           = ath9k_change_chanctx;
2731         ath9k_ops.assign_vif_chanctx       = ath9k_assign_vif_chanctx;
2732         ath9k_ops.unassign_vif_chanctx     = ath9k_unassign_vif_chanctx;
2733         ath9k_ops.mgd_prepare_tx           = ath9k_mgd_prepare_tx;
2734 }
2735
2736 #endif
2737
2738 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2739                              int *dbm)
2740 {
2741         struct ath_softc *sc = hw->priv;
2742         struct ath_vif *avp = (void *)vif->drv_priv;
2743
2744         mutex_lock(&sc->mutex);
2745         if (avp->chanctx)
2746                 *dbm = avp->chanctx->cur_txpower;
2747         else
2748                 *dbm = sc->cur_chan->cur_txpower;
2749         mutex_unlock(&sc->mutex);
2750
2751         *dbm /= 2;
2752
2753         return 0;
2754 }
2755
2756 struct ieee80211_ops ath9k_ops = {
2757         .tx                 = ath9k_tx,
2758         .start              = ath9k_start,
2759         .stop               = ath9k_stop,
2760         .add_interface      = ath9k_add_interface,
2761         .change_interface   = ath9k_change_interface,
2762         .remove_interface   = ath9k_remove_interface,
2763         .config             = ath9k_config,
2764         .configure_filter   = ath9k_configure_filter,
2765         .sta_state          = ath9k_sta_state,
2766         .sta_notify         = ath9k_sta_notify,
2767         .conf_tx            = ath9k_conf_tx,
2768         .bss_info_changed   = ath9k_bss_info_changed,
2769         .set_key            = ath9k_set_key,
2770         .get_tsf            = ath9k_get_tsf,
2771         .set_tsf            = ath9k_set_tsf,
2772         .reset_tsf          = ath9k_reset_tsf,
2773         .ampdu_action       = ath9k_ampdu_action,
2774         .get_survey         = ath9k_get_survey,
2775         .rfkill_poll        = ath9k_rfkill_poll_state,
2776         .set_coverage_class = ath9k_set_coverage_class,
2777         .flush              = ath9k_flush,
2778         .tx_frames_pending  = ath9k_tx_frames_pending,
2779         .tx_last_beacon     = ath9k_tx_last_beacon,
2780         .release_buffered_frames = ath9k_release_buffered_frames,
2781         .get_stats          = ath9k_get_stats,
2782         .set_antenna        = ath9k_set_antenna,
2783         .get_antenna        = ath9k_get_antenna,
2784
2785 #ifdef CONFIG_ATH9K_WOW
2786         .suspend            = ath9k_suspend,
2787         .resume             = ath9k_resume,
2788         .set_wakeup         = ath9k_set_wakeup,
2789 #endif
2790
2791 #ifdef CONFIG_ATH9K_DEBUGFS
2792         .get_et_sset_count  = ath9k_get_et_sset_count,
2793         .get_et_stats       = ath9k_get_et_stats,
2794         .get_et_strings     = ath9k_get_et_strings,
2795 #endif
2796
2797 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2798         .sta_add_debugfs    = ath9k_sta_add_debugfs,
2799 #endif
2800         .sw_scan_start      = ath9k_sw_scan_start,
2801         .sw_scan_complete   = ath9k_sw_scan_complete,
2802         .get_txpower        = ath9k_get_txpower,
2803         .wake_tx_queue      = ath9k_wake_tx_queue,
2804 };