drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/delay.h>
  19 #include "ath9k.h"
  20 #include "btcoex.h"
  21
  22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23 {
  24         /*
  25          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26          *   0 for no restriction
  27          *   1 for 1/4 us
  28          *   2 for 1/2 us
  29          *   3 for 1 us
  30          *   4 for 2 us
  31          *   5 for 4 us
  32          *   6 for 8 us
  33          *   7 for 16 us
  34          */
  35         switch (mpdudensity) {
  36         case 0:
  37                 return 0;
  38         case 1:
  39         case 2:
  40         case 3:
  41                 /* Our lower layer calculations limit our precision to
  42                    1 microsecond */
  43                 return 1;
  44         case 4:
  45                 return 2;
  46         case 5:
  47                 return 4;
  48         case 6:
  49                 return 8;
  50         case 7:
  51                 return 16;
  52         default:
  53                 return 0;
  54         }
  55 }
  56
  57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
  58                                      bool sw_pending)
  59 {
  60         bool pending = false;
  61
  62         spin_lock_bh(&txq->axq_lock);
  63
  64         if (txq->axq_depth) {
  65                 pending = true;
  66                 goto out;
  67         }
  68
  69         if (!sw_pending)
  70                 goto out;
  71
  72         if (txq->mac80211_qnum >= 0) {
  73                 struct ath_acq *acq;
  74
  75                 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
  76                 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
  77                         pending = true;
  78         }
  79 out:
  80         spin_unlock_bh(&txq->axq_lock);
  81         return pending;
  82 }
  83
  84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  85 {
  86         unsigned long flags;
  87         bool ret;
  88
  89         spin_lock_irqsave(&sc->sc_pm_lock, flags);
  90         ret = ath9k_hw_setpower(sc->sc_ah, mode);
  91         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  92
  93         return ret;
  94 }
  95
  96 void ath_ps_full_sleep(unsigned long data)
  97 {
  98         struct ath_softc *sc = (struct ath_softc *) data;
  99         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 100         bool reset;
 101
 102         spin_lock(&common->cc_lock);
 103         ath_hw_cycle_counters_update(common);
 104         spin_unlock(&common->cc_lock);
 105
 106         ath9k_hw_setrxabort(sc->sc_ah, 1);
 107         ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
 108
 109         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 110 }
 111
 112 void ath9k_ps_wakeup(struct ath_softc *sc)
 113 {
 114         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 115         unsigned long flags;
 116         enum ath9k_power_mode power_mode;
 117
 118         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 119         if (++sc->ps_usecount != 1)
 120                 goto unlock;
 121
 122         del_timer_sync(&sc->sleep_timer);
 123         power_mode = sc->sc_ah->power_mode;
 124         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 125
 126         /*
 127          * While the hardware is asleep, the cycle counters contain no
 128          * useful data. Better clear them now so that they don't mess up
 129          * survey data results.
 130          */
 131         if (power_mode != ATH9K_PM_AWAKE) {
 132                 spin_lock(&common->cc_lock);
 133                 ath_hw_cycle_counters_update(common);
 134                 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
 135                 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
 136                 spin_unlock(&common->cc_lock);
 137         }
 138
 139  unlock:
 140         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 141 }
 142
 143 void ath9k_ps_restore(struct ath_softc *sc)
 144 {
 145         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 146         enum ath9k_power_mode mode;
 147         unsigned long flags;
 148
 149         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 150         if (--sc->ps_usecount != 0)
 151                 goto unlock;
 152
 153         if (sc->ps_idle) {
 154                 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
 155                 goto unlock;
 156         }
 157
 158         if (sc->ps_enabled &&
 159                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
 160                                      PS_WAIT_FOR_CAB |
 161                                      PS_WAIT_FOR_PSPOLL_DATA |
 162                                      PS_WAIT_FOR_TX_ACK |
 163                                      PS_WAIT_FOR_ANI))) {
 164                 mode = ATH9K_PM_NETWORK_SLEEP;
 165                 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
 166                         ath9k_btcoex_stop_gen_timer(sc);
 167         } else {
 168                 goto unlock;
 169         }
 170
 171         spin_lock(&common->cc_lock);
 172         ath_hw_cycle_counters_update(common);
 173         spin_unlock(&common->cc_lock);
 174
 175         ath9k_hw_setpower(sc->sc_ah, mode);
 176
 177  unlock:
 178         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 179 }
 180
 181 static void __ath_cancel_work(struct ath_softc *sc)
 182 {
 183         cancel_work_sync(&sc->paprd_work);
 184         cancel_delayed_work_sync(&sc->hw_check_work);
 185         cancel_delayed_work_sync(&sc->hw_pll_work);
 186
 187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 188         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
 189                 cancel_work_sync(&sc->mci_work);
 190 #endif
 191 }
 192
 193 void ath_cancel_work(struct ath_softc *sc)
 194 {
 195         __ath_cancel_work(sc);
 196         cancel_work_sync(&sc->hw_reset_work);
 197 }
 198
 199 void ath_restart_work(struct ath_softc *sc)
 200 {
 201         ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
 202                                      ATH_HW_CHECK_POLL_INT);
 203
 204         if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
 205                 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
 206                                      msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
 207
 208         ath_start_ani(sc);
 209 }
 210
 211 static bool ath_prepare_reset(struct ath_softc *sc)
 212 {
 213         struct ath_hw *ah = sc->sc_ah;
 214         bool ret = true;
 215
 216         ieee80211_stop_queues(sc->hw);
 217         ath_stop_ani(sc);
 218         ath9k_hw_disable_interrupts(ah);
 219
 220         if (AR_SREV_9300_20_OR_LATER(ah)) {
 221                 ret &= ath_stoprecv(sc);
 222                 ret &= ath_drain_all_txq(sc);
 223         } else {
 224                 ret &= ath_drain_all_txq(sc);
 225                 ret &= ath_stoprecv(sc);
 226         }
 227
 228         return ret;
 229 }
 230
 231 static bool ath_complete_reset(struct ath_softc *sc, bool start)
 232 {
 233         struct ath_hw *ah = sc->sc_ah;
 234         struct ath_common *common = ath9k_hw_common(ah);
 235         unsigned long flags;
 236
 237         ath9k_calculate_summary_state(sc, sc->cur_chan);
 238         ath_startrecv(sc);
 239         ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
 240                                sc->cur_chan->txpower,
 241                                &sc->cur_chan->cur_txpower);
 242         clear_bit(ATH_OP_HW_RESET, &common->op_flags);
 243
 244         if (!sc->cur_chan->offchannel && start) {
 245                 /* restore per chanctx TSF timer */
 246                 if (sc->cur_chan->tsf_val) {
 247                         u32 offset;
 248
 249                         offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
 250                                                          NULL);
 251                         ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
 252                 }
 253
 254
 255                 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
 256                         goto work;
 257
 258                 if (ah->opmode == NL80211_IFTYPE_STATION &&
 259                     test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
 260                         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 261                         sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
 262                         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 263                 } else {
 264                         ath9k_set_beacon(sc);
 265                 }
 266         work:
 267                 ath_restart_work(sc);
 268                 ath_txq_schedule_all(sc);
 269         }
 270
 271         sc->gtt_cnt = 0;
 272
 273         ath9k_hw_set_interrupts(ah);
 274         ath9k_hw_enable_interrupts(ah);
 275         ieee80211_wake_queues(sc->hw);
 276         ath9k_p2p_ps_timer(sc);
 277
 278         return true;
 279 }
 280
 281 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
 282 {
 283         struct ath_hw *ah = sc->sc_ah;
 284         struct ath_common *common = ath9k_hw_common(ah);
 285         struct ath9k_hw_cal_data *caldata = NULL;
 286         bool fastcc = true;
 287         int r;
 288
 289         __ath_cancel_work(sc);
 290
 291         disable_irq(sc->irq);
 292         tasklet_disable(&sc->intr_tq);
 293         tasklet_disable(&sc->bcon_tasklet);
 294         spin_lock_bh(&sc->sc_pcu_lock);
 295
 296         if (!sc->cur_chan->offchannel) {
 297                 fastcc = false;
 298                 caldata = &sc->cur_chan->caldata;
 299         }
 300
 301         if (!hchan) {
 302                 fastcc = false;
 303                 hchan = ah->curchan;
 304         }
 305
 306         if (!hchan) {
 307                 fastcc = false;
 308                 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
 309         }
 310
 311         if (!ath_prepare_reset(sc))
 312                 fastcc = false;
 313
 314         if (ath9k_is_chanctx_enabled())
 315                 fastcc = false;
 316
 317         spin_lock_bh(&sc->chan_lock);
 318         sc->cur_chandef = sc->cur_chan->chandef;
 319         spin_unlock_bh(&sc->chan_lock);
 320
 321         ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
 322                 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
 323
 324         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
 325         if (r) {
 326                 ath_err(common,
 327                         "Unable to reset channel, reset status %d\n", r);
 328
 329                 ath9k_hw_enable_interrupts(ah);
 330                 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
 331
 332                 goto out;
 333         }
 334
 335         if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
 336             sc->cur_chan->offchannel)
 337                 ath9k_mci_set_txpower(sc, true, false);
 338
 339         if (!ath_complete_reset(sc, true))
 340                 r = -EIO;
 341
 342 out:
 343         enable_irq(sc->irq);
 344         spin_unlock_bh(&sc->sc_pcu_lock);
 345         tasklet_enable(&sc->bcon_tasklet);
 346         tasklet_enable(&sc->intr_tq);
 347
 348         return r;
 349 }
 350
 351 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
 352                             struct ieee80211_vif *vif)
 353 {
 354         struct ath_node *an;
 355         an = (struct ath_node *)sta->drv_priv;
 356
 357         an->sc = sc;
 358         an->sta = sta;
 359         an->vif = vif;
 360         memset(&an->key_idx, 0, sizeof(an->key_idx));
 361
 362         ath_tx_node_init(sc, an);
 363
 364         ath_dynack_node_init(sc->sc_ah, an);
 365 }
 366
 367 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 368 {
 369         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 370         ath_tx_node_cleanup(sc, an);
 371
 372         ath_dynack_node_deinit(sc->sc_ah, an);
 373 }
 374
 375 void ath9k_tasklet(unsigned long data)
 376 {
 377         struct ath_softc *sc = (struct ath_softc *)data;
 378         struct ath_hw *ah = sc->sc_ah;
 379         struct ath_common *common = ath9k_hw_common(ah);
 380         enum ath_reset_type type;
 381         unsigned long flags;
 382         u32 status;
 383         u32 rxmask;
 384
 385         spin_lock_irqsave(&sc->intr_lock, flags);
 386         status = sc->intrstatus;
 387         sc->intrstatus = 0;
 388         spin_unlock_irqrestore(&sc->intr_lock, flags);
 389
 390         ath9k_ps_wakeup(sc);
 391         spin_lock(&sc->sc_pcu_lock);
 392
 393         if (status & ATH9K_INT_FATAL) {
 394                 type = RESET_TYPE_FATAL_INT;
 395                 ath9k_queue_reset(sc, type);
 396                 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
 397                 goto out;
 398         }
 399
 400         if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 401             (status & ATH9K_INT_BB_WATCHDOG)) {
 402                 spin_lock(&common->cc_lock);
 403                 ath_hw_cycle_counters_update(common);
 404                 ar9003_hw_bb_watchdog_dbg_info(ah);
 405                 spin_unlock(&common->cc_lock);
 406
 407                 if (ar9003_hw_bb_watchdog_check(ah)) {
 408                         type = RESET_TYPE_BB_WATCHDOG;
 409                         ath9k_queue_reset(sc, type);
 410
 411                         ath_dbg(common, RESET,
 412                                 "BB_WATCHDOG: Skipping interrupts\n");
 413                         goto out;
 414                 }
 415         }
 416
 417         if (status & ATH9K_INT_GTT) {
 418                 sc->gtt_cnt++;
 419
 420                 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
 421                         type = RESET_TYPE_TX_GTT;
 422                         ath9k_queue_reset(sc, type);
 423                         ath_dbg(common, RESET,
 424                                 "GTT: Skipping interrupts\n");
 425                         goto out;
 426                 }
 427         }
 428
 429         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 430         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 431                 /*
 432                  * TSF sync does not look correct; remain awake to sync with
 433                  * the next Beacon.
 434                  */
 435                 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
 436                 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
 437         }
 438         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 439
 440         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 441                 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
 442                           ATH9K_INT_RXORN);
 443         else
 444                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 445
 446         if (status & rxmask) {
 447                 /* Check for high priority Rx first */
 448                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 449                     (status & ATH9K_INT_RXHP))
 450                         ath_rx_tasklet(sc, 0, true);
 451
 452                 ath_rx_tasklet(sc, 0, false);
 453         }
 454
 455         if (status & ATH9K_INT_TX) {
 456                 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 457                         /*
 458                          * For EDMA chips, TX completion is enabled for the
 459                          * beacon queue, so if a beacon has been transmitted
 460                          * successfully after a GTT interrupt, the GTT counter
 461                          * gets reset to zero here.
 462                          */
 463                         sc->gtt_cnt = 0;
 464
 465                         ath_tx_edma_tasklet(sc);
 466                 } else {
 467                         ath_tx_tasklet(sc);
 468                 }
 469
 470                 wake_up(&sc->tx_wait);
 471         }
 472
 473         if (status & ATH9K_INT_GENTIMER)
 474                 ath_gen_timer_isr(sc->sc_ah);
 475
 476         ath9k_btcoex_handle_interrupt(sc, status);
 477
 478         /* re-enable hardware interrupt */
 479         ath9k_hw_resume_interrupts(ah);
 480 out:
 481         spin_unlock(&sc->sc_pcu_lock);
 482         ath9k_ps_restore(sc);
 483 }
 484
 485 irqreturn_t ath_isr(int irq, void *dev)
 486 {
 487 #define SCHED_INTR (                            \
 488                 ATH9K_INT_FATAL |               \
 489                 ATH9K_INT_BB_WATCHDOG |         \
 490                 ATH9K_INT_RXORN |               \
 491                 ATH9K_INT_RXEOL |               \
 492                 ATH9K_INT_RX |                  \
 493                 ATH9K_INT_RXLP |                \
 494                 ATH9K_INT_RXHP |                \
 495                 ATH9K_INT_TX |                  \
 496                 ATH9K_INT_BMISS |               \
 497                 ATH9K_INT_CST |                 \
 498                 ATH9K_INT_GTT |                 \
 499                 ATH9K_INT_TSFOOR |              \
 500                 ATH9K_INT_GENTIMER |            \
 501                 ATH9K_INT_MCI)
 502
 503         struct ath_softc *sc = dev;
 504         struct ath_hw *ah = sc->sc_ah;
 505         struct ath_common *common = ath9k_hw_common(ah);
 506         enum ath9k_int status;
 507         u32 sync_cause = 0;
 508         bool sched = false;
 509
 510         /*
 511          * The hardware is not ready/present, don't
 512          * touch anything. Note this can happen early
 513          * on if the IRQ is shared.
 514          */
 515         if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
 516                 return IRQ_NONE;
 517
 518         /* shared irq, not for us */
 519         if (!ath9k_hw_intrpend(ah))
 520                 return IRQ_NONE;
 521
 522         /*
 523          * Figure out the reason(s) for the interrupt.  Note
 524          * that the hal returns a pseudo-ISR that may include
 525          * bits we haven't explicitly enabled so we mask the
 526          * value to insure we only process bits we requested.
 527          */
 528         ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
 529         ath9k_debug_sync_cause(sc, sync_cause);
 530         status &= ah->imask;    /* discard unasked-for bits */
 531
 532         if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
 533                 return IRQ_HANDLED;
 534
 535         /*
 536          * If there are no status bits set, then this interrupt was not
 537          * for me (should have been caught above).
 538          */
 539         if (!status)
 540                 return IRQ_NONE;
 541
 542         /* Cache the status */
 543         spin_lock(&sc->intr_lock);
 544         sc->intrstatus |= status;
 545         spin_unlock(&sc->intr_lock);
 546
 547         if (status & SCHED_INTR)
 548                 sched = true;
 549
 550         /*
 551          * If a FATAL interrupt is received, we have to reset the chip
 552          * immediately.
 553          */
 554         if (status & ATH9K_INT_FATAL)
 555                 goto chip_reset;
 556
 557         if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 558             (status & ATH9K_INT_BB_WATCHDOG))
 559                 goto chip_reset;
 560
 561         if (status & ATH9K_INT_SWBA)
 562                 tasklet_schedule(&sc->bcon_tasklet);
 563
 564         if (status & ATH9K_INT_TXURN)
 565                 ath9k_hw_updatetxtriglevel(ah, true);
 566
 567         if (status & ATH9K_INT_RXEOL) {
 568                 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 569                 ath9k_hw_set_interrupts(ah);
 570         }
 571
 572         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 573                 if (status & ATH9K_INT_TIM_TIMER) {
 574                         if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
 575                                 goto chip_reset;
 576                         /* Clear RxAbort bit so that we can
 577                          * receive frames */
 578                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 579                         spin_lock(&sc->sc_pm_lock);
 580                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 581                         sc->ps_flags |= PS_WAIT_FOR_BEACON;
 582                         spin_unlock(&sc->sc_pm_lock);
 583                 }
 584
 585 chip_reset:
 586
 587         ath_debug_stat_interrupt(sc, status);
 588
 589         if (sched) {
 590                 /* turn off every interrupt */
 591                 ath9k_hw_kill_interrupts(ah);
 592                 tasklet_schedule(&sc->intr_tq);
 593         }
 594
 595         return IRQ_HANDLED;
 596
 597 #undef SCHED_INTR
 598 }
 599
 600 /*
 601  * This function is called when a HW reset cannot be deferred
 602  * and has to be immediate.
 603  */
 604 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
 605 {
 606         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 607         int r;
 608
 609         ath9k_hw_kill_interrupts(sc->sc_ah);
 610         set_bit(ATH_OP_HW_RESET, &common->op_flags);
 611
 612         ath9k_ps_wakeup(sc);
 613         r = ath_reset_internal(sc, hchan);
 614         ath9k_ps_restore(sc);
 615
 616         return r;
 617 }
 618
 619 /*
 620  * When a HW reset can be deferred, it is added to the
 621  * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
 622  * queueing.
 623  */
 624 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
 625 {
 626         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 627 #ifdef CONFIG_ATH9K_DEBUGFS
 628         RESET_STAT_INC(sc, type);
 629 #endif
 630         ath9k_hw_kill_interrupts(sc->sc_ah);
 631         set_bit(ATH_OP_HW_RESET, &common->op_flags);
 632         ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
 633 }
 634
 635 void ath_reset_work(struct work_struct *work)
 636 {
 637         struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
 638
 639         ath9k_ps_wakeup(sc);
 640         ath_reset_internal(sc, NULL);
 641         ath9k_ps_restore(sc);
 642 }
 643
 644 /**********************/
 645 /* mac80211 callbacks */
 646 /**********************/
 647
 648 static int ath9k_start(struct ieee80211_hw *hw)
 649 {
 650         struct ath_softc *sc = hw->priv;
 651         struct ath_hw *ah = sc->sc_ah;
 652         struct ath_common *common = ath9k_hw_common(ah);
 653         struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
 654         struct ath_chanctx *ctx = sc->cur_chan;
 655         struct ath9k_channel *init_channel;
 656         int r;
 657
 658         ath_dbg(common, CONFIG,
 659                 "Starting driver with initial channel: %d MHz\n",
 660                 curchan->center_freq);
 661
 662         ath9k_ps_wakeup(sc);
 663         mutex_lock(&sc->mutex);
 664
 665         init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
 666         sc->cur_chandef = hw->conf.chandef;
 667
 668         /* Reset SERDES registers */
 669         ath9k_hw_configpcipowersave(ah, false);
 670
 671         /*
 672          * The basic interface to setting the hardware in a good
 673          * state is ``reset''.  On return the hardware is known to
 674          * be powered up and with interrupts disabled.  This must
 675          * be followed by initialization of the appropriate bits
 676          * and then setup of the interrupt mask.
 677          */
 678         spin_lock_bh(&sc->sc_pcu_lock);
 679
 680         atomic_set(&ah->intr_ref_cnt, -1);
 681
 682         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
 683         if (r) {
 684                 ath_err(common,
 685                         "Unable to reset hardware; reset status %d (freq %u MHz)\n",
 686                         r, curchan->center_freq);
 687                 ah->reset_power_on = false;
 688         }
 689
 690         /* Setup our intr mask. */
 691         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
 692                     ATH9K_INT_RXORN | ATH9K_INT_FATAL |
 693                     ATH9K_INT_GLOBAL;
 694
 695         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 696                 ah->imask |= ATH9K_INT_RXHP |
 697                              ATH9K_INT_RXLP;
 698         else
 699                 ah->imask |= ATH9K_INT_RX;
 700
 701         if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
 702                 ah->imask |= ATH9K_INT_BB_WATCHDOG;
 703
 704         /*
 705          * Enable GTT interrupts only for AR9003/AR9004 chips
 706          * for now.
 707          */
 708         if (AR_SREV_9300_20_OR_LATER(ah))
 709                 ah->imask |= ATH9K_INT_GTT;
 710
 711         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
 712                 ah->imask |= ATH9K_INT_CST;
 713
 714         ath_mci_enable(sc);
 715
 716         clear_bit(ATH_OP_INVALID, &common->op_flags);
 717         sc->sc_ah->is_monitoring = false;
 718
 719         if (!ath_complete_reset(sc, false))
 720                 ah->reset_power_on = false;
 721
 722         if (ah->led_pin >= 0) {
 723                 ath9k_hw_set_gpio(ah, ah->led_pin,
 724                                   (ah->config.led_active_high) ? 1 : 0);
 725                 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
 726                                           AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 727         }
 728
 729         /*
 730          * Reset key cache to sane defaults (all entries cleared) instead of
 731          * semi-random values after suspend/resume.
 732          */
 733         ath9k_cmn_init_crypto(sc->sc_ah);
 734
 735         ath9k_hw_reset_tsf(ah);
 736
 737         spin_unlock_bh(&sc->sc_pcu_lock);
 738
 739         ath9k_rng_start(sc);
 740
 741         mutex_unlock(&sc->mutex);
 742
 743         ath9k_ps_restore(sc);
 744
 745         return 0;
 746 }
 747
 748 static void ath9k_tx(struct ieee80211_hw *hw,
 749                      struct ieee80211_tx_control *control,
 750                      struct sk_buff *skb)
 751 {
 752         struct ath_softc *sc = hw->priv;
 753         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 754         struct ath_tx_control txctl;
 755         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 756         unsigned long flags;
 757
 758         if (sc->ps_enabled) {
 759                 /*
 760                  * mac80211 does not set PM field for normal data frames, so we
 761                  * need to update that based on the current PS mode.
 762                  */
 763                 if (ieee80211_is_data(hdr->frame_control) &&
 764                     !ieee80211_is_nullfunc(hdr->frame_control) &&
 765                     !ieee80211_has_pm(hdr->frame_control)) {
 766                         ath_dbg(common, PS,
 767                                 "Add PM=1 for a TX frame while in PS mode\n");
 768                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
 769                 }
 770         }
 771
 772         if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
 773                 /*
 774                  * We are using PS-Poll and mac80211 can request TX while in
 775                  * power save mode. Need to wake up hardware for the TX to be
 776                  * completed and if needed, also for RX of buffered frames.
 777                  */
 778                 ath9k_ps_wakeup(sc);
 779                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
 780                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 781                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 782                 if (ieee80211_is_pspoll(hdr->frame_control)) {
 783                         ath_dbg(common, PS,
 784                                 "Sending PS-Poll to pick a buffered frame\n");
 785                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
 786                 } else {
 787                         ath_dbg(common, PS, "Wake up to complete TX\n");
 788                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
 789                 }
 790                 /*
 791                  * The actual restore operation will happen only after
 792                  * the ps_flags bit is cleared. We are just dropping
 793                  * the ps_usecount here.
 794                  */
 795                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 796                 ath9k_ps_restore(sc);
 797         }
 798
 799         /*
 800          * Cannot tx while the hardware is in full sleep, it first needs a full
 801          * chip reset to recover from that
 802          */
 803         if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
 804                 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
 805                 goto exit;
 806         }
 807
 808         memset(&txctl, 0, sizeof(struct ath_tx_control));
 809         txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
 810         txctl.sta = control->sta;
 811
 812         ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
 813
 814         if (ath_tx_start(hw, skb, &txctl) != 0) {
 815                 ath_dbg(common, XMIT, "TX failed\n");
 816                 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
 817                 goto exit;
 818         }
 819
 820         return;
 821 exit:
 822         ieee80211_free_txskb(hw, skb);
 823 }
 824
 825 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
 826 {
 827         struct ath_buf *bf;
 828         struct ieee80211_tx_info *txinfo;
 829         struct ath_frame_info *fi;
 830
 831         list_for_each_entry(bf, txq_list, list) {
 832                 if (bf->bf_state.stale || !bf->bf_mpdu)
 833                         continue;
 834
 835                 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
 836                 fi = (struct ath_frame_info *)&txinfo->rate_driver_data[0];
 837                 if (fi->keyix == keyix)
 838                         return true;
 839         }
 840
 841         return false;
 842 }
 843
 844 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
 845 {
 846         struct ath_hw *ah = sc->sc_ah;
 847         int i;
 848         struct ath_txq *txq;
 849         bool key_in_use = false;
 850
 851         for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
 852                 if (!ATH_TXQ_SETUP(sc, i))
 853                         continue;
 854                 txq = &sc->tx.txq[i];
 855                 if (!txq->axq_depth)
 856                         continue;
 857                 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
 858                         continue;
 859
 860                 ath_txq_lock(sc, txq);
 861                 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
 862                 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 863                         int idx = txq->txq_tailidx;
 864
 865                         while (!key_in_use &&
 866                                !list_empty(&txq->txq_fifo[idx])) {
 867                                 key_in_use = ath9k_txq_list_has_key(
 868                                         &txq->txq_fifo[idx], keyix);
 869                                 INCR(idx, ATH_TXFIFO_DEPTH);
 870                         }
 871                 }
 872                 ath_txq_unlock(sc, txq);
 873         }
 874
 875         return key_in_use;
 876 }
 877
 878 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
 879 {
 880         struct ath_hw *ah = sc->sc_ah;
 881         struct ath_common *common = ath9k_hw_common(ah);
 882
 883         if (!test_bit(keyix, ah->pending_del_keymap) ||
 884             ath9k_txq_has_key(sc, keyix))
 885                 return;
 886
 887         /* No more TXQ frames point to this key cache entry, so delete it. */
 888         clear_bit(keyix, ah->pending_del_keymap);
 889         ath_key_delete(common, keyix);
 890 }
 891
 892 static void ath9k_stop(struct ieee80211_hw *hw)
 893 {
 894         struct ath_softc *sc = hw->priv;
 895         struct ath_hw *ah = sc->sc_ah;
 896         struct ath_common *common = ath9k_hw_common(ah);
 897         bool prev_idle;
 898         int i;
 899
 900         ath9k_deinit_channel_context(sc);
 901
 902         mutex_lock(&sc->mutex);
 903
 904         ath9k_rng_stop(sc);
 905
 906         ath_cancel_work(sc);
 907
 908         if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
 909                 ath_dbg(common, ANY, "Device not present\n");
 910                 mutex_unlock(&sc->mutex);
 911                 return;
 912         }
 913
 914         /* Ensure HW is awake when we try to shut it down. */
 915         ath9k_ps_wakeup(sc);
 916
 917         spin_lock_bh(&sc->sc_pcu_lock);
 918
 919         /* prevent tasklets to enable interrupts once we disable them */
 920         ah->imask &= ~ATH9K_INT_GLOBAL;
 921
 922         /* make sure h/w will not generate any interrupt
 923          * before setting the invalid flag. */
 924         ath9k_hw_disable_interrupts(ah);
 925
 926         spin_unlock_bh(&sc->sc_pcu_lock);
 927
 928         /* we can now sync irq and kill any running tasklets, since we already
 929          * disabled interrupts and not holding a spin lock */
 930         synchronize_irq(sc->irq);
 931         tasklet_kill(&sc->intr_tq);
 932         tasklet_kill(&sc->bcon_tasklet);
 933
 934         prev_idle = sc->ps_idle;
 935         sc->ps_idle = true;
 936
 937         spin_lock_bh(&sc->sc_pcu_lock);
 938
 939         if (ah->led_pin >= 0) {
 940                 ath9k_hw_set_gpio(ah, ah->led_pin,
 941                                   (ah->config.led_active_high) ? 0 : 1);
 942                 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
 943         }
 944
 945         ath_prepare_reset(sc);
 946
 947         if (sc->rx.frag) {
 948                 dev_kfree_skb_any(sc->rx.frag);
 949                 sc->rx.frag = NULL;
 950         }
 951
 952         if (!ah->curchan)
 953                 ah->curchan = ath9k_cmn_get_channel(hw, ah,
 954                                                     &sc->cur_chan->chandef);
 955
 956         ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 957
 958         set_bit(ATH_OP_INVALID, &common->op_flags);
 959
 960         ath9k_hw_phy_disable(ah);
 961
 962         ath9k_hw_configpcipowersave(ah, true);
 963
 964         spin_unlock_bh(&sc->sc_pcu_lock);
 965
 966         for (i = 0; i < ATH_KEYMAX; i++)
 967                 ath9k_pending_key_del(sc, i);
 968
 969         /* Clear key cache entries explicitly to get rid of any potentially
 970          * remaining keys.
 971          */
 972         ath9k_cmn_init_crypto(sc->sc_ah);
 973
 974         ath9k_ps_restore(sc);
 975
 976         sc->ps_idle = prev_idle;
 977
 978         mutex_unlock(&sc->mutex);
 979
 980         ath_dbg(common, CONFIG, "Driver halt\n");
 981 }
 982
 983 static bool ath9k_uses_beacons(int type)
 984 {
 985         switch (type) {
 986         case NL80211_IFTYPE_AP:
 987         case NL80211_IFTYPE_ADHOC:
 988         case NL80211_IFTYPE_MESH_POINT:
 989                 return true;
 990         default:
 991                 return false;
 992         }
 993 }
 994
 995 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
 996                                       struct ieee80211_vif *vif)
 997 {
 998         /* Use the first (configured) interface, but prefering AP interfaces. */
 999         if (!iter_data->primary_beacon_vif) {
1000                 iter_data->primary_beacon_vif = vif;
1001         } else {
1002                 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1003                     vif->type == NL80211_IFTYPE_AP)
1004                         iter_data->primary_beacon_vif = vif;
1005         }
1006
1007         iter_data->beacons = true;
1008         iter_data->nbcnvifs += 1;
1009 }
1010
1011 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1012                            u8 *mac, struct ieee80211_vif *vif)
1013 {
1014         struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1015         int i;
1016
1017         if (iter_data->has_hw_macaddr) {
1018                 for (i = 0; i < ETH_ALEN; i++)
1019                         iter_data->mask[i] &=
1020                                 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1021         } else {
1022                 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1023                 iter_data->has_hw_macaddr = true;
1024         }
1025
1026         if (!vif->bss_conf.use_short_slot)
1027                 iter_data->slottime = 20;
1028
1029         switch (vif->type) {
1030         case NL80211_IFTYPE_AP:
1031                 iter_data->naps++;
1032                 if (vif->bss_conf.enable_beacon)
1033                         ath9k_vif_iter_set_beacon(iter_data, vif);
1034                 break;
1035         case NL80211_IFTYPE_STATION:
1036                 iter_data->nstations++;
1037                 if (avp->assoc && !iter_data->primary_sta)
1038                         iter_data->primary_sta = vif;
1039                 break;
1040         case NL80211_IFTYPE_OCB:
1041                 iter_data->nocbs++;
1042                 break;
1043         case NL80211_IFTYPE_ADHOC:
1044                 iter_data->nadhocs++;
1045                 if (vif->bss_conf.enable_beacon)
1046                         ath9k_vif_iter_set_beacon(iter_data, vif);
1047                 break;
1048         case NL80211_IFTYPE_MESH_POINT:
1049                 iter_data->nmeshes++;
1050                 if (vif->bss_conf.enable_beacon)
1051                         ath9k_vif_iter_set_beacon(iter_data, vif);
1052                 break;
1053         case NL80211_IFTYPE_WDS:
1054                 iter_data->nwds++;
1055                 break;
1056         default:
1057                 break;
1058         }
1059 }
1060
1061 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1062                                     struct ath_chanctx *ctx,
1063                                     struct ath9k_vif_iter_data *iter_data)
1064 {
1065         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1066         struct ath_vif *avp;
1067         int i;
1068
1069         if (!ath9k_is_chanctx_enabled())
1070                 return;
1071
1072         list_for_each_entry(avp, &ctx->vifs, list) {
1073                 if (ctx->nvifs_assigned != 1)
1074                         continue;
1075
1076                 if (!iter_data->has_hw_macaddr)
1077                         continue;
1078
1079                 ether_addr_copy(common->curbssid, avp->bssid);
1080
1081                 /* perm_addr will be used as the p2p device address. */
1082                 for (i = 0; i < ETH_ALEN; i++)
1083                         iter_data->mask[i] &=
1084                                 ~(iter_data->hw_macaddr[i] ^
1085                                   sc->hw->wiphy->perm_addr[i]);
1086         }
1087 }
1088
1089 /* Called with sc->mutex held. */
1090 void ath9k_calculate_iter_data(struct ath_softc *sc,
1091                                struct ath_chanctx *ctx,
1092                                struct ath9k_vif_iter_data *iter_data)
1093 {
1094         struct ath_vif *avp;
1095
1096         /*
1097          * The hardware will use primary station addr together with the
1098          * BSSID mask when matching addresses.
1099          */
1100         memset(iter_data, 0, sizeof(*iter_data));
1101         eth_broadcast_addr(iter_data->mask);
1102         iter_data->slottime = 9;
1103
1104         list_for_each_entry(avp, &ctx->vifs, list)
1105                 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1106
1107         ath9k_update_bssid_mask(sc, ctx, iter_data);
1108 }
1109
1110 static void ath9k_set_assoc_state(struct ath_softc *sc,
1111                                   struct ieee80211_vif *vif, bool changed)
1112 {
1113         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1114         struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1115         unsigned long flags;
1116
1117         set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1118
1119         ether_addr_copy(common->curbssid, avp->bssid);
1120         common->curaid = avp->aid;
1121         ath9k_hw_write_associd(sc->sc_ah);
1122
1123         if (changed) {
1124                 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1125                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1126
1127                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1128                 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1129                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1130         }
1131
1132         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1133                 ath9k_mci_update_wlan_channels(sc, false);
1134
1135         ath_dbg(common, CONFIG,
1136                 "Primary Station interface: %pM, BSSID: %pM\n",
1137                 vif->addr, common->curbssid);
1138 }
1139
1140 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1141 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1142 {
1143         struct ath_hw *ah = sc->sc_ah;
1144         struct ath_common *common = ath9k_hw_common(ah);
1145         struct ieee80211_vif *vif = NULL;
1146
1147         ath9k_ps_wakeup(sc);
1148
1149         if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1150                 vif = sc->offchannel.scan_vif;
1151         else
1152                 vif = sc->offchannel.roc_vif;
1153
1154         if (WARN_ON(!vif))
1155                 goto exit;
1156
1157         eth_zero_addr(common->curbssid);
1158         eth_broadcast_addr(common->bssidmask);
1159         memcpy(common->macaddr, vif->addr, ETH_ALEN);
1160         common->curaid = 0;
1161         ah->opmode = vif->type;
1162         ah->imask &= ~ATH9K_INT_SWBA;
1163         ah->imask &= ~ATH9K_INT_TSFOOR;
1164         ah->slottime = 9;
1165
1166         ath_hw_setbssidmask(common);
1167         ath9k_hw_setopmode(ah);
1168         ath9k_hw_write_associd(sc->sc_ah);
1169         ath9k_hw_set_interrupts(ah);
1170         ath9k_hw_init_global_settings(ah);
1171
1172 exit:
1173         ath9k_ps_restore(sc);
1174 }
1175 #endif
1176
1177 /* Called with sc->mutex held. */
1178 void ath9k_calculate_summary_state(struct ath_softc *sc,
1179                                    struct ath_chanctx *ctx)
1180 {
1181         struct ath_hw *ah = sc->sc_ah;
1182         struct ath_common *common = ath9k_hw_common(ah);
1183         struct ath9k_vif_iter_data iter_data;
1184
1185         ath_chanctx_check_active(sc, ctx);
1186
1187         if (ctx != sc->cur_chan)
1188                 return;
1189
1190 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1191         if (ctx == &sc->offchannel.chan)
1192                 return ath9k_set_offchannel_state(sc);
1193 #endif
1194
1195         ath9k_ps_wakeup(sc);
1196         ath9k_calculate_iter_data(sc, ctx, &iter_data);
1197
1198         if (iter_data.has_hw_macaddr)
1199                 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1200
1201         memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1202         ath_hw_setbssidmask(common);
1203
1204         if (iter_data.naps > 0) {
1205                 ath9k_hw_set_tsfadjust(ah, true);
1206                 ah->opmode = NL80211_IFTYPE_AP;
1207         } else {
1208                 ath9k_hw_set_tsfadjust(ah, false);
1209                 if (iter_data.beacons)
1210                         ath9k_beacon_ensure_primary_slot(sc);
1211
1212                 if (iter_data.nmeshes)
1213                         ah->opmode = NL80211_IFTYPE_MESH_POINT;
1214                 else if (iter_data.nocbs)
1215                         ah->opmode = NL80211_IFTYPE_OCB;
1216                 else if (iter_data.nwds)
1217                         ah->opmode = NL80211_IFTYPE_AP;
1218                 else if (iter_data.nadhocs)
1219                         ah->opmode = NL80211_IFTYPE_ADHOC;
1220                 else
1221                         ah->opmode = NL80211_IFTYPE_STATION;
1222         }
1223
1224         ath9k_hw_setopmode(ah);
1225
1226         ctx->switch_after_beacon = false;
1227         if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1228                 ah->imask |= ATH9K_INT_TSFOOR;
1229         else {
1230                 ah->imask &= ~ATH9K_INT_TSFOOR;
1231                 if (iter_data.naps == 1 && iter_data.beacons)
1232                         ctx->switch_after_beacon = true;
1233         }
1234
1235         if (ah->opmode == NL80211_IFTYPE_STATION) {
1236                 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1237
1238                 if (iter_data.primary_sta) {
1239                         iter_data.primary_beacon_vif = iter_data.primary_sta;
1240                         iter_data.beacons = true;
1241                         ath9k_set_assoc_state(sc, iter_data.primary_sta,
1242                                               changed);
1243                         ctx->primary_sta = iter_data.primary_sta;
1244                 } else {
1245                         ctx->primary_sta = NULL;
1246                         eth_zero_addr(common->curbssid);
1247                         common->curaid = 0;
1248                         ath9k_hw_write_associd(sc->sc_ah);
1249                         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1250                                 ath9k_mci_update_wlan_channels(sc, true);
1251                 }
1252         }
1253         sc->nbcnvifs = iter_data.nbcnvifs;
1254         ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1255                             iter_data.beacons);
1256         ath9k_hw_set_interrupts(ah);
1257
1258         if (ah->slottime != iter_data.slottime) {
1259                 ah->slottime = iter_data.slottime;
1260                 ath9k_hw_init_global_settings(ah);
1261         }
1262
1263         if (iter_data.primary_sta)
1264                 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1265         else
1266                 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1267
1268         ath_dbg(common, CONFIG,
1269                 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1270                 common->macaddr, common->curbssid, common->bssidmask);
1271
1272         ath9k_ps_restore(sc);
1273 }
1274
1275 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1276 {
1277         int *power = (int *)data;
1278
1279         if (*power < vif->bss_conf.txpower)
1280                 *power = vif->bss_conf.txpower;
1281 }
1282
1283 /* Called with sc->mutex held. */
1284 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1285 {
1286         int power;
1287         struct ath_hw *ah = sc->sc_ah;
1288         struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1289
1290         ath9k_ps_wakeup(sc);
1291         if (ah->tpc_enabled) {
1292                 power = (vif) ? vif->bss_conf.txpower : -1;
1293                 ieee80211_iterate_active_interfaces_atomic(
1294                                 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1295                                 ath9k_tpc_vif_iter, &power);
1296                 if (power == -1)
1297                         power = sc->hw->conf.power_level;
1298         } else {
1299                 power = sc->hw->conf.power_level;
1300         }
1301         sc->cur_chan->txpower = 2 * power;
1302         ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1303         sc->cur_chan->cur_txpower = reg->max_power_level;
1304         ath9k_ps_restore(sc);
1305 }
1306
1307 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1308                                    struct ieee80211_vif *vif)
1309 {
1310         int i;
1311
1312         if (!ath9k_is_chanctx_enabled())
1313                 return;
1314
1315         for (i = 0; i < IEEE80211_NUM_ACS; i++)
1316                 vif->hw_queue[i] = i;
1317
1318         if (vif->type == NL80211_IFTYPE_AP ||
1319             vif->type == NL80211_IFTYPE_MESH_POINT)
1320                 vif->cab_queue = hw->queues - 2;
1321         else
1322                 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1323 }
1324
1325 static int ath9k_add_interface(struct ieee80211_hw *hw,
1326                                struct ieee80211_vif *vif)
1327 {
1328         struct ath_softc *sc = hw->priv;
1329         struct ath_hw *ah = sc->sc_ah;
1330         struct ath_common *common = ath9k_hw_common(ah);
1331         struct ath_vif *avp = (void *)vif->drv_priv;
1332         struct ath_node *an = &avp->mcast_node;
1333
1334         mutex_lock(&sc->mutex);
1335         if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1336                 if (sc->cur_chan->nvifs >= 1) {
1337                         mutex_unlock(&sc->mutex);
1338                         return -EOPNOTSUPP;
1339                 }
1340                 sc->tx99_vif = vif;
1341         }
1342
1343         ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1344         sc->cur_chan->nvifs++;
1345
1346         if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1347                 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1348
1349         if (ath9k_uses_beacons(vif->type))
1350                 ath9k_beacon_assign_slot(sc, vif);
1351
1352         avp->vif = vif;
1353         if (!ath9k_is_chanctx_enabled()) {
1354                 avp->chanctx = sc->cur_chan;
1355                 list_add_tail(&avp->list, &avp->chanctx->vifs);
1356         }
1357
1358         ath9k_calculate_summary_state(sc, avp->chanctx);
1359
1360         ath9k_assign_hw_queues(hw, vif);
1361
1362         ath9k_set_txpower(sc, vif);
1363
1364         an->sc = sc;
1365         an->sta = NULL;
1366         an->vif = vif;
1367         an->no_ps_filter = true;
1368         ath_tx_node_init(sc, an);
1369
1370         mutex_unlock(&sc->mutex);
1371         return 0;
1372 }
1373
1374 static int ath9k_change_interface(struct ieee80211_hw *hw,
1375                                   struct ieee80211_vif *vif,
1376                                   enum nl80211_iftype new_type,
1377                                   bool p2p)
1378 {
1379         struct ath_softc *sc = hw->priv;
1380         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1381         struct ath_vif *avp = (void *)vif->drv_priv;
1382
1383         mutex_lock(&sc->mutex);
1384
1385         if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1386                 mutex_unlock(&sc->mutex);
1387                 return -EOPNOTSUPP;
1388         }
1389
1390         ath_dbg(common, CONFIG, "Change Interface\n");
1391
1392         if (ath9k_uses_beacons(vif->type))
1393                 ath9k_beacon_remove_slot(sc, vif);
1394
1395         vif->type = new_type;
1396         vif->p2p = p2p;
1397
1398         if (ath9k_uses_beacons(vif->type))
1399                 ath9k_beacon_assign_slot(sc, vif);
1400
1401         ath9k_assign_hw_queues(hw, vif);
1402         ath9k_calculate_summary_state(sc, avp->chanctx);
1403
1404         ath9k_set_txpower(sc, vif);
1405
1406         mutex_unlock(&sc->mutex);
1407         return 0;
1408 }
1409
1410 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1411                                    struct ieee80211_vif *vif)
1412 {
1413         struct ath_softc *sc = hw->priv;
1414         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1415         struct ath_vif *avp = (void *)vif->drv_priv;
1416
1417         ath_dbg(common, CONFIG, "Detach Interface\n");
1418
1419         mutex_lock(&sc->mutex);
1420
1421         ath9k_p2p_remove_vif(sc, vif);
1422
1423         sc->cur_chan->nvifs--;
1424         sc->tx99_vif = NULL;
1425         if (!ath9k_is_chanctx_enabled())
1426                 list_del(&avp->list);
1427
1428         if (ath9k_uses_beacons(vif->type))
1429                 ath9k_beacon_remove_slot(sc, vif);
1430
1431         ath_tx_node_cleanup(sc, &avp->mcast_node);
1432
1433         ath9k_calculate_summary_state(sc, avp->chanctx);
1434
1435         ath9k_set_txpower(sc, NULL);
1436
1437         mutex_unlock(&sc->mutex);
1438 }
1439
1440 static void ath9k_enable_ps(struct ath_softc *sc)
1441 {
1442         struct ath_hw *ah = sc->sc_ah;
1443         struct ath_common *common = ath9k_hw_common(ah);
1444
1445         if (IS_ENABLED(CONFIG_ATH9K_TX99))
1446                 return;
1447
1448         sc->ps_enabled = true;
1449         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1450                 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1451                         ah->imask |= ATH9K_INT_TIM_TIMER;
1452                         ath9k_hw_set_interrupts(ah);
1453                 }
1454                 ath9k_hw_setrxabort(ah, 1);
1455         }
1456         ath_dbg(common, PS, "PowerSave enabled\n");
1457 }
1458
1459 static void ath9k_disable_ps(struct ath_softc *sc)
1460 {
1461         struct ath_hw *ah = sc->sc_ah;
1462         struct ath_common *common = ath9k_hw_common(ah);
1463
1464         if (IS_ENABLED(CONFIG_ATH9K_TX99))
1465                 return;
1466
1467         sc->ps_enabled = false;
1468         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1469         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1470                 ath9k_hw_setrxabort(ah, 0);
1471                 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1472                                   PS_WAIT_FOR_CAB |
1473                                   PS_WAIT_FOR_PSPOLL_DATA |
1474                                   PS_WAIT_FOR_TX_ACK);
1475                 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1476                         ah->imask &= ~ATH9K_INT_TIM_TIMER;
1477                         ath9k_hw_set_interrupts(ah);
1478                 }
1479         }
1480         ath_dbg(common, PS, "PowerSave disabled\n");
1481 }
1482
1483 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1484 {
1485         struct ath_softc *sc = hw->priv;
1486         struct ath_hw *ah = sc->sc_ah;
1487         struct ath_common *common = ath9k_hw_common(ah);
1488         struct ieee80211_conf *conf = &hw->conf;
1489         struct ath_chanctx *ctx = sc->cur_chan;
1490
1491         ath9k_ps_wakeup(sc);
1492         mutex_lock(&sc->mutex);
1493
1494         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1495                 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1496                 if (sc->ps_idle) {
1497                         ath_cancel_work(sc);
1498                         ath9k_stop_btcoex(sc);
1499                 } else {
1500                         ath9k_start_btcoex(sc);
1501                         /*
1502                          * The chip needs a reset to properly wake up from
1503                          * full sleep
1504                          */
1505                         ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1506                 }
1507         }
1508
1509         /*
1510          * We just prepare to enable PS. We have to wait until our AP has
1511          * ACK'd our null data frame to disable RX otherwise we'll ignore
1512          * those ACKs and end up retransmitting the same null data frames.
1513          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1514          */
1515         if (changed & IEEE80211_CONF_CHANGE_PS) {
1516                 unsigned long flags;
1517                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1518                 if (conf->flags & IEEE80211_CONF_PS)
1519                         ath9k_enable_ps(sc);
1520                 else
1521                         ath9k_disable_ps(sc);
1522                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1523         }
1524
1525         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1526                 if (conf->flags & IEEE80211_CONF_MONITOR) {
1527                         ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1528                         sc->sc_ah->is_monitoring = true;
1529                 } else {
1530                         ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1531                         sc->sc_ah->is_monitoring = false;
1532                 }
1533         }
1534
1535         if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1536                 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1537                 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1538         }
1539
1540         if (changed & IEEE80211_CONF_CHANGE_POWER)
1541                 ath9k_set_txpower(sc, NULL);
1542
1543         mutex_unlock(&sc->mutex);
1544         ath9k_ps_restore(sc);
1545
1546         return 0;
1547 }
1548
1549 #define SUPPORTED_FILTERS                       \
1550         (FIF_ALLMULTI |                         \
1551         FIF_CONTROL |                           \
1552         FIF_PSPOLL |                            \
1553         FIF_OTHER_BSS |                         \
1554         FIF_BCN_PRBRESP_PROMISC |               \
1555         FIF_PROBE_REQ |                         \
1556         FIF_FCSFAIL)
1557
1558 /* FIXME: sc->sc_full_reset ? */
1559 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1560                                    unsigned int changed_flags,
1561                                    unsigned int *total_flags,
1562                                    u64 multicast)
1563 {
1564         struct ath_softc *sc = hw->priv;
1565         struct ath_chanctx *ctx;
1566         u32 rfilt;
1567
1568         changed_flags &= SUPPORTED_FILTERS;
1569         *total_flags &= SUPPORTED_FILTERS;
1570
1571         spin_lock_bh(&sc->chan_lock);
1572         ath_for_each_chanctx(sc, ctx)
1573                 ctx->rxfilter = *total_flags;
1574 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1575         sc->offchannel.chan.rxfilter = *total_flags;
1576 #endif
1577         spin_unlock_bh(&sc->chan_lock);
1578
1579         ath9k_ps_wakeup(sc);
1580         rfilt = ath_calcrxfilter(sc);
1581         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1582         ath9k_ps_restore(sc);
1583
1584         ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1585                 rfilt);
1586 }
1587
1588 static int ath9k_sta_add(struct ieee80211_hw *hw,
1589                          struct ieee80211_vif *vif,
1590                          struct ieee80211_sta *sta)
1591 {
1592         struct ath_softc *sc = hw->priv;
1593         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1594         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1595         struct ieee80211_key_conf ps_key = { };
1596         int key;
1597
1598         ath_node_attach(sc, sta, vif);
1599
1600         if (vif->type != NL80211_IFTYPE_AP &&
1601             vif->type != NL80211_IFTYPE_AP_VLAN)
1602                 return 0;
1603
1604         key = ath_key_config(common, vif, sta, &ps_key);
1605         if (key > 0) {
1606                 an->ps_key = key;
1607                 an->key_idx[0] = key;
1608         }
1609
1610         return 0;
1611 }
1612
1613 static void ath9k_del_ps_key(struct ath_softc *sc,
1614                              struct ieee80211_vif *vif,
1615                              struct ieee80211_sta *sta)
1616 {
1617         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1618         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1619
1620         if (!an->ps_key)
1621             return;
1622
1623         ath_key_delete(common, an->ps_key);
1624         an->ps_key = 0;
1625         an->key_idx[0] = 0;
1626 }
1627
1628 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1629                             struct ieee80211_vif *vif,
1630                             struct ieee80211_sta *sta)
1631 {
1632         struct ath_softc *sc = hw->priv;
1633
1634         ath9k_del_ps_key(sc, vif, sta);
1635         ath_node_detach(sc, sta);
1636
1637         return 0;
1638 }
1639
1640 static int ath9k_sta_state(struct ieee80211_hw *hw,
1641                            struct ieee80211_vif *vif,
1642                            struct ieee80211_sta *sta,
1643                            enum ieee80211_sta_state old_state,
1644                            enum ieee80211_sta_state new_state)
1645 {
1646         struct ath_softc *sc = hw->priv;
1647         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1648         int ret = 0;
1649
1650         if (old_state == IEEE80211_STA_NOTEXIST &&
1651             new_state == IEEE80211_STA_NONE) {
1652                 ret = ath9k_sta_add(hw, vif, sta);
1653                 ath_dbg(common, CONFIG,
1654                         "Add station: %pM\n", sta->addr);
1655         } else if (old_state == IEEE80211_STA_NONE &&
1656                    new_state == IEEE80211_STA_NOTEXIST) {
1657                 ret = ath9k_sta_remove(hw, vif, sta);
1658                 ath_dbg(common, CONFIG,
1659                         "Remove station: %pM\n", sta->addr);
1660         }
1661
1662         if (ath9k_is_chanctx_enabled()) {
1663                 if (vif->type == NL80211_IFTYPE_STATION) {
1664                         if (old_state == IEEE80211_STA_ASSOC &&
1665                             new_state == IEEE80211_STA_AUTHORIZED)
1666                                 ath_chanctx_event(sc, vif,
1667                                                   ATH_CHANCTX_EVENT_AUTHORIZED);
1668                 }
1669         }
1670
1671         return ret;
1672 }
1673
1674 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1675                                     struct ath_node *an,
1676                                     bool set)
1677 {
1678         int i;
1679
1680         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1681                 if (!an->key_idx[i])
1682                         continue;
1683                 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1684         }
1685 }
1686
1687 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1688                          struct ieee80211_vif *vif,
1689                          enum sta_notify_cmd cmd,
1690                          struct ieee80211_sta *sta)
1691 {
1692         struct ath_softc *sc = hw->priv;
1693         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1694
1695         switch (cmd) {
1696         case STA_NOTIFY_SLEEP:
1697                 an->sleeping = true;
1698                 ath_tx_aggr_sleep(sta, sc, an);
1699                 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1700                 break;
1701         case STA_NOTIFY_AWAKE:
1702                 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1703                 an->sleeping = false;
1704                 ath_tx_aggr_wakeup(sc, an);
1705                 break;
1706         }
1707 }
1708
1709 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1710                          struct ieee80211_vif *vif, u16 queue,
1711                          const struct ieee80211_tx_queue_params *params)
1712 {
1713         struct ath_softc *sc = hw->priv;
1714         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1715         struct ath_txq *txq;
1716         struct ath9k_tx_queue_info qi;
1717         int ret = 0;
1718
1719         if (queue >= IEEE80211_NUM_ACS)
1720                 return 0;
1721
1722         txq = sc->tx.txq_map[queue];
1723
1724         ath9k_ps_wakeup(sc);
1725         mutex_lock(&sc->mutex);
1726
1727         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1728
1729         qi.tqi_aifs = params->aifs;
1730         qi.tqi_cwmin = params->cw_min;
1731         qi.tqi_cwmax = params->cw_max;
1732         qi.tqi_burstTime = params->txop * 32;
1733
1734         ath_dbg(common, CONFIG,
1735                 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1736                 queue, txq->axq_qnum, params->aifs, params->cw_min,
1737                 params->cw_max, params->txop);
1738
1739         ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1740         ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1741         if (ret)
1742                 ath_err(common, "TXQ Update failed\n");
1743
1744         mutex_unlock(&sc->mutex);
1745         ath9k_ps_restore(sc);
1746
1747         return ret;
1748 }
1749
1750 static int ath9k_set_key(struct ieee80211_hw *hw,
1751                          enum set_key_cmd cmd,
1752                          struct ieee80211_vif *vif,
1753                          struct ieee80211_sta *sta,
1754                          struct ieee80211_key_conf *key)
1755 {
1756         struct ath_softc *sc = hw->priv;
1757         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1758         struct ath_node *an = NULL;
1759         int ret = 0, i;
1760
1761         if (ath9k_modparam_nohwcrypt)
1762                 return -ENOSPC;
1763
1764         if ((vif->type == NL80211_IFTYPE_ADHOC ||
1765              vif->type == NL80211_IFTYPE_MESH_POINT) &&
1766             (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1767              key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1768             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1769                 /*
1770                  * For now, disable hw crypto for the RSN IBSS group keys. This
1771                  * could be optimized in the future to use a modified key cache
1772                  * design to support per-STA RX GTK, but until that gets
1773                  * implemented, use of software crypto for group addressed
1774                  * frames is a acceptable to allow RSN IBSS to be used.
1775                  */
1776                 return -EOPNOTSUPP;
1777         }
1778
1779         mutex_lock(&sc->mutex);
1780         ath9k_ps_wakeup(sc);
1781         ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1782         if (sta)
1783                 an = (struct ath_node *)sta->drv_priv;
1784
1785         /* Delete pending key cache entries if no more frames are pointing to
1786          * them in TXQs.
1787          */
1788         for (i = 0; i < ATH_KEYMAX; i++)
1789                 ath9k_pending_key_del(sc, i);
1790
1791         switch (cmd) {
1792         case SET_KEY:
1793                 if (sta)
1794                         ath9k_del_ps_key(sc, vif, sta);
1795
1796                 key->hw_key_idx = 0;
1797                 ret = ath_key_config(common, vif, sta, key);
1798                 if (ret >= 0) {
1799                         key->hw_key_idx = ret;
1800                         /* push IV and Michael MIC generation to stack */
1801                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1802                         if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1803                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1804                         if (sc->sc_ah->sw_mgmt_crypto_tx &&
1805                             key->cipher == WLAN_CIPHER_SUITE_CCMP)
1806                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1807                         ret = 0;
1808                 }
1809                 if (an && key->hw_key_idx) {
1810                         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1811                                 if (an->key_idx[i])
1812                                         continue;
1813                                 an->key_idx[i] = key->hw_key_idx;
1814                                 break;
1815                         }
1816                         WARN_ON(i == ARRAY_SIZE(an->key_idx));
1817                 }
1818                 break;
1819         case DISABLE_KEY:
1820                 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1821                         /* Delay key cache entry deletion until there are no
1822                          * remaining TXQ frames pointing to this entry.
1823                          */
1824                         set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1825                         ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1826                 } else {
1827                         ath_key_delete(common, key->hw_key_idx);
1828                 }
1829                 if (an) {
1830                         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1831                                 if (an->key_idx[i] != key->hw_key_idx)
1832                                         continue;
1833                                 an->key_idx[i] = 0;
1834                                 break;
1835                         }
1836                 }
1837                 key->hw_key_idx = 0;
1838                 break;
1839         default:
1840                 ret = -EINVAL;
1841         }
1842
1843         ath9k_ps_restore(sc);
1844         mutex_unlock(&sc->mutex);
1845
1846         return ret;
1847 }
1848
1849 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1850                                    struct ieee80211_vif *vif,
1851                                    struct ieee80211_bss_conf *bss_conf,
1852                                    u32 changed)
1853 {
1854 #define CHECK_ANI                               \
1855         (BSS_CHANGED_ASSOC |                    \
1856          BSS_CHANGED_IBSS |                     \
1857          BSS_CHANGED_BEACON_ENABLED)
1858
1859         struct ath_softc *sc = hw->priv;
1860         struct ath_hw *ah = sc->sc_ah;
1861         struct ath_common *common = ath9k_hw_common(ah);
1862         struct ath_vif *avp = (void *)vif->drv_priv;
1863         int slottime;
1864
1865         ath9k_ps_wakeup(sc);
1866         mutex_lock(&sc->mutex);
1867
1868         if (changed & BSS_CHANGED_ASSOC) {
1869                 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1870                         bss_conf->bssid, bss_conf->assoc);
1871
1872                 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1873                 avp->aid = bss_conf->aid;
1874                 avp->assoc = bss_conf->assoc;
1875
1876                 ath9k_calculate_summary_state(sc, avp->chanctx);
1877         }
1878
1879         if ((changed & BSS_CHANGED_IBSS) ||
1880               (changed & BSS_CHANGED_OCB)) {
1881                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1882                 common->curaid = bss_conf->aid;
1883                 ath9k_hw_write_associd(sc->sc_ah);
1884         }
1885
1886         if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1887             (changed & BSS_CHANGED_BEACON_INT) ||
1888             (changed & BSS_CHANGED_BEACON_INFO)) {
1889                 ath9k_calculate_summary_state(sc, avp->chanctx);
1890         }
1891
1892         if ((avp->chanctx == sc->cur_chan) &&
1893             (changed & BSS_CHANGED_ERP_SLOT)) {
1894                 if (bss_conf->use_short_slot)
1895                         slottime = 9;
1896                 else
1897                         slottime = 20;
1898
1899                 if (vif->type == NL80211_IFTYPE_AP) {
1900                         /*
1901                          * Defer update, so that connected stations can adjust
1902                          * their settings at the same time.
1903                          * See beacon.c for more details
1904                          */
1905                         sc->beacon.slottime = slottime;
1906                         sc->beacon.updateslot = UPDATE;
1907                 } else {
1908                         ah->slottime = slottime;
1909                         ath9k_hw_init_global_settings(ah);
1910                 }
1911         }
1912
1913         if (changed & BSS_CHANGED_P2P_PS)
1914                 ath9k_p2p_bss_info_changed(sc, vif);
1915
1916         if (changed & CHECK_ANI)
1917                 ath_check_ani(sc);
1918
1919         if (changed & BSS_CHANGED_TXPOWER) {
1920                 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1921                         vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1922                 ath9k_set_txpower(sc, vif);
1923         }
1924
1925         mutex_unlock(&sc->mutex);
1926         ath9k_ps_restore(sc);
1927
1928 #undef CHECK_ANI
1929 }
1930
1931 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1932 {
1933         struct ath_softc *sc = hw->priv;
1934         struct ath_vif *avp = (void *)vif->drv_priv;
1935         u64 tsf;
1936
1937         mutex_lock(&sc->mutex);
1938         ath9k_ps_wakeup(sc);
1939         /* Get current TSF either from HW or kernel time. */
1940         if (sc->cur_chan == avp->chanctx) {
1941                 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1942         } else {
1943                 tsf = sc->cur_chan->tsf_val +
1944                       ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1945         }
1946         tsf += le64_to_cpu(avp->tsf_adjust);
1947         ath9k_ps_restore(sc);
1948         mutex_unlock(&sc->mutex);
1949
1950         return tsf;
1951 }
1952
1953 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1954                           struct ieee80211_vif *vif,
1955                           u64 tsf)
1956 {
1957         struct ath_softc *sc = hw->priv;
1958         struct ath_vif *avp = (void *)vif->drv_priv;
1959
1960         mutex_lock(&sc->mutex);
1961         ath9k_ps_wakeup(sc);
1962         tsf -= le64_to_cpu(avp->tsf_adjust);
1963         getrawmonotonic(&avp->chanctx->tsf_ts);
1964         if (sc->cur_chan == avp->chanctx)
1965                 ath9k_hw_settsf64(sc->sc_ah, tsf);
1966         avp->chanctx->tsf_val = tsf;
1967         ath9k_ps_restore(sc);
1968         mutex_unlock(&sc->mutex);
1969 }
1970
1971 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1972 {
1973         struct ath_softc *sc = hw->priv;
1974         struct ath_vif *avp = (void *)vif->drv_priv;
1975
1976         mutex_lock(&sc->mutex);
1977
1978         ath9k_ps_wakeup(sc);
1979         getrawmonotonic(&avp->chanctx->tsf_ts);
1980         if (sc->cur_chan == avp->chanctx)
1981                 ath9k_hw_reset_tsf(sc->sc_ah);
1982         avp->chanctx->tsf_val = 0;
1983         ath9k_ps_restore(sc);
1984
1985         mutex_unlock(&sc->mutex);
1986 }
1987
1988 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1989                               struct ieee80211_vif *vif,
1990                               struct ieee80211_ampdu_params *params)
1991 {
1992         struct ath_softc *sc = hw->priv;
1993         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1994         bool flush = false;
1995         int ret = 0;
1996         struct ieee80211_sta *sta = params->sta;
1997         struct ath_node *an = (struct ath_node *)sta->drv_priv;
1998         enum ieee80211_ampdu_mlme_action action = params->action;
1999         u16 tid = params->tid;
2000         u16 *ssn = &params->ssn;
2001         struct ath_atx_tid *atid;
2002
2003         mutex_lock(&sc->mutex);
2004
2005         switch (action) {
2006         case IEEE80211_AMPDU_RX_START:
2007                 break;
2008         case IEEE80211_AMPDU_RX_STOP:
2009                 break;
2010         case IEEE80211_AMPDU_TX_START:
2011                 if (ath9k_is_chanctx_enabled()) {
2012                         if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2013                                 ret = -EBUSY;
2014                                 break;
2015                         }
2016                 }
2017                 ath9k_ps_wakeup(sc);
2018                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2019                 if (!ret)
2020                         ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2021                 ath9k_ps_restore(sc);
2022                 break;
2023         case IEEE80211_AMPDU_TX_STOP_FLUSH:
2024         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2025                 flush = true;
2026         case IEEE80211_AMPDU_TX_STOP_CONT:
2027                 ath9k_ps_wakeup(sc);
2028                 ath_tx_aggr_stop(sc, sta, tid);
2029                 if (!flush)
2030                         ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2031                 ath9k_ps_restore(sc);
2032                 break;
2033         case IEEE80211_AMPDU_TX_OPERATIONAL:
2034                 atid = ath_node_to_tid(an, tid);
2035                 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2036                                 sta->ht_cap.ampdu_factor;
2037                 break;
2038         default:
2039                 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2040         }
2041
2042         mutex_unlock(&sc->mutex);
2043
2044         return ret;
2045 }
2046
2047 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2048                              struct survey_info *survey)
2049 {
2050         struct ath_softc *sc = hw->priv;
2051         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2052         struct ieee80211_supported_band *sband;
2053         struct ieee80211_channel *chan;
2054         int pos;
2055
2056         if (IS_ENABLED(CONFIG_ATH9K_TX99))
2057                 return -EOPNOTSUPP;
2058
2059         spin_lock_bh(&common->cc_lock);
2060         if (idx == 0)
2061                 ath_update_survey_stats(sc);
2062
2063         sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2064         if (sband && idx >= sband->n_channels) {
2065                 idx -= sband->n_channels;
2066                 sband = NULL;
2067         }
2068
2069         if (!sband)
2070                 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2071
2072         if (!sband || idx >= sband->n_channels) {
2073                 spin_unlock_bh(&common->cc_lock);
2074                 return -ENOENT;
2075         }
2076
2077         chan = &sband->channels[idx];
2078         pos = chan->hw_value;
2079         memcpy(survey, &sc->survey[pos], sizeof(*survey));
2080         survey->channel = chan;
2081         spin_unlock_bh(&common->cc_lock);
2082
2083         return 0;
2084 }
2085
2086 static void ath9k_enable_dynack(struct ath_softc *sc)
2087 {
2088 #ifdef CONFIG_ATH9K_DYNACK
2089         u32 rfilt;
2090         struct ath_hw *ah = sc->sc_ah;
2091
2092         ath_dynack_reset(ah);
2093
2094         ah->dynack.enabled = true;
2095         rfilt = ath_calcrxfilter(sc);
2096         ath9k_hw_setrxfilter(ah, rfilt);
2097 #endif
2098 }
2099
2100 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2101                                      s16 coverage_class)
2102 {
2103         struct ath_softc *sc = hw->priv;
2104         struct ath_hw *ah = sc->sc_ah;
2105
2106         if (IS_ENABLED(CONFIG_ATH9K_TX99))
2107                 return;
2108
2109         mutex_lock(&sc->mutex);
2110
2111         if (coverage_class >= 0) {
2112                 ah->coverage_class = coverage_class;
2113                 if (ah->dynack.enabled) {
2114                         u32 rfilt;
2115
2116                         ah->dynack.enabled = false;
2117                         rfilt = ath_calcrxfilter(sc);
2118                         ath9k_hw_setrxfilter(ah, rfilt);
2119                 }
2120                 ath9k_ps_wakeup(sc);
2121                 ath9k_hw_init_global_settings(ah);
2122                 ath9k_ps_restore(sc);
2123         } else if (!ah->dynack.enabled) {
2124                 ath9k_enable_dynack(sc);
2125         }
2126
2127         mutex_unlock(&sc->mutex);
2128 }
2129
2130 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2131                                  bool sw_pending)
2132 {
2133         int i, npend = 0;
2134
2135         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2136                 if (!ATH_TXQ_SETUP(sc, i))
2137                         continue;
2138
2139                 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2140                                                  sw_pending);
2141                 if (npend)
2142                         break;
2143         }
2144
2145         return !!npend;
2146 }
2147
2148 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2149                         u32 queues, bool drop)
2150 {
2151         struct ath_softc *sc = hw->priv;
2152         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2153
2154         if (ath9k_is_chanctx_enabled()) {
2155                 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2156                         goto flush;
2157
2158                 /*
2159                  * If MCC is active, extend the flush timeout
2160                  * and wait for the HW/SW queues to become
2161                  * empty. This needs to be done outside the
2162                  * sc->mutex lock to allow the channel scheduler
2163                  * to switch channel contexts.
2164                  *
2165                  * The vif queues have been stopped in mac80211,
2166                  * so there won't be any incoming frames.
2167                  */
2168                 __ath9k_flush(hw, queues, drop, true, true);
2169                 return;
2170         }
2171 flush:
2172         mutex_lock(&sc->mutex);
2173         __ath9k_flush(hw, queues, drop, true, false);
2174         mutex_unlock(&sc->mutex);
2175 }
2176
2177 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2178                    bool sw_pending, bool timeout_override)
2179 {
2180         struct ath_softc *sc = hw->priv;
2181         struct ath_hw *ah = sc->sc_ah;
2182         struct ath_common *common = ath9k_hw_common(ah);
2183         int timeout;
2184         bool drain_txq;
2185
2186         cancel_delayed_work_sync(&sc->hw_check_work);
2187
2188         if (ah->ah_flags & AH_UNPLUGGED) {
2189                 ath_dbg(common, ANY, "Device has been unplugged!\n");
2190                 return;
2191         }
2192
2193         if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2194                 ath_dbg(common, ANY, "Device not present\n");
2195                 return;
2196         }
2197
2198         spin_lock_bh(&sc->chan_lock);
2199         if (timeout_override)
2200                 timeout = HZ / 5;
2201         else
2202                 timeout = sc->cur_chan->flush_timeout;
2203         spin_unlock_bh(&sc->chan_lock);
2204
2205         ath_dbg(common, CHAN_CTX,
2206                 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2207
2208         if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2209                                timeout) > 0)
2210                 drop = false;
2211
2212         if (drop) {
2213                 ath9k_ps_wakeup(sc);
2214                 spin_lock_bh(&sc->sc_pcu_lock);
2215                 drain_txq = ath_drain_all_txq(sc);
2216                 spin_unlock_bh(&sc->sc_pcu_lock);
2217
2218                 if (!drain_txq)
2219                         ath_reset(sc, NULL);
2220
2221                 ath9k_ps_restore(sc);
2222         }
2223
2224         ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2225                                      ATH_HW_CHECK_POLL_INT);
2226 }
2227
2228 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2229 {
2230         struct ath_softc *sc = hw->priv;
2231
2232         return ath9k_has_tx_pending(sc, true);
2233 }
2234
2235 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2236 {
2237         struct ath_softc *sc = hw->priv;
2238         struct ath_hw *ah = sc->sc_ah;
2239         struct ieee80211_vif *vif;
2240         struct ath_vif *avp;
2241         struct ath_buf *bf;
2242         struct ath_tx_status ts;
2243         bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2244         int status;
2245
2246         vif = sc->beacon.bslot[0];
2247         if (!vif)
2248                 return 0;
2249
2250         if (!vif->bss_conf.enable_beacon)
2251                 return 0;
2252
2253         avp = (void *)vif->drv_priv;
2254
2255         if (!sc->beacon.tx_processed && !edma) {
2256                 tasklet_disable(&sc->bcon_tasklet);
2257
2258                 bf = avp->av_bcbuf;
2259                 if (!bf || !bf->bf_mpdu)
2260                         goto skip;
2261
2262                 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2263                 if (status == -EINPROGRESS)
2264                         goto skip;
2265
2266                 sc->beacon.tx_processed = true;
2267                 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2268
2269 skip:
2270                 tasklet_enable(&sc->bcon_tasklet);
2271         }
2272
2273         return sc->beacon.tx_last;
2274 }
2275
2276 static int ath9k_get_stats(struct ieee80211_hw *hw,
2277                            struct ieee80211_low_level_stats *stats)
2278 {
2279         struct ath_softc *sc = hw->priv;
2280         struct ath_hw *ah = sc->sc_ah;
2281         struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2282
2283         stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2284         stats->dot11RTSFailureCount = mib_stats->rts_bad;
2285         stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2286         stats->dot11RTSSuccessCount = mib_stats->rts_good;
2287         return 0;
2288 }
2289
2290 static u32 fill_chainmask(u32 cap, u32 new)
2291 {
2292         u32 filled = 0;
2293         int i;
2294
2295         for (i = 0; cap && new; i++, cap >>= 1) {
2296                 if (!(cap & BIT(0)))
2297                         continue;
2298
2299                 if (new & BIT(0))
2300                         filled |= BIT(i);
2301
2302                 new >>= 1;
2303         }
2304
2305         return filled;
2306 }
2307
2308 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2309 {
2310         if (AR_SREV_9300_20_OR_LATER(ah))
2311                 return true;
2312
2313         switch (val & 0x7) {
2314         case 0x1:
2315         case 0x3:
2316         case 0x7:
2317                 return true;
2318         case 0x2:
2319                 return (ah->caps.rx_chainmask == 1);
2320         default:
2321                 return false;
2322         }
2323 }
2324
2325 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2326 {
2327         struct ath_softc *sc = hw->priv;
2328         struct ath_hw *ah = sc->sc_ah;
2329
2330         if (ah->caps.rx_chainmask != 1)
2331                 rx_ant |= tx_ant;
2332
2333         if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2334                 return -EINVAL;
2335
2336         sc->ant_rx = rx_ant;
2337         sc->ant_tx = tx_ant;
2338
2339         if (ah->caps.rx_chainmask == 1)
2340                 return 0;
2341
2342         /* AR9100 runs into calibration issues if not all rx chains are enabled */
2343         if (AR_SREV_9100(ah))
2344                 ah->rxchainmask = 0x7;
2345         else
2346                 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2347
2348         ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2349         ath9k_cmn_reload_chainmask(ah);
2350
2351         return 0;
2352 }
2353
2354 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2355 {
2356         struct ath_softc *sc = hw->priv;
2357
2358         *tx_ant = sc->ant_tx;
2359         *rx_ant = sc->ant_rx;
2360         return 0;
2361 }
2362
2363 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2364                                 struct ieee80211_vif *vif,
2365                                 const u8 *mac_addr)
2366 {
2367         struct ath_softc *sc = hw->priv;
2368         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2369         set_bit(ATH_OP_SCANNING, &common->op_flags);
2370 }
2371
2372 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2373                                    struct ieee80211_vif *vif)
2374 {
2375         struct ath_softc *sc = hw->priv;
2376         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2377         clear_bit(ATH_OP_SCANNING, &common->op_flags);
2378 }
2379
2380 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2381
2382 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2383 {
2384         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2385
2386         if (sc->offchannel.roc_vif) {
2387                 ath_dbg(common, CHAN_CTX,
2388                         "%s: Aborting RoC\n", __func__);
2389
2390                 del_timer_sync(&sc->offchannel.timer);
2391                 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2392                         ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2393         }
2394
2395         if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2396                 ath_dbg(common, CHAN_CTX,
2397                         "%s: Aborting HW scan\n", __func__);
2398
2399                 del_timer_sync(&sc->offchannel.timer);
2400                 ath_scan_complete(sc, true);
2401         }
2402 }
2403
2404 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2405                          struct ieee80211_scan_request *hw_req)
2406 {
2407         struct cfg80211_scan_request *req = &hw_req->req;
2408         struct ath_softc *sc = hw->priv;
2409         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2410         int ret = 0;
2411
2412         mutex_lock(&sc->mutex);
2413
2414         if (WARN_ON(sc->offchannel.scan_req)) {
2415                 ret = -EBUSY;
2416                 goto out;
2417         }
2418
2419         ath9k_ps_wakeup(sc);
2420         set_bit(ATH_OP_SCANNING, &common->op_flags);
2421         sc->offchannel.scan_vif = vif;
2422         sc->offchannel.scan_req = req;
2423         sc->offchannel.scan_idx = 0;
2424
2425         ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2426                 vif->addr);
2427
2428         if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2429                 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2430                 ath_offchannel_next(sc);
2431         }
2432
2433 out:
2434         mutex_unlock(&sc->mutex);
2435
2436         return ret;
2437 }
2438
2439 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2440                                  struct ieee80211_vif *vif)
2441 {
2442         struct ath_softc *sc = hw->priv;
2443         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2444
2445         ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2446
2447         mutex_lock(&sc->mutex);
2448         del_timer_sync(&sc->offchannel.timer);
2449         ath_scan_complete(sc, true);
2450         mutex_unlock(&sc->mutex);
2451 }
2452
2453 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2454                                    struct ieee80211_vif *vif,
2455                                    struct ieee80211_channel *chan, int duration,
2456                                    enum ieee80211_roc_type type)
2457 {
2458         struct ath_softc *sc = hw->priv;
2459         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2460         int ret = 0;
2461
2462         mutex_lock(&sc->mutex);
2463
2464         if (WARN_ON(sc->offchannel.roc_vif)) {
2465                 ret = -EBUSY;
2466                 goto out;
2467         }
2468
2469         ath9k_ps_wakeup(sc);
2470         sc->offchannel.roc_vif = vif;
2471         sc->offchannel.roc_chan = chan;
2472         sc->offchannel.roc_duration = duration;
2473
2474         ath_dbg(common, CHAN_CTX,
2475                 "RoC request on vif: %pM, type: %d duration: %d\n",
2476                 vif->addr, type, duration);
2477
2478         if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2479                 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2480                 ath_offchannel_next(sc);
2481         }
2482
2483 out:
2484         mutex_unlock(&sc->mutex);
2485
2486         return ret;
2487 }
2488
2489 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2490 {
2491         struct ath_softc *sc = hw->priv;
2492         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2493
2494         mutex_lock(&sc->mutex);
2495
2496         ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2497         del_timer_sync(&sc->offchannel.timer);
2498
2499         if (sc->offchannel.roc_vif) {
2500                 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2501                         ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2502         }
2503
2504         mutex_unlock(&sc->mutex);
2505
2506         return 0;
2507 }
2508
2509 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2510                              struct ieee80211_chanctx_conf *conf)
2511 {
2512         struct ath_softc *sc = hw->priv;
2513         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2514         struct ath_chanctx *ctx, **ptr;
2515         int pos;
2516
2517         mutex_lock(&sc->mutex);
2518
2519         ath_for_each_chanctx(sc, ctx) {
2520                 if (ctx->assigned)
2521                         continue;
2522
2523                 ptr = (void *) conf->drv_priv;
2524                 *ptr = ctx;
2525                 ctx->assigned = true;
2526                 pos = ctx - &sc->chanctx[0];
2527                 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2528
2529                 ath_dbg(common, CHAN_CTX,
2530                         "Add channel context: %d MHz\n",
2531                         conf->def.chan->center_freq);
2532
2533                 ath_chanctx_set_channel(sc, ctx, &conf->def);
2534
2535                 mutex_unlock(&sc->mutex);
2536                 return 0;
2537         }
2538
2539         mutex_unlock(&sc->mutex);
2540         return -ENOSPC;
2541 }
2542
2543
2544 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2545                                  struct ieee80211_chanctx_conf *conf)
2546 {
2547         struct ath_softc *sc = hw->priv;
2548         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2549         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2550
2551         mutex_lock(&sc->mutex);
2552
2553         ath_dbg(common, CHAN_CTX,
2554                 "Remove channel context: %d MHz\n",
2555                 conf->def.chan->center_freq);
2556
2557         ctx->assigned = false;
2558         ctx->hw_queue_base = 0;
2559         ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2560
2561         mutex_unlock(&sc->mutex);
2562 }
2563
2564 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2565                                  struct ieee80211_chanctx_conf *conf,
2566                                  u32 changed)
2567 {
2568         struct ath_softc *sc = hw->priv;
2569         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2570         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2571
2572         mutex_lock(&sc->mutex);
2573         ath_dbg(common, CHAN_CTX,
2574                 "Change channel context: %d MHz\n",
2575                 conf->def.chan->center_freq);
2576         ath_chanctx_set_channel(sc, ctx, &conf->def);
2577         mutex_unlock(&sc->mutex);
2578 }
2579
2580 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2581                                     struct ieee80211_vif *vif,
2582                                     struct ieee80211_chanctx_conf *conf)
2583 {
2584         struct ath_softc *sc = hw->priv;
2585         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2586         struct ath_vif *avp = (void *)vif->drv_priv;
2587         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2588         int i;
2589
2590         ath9k_cancel_pending_offchannel(sc);
2591
2592         mutex_lock(&sc->mutex);
2593
2594         ath_dbg(common, CHAN_CTX,
2595                 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2596                 vif->addr, vif->type, vif->p2p,
2597                 conf->def.chan->center_freq);
2598
2599         avp->chanctx = ctx;
2600         ctx->nvifs_assigned++;
2601         list_add_tail(&avp->list, &ctx->vifs);
2602         ath9k_calculate_summary_state(sc, ctx);
2603         for (i = 0; i < IEEE80211_NUM_ACS; i++)
2604                 vif->hw_queue[i] = ctx->hw_queue_base + i;
2605
2606         mutex_unlock(&sc->mutex);
2607
2608         return 0;
2609 }
2610
2611 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2612                                        struct ieee80211_vif *vif,
2613                                        struct ieee80211_chanctx_conf *conf)
2614 {
2615         struct ath_softc *sc = hw->priv;
2616         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2617         struct ath_vif *avp = (void *)vif->drv_priv;
2618         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2619         int ac;
2620
2621         ath9k_cancel_pending_offchannel(sc);
2622
2623         mutex_lock(&sc->mutex);
2624
2625         ath_dbg(common, CHAN_CTX,
2626                 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2627                 vif->addr, vif->type, vif->p2p,
2628                 conf->def.chan->center_freq);
2629
2630         avp->chanctx = NULL;
2631         ctx->nvifs_assigned--;
2632         list_del(&avp->list);
2633         ath9k_calculate_summary_state(sc, ctx);
2634         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2635                 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2636
2637         mutex_unlock(&sc->mutex);
2638 }
2639
2640 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2641                                  struct ieee80211_vif *vif)
2642 {
2643         struct ath_softc *sc = hw->priv;
2644         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2645         struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2646         struct ath_beacon_config *cur_conf;
2647         struct ath_chanctx *go_ctx;
2648         unsigned long timeout;
2649         bool changed = false;
2650         u32 beacon_int;
2651
2652         if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2653                 return;
2654
2655         if (!avp->chanctx)
2656                 return;
2657
2658         mutex_lock(&sc->mutex);
2659
2660         spin_lock_bh(&sc->chan_lock);
2661         if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2662                 changed = true;
2663         spin_unlock_bh(&sc->chan_lock);
2664
2665         if (!changed)
2666                 goto out;
2667
2668         ath9k_cancel_pending_offchannel(sc);
2669
2670         go_ctx = ath_is_go_chanctx_present(sc);
2671
2672         if (go_ctx) {
2673                 /*
2674                  * Wait till the GO interface gets a chance
2675                  * to send out an NoA.
2676                  */
2677                 spin_lock_bh(&sc->chan_lock);
2678                 sc->sched.mgd_prepare_tx = true;
2679                 cur_conf = &go_ctx->beacon;
2680                 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2681                 spin_unlock_bh(&sc->chan_lock);
2682
2683                 timeout = usecs_to_jiffies(beacon_int * 2);
2684                 init_completion(&sc->go_beacon);
2685
2686                 mutex_unlock(&sc->mutex);
2687
2688                 if (wait_for_completion_timeout(&sc->go_beacon,
2689                                                 timeout) == 0) {
2690                         ath_dbg(common, CHAN_CTX,
2691                                 "Failed to send new NoA\n");
2692
2693                         spin_lock_bh(&sc->chan_lock);
2694                         sc->sched.mgd_prepare_tx = false;
2695                         spin_unlock_bh(&sc->chan_lock);
2696                 }
2697
2698                 mutex_lock(&sc->mutex);
2699         }
2700
2701         ath_dbg(common, CHAN_CTX,
2702                 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2703                 __func__, vif->addr);
2704
2705         spin_lock_bh(&sc->chan_lock);
2706         sc->next_chan = avp->chanctx;
2707         sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2708         spin_unlock_bh(&sc->chan_lock);
2709
2710         ath_chanctx_set_next(sc, true);
2711 out:
2712         mutex_unlock(&sc->mutex);
2713 }
2714
2715 void ath9k_fill_chanctx_ops(void)
2716 {
2717         if (!ath9k_is_chanctx_enabled())
2718                 return;
2719
2720         ath9k_ops.hw_scan                  = ath9k_hw_scan;
2721         ath9k_ops.cancel_hw_scan           = ath9k_cancel_hw_scan;
2722         ath9k_ops.remain_on_channel        = ath9k_remain_on_channel;
2723         ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2724         ath9k_ops.add_chanctx              = ath9k_add_chanctx;
2725         ath9k_ops.remove_chanctx           = ath9k_remove_chanctx;
2726         ath9k_ops.change_chanctx           = ath9k_change_chanctx;
2727         ath9k_ops.assign_vif_chanctx       = ath9k_assign_vif_chanctx;
2728         ath9k_ops.unassign_vif_chanctx     = ath9k_unassign_vif_chanctx;
2729         ath9k_ops.mgd_prepare_tx           = ath9k_mgd_prepare_tx;
2730 }
2731
2732 #endif
2733
2734 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2735                              int *dbm)
2736 {
2737         struct ath_softc *sc = hw->priv;
2738         struct ath_vif *avp = (void *)vif->drv_priv;
2739
2740         mutex_lock(&sc->mutex);
2741         if (avp->chanctx)
2742                 *dbm = avp->chanctx->cur_txpower;
2743         else
2744                 *dbm = sc->cur_chan->cur_txpower;
2745         mutex_unlock(&sc->mutex);
2746
2747         *dbm /= 2;
2748
2749         return 0;
2750 }
2751
2752 struct ieee80211_ops ath9k_ops = {
2753         .tx                 = ath9k_tx,
2754         .start              = ath9k_start,
2755         .stop               = ath9k_stop,
2756         .add_interface      = ath9k_add_interface,
2757         .change_interface   = ath9k_change_interface,
2758         .remove_interface   = ath9k_remove_interface,
2759         .config             = ath9k_config,
2760         .configure_filter   = ath9k_configure_filter,
2761         .sta_state          = ath9k_sta_state,
2762         .sta_notify         = ath9k_sta_notify,
2763         .conf_tx            = ath9k_conf_tx,
2764         .bss_info_changed   = ath9k_bss_info_changed,
2765         .set_key            = ath9k_set_key,
2766         .get_tsf            = ath9k_get_tsf,
2767         .set_tsf            = ath9k_set_tsf,
2768         .reset_tsf          = ath9k_reset_tsf,
2769         .ampdu_action       = ath9k_ampdu_action,
2770         .get_survey         = ath9k_get_survey,
2771         .rfkill_poll        = ath9k_rfkill_poll_state,
2772         .set_coverage_class = ath9k_set_coverage_class,
2773         .flush              = ath9k_flush,
2774         .tx_frames_pending  = ath9k_tx_frames_pending,
2775         .tx_last_beacon     = ath9k_tx_last_beacon,
2776         .release_buffered_frames = ath9k_release_buffered_frames,
2777         .get_stats          = ath9k_get_stats,
2778         .set_antenna        = ath9k_set_antenna,
2779         .get_antenna        = ath9k_get_antenna,
2780
2781 #ifdef CONFIG_ATH9K_WOW
2782         .suspend            = ath9k_suspend,
2783         .resume             = ath9k_resume,
2784         .set_wakeup         = ath9k_set_wakeup,
2785 #endif
2786
2787 #ifdef CONFIG_ATH9K_DEBUGFS
2788         .get_et_sset_count  = ath9k_get_et_sset_count,
2789         .get_et_stats       = ath9k_get_et_stats,
2790         .get_et_strings     = ath9k_get_et_strings,
2791 #endif
2792
2793 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2794         .sta_add_debugfs    = ath9k_sta_add_debugfs,
2795 #endif
2796         .sw_scan_start      = ath9k_sw_scan_start,
2797         .sw_scan_complete   = ath9k_sw_scan_complete,
2798         .get_txpower        = ath9k_get_txpower,
2799         .wake_tx_queue      = ath9k_wake_tx_queue,
2800 };