2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
24 #include <linux/of_net.h>
25 #include <linux/relay.h>
26 #include <net/ieee80211_radiotap.h>
30 struct ath9k_eeprom_ctx {
31 struct completion complete;
35 static char *dev_info = "ath9k";
37 MODULE_AUTHOR("Atheros Communications");
38 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
39 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
40 MODULE_LICENSE("Dual BSD/GPL");
42 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
43 module_param_named(debug, ath9k_debug, uint, 0);
44 MODULE_PARM_DESC(debug, "Debugging mask");
46 int ath9k_modparam_nohwcrypt;
47 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
48 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
51 module_param_named(blink, ath9k_led_blink, int, 0444);
52 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
54 static int ath9k_led_active_high = -1;
55 module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
56 MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
58 static int ath9k_btcoex_enable;
59 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
60 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
62 static int ath9k_bt_ant_diversity;
63 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
64 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
66 static int ath9k_ps_enable;
67 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
68 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
70 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
72 int ath9k_use_chanctx;
73 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
74 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
76 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
78 bool is_ath9k_unloaded;
80 #ifdef CONFIG_MAC80211_LEDS
81 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
82 { .throughput = 0 * 1024, .blink_time = 334 },
83 { .throughput = 1 * 1024, .blink_time = 260 },
84 { .throughput = 5 * 1024, .blink_time = 220 },
85 { .throughput = 10 * 1024, .blink_time = 190 },
86 { .throughput = 20 * 1024, .blink_time = 170 },
87 { .throughput = 50 * 1024, .blink_time = 150 },
88 { .throughput = 70 * 1024, .blink_time = 130 },
89 { .throughput = 100 * 1024, .blink_time = 110 },
90 { .throughput = 200 * 1024, .blink_time = 80 },
91 { .throughput = 300 * 1024, .blink_time = 50 },
95 static void ath9k_deinit_softc(struct ath_softc *sc);
97 static void ath9k_op_ps_wakeup(struct ath_common *common)
99 ath9k_ps_wakeup((struct ath_softc *) common->priv);
102 static void ath9k_op_ps_restore(struct ath_common *common)
104 ath9k_ps_restore((struct ath_softc *) common->priv);
107 static const struct ath_ps_ops ath9k_ps_ops = {
108 .wakeup = ath9k_op_ps_wakeup,
109 .restore = ath9k_op_ps_restore,
113 * Read and write, they both share the same lock. We do this to serialize
114 * reads and writes on Atheros 802.11n PCI devices only. This is required
115 * as the FIFO on these devices can only accept sanely 2 requests.
118 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
120 struct ath_hw *ah = (struct ath_hw *) hw_priv;
121 struct ath_common *common = ath9k_hw_common(ah);
122 struct ath_softc *sc = (struct ath_softc *) common->priv;
124 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
126 spin_lock_irqsave(&sc->sc_serial_rw, flags);
127 iowrite32(val, sc->mem + reg_offset);
128 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
130 iowrite32(val, sc->mem + reg_offset);
133 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
135 struct ath_hw *ah = (struct ath_hw *) hw_priv;
136 struct ath_common *common = ath9k_hw_common(ah);
137 struct ath_softc *sc = (struct ath_softc *) common->priv;
140 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
142 spin_lock_irqsave(&sc->sc_serial_rw, flags);
143 val = ioread32(sc->mem + reg_offset);
144 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
146 val = ioread32(sc->mem + reg_offset);
150 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
155 for (i = 0; i < count; i++)
156 val[i] = ath9k_ioread32(hw_priv, addr[i]);
160 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
165 val = ioread32(sc->mem + reg_offset);
168 iowrite32(val, sc->mem + reg_offset);
173 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
175 struct ath_hw *ah = (struct ath_hw *) hw_priv;
176 struct ath_common *common = ath9k_hw_common(ah);
177 struct ath_softc *sc = (struct ath_softc *) common->priv;
181 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
182 spin_lock_irqsave(&sc->sc_serial_rw, flags);
183 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
184 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
186 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
191 /**************************/
193 /**************************/
195 static void ath9k_reg_notifier(struct wiphy *wiphy,
196 struct regulatory_request *request)
198 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
199 struct ath_softc *sc = hw->priv;
200 struct ath_hw *ah = sc->sc_ah;
201 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
203 ath_reg_notifier_apply(wiphy, request, reg);
209 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
211 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
212 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
213 sc->cur_chan->txpower,
214 &sc->cur_chan->cur_txpower);
215 /* synchronize DFS detector if regulatory domain changed */
216 if (sc->dfs_detector != NULL)
217 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
218 request->dfs_region);
219 ath9k_ps_restore(sc);
223 * This function will allocate both the DMA descriptor structure, and the
224 * buffers it contains. These are used to contain the descriptors used
227 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
228 struct list_head *head, const char *name,
229 int nbuf, int ndesc, bool is_tx)
231 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
233 int i, bsize, desc_len;
235 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
238 INIT_LIST_HEAD(head);
241 desc_len = sc->sc_ah->caps.tx_desc_len;
243 desc_len = sizeof(struct ath_desc);
245 /* ath_desc must be a multiple of DWORDs */
246 if ((desc_len % 4) != 0) {
247 ath_err(common, "ath_desc not DWORD aligned\n");
248 BUG_ON((desc_len % 4) != 0);
252 dd->dd_desc_len = desc_len * nbuf * ndesc;
255 * Need additional DMA memory because we can't use
256 * descriptors that cross the 4K page boundary. Assume
257 * one skipped descriptor per 4K page.
259 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
261 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
264 while (ndesc_skipped) {
265 dma_len = ndesc_skipped * desc_len;
266 dd->dd_desc_len += dma_len;
268 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
272 /* allocate descriptors */
273 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
274 &dd->dd_desc_paddr, GFP_KERNEL);
278 ds = (u8 *) dd->dd_desc;
279 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
280 name, ds, (u32) dd->dd_desc_len,
281 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
283 /* allocate buffers */
287 bsize = sizeof(struct ath_buf) * nbuf;
288 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
292 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
294 bf->bf_daddr = DS2PHYS(dd, ds);
296 if (!(sc->sc_ah->caps.hw_caps &
297 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
299 * Skip descriptor addresses which can cause 4KB
300 * boundary crossing (addr + length) with a 32 dword
303 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
304 BUG_ON((caddr_t) bf->bf_desc >=
305 ((caddr_t) dd->dd_desc +
308 ds += (desc_len * ndesc);
310 bf->bf_daddr = DS2PHYS(dd, ds);
313 list_add_tail(&bf->list, head);
316 struct ath_rxbuf *bf;
318 bsize = sizeof(struct ath_rxbuf) * nbuf;
319 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
323 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
325 bf->bf_daddr = DS2PHYS(dd, ds);
327 if (!(sc->sc_ah->caps.hw_caps &
328 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
330 * Skip descriptor addresses which can cause 4KB
331 * boundary crossing (addr + length) with a 32 dword
334 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
335 BUG_ON((caddr_t) bf->bf_desc >=
336 ((caddr_t) dd->dd_desc +
339 ds += (desc_len * ndesc);
341 bf->bf_daddr = DS2PHYS(dd, ds);
344 list_add_tail(&bf->list, head);
350 static int ath9k_init_queues(struct ath_softc *sc)
354 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
355 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
358 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
360 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
361 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
362 sc->tx.txq_map[i]->mac80211_qnum = i;
367 static void ath9k_init_misc(struct ath_softc *sc)
369 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
372 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
374 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
375 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
376 sc->beacon.slottime = 9;
378 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
379 sc->beacon.bslot[i] = NULL;
381 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
382 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
384 sc->spec_priv.ah = sc->sc_ah;
385 sc->spec_priv.spec_config.enabled = 0;
386 sc->spec_priv.spec_config.short_repeat = true;
387 sc->spec_priv.spec_config.count = 8;
388 sc->spec_priv.spec_config.endless = false;
389 sc->spec_priv.spec_config.period = 0xFF;
390 sc->spec_priv.spec_config.fft_period = 0xF;
393 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
395 struct ath_hw *ah = sc->sc_ah;
396 struct ath9k_hw_capabilities *pCap = &ah->caps;
397 struct ath_common *common = ath9k_hw_common(ah);
399 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
402 if (common->bus_ops->ath_bus_type != ATH_PCI)
405 if (sc->driver_data & (ATH9K_PCI_CUS198 |
407 ah->config.xlna_gpio = 9;
408 ah->config.xatten_margin_cfg = true;
409 ah->config.alt_mingainidx = true;
410 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
411 sc->ant_comb.low_rssi_thresh = 20;
412 sc->ant_comb.fast_div_bias = 3;
414 ath_info(common, "Set parameters for %s\n",
415 (sc->driver_data & ATH9K_PCI_CUS198) ?
416 "CUS198" : "CUS230");
419 if (sc->driver_data & ATH9K_PCI_CUS217)
420 ath_info(common, "CUS217 card detected\n");
422 if (sc->driver_data & ATH9K_PCI_CUS252)
423 ath_info(common, "CUS252 card detected\n");
425 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
426 ath_info(common, "WB335 1-ANT card detected\n");
428 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
429 ath_info(common, "WB335 2-ANT card detected\n");
431 if (sc->driver_data & ATH9K_PCI_KILLER)
432 ath_info(common, "Killer Wireless card detected\n");
435 * Some WB335 cards do not support antenna diversity. Since
436 * we use a hardcoded value for AR9565 instead of using the
437 * EEPROM/OTP data, remove the combining feature from
438 * the HW capabilities bitmap.
440 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
441 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
442 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
445 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
446 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
447 ath_info(common, "Set BT/WLAN RX diversity capability\n");
450 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
451 ah->config.pcie_waen = 0x0040473b;
452 ath_info(common, "Enable WAR for ASPM D3/L1\n");
456 * The default value of pll_pwrsave is 1.
457 * For certain AR9485 cards, it is set to 0.
458 * For AR9462, AR9565 it's set to 7.
460 ah->config.pll_pwrsave = 1;
462 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
463 ah->config.pll_pwrsave = 0;
464 ath_info(common, "Disable PLL PowerSave\n");
467 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
468 ah->config.led_active_high = true;
471 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
474 struct ath9k_eeprom_ctx *ec = ctx;
477 ec->ah->eeprom_blob = eeprom_blob;
479 complete(&ec->complete);
482 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
484 struct ath9k_eeprom_ctx ec;
485 struct ath_hw *ah = sc->sc_ah;
488 /* try to load the EEPROM content asynchronously */
489 init_completion(&ec.complete);
492 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
493 &ec, ath9k_eeprom_request_cb);
495 ath_err(ath9k_hw_common(ah),
496 "EEPROM request failed\n");
500 wait_for_completion(&ec.complete);
502 if (!ah->eeprom_blob) {
503 ath_err(ath9k_hw_common(ah),
504 "Unable to load EEPROM file %s\n", name);
511 static void ath9k_eeprom_release(struct ath_softc *sc)
513 release_firmware(sc->sc_ah->eeprom_blob);
516 static int ath9k_init_platform(struct ath_softc *sc)
518 struct ath9k_platform_data *pdata = sc->dev->platform_data;
519 struct ath_hw *ah = sc->sc_ah;
520 struct ath_common *common = ath9k_hw_common(ah);
526 if (!pdata->use_eeprom) {
527 ah->ah_flags &= ~AH_USE_EEPROM;
528 ah->gpio_mask = pdata->gpio_mask;
529 ah->gpio_val = pdata->gpio_val;
530 ah->led_pin = pdata->led_pin;
531 ah->is_clk_25mhz = pdata->is_clk_25mhz;
532 ah->get_mac_revision = pdata->get_mac_revision;
533 ah->external_reset = pdata->external_reset;
534 ah->disable_2ghz = pdata->disable_2ghz;
535 ah->disable_5ghz = pdata->disable_5ghz;
537 if (!pdata->endian_check)
538 ah->ah_flags |= AH_NO_EEP_SWAP;
541 if (pdata->eeprom_name) {
542 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
547 if (pdata->led_active_high)
548 ah->config.led_active_high = true;
550 if (pdata->tx_gain_buffalo)
551 ah->config.tx_gain_buffalo = true;
554 ether_addr_copy(common->macaddr, pdata->macaddr);
559 static int ath9k_of_init(struct ath_softc *sc)
561 struct device_node *np = sc->dev->of_node;
562 struct ath_hw *ah = sc->sc_ah;
563 struct ath_common *common = ath9k_hw_common(ah);
564 enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
566 char eeprom_name[100];
569 if (!of_device_is_available(np))
572 ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
574 if (of_property_read_bool(np, "qca,no-eeprom")) {
575 /* ath9k-eeprom-<bus>-<id>.bin */
576 scnprintf(eeprom_name, sizeof(eeprom_name),
577 "ath9k-eeprom-%s-%s.bin",
578 ath_bus_type_to_string(bus_type), dev_name(ah->dev));
580 ret = ath9k_eeprom_request(sc, eeprom_name);
584 ah->ah_flags &= ~AH_USE_EEPROM;
585 ah->ah_flags |= AH_NO_EEP_SWAP;
588 mac = of_get_mac_address(np);
590 ether_addr_copy(common->macaddr, mac);
595 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
596 const struct ath_bus_ops *bus_ops)
598 struct ath_hw *ah = NULL;
599 struct ath9k_hw_capabilities *pCap;
600 struct ath_common *common;
604 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
610 ah->hw_version.devid = devid;
611 ah->ah_flags |= AH_USE_EEPROM;
613 ah->reg_ops.read = ath9k_ioread32;
614 ah->reg_ops.multi_read = ath9k_multi_ioread32;
615 ah->reg_ops.write = ath9k_iowrite32;
616 ah->reg_ops.rmw = ath9k_reg_rmw;
619 common = ath9k_hw_common(ah);
621 /* Will be cleared in ath9k_start() */
622 set_bit(ATH_OP_INVALID, &common->op_flags);
623 sc->airtime_flags = (AIRTIME_USE_TX | AIRTIME_USE_RX |
624 AIRTIME_USE_NEW_QUEUES);
627 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
628 sc->tx99_power = MAX_RATE_POWER + 1;
629 init_waitqueue_head(&sc->tx_wait);
630 sc->cur_chan = &sc->chanctx[0];
631 if (!ath9k_is_chanctx_enabled())
632 sc->cur_chan->hw_queue_base = 0;
634 common->ops = &ah->reg_ops;
635 common->bus_ops = bus_ops;
636 common->ps_ops = &ath9k_ps_ops;
640 common->debug_mask = ath9k_debug;
641 common->btcoex_enabled = ath9k_btcoex_enable == 1;
642 common->disable_ani = false;
647 ath9k_init_pcoem_platform(sc);
649 ret = ath9k_init_platform(sc);
653 ret = ath9k_of_init(sc);
657 if (ath9k_led_active_high != -1)
658 ah->config.led_active_high = ath9k_led_active_high == 1;
661 * Enable WLAN/BT RX Antenna diversity only when:
663 * - BTCOEX is disabled.
664 * - the user manually requests the feature.
665 * - the HW cap is set using the platform data.
667 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
668 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
669 common->bt_ant_diversity = 1;
671 spin_lock_init(&common->cc_lock);
672 spin_lock_init(&sc->intr_lock);
673 spin_lock_init(&sc->sc_serial_rw);
674 spin_lock_init(&sc->sc_pm_lock);
675 spin_lock_init(&sc->chan_lock);
676 mutex_init(&sc->mutex);
677 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
678 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
681 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
682 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
683 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
684 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
685 INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work);
687 ath9k_init_channel_context(sc);
690 * Cache line size is used to size and align various
691 * structures used to communicate with the hardware.
693 ath_read_cachesize(common, &csz);
694 common->cachelsz = csz << 2; /* convert to bytes */
696 /* Initializes the hardware for all supported chipsets */
697 ret = ath9k_hw_init(ah);
701 ret = ath9k_init_queues(sc);
705 ret = ath9k_init_btcoex(sc);
709 ret = ath9k_cmn_init_channels_rates(common);
713 ret = ath9k_init_p2p(sc);
717 ath9k_cmn_init_crypto(sc->sc_ah);
719 ath_chanctx_init(sc);
720 ath9k_offchannel_init(sc);
722 if (common->bus_ops->aspm_init)
723 common->bus_ops->aspm_init(common);
728 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
729 if (ATH_TXQ_SETUP(sc, i))
730 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
734 ath9k_eeprom_release(sc);
735 dev_kfree_skb_any(sc->tx99_skb);
739 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
741 struct ieee80211_supported_band *sband;
742 struct ieee80211_channel *chan;
743 struct ath_hw *ah = sc->sc_ah;
744 struct ath_common *common = ath9k_hw_common(ah);
745 struct cfg80211_chan_def chandef;
748 sband = &common->sbands[band];
749 for (i = 0; i < sband->n_channels; i++) {
750 chan = &sband->channels[i];
751 ah->curchan = &ah->channels[chan->hw_value];
752 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
753 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
754 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
758 static void ath9k_init_txpower_limits(struct ath_softc *sc)
760 struct ath_hw *ah = sc->sc_ah;
761 struct ath9k_channel *curchan = ah->curchan;
763 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
764 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
765 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
766 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
768 ah->curchan = curchan;
771 static const struct ieee80211_iface_limit if_limits[] = {
772 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
774 #ifdef CONFIG_MAC80211_MESH
775 BIT(NL80211_IFTYPE_MESH_POINT) |
777 BIT(NL80211_IFTYPE_AP) },
778 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
779 BIT(NL80211_IFTYPE_P2P_GO) },
782 #ifdef CONFIG_WIRELESS_WDS
783 static const struct ieee80211_iface_limit wds_limits[] = {
784 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) },
788 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
790 static const struct ieee80211_iface_limit if_limits_multi[] = {
791 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
792 BIT(NL80211_IFTYPE_AP) |
793 BIT(NL80211_IFTYPE_P2P_CLIENT) |
794 BIT(NL80211_IFTYPE_P2P_GO) },
795 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
796 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
799 static const struct ieee80211_iface_combination if_comb_multi[] = {
801 .limits = if_limits_multi,
802 .n_limits = ARRAY_SIZE(if_limits_multi),
804 .num_different_channels = 2,
805 .beacon_int_infra_match = true,
809 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
811 static const struct ieee80211_iface_combination if_comb[] = {
814 .n_limits = ARRAY_SIZE(if_limits),
815 .max_interfaces = 2048,
816 .num_different_channels = 1,
817 .beacon_int_infra_match = true,
818 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
819 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
820 BIT(NL80211_CHAN_WIDTH_20) |
821 BIT(NL80211_CHAN_WIDTH_40),
824 #ifdef CONFIG_WIRELESS_WDS
826 .limits = wds_limits,
827 .n_limits = ARRAY_SIZE(wds_limits),
828 .max_interfaces = 2048,
829 .num_different_channels = 1,
830 .beacon_int_infra_match = true,
835 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
836 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
838 struct ath_hw *ah = sc->sc_ah;
839 struct ath_common *common = ath9k_hw_common(ah);
841 if (!ath9k_is_chanctx_enabled())
844 ieee80211_hw_set(hw, QUEUE_CONTROL);
845 hw->queues = ATH9K_NUM_TX_QUEUES;
846 hw->offchannel_tx_hw_queue = hw->queues - 1;
847 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
848 hw->wiphy->iface_combinations = if_comb_multi;
849 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
850 hw->wiphy->max_scan_ssids = 255;
851 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
852 hw->wiphy->max_remain_on_channel_duration = 10000;
853 hw->chanctx_data_size = sizeof(void *);
854 hw->extra_beacon_tailroom =
855 sizeof(struct ieee80211_p2p_noa_attr) + 9;
857 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
859 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
861 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
863 struct ath_hw *ah = sc->sc_ah;
864 struct ath_common *common = ath9k_hw_common(ah);
866 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
867 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
868 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
869 ieee80211_hw_set(hw, SPECTRUM_MGMT);
870 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
871 ieee80211_hw_set(hw, SIGNAL_DBM);
872 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
873 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
874 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
875 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
878 ieee80211_hw_set(hw, SUPPORTS_PS);
880 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
881 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
883 if (AR_SREV_9280_20_OR_LATER(ah))
884 hw->radiotap_mcs_details |=
885 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
888 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
889 ieee80211_hw_set(hw, MFP_CAPABLE);
891 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
892 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
893 NL80211_FEATURE_P2P_GO_CTWIN;
895 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {
896 hw->wiphy->interface_modes =
897 BIT(NL80211_IFTYPE_P2P_GO) |
898 BIT(NL80211_IFTYPE_P2P_CLIENT) |
899 BIT(NL80211_IFTYPE_AP) |
900 BIT(NL80211_IFTYPE_STATION) |
901 BIT(NL80211_IFTYPE_ADHOC) |
902 BIT(NL80211_IFTYPE_MESH_POINT) |
903 #ifdef CONFIG_WIRELESS_WDS
904 BIT(NL80211_IFTYPE_WDS) |
906 BIT(NL80211_IFTYPE_OCB);
908 if (ath9k_is_chanctx_enabled())
909 hw->wiphy->interface_modes |=
910 BIT(NL80211_IFTYPE_P2P_DEVICE);
912 hw->wiphy->iface_combinations = if_comb;
913 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
916 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
918 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
919 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
920 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
921 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
922 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
923 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
927 hw->max_listen_interval = 10;
928 hw->max_rate_tries = 10;
929 hw->sta_data_size = sizeof(struct ath_node);
930 hw->vif_data_size = sizeof(struct ath_vif);
931 hw->txq_data_size = sizeof(struct ath_atx_tid);
932 hw->extra_tx_headroom = 4;
934 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
935 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
937 /* single chain devices with rx diversity */
938 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
939 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
941 sc->ant_rx = hw->wiphy->available_antennas_rx;
942 sc->ant_tx = hw->wiphy->available_antennas_tx;
944 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
945 hw->wiphy->bands[NL80211_BAND_2GHZ] =
946 &common->sbands[NL80211_BAND_2GHZ];
947 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
948 hw->wiphy->bands[NL80211_BAND_5GHZ] =
949 &common->sbands[NL80211_BAND_5GHZ];
951 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
952 ath9k_set_mcc_capab(sc, hw);
955 ath9k_cmn_reload_chainmask(ah);
957 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
959 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
962 int ath9k_init_device(u16 devid, struct ath_softc *sc,
963 const struct ath_bus_ops *bus_ops)
965 struct ieee80211_hw *hw = sc->hw;
966 struct ath_common *common;
969 struct ath_regulatory *reg;
971 /* Bring up device */
972 error = ath9k_init_softc(devid, sc, bus_ops);
977 common = ath9k_hw_common(ah);
978 ath9k_set_hw_capab(sc, hw);
980 /* Initialize regulatory */
981 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
986 reg = &common->regulatory;
989 error = ath_tx_init(sc, ATH_TXBUF);
994 error = ath_rx_init(sc, ATH_RXBUF);
998 ath9k_init_txpower_limits(sc);
1000 #ifdef CONFIG_MAC80211_LEDS
1001 /* must be initialized before ieee80211_register_hw */
1002 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1003 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1004 ARRAY_SIZE(ath9k_tpt_blink));
1007 /* Register with mac80211 */
1008 error = ieee80211_register_hw(hw);
1012 error = ath9k_init_debug(ah);
1014 ath_err(common, "Unable to create debugfs files\n");
1018 /* Handle world regulatory */
1019 if (!ath_is_world_regd(reg)) {
1020 error = regulatory_hint(hw->wiphy, reg->alpha2);
1026 ath_start_rfkill_poll(sc);
1031 ath9k_deinit_debug(sc);
1033 ieee80211_unregister_hw(hw);
1037 ath9k_deinit_softc(sc);
1041 /*****************************/
1042 /* De-Initialization */
1043 /*****************************/
1045 static void ath9k_deinit_softc(struct ath_softc *sc)
1049 ath9k_deinit_p2p(sc);
1050 ath9k_deinit_btcoex(sc);
1052 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1053 if (ATH_TXQ_SETUP(sc, i))
1054 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1056 del_timer_sync(&sc->sleep_timer);
1057 ath9k_hw_deinit(sc->sc_ah);
1058 if (sc->dfs_detector != NULL)
1059 sc->dfs_detector->exit(sc->dfs_detector);
1061 ath9k_eeprom_release(sc);
1064 void ath9k_deinit_device(struct ath_softc *sc)
1066 struct ieee80211_hw *hw = sc->hw;
1068 ath9k_ps_wakeup(sc);
1070 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1071 ath_deinit_leds(sc);
1073 ath9k_ps_restore(sc);
1075 ath9k_deinit_debug(sc);
1076 ath9k_deinit_wow(hw);
1077 ieee80211_unregister_hw(hw);
1079 ath9k_deinit_softc(sc);
1082 /************************/
1084 /************************/
1086 static int __init ath9k_init(void)
1090 error = ath_pci_init();
1092 pr_err("No PCI devices found, driver not installed\n");
1097 error = ath_ahb_init();
1110 module_init(ath9k_init);
1112 static void __exit ath9k_exit(void)
1114 is_ath9k_unloaded = true;
1117 pr_info("%s: Driver unloaded\n", dev_info);
1119 module_exit(ath9k_exit);