drivers/net/wireless/ath/ath9k/eeprom_4k.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9002_phy.h"
  20
  21 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  22 {
  23         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  24 }
  25
  26 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  27 {
  28         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  29 }
  30
  31 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  32
  33 static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  34 {
  35         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  36         int addr, eep_start_loc = 64;
  37
  38         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  39                 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data))
  40                         return false;
  41                 eep_data++;
  42         }
  43
  44         return true;
  45 }
  46
  47 static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
  48 {
  49         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  50
  51         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
  52
  53         return true;
  54 }
  55
  56 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  57 {
  58         struct ath_common *common = ath9k_hw_common(ah);
  59
  60         if (!ath9k_hw_use_flash(ah)) {
  61                 ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n");
  62         }
  63
  64         if (common->bus_ops->ath_bus_type == ATH_USB)
  65                 return __ath9k_hw_usb_4k_fill_eeprom(ah);
  66         else
  67                 return __ath9k_hw_4k_fill_eeprom(ah);
  68 }
  69
  70 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
  71 static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size,
  72                                       struct modal_eep_4k_header *modal_hdr)
  73 {
  74         PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
  75         PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
  76         PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
  77         PR_EEP("Switch Settle", modal_hdr->switchSettling);
  78         PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
  79         PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
  80         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
  81         PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
  82         PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
  83         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
  84         PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
  85         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
  86         PR_EEP("CCA Threshold)", modal_hdr->thresh62);
  87         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
  88         PR_EEP("xpdGain", modal_hdr->xpdGain);
  89         PR_EEP("External PD", modal_hdr->xpd);
  90         PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
  91         PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
  92         PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
  93         PR_EEP("O/D Bias Version", modal_hdr->version);
  94         PR_EEP("CCK OutputBias", modal_hdr->ob_0);
  95         PR_EEP("BPSK OutputBias", modal_hdr->ob_1);
  96         PR_EEP("QPSK OutputBias", modal_hdr->ob_2);
  97         PR_EEP("16QAM OutputBias", modal_hdr->ob_3);
  98         PR_EEP("64QAM OutputBias", modal_hdr->ob_4);
  99         PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0);
 100         PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1);
 101         PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2);
 102         PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3);
 103         PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4);
 104         PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0);
 105         PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1);
 106         PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2);
 107         PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3);
 108         PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4);
 109         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
 110         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
 111         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
 112         PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
 113         PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
 114         PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
 115         PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
 116         PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
 117         PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
 118         PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1);
 119         PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2);
 120         PR_EEP("TX Diversity", modal_hdr->tx_diversity);
 121
 122         return len;
 123 }
 124
 125 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 126                                        u8 *buf, u32 len, u32 size)
 127 {
 128         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 129         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 130
 131         if (!dump_base_hdr) {
 132                 len += scnprintf(buf + len, size - len,
 133                                  "%20s :\n", "2GHz modal Header");
 134                 len = ath9k_dump_4k_modal_eeprom(buf, len, size,
 135                                                  &eep->modalHeader);
 136                 goto out;
 137         }
 138
 139         PR_EEP("Major Version", pBase->version >> 12);
 140         PR_EEP("Minor Version", pBase->version & 0xFFF);
 141         PR_EEP("Checksum", pBase->checksum);
 142         PR_EEP("Length", pBase->length);
 143         PR_EEP("RegDomain1", pBase->regDmn[0]);
 144         PR_EEP("RegDomain2", pBase->regDmn[1]);
 145         PR_EEP("TX Mask", pBase->txMask);
 146         PR_EEP("RX Mask", pBase->rxMask);
 147         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
 148         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
 149         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
 150                                         AR5416_OPFLAGS_N_2G_HT20));
 151         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
 152                                         AR5416_OPFLAGS_N_2G_HT40));
 153         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
 154                                         AR5416_OPFLAGS_N_5G_HT20));
 155         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
 156                                         AR5416_OPFLAGS_N_5G_HT40));
 157         PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
 158         PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
 159         PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
 160         PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
 161         PR_EEP("TX Gain type", pBase->txGainType);
 162
 163         len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
 164                          pBase->macAddr);
 165
 166 out:
 167         if (len > size)
 168                 len = size;
 169
 170         return len;
 171 }
 172 #else
 173 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 174                                        u8 *buf, u32 len, u32 size)
 175 {
 176         return 0;
 177 }
 178 #endif
 179
 180 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 181 {
 182         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 183         u32 el;
 184         bool need_swap;
 185         int i, err;
 186
 187         err = ath9k_hw_nvram_swap_data(ah, &need_swap, SIZE_EEPROM_4K);
 188         if (err)
 189                 return err;
 190
 191         if (need_swap)
 192                 el = swab16(eep->baseEepHeader.length);
 193         else
 194                 el = eep->baseEepHeader.length;
 195
 196         el = min(el / sizeof(u16), SIZE_EEPROM_4K);
 197         if (!ath9k_hw_nvram_validate_checksum(ah, el))
 198                 return -EINVAL;
 199
 200         if (need_swap) {
 201                 u32 integer;
 202                 u16 word;
 203
 204                 word = swab16(eep->baseEepHeader.length);
 205                 eep->baseEepHeader.length = word;
 206
 207                 word = swab16(eep->baseEepHeader.checksum);
 208                 eep->baseEepHeader.checksum = word;
 209
 210                 word = swab16(eep->baseEepHeader.version);
 211                 eep->baseEepHeader.version = word;
 212
 213                 word = swab16(eep->baseEepHeader.regDmn[0]);
 214                 eep->baseEepHeader.regDmn[0] = word;
 215
 216                 word = swab16(eep->baseEepHeader.regDmn[1]);
 217                 eep->baseEepHeader.regDmn[1] = word;
 218
 219                 word = swab16(eep->baseEepHeader.rfSilent);
 220                 eep->baseEepHeader.rfSilent = word;
 221
 222                 word = swab16(eep->baseEepHeader.blueToothOptions);
 223                 eep->baseEepHeader.blueToothOptions = word;
 224
 225                 word = swab16(eep->baseEepHeader.deviceCap);
 226                 eep->baseEepHeader.deviceCap = word;
 227
 228                 integer = swab32(eep->modalHeader.antCtrlCommon);
 229                 eep->modalHeader.antCtrlCommon = integer;
 230
 231                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 232                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 233                         eep->modalHeader.antCtrlChain[i] = integer;
 234                 }
 235
 236                 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 237                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 238                         eep->modalHeader.spurChans[i].spurChan = word;
 239                 }
 240         }
 241
 242         if (!ath9k_hw_nvram_check_version(ah, AR5416_EEP_VER,
 243             AR5416_EEP_NO_BACK_VER))
 244                 return -EINVAL;
 245
 246         return 0;
 247 }
 248
 249 #undef SIZE_EEPROM_4K
 250
 251 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 252                                   enum eeprom_param param)
 253 {
 254         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 255         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 256         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 257         u16 ver_minor;
 258
 259         ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 260
 261         switch (param) {
 262         case EEP_NFTHRESH_2:
 263                 return pModal->noiseFloorThreshCh[0];
 264         case EEP_MAC_LSW:
 265                 return get_unaligned_be16(pBase->macAddr);
 266         case EEP_MAC_MID:
 267                 return get_unaligned_be16(pBase->macAddr + 2);
 268         case EEP_MAC_MSW:
 269                 return get_unaligned_be16(pBase->macAddr + 4);
 270         case EEP_REG_0:
 271                 return pBase->regDmn[0];
 272         case EEP_OP_CAP:
 273                 return pBase->deviceCap;
 274         case EEP_OP_MODE:
 275                 return pBase->opCapFlags;
 276         case EEP_RF_SILENT:
 277                 return pBase->rfSilent;
 278         case EEP_OB_2:
 279                 return pModal->ob_0;
 280         case EEP_DB_2:
 281                 return pModal->db1_1;
 282         case EEP_MINOR_REV:
 283                 return ver_minor;
 284         case EEP_TX_MASK:
 285                 return pBase->txMask;
 286         case EEP_RX_MASK:
 287                 return pBase->rxMask;
 288         case EEP_FRAC_N_5G:
 289                 return 0;
 290         case EEP_PWR_TABLE_OFFSET:
 291                 return AR5416_PWR_TABLE_OFFSET_DB;
 292         case EEP_MODAL_VER:
 293                 return pModal->version;
 294         case EEP_ANT_DIV_CTL1:
 295                 return pModal->antdiv_ctl1;
 296         case EEP_TXGAIN_TYPE:
 297                 return pBase->txGainType;
 298         case EEP_ANTENNA_GAIN_2G:
 299                 return pModal->antennaGainCh[0];
 300         default:
 301                 return 0;
 302         }
 303 }
 304
 305 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 306                                   struct ath9k_channel *chan)
 307 {
 308         struct ath_common *common = ath9k_hw_common(ah);
 309         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 310         struct cal_data_per_freq_4k *pRawDataset;
 311         u8 *pCalBChans = NULL;
 312         u16 pdGainOverlap_t2;
 313         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 314         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 315         u16 numPiers, i, j;
 316         u16 numXpdGain, xpdMask;
 317         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 318         u32 reg32, regOffset, regChainOffset;
 319
 320         xpdMask = pEepData->modalHeader.xpdGain;
 321
 322         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 323             AR5416_EEP_MINOR_VER_2) {
 324                 pdGainOverlap_t2 =
 325                         pEepData->modalHeader.pdGainOverlap;
 326         } else {
 327                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 328                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 329         }
 330
 331         pCalBChans = pEepData->calFreqPier2G;
 332         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 333
 334         numXpdGain = 0;
 335
 336         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 337                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 338                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 339                                 break;
 340                         xpdGainValues[numXpdGain] =
 341                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 342                         numXpdGain++;
 343                 }
 344         }
 345
 346         ENABLE_REG_RMW_BUFFER(ah);
 347         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 348                       (numXpdGain - 1) & 0x3);
 349         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 350                       xpdGainValues[0]);
 351         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 352                       xpdGainValues[1]);
 353         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 354         REG_RMW_BUFFER_FLUSH(ah);
 355
 356         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 357                 regChainOffset = i * 0x1000;
 358
 359                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 360                         pRawDataset = pEepData->calPierData2G[i];
 361
 362                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
 363                                             pRawDataset, pCalBChans,
 364                                             numPiers, pdGainOverlap_t2,
 365                                             gainBoundaries,
 366                                             pdadcValues, numXpdGain);
 367
 368                         ENABLE_REGWRITE_BUFFER(ah);
 369
 370                         REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 371                                   SM(pdGainOverlap_t2,
 372                                      AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 373                                   | SM(gainBoundaries[0],
 374                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 375                                   | SM(gainBoundaries[1],
 376                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 377                                   | SM(gainBoundaries[2],
 378                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 379                                   | SM(gainBoundaries[3],
 380                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 381
 382                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 383                         for (j = 0; j < 32; j++) {
 384                                 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
 385                                 REG_WRITE(ah, regOffset, reg32);
 386
 387                                 ath_dbg(common, EEPROM,
 388                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 389                                         i, regChainOffset, regOffset,
 390                                         reg32);
 391                                 ath_dbg(common, EEPROM,
 392                                         "PDADC: Chain %d | "
 393                                         "PDADC %3d Value %3d | "
 394                                         "PDADC %3d Value %3d | "
 395                                         "PDADC %3d Value %3d | "
 396                                         "PDADC %3d Value %3d |\n",
 397                                         i, 4 * j, pdadcValues[4 * j],
 398                                         4 * j + 1, pdadcValues[4 * j + 1],
 399                                         4 * j + 2, pdadcValues[4 * j + 2],
 400                                         4 * j + 3, pdadcValues[4 * j + 3]);
 401
 402                                 regOffset += 4;
 403                         }
 404
 405                         REGWRITE_BUFFER_FLUSH(ah);
 406                 }
 407         }
 408 }
 409
 410 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 411                                                  struct ath9k_channel *chan,
 412                                                  int16_t *ratesArray,
 413                                                  u16 cfgCtl,
 414                                                  u16 antenna_reduction,
 415                                                  u16 powerLimit)
 416 {
 417 #define CMP_TEST_GRP \
 418         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
 419          pEepData->ctlIndex[i])                                         \
 420         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 421             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 422
 423         int i;
 424         u16 twiceMinEdgePower;
 425         u16 twiceMaxEdgePower;
 426         u16 scaledPower = 0, minCtlPower;
 427         u16 numCtlModes;
 428         const u16 *pCtlMode;
 429         u16 ctlMode, freq;
 430         struct chan_centers centers;
 431         struct cal_ctl_data_4k *rep;
 432         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 433         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 434                 0, { 0, 0, 0, 0}
 435         };
 436         struct cal_target_power_leg targetPowerOfdmExt = {
 437                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 438                 0, { 0, 0, 0, 0 }
 439         };
 440         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 441                 0, {0, 0, 0, 0}
 442         };
 443         static const u16 ctlModesFor11g[] = {
 444                 CTL_11B, CTL_11G, CTL_2GHT20,
 445                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 446         };
 447
 448         ath9k_hw_get_channel_centers(ah, chan, &centers);
 449
 450         scaledPower = powerLimit - antenna_reduction;
 451         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 452         pCtlMode = ctlModesFor11g;
 453
 454         ath9k_hw_get_legacy_target_powers(ah, chan,
 455                         pEepData->calTargetPowerCck,
 456                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 457                         &targetPowerCck, 4, false);
 458         ath9k_hw_get_legacy_target_powers(ah, chan,
 459                         pEepData->calTargetPower2G,
 460                         AR5416_NUM_2G_20_TARGET_POWERS,
 461                         &targetPowerOfdm, 4, false);
 462         ath9k_hw_get_target_powers(ah, chan,
 463                         pEepData->calTargetPower2GHT20,
 464                         AR5416_NUM_2G_20_TARGET_POWERS,
 465                         &targetPowerHt20, 8, false);
 466
 467         if (IS_CHAN_HT40(chan)) {
 468                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 469                 ath9k_hw_get_target_powers(ah, chan,
 470                                 pEepData->calTargetPower2GHT40,
 471                                 AR5416_NUM_2G_40_TARGET_POWERS,
 472                                 &targetPowerHt40, 8, true);
 473                 ath9k_hw_get_legacy_target_powers(ah, chan,
 474                                 pEepData->calTargetPowerCck,
 475                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 476                                 &targetPowerCckExt, 4, true);
 477                 ath9k_hw_get_legacy_target_powers(ah, chan,
 478                                 pEepData->calTargetPower2G,
 479                                 AR5416_NUM_2G_20_TARGET_POWERS,
 480                                 &targetPowerOfdmExt, 4, true);
 481         }
 482
 483         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 484                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 485                         (pCtlMode[ctlMode] == CTL_2GHT40);
 486
 487                 if (isHt40CtlMode)
 488                         freq = centers.synth_center;
 489                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 490                         freq = centers.ext_center;
 491                 else
 492                         freq = centers.ctl_center;
 493
 494                 twiceMaxEdgePower = MAX_RATE_POWER;
 495
 496                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 497                              pEepData->ctlIndex[i]; i++) {
 498
 499                         if (CMP_TEST_GRP) {
 500                                 rep = &(pEepData->ctlData[i]);
 501
 502                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
 503                                         freq,
 504                                         rep->ctlEdges[
 505                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
 506                                         IS_CHAN_2GHZ(chan),
 507                                         AR5416_EEP4K_NUM_BAND_EDGES);
 508
 509                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 510                                         twiceMaxEdgePower =
 511                                                 min(twiceMaxEdgePower,
 512                                                     twiceMinEdgePower);
 513                                 } else {
 514                                         twiceMaxEdgePower = twiceMinEdgePower;
 515                                         break;
 516                                 }
 517                         }
 518                 }
 519
 520                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 521
 522                 switch (pCtlMode[ctlMode]) {
 523                 case CTL_11B:
 524                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 525                                 targetPowerCck.tPow2x[i] =
 526                                         min((u16)targetPowerCck.tPow2x[i],
 527                                             minCtlPower);
 528                         }
 529                         break;
 530                 case CTL_11G:
 531                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 532                                 targetPowerOfdm.tPow2x[i] =
 533                                         min((u16)targetPowerOfdm.tPow2x[i],
 534                                             minCtlPower);
 535                         }
 536                         break;
 537                 case CTL_2GHT20:
 538                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 539                                 targetPowerHt20.tPow2x[i] =
 540                                         min((u16)targetPowerHt20.tPow2x[i],
 541                                             minCtlPower);
 542                         }
 543                         break;
 544                 case CTL_11B_EXT:
 545                         targetPowerCckExt.tPow2x[0] =
 546                                 min((u16)targetPowerCckExt.tPow2x[0],
 547                                     minCtlPower);
 548                         break;
 549                 case CTL_11G_EXT:
 550                         targetPowerOfdmExt.tPow2x[0] =
 551                                 min((u16)targetPowerOfdmExt.tPow2x[0],
 552                                     minCtlPower);
 553                         break;
 554                 case CTL_2GHT40:
 555                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 556                                 targetPowerHt40.tPow2x[i] =
 557                                         min((u16)targetPowerHt40.tPow2x[i],
 558                                             minCtlPower);
 559                         }
 560                         break;
 561                 default:
 562                         break;
 563                 }
 564         }
 565
 566         ratesArray[rate6mb] =
 567         ratesArray[rate9mb] =
 568         ratesArray[rate12mb] =
 569         ratesArray[rate18mb] =
 570         ratesArray[rate24mb] =
 571         targetPowerOfdm.tPow2x[0];
 572
 573         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 574         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 575         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 576         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 577
 578         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 579                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 580
 581         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 582         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 583         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 584         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 585
 586         if (IS_CHAN_HT40(chan)) {
 587                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 588                         ratesArray[rateHt40_0 + i] =
 589                                 targetPowerHt40.tPow2x[i];
 590                 }
 591                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 592                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
 593                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 594                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 595         }
 596
 597 #undef CMP_TEST_GRP
 598 }
 599
 600 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 601                                     struct ath9k_channel *chan,
 602                                     u16 cfgCtl,
 603                                     u8 twiceAntennaReduction,
 604                                     u8 powerLimit, bool test)
 605 {
 606         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 607         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 608         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
 609         int16_t ratesArray[Ar5416RateSize];
 610         u8 ht40PowerIncForPdadc = 2;
 611         int i;
 612
 613         memset(ratesArray, 0, sizeof(ratesArray));
 614
 615         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 616             AR5416_EEP_MINOR_VER_2) {
 617                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 618         }
 619
 620         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
 621                                              &ratesArray[0], cfgCtl,
 622                                              twiceAntennaReduction,
 623                                              powerLimit);
 624
 625         ath9k_hw_set_4k_power_cal_table(ah, chan);
 626
 627         regulatory->max_power_level = 0;
 628         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 629                 if (ratesArray[i] > MAX_RATE_POWER)
 630                         ratesArray[i] = MAX_RATE_POWER;
 631
 632                 if (ratesArray[i] > regulatory->max_power_level)
 633                         regulatory->max_power_level = ratesArray[i];
 634         }
 635
 636         if (test)
 637             return;
 638
 639         for (i = 0; i < Ar5416RateSize; i++)
 640                 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
 641
 642         ENABLE_REGWRITE_BUFFER(ah);
 643
 644         /* OFDM power per rate */
 645         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 646                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 647                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 648                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 649                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 650         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 651                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 652                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 653                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 654                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 655
 656         /* CCK power per rate */
 657         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 658                   ATH9K_POW_SM(ratesArray[rate2s], 24)
 659                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
 660                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
 661                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
 662         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 663                   ATH9K_POW_SM(ratesArray[rate11s], 24)
 664                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
 665                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 666                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 667
 668         /* HT20 power per rate */
 669         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 670                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 671                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 672                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 673                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 674         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 675                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 676                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 677                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 678                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 679
 680         /* HT40 power per rate */
 681         if (IS_CHAN_HT40(chan)) {
 682                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 683                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
 684                                        ht40PowerIncForPdadc, 24)
 685                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 686                                          ht40PowerIncForPdadc, 16)
 687                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 688                                          ht40PowerIncForPdadc, 8)
 689                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 690                                          ht40PowerIncForPdadc, 0));
 691                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 692                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
 693                                        ht40PowerIncForPdadc, 24)
 694                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 695                                          ht40PowerIncForPdadc, 16)
 696                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 697                                          ht40PowerIncForPdadc, 8)
 698                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 699                                          ht40PowerIncForPdadc, 0));
 700                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 701                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 702                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 703                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 704                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 705         }
 706
 707         /* TPC initializations */
 708         if (ah->tpc_enabled) {
 709                 int ht40_delta;
 710
 711                 ht40_delta = (IS_CHAN_HT40(chan)) ? ht40PowerIncForPdadc : 0;
 712                 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta);
 713                 /* Enable TPC */
 714                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
 715                         MAX_RATE_POWER | AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
 716         } else {
 717                 /* Disable TPC */
 718                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
 719         }
 720
 721         REGWRITE_BUFFER_FLUSH(ah);
 722 }
 723
 724 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
 725                                  struct modal_eep_4k_header *pModal,
 726                                  struct ar5416_eeprom_4k *eep,
 727                                  u8 txRxAttenLocal)
 728 {
 729         ENABLE_REG_RMW_BUFFER(ah);
 730         REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0,
 731                 pModal->antCtrlChain[0], 0);
 732
 733         REG_RMW(ah, AR_PHY_TIMING_CTRL4(0),
 734                 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 735                 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF),
 736                 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF);
 737
 738         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 739             AR5416_EEP_MINOR_VER_3) {
 740                 txRxAttenLocal = pModal->txRxAttenCh[0];
 741
 742                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 743                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
 744                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 745                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 746                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 747                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 748                               pModal->xatten2Margin[0]);
 749                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 750                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
 751
 752                 /* Set the block 1 value to block 0 value */
 753                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 754                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 755                               pModal->bswMargin[0]);
 756                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 757                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 758                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 759                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 760                               pModal->xatten2Margin[0]);
 761                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 762                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 763                               pModal->xatten2Db[0]);
 764         }
 765
 766         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 767                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 768         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 769                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 770
 771         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 772                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 773         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 774                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 775         REG_RMW_BUFFER_FLUSH(ah);
 776 }
 777
 778 /*
 779  * Read EEPROM header info and program the device for correct operation
 780  * given the channel value.
 781  */
 782 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 783                                          struct ath9k_channel *chan)
 784 {
 785         struct ath9k_hw_capabilities *pCap = &ah->caps;
 786         struct modal_eep_4k_header *pModal;
 787         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 788         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 789         u8 txRxAttenLocal;
 790         u8 ob[5], db1[5], db2[5];
 791         u8 ant_div_control1, ant_div_control2;
 792         u8 bb_desired_scale;
 793         u32 regVal;
 794
 795         pModal = &eep->modalHeader;
 796         txRxAttenLocal = 23;
 797
 798         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 799
 800         /* Single chain for 4K EEPROM*/
 801         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
 802
 803         /* Initialize Ant Diversity settings from EEPROM */
 804         if (pModal->version >= 3) {
 805                 ant_div_control1 = pModal->antdiv_ctl1;
 806                 ant_div_control2 = pModal->antdiv_ctl2;
 807
 808                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 809                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
 810
 811                 regVal |= SM(ant_div_control1,
 812                              AR_PHY_9285_ANT_DIV_CTL);
 813                 regVal |= SM(ant_div_control2,
 814                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
 815                 regVal |= SM((ant_div_control2 >> 2),
 816                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
 817                 regVal |= SM((ant_div_control1 >> 1),
 818                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
 819                 regVal |= SM((ant_div_control1 >> 2),
 820                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
 821
 822
 823                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 824                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 825                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 826                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 827                 regVal |= SM((ant_div_control1 >> 3),
 828                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 829
 830                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
 831                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 832
 833                 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
 834                         /*
 835                          * If diversity combining is enabled,
 836                          * set MAIN to LNA1 and ALT to LNA2 initially.
 837                          */
 838                         regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 839                         regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
 840                                      AR_PHY_9285_ANT_DIV_ALT_LNACONF));
 841
 842                         regVal |= (ATH_ANT_DIV_COMB_LNA1 <<
 843                                    AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S);
 844                         regVal |= (ATH_ANT_DIV_COMB_LNA2 <<
 845                                    AR_PHY_9285_ANT_DIV_ALT_LNACONF_S);
 846                         regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS));
 847                         regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S);
 848                         REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 849                 }
 850         }
 851
 852         if (pModal->version >= 2) {
 853                 ob[0] = pModal->ob_0;
 854                 ob[1] = pModal->ob_1;
 855                 ob[2] = pModal->ob_2;
 856                 ob[3] = pModal->ob_3;
 857                 ob[4] = pModal->ob_4;
 858
 859                 db1[0] = pModal->db1_0;
 860                 db1[1] = pModal->db1_1;
 861                 db1[2] = pModal->db1_2;
 862                 db1[3] = pModal->db1_3;
 863                 db1[4] = pModal->db1_4;
 864
 865                 db2[0] = pModal->db2_0;
 866                 db2[1] = pModal->db2_1;
 867                 db2[2] = pModal->db2_2;
 868                 db2[3] = pModal->db2_3;
 869                 db2[4] = pModal->db2_4;
 870         } else if (pModal->version == 1) {
 871                 ob[0] = pModal->ob_0;
 872                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
 873                 db1[0] = pModal->db1_0;
 874                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
 875                 db2[0] = pModal->db2_0;
 876                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
 877         } else {
 878                 int i;
 879
 880                 for (i = 0; i < 5; i++) {
 881                         ob[i] = pModal->ob_0;
 882                         db1[i] = pModal->db1_0;
 883                         db2[i] = pModal->db1_0;
 884                 }
 885         }
 886
 887         ENABLE_REG_RMW_BUFFER(ah);
 888         if (AR_SREV_9271(ah)) {
 889                 ath9k_hw_analog_shift_rmw(ah,
 890                                           AR9285_AN_RF2G3,
 891                                           AR9271_AN_RF2G3_OB_cck,
 892                                           AR9271_AN_RF2G3_OB_cck_S,
 893                                           ob[0]);
 894                 ath9k_hw_analog_shift_rmw(ah,
 895                                           AR9285_AN_RF2G3,
 896                                           AR9271_AN_RF2G3_OB_psk,
 897                                           AR9271_AN_RF2G3_OB_psk_S,
 898                                           ob[1]);
 899                 ath9k_hw_analog_shift_rmw(ah,
 900                                           AR9285_AN_RF2G3,
 901                                           AR9271_AN_RF2G3_OB_qam,
 902                                           AR9271_AN_RF2G3_OB_qam_S,
 903                                           ob[2]);
 904                 ath9k_hw_analog_shift_rmw(ah,
 905                                           AR9285_AN_RF2G3,
 906                                           AR9271_AN_RF2G3_DB_1,
 907                                           AR9271_AN_RF2G3_DB_1_S,
 908                                           db1[0]);
 909                 ath9k_hw_analog_shift_rmw(ah,
 910                                           AR9285_AN_RF2G4,
 911                                           AR9271_AN_RF2G4_DB_2,
 912                                           AR9271_AN_RF2G4_DB_2_S,
 913                                           db2[0]);
 914         } else {
 915                 ath9k_hw_analog_shift_rmw(ah,
 916                                           AR9285_AN_RF2G3,
 917                                           AR9285_AN_RF2G3_OB_0,
 918                                           AR9285_AN_RF2G3_OB_0_S,
 919                                           ob[0]);
 920                 ath9k_hw_analog_shift_rmw(ah,
 921                                           AR9285_AN_RF2G3,
 922                                           AR9285_AN_RF2G3_OB_1,
 923                                           AR9285_AN_RF2G3_OB_1_S,
 924                                           ob[1]);
 925                 ath9k_hw_analog_shift_rmw(ah,
 926                                           AR9285_AN_RF2G3,
 927                                           AR9285_AN_RF2G3_OB_2,
 928                                           AR9285_AN_RF2G3_OB_2_S,
 929                                           ob[2]);
 930                 ath9k_hw_analog_shift_rmw(ah,
 931                                           AR9285_AN_RF2G3,
 932                                           AR9285_AN_RF2G3_OB_3,
 933                                           AR9285_AN_RF2G3_OB_3_S,
 934                                           ob[3]);
 935                 ath9k_hw_analog_shift_rmw(ah,
 936                                           AR9285_AN_RF2G3,
 937                                           AR9285_AN_RF2G3_OB_4,
 938                                           AR9285_AN_RF2G3_OB_4_S,
 939                                           ob[4]);
 940
 941                 ath9k_hw_analog_shift_rmw(ah,
 942                                           AR9285_AN_RF2G3,
 943                                           AR9285_AN_RF2G3_DB1_0,
 944                                           AR9285_AN_RF2G3_DB1_0_S,
 945                                           db1[0]);
 946                 ath9k_hw_analog_shift_rmw(ah,
 947                                           AR9285_AN_RF2G3,
 948                                           AR9285_AN_RF2G3_DB1_1,
 949                                           AR9285_AN_RF2G3_DB1_1_S,
 950                                           db1[1]);
 951                 ath9k_hw_analog_shift_rmw(ah,
 952                                           AR9285_AN_RF2G3,
 953                                           AR9285_AN_RF2G3_DB1_2,
 954                                           AR9285_AN_RF2G3_DB1_2_S,
 955                                           db1[2]);
 956                 ath9k_hw_analog_shift_rmw(ah,
 957                                           AR9285_AN_RF2G4,
 958                                           AR9285_AN_RF2G4_DB1_3,
 959                                           AR9285_AN_RF2G4_DB1_3_S,
 960                                           db1[3]);
 961                 ath9k_hw_analog_shift_rmw(ah,
 962                                           AR9285_AN_RF2G4,
 963                                           AR9285_AN_RF2G4_DB1_4,
 964                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
 965
 966                 ath9k_hw_analog_shift_rmw(ah,
 967                                           AR9285_AN_RF2G4,
 968                                           AR9285_AN_RF2G4_DB2_0,
 969                                           AR9285_AN_RF2G4_DB2_0_S,
 970                                           db2[0]);
 971                 ath9k_hw_analog_shift_rmw(ah,
 972                                           AR9285_AN_RF2G4,
 973                                           AR9285_AN_RF2G4_DB2_1,
 974                                           AR9285_AN_RF2G4_DB2_1_S,
 975                                           db2[1]);
 976                 ath9k_hw_analog_shift_rmw(ah,
 977                                           AR9285_AN_RF2G4,
 978                                           AR9285_AN_RF2G4_DB2_2,
 979                                           AR9285_AN_RF2G4_DB2_2_S,
 980                                           db2[2]);
 981                 ath9k_hw_analog_shift_rmw(ah,
 982                                           AR9285_AN_RF2G4,
 983                                           AR9285_AN_RF2G4_DB2_3,
 984                                           AR9285_AN_RF2G4_DB2_3_S,
 985                                           db2[3]);
 986                 ath9k_hw_analog_shift_rmw(ah,
 987                                           AR9285_AN_RF2G4,
 988                                           AR9285_AN_RF2G4_DB2_4,
 989                                           AR9285_AN_RF2G4_DB2_4_S,
 990                                           db2[4]);
 991         }
 992         REG_RMW_BUFFER_FLUSH(ah);
 993
 994         ENABLE_REG_RMW_BUFFER(ah);
 995         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 996                       pModal->switchSettling);
 997         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 998                       pModal->adcDesiredSize);
 999
1000         REG_RMW(ah, AR_PHY_RF_CTL4,
1001                 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1002                 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1003                 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1004                 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON), 0);
1005
1006         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1007                       pModal->txEndToRxOn);
1008
1009         if (AR_SREV_9271_10(ah))
1010                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1011                               pModal->txEndToRxOn);
1012         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1013                       pModal->thresh62);
1014         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1015                       pModal->thresh62);
1016
1017         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1018                                                 AR5416_EEP_MINOR_VER_2) {
1019                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1020                               pModal->txFrameToDataStart);
1021                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1022                               pModal->txFrameToPaOn);
1023         }
1024
1025         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1026                                                 AR5416_EEP_MINOR_VER_3) {
1027                 if (IS_CHAN_HT40(chan))
1028                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1029                                       AR_PHY_SETTLING_SWITCH,
1030                                       pModal->swSettleHt40);
1031         }
1032
1033         REG_RMW_BUFFER_FLUSH(ah);
1034
1035         bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1036                         EEP_4K_BB_DESIRED_SCALE_MASK);
1037         if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1038                 u32 pwrctrl, mask, clr;
1039
1040                 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1041                 pwrctrl = mask * bb_desired_scale;
1042                 clr = mask * 0x1f;
1043                 ENABLE_REG_RMW_BUFFER(ah);
1044                 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1045                 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1046                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1047
1048                 mask = BIT(0)|BIT(5)|BIT(15);
1049                 pwrctrl = mask * bb_desired_scale;
1050                 clr = mask * 0x1f;
1051                 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1052
1053                 mask = BIT(0)|BIT(5);
1054                 pwrctrl = mask * bb_desired_scale;
1055                 clr = mask * 0x1f;
1056                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1057                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1058                 REG_RMW_BUFFER_FLUSH(ah);
1059         }
1060 }
1061
1062 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1063 {
1064         return ah->eeprom.map4k.modalHeader.spurChans[i].spurChan;
1065 }
1066
1067 const struct eeprom_ops eep_4k_ops = {
1068         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1069         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1070         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1071         .dump_eeprom            = ath9k_hw_4k_dump_eeprom,
1072         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1073         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1074         .set_board_values       = ath9k_hw_4k_set_board_values,
1075         .set_txpower            = ath9k_hw_4k_set_txpower,
1076         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1077 };