2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/export.h>
19 #include "ar9003_phy.h"
21 #define AR9300_OFDM_RATES 8
22 #define AR9300_HT_SS_RATES 8
23 #define AR9300_HT_DS_RATES 8
24 #define AR9300_HT_TS_RATES 8
26 #define AR9300_11NA_OFDM_SHIFT 0
27 #define AR9300_11NA_HT_SS_SHIFT 8
28 #define AR9300_11NA_HT_DS_SHIFT 16
29 #define AR9300_11NA_HT_TS_SHIFT 24
31 #define AR9300_11NG_OFDM_SHIFT 4
32 #define AR9300_11NG_HT_SS_SHIFT 12
33 #define AR9300_11NG_HT_DS_SHIFT 20
34 #define AR9300_11NG_HT_TS_SHIFT 28
36 static const int firstep_table[] =
37 /* level: 0 1 2 3 4 5 6 7 8 */
38 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
40 static const int cycpwrThr1_table[] =
41 /* level: 0 1 2 3 4 5 6 7 8 */
42 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
45 * register values to turn OFDM weak signal detection OFF
47 static const int m1ThreshLow_off = 127;
48 static const int m2ThreshLow_off = 127;
49 static const int m1Thresh_off = 127;
50 static const int m2Thresh_off = 127;
51 static const int m2CountThr_off = 31;
52 static const int m2CountThrLow_off = 63;
53 static const int m1ThreshLowExt_off = 127;
54 static const int m2ThreshLowExt_off = 127;
55 static const int m1ThreshExt_off = 127;
56 static const int m2ThreshExt_off = 127;
58 static const u8 ofdm2pwr[] = {
59 ALL_TARGET_LEGACY_6_24,
60 ALL_TARGET_LEGACY_6_24,
61 ALL_TARGET_LEGACY_6_24,
62 ALL_TARGET_LEGACY_6_24,
63 ALL_TARGET_LEGACY_6_24,
69 static const u8 mcs2pwr_ht20[] = {
70 ALL_TARGET_HT20_0_8_16,
71 ALL_TARGET_HT20_1_3_9_11_17_19,
72 ALL_TARGET_HT20_1_3_9_11_17_19,
73 ALL_TARGET_HT20_1_3_9_11_17_19,
78 ALL_TARGET_HT20_0_8_16,
79 ALL_TARGET_HT20_1_3_9_11_17_19,
80 ALL_TARGET_HT20_1_3_9_11_17_19,
81 ALL_TARGET_HT20_1_3_9_11_17_19,
86 ALL_TARGET_HT20_0_8_16,
87 ALL_TARGET_HT20_1_3_9_11_17_19,
88 ALL_TARGET_HT20_1_3_9_11_17_19,
89 ALL_TARGET_HT20_1_3_9_11_17_19,
96 static const u8 mcs2pwr_ht40[] = {
97 ALL_TARGET_HT40_0_8_16,
98 ALL_TARGET_HT40_1_3_9_11_17_19,
99 ALL_TARGET_HT40_1_3_9_11_17_19,
100 ALL_TARGET_HT40_1_3_9_11_17_19,
105 ALL_TARGET_HT40_0_8_16,
106 ALL_TARGET_HT40_1_3_9_11_17_19,
107 ALL_TARGET_HT40_1_3_9_11_17_19,
108 ALL_TARGET_HT40_1_3_9_11_17_19,
113 ALL_TARGET_HT40_0_8_16,
114 ALL_TARGET_HT40_1_3_9_11_17_19,
115 ALL_TARGET_HT40_1_3_9_11_17_19,
116 ALL_TARGET_HT40_1_3_9_11_17_19,
124 * ar9003_hw_set_channel - set channel on single-chip device
125 * @ah: atheros hardware structure
128 * This is the function to change channel on single-chip devices, that is
129 * for AR9300 family of chipsets.
131 * This function takes the channel value in MHz and sets
132 * hardware channel value. Assumes writes have been enabled to analog bus.
137 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
141 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
142 * (freq_ref = 40MHz/(24>>amodeRefSel))
144 * For 5GHz channels which are 5MHz spaced,
145 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
148 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
150 u16 bMode, fracMode = 0, aModeRefSel = 0;
151 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
152 struct chan_centers centers;
153 int loadSynthChannel;
155 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
156 freq = centers.synth_center;
158 if (freq < 4800) { /* 2 GHz, fractional mode */
159 if (AR_SREV_9330(ah)) {
160 if (ah->is_clk_25mhz)
165 channelSel = (freq * 4) / div;
166 chan_frac = (((freq * 4) % div) * 0x20000) / div;
167 channelSel = (channelSel << 17) | chan_frac;
168 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
170 * freq_ref = 40 / (refdiva >> amoderefsel);
171 * where refdiva=1 and amoderefsel=0
172 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
173 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
175 channelSel = (freq * 4) / 120;
176 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
177 channelSel = (channelSel << 17) | chan_frac;
178 } else if (AR_SREV_9340(ah)) {
179 if (ah->is_clk_25mhz) {
180 channelSel = (freq * 2) / 75;
181 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
182 channelSel = (channelSel << 17) | chan_frac;
184 channelSel = CHANSEL_2G(freq) >> 1;
186 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
188 if (ah->is_clk_25mhz)
193 channelSel = (freq * 4) / div;
194 chan_frac = (((freq * 4) % div) * 0x20000) / div;
195 channelSel = (channelSel << 17) | chan_frac;
197 channelSel = CHANSEL_2G(freq);
202 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
203 AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
205 channelSel = freq / 75;
206 chan_frac = ((freq % 75) * 0x20000) / 75;
207 channelSel = (channelSel << 17) | chan_frac;
209 channelSel = CHANSEL_5G(freq);
210 /* Doubler is ON, so, divide channelSel by 2. */
217 /* Enable fractional mode for all channels */
220 loadSynthChannel = 0;
222 reg32 = (bMode << 29);
223 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
225 /* Enable Long shift Select for Synthesizer */
226 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
227 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
229 /* Program Synth. setting */
230 reg32 = (channelSel << 2) | (fracMode << 30) |
231 (aModeRefSel << 28) | (loadSynthChannel << 31);
232 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
234 /* Toggle Load Synth channel bit */
235 loadSynthChannel = 1;
236 reg32 = (channelSel << 2) | (fracMode << 30) |
237 (aModeRefSel << 28) | (loadSynthChannel << 31);
238 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
246 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
247 * @ah: atheros hardware structure
250 * For single-chip solutions. Converts to baseband spur frequency given the
251 * input channel frequency and compute register settings below.
253 * Spur mitigation for MRC CCK
255 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
256 struct ath9k_channel *chan)
258 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
259 int cur_bb_spur, negative = 0, cck_spur_freq;
261 int range, max_spur_cnts, synth_freq;
262 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
265 * Need to verify range +/- 10 MHz in control channel, otherwise spur
266 * is out-of-band and can be ignored.
269 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
270 AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
271 if (spur_fbin_ptr[0] == 0) /* No spur */
274 if (IS_CHAN_HT40(chan)) {
276 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
277 AR_PHY_GC_DYN2040_PRI_CH) == 0)
278 synth_freq = chan->channel + 10;
280 synth_freq = chan->channel - 10;
283 synth_freq = chan->channel;
286 range = AR_SREV_9462(ah) ? 5 : 10;
288 synth_freq = chan->channel;
291 for (i = 0; i < max_spur_cnts; i++) {
292 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
296 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
297 AR_SREV_9550(ah) || AR_SREV_9561(ah))
298 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
301 cur_bb_spur = spur_freq[i];
303 cur_bb_spur -= synth_freq;
304 if (cur_bb_spur < 0) {
306 cur_bb_spur = -cur_bb_spur;
308 if (cur_bb_spur < range) {
309 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
312 cck_spur_freq = -cck_spur_freq;
314 cck_spur_freq = cck_spur_freq & 0xfffff;
316 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
317 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
318 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
319 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
320 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
321 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
323 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
324 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
326 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
327 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
334 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
335 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
336 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
337 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
338 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
339 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
342 /* Clean all spur register fields */
343 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
345 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
346 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
347 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
348 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
349 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
350 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
351 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
352 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
354 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
355 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
356 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
357 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
358 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
359 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
360 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
361 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
362 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
364 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
365 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
366 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
367 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
368 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
369 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
370 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
371 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
372 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
373 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
374 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
375 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
376 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
377 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
378 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
379 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
380 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
381 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
382 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
383 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
386 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
389 int spur_delta_phase,
390 int spur_subchannel_sd,
396 /* OFDM Spur mitigation */
397 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
398 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
399 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
400 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
401 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
402 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
403 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
404 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
405 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
406 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
408 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
409 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
410 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
412 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
413 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
415 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
416 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
417 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
419 if (!AR_SREV_9340(ah) &&
420 REG_READ_FIELD(ah, AR_PHY_MODE,
421 AR_PHY_MODE_DYNAMIC) == 0x1)
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
423 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
425 mask_index = (freq_offset << 4) / 5;
427 mask_index = mask_index - 1;
429 mask_index = mask_index & 0x7f;
431 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
432 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
433 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
434 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
435 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
436 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
437 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
438 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
439 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
440 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
441 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
442 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
443 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
444 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
445 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
446 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
447 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
448 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
449 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
450 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
453 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
458 mask_index = (freq_offset << 4) / 5;
460 mask_index = mask_index - 1;
462 mask_index = mask_index & 0x7f;
464 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
465 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
469 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
470 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
473 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
474 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
476 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
477 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
478 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
479 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
482 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
483 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
486 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
487 struct ath9k_channel *chan,
492 int spur_freq_sd = 0;
493 int spur_subchannel_sd = 0;
494 int spur_delta_phase = 0;
496 if (IS_CHAN_HT40(chan)) {
497 if (freq_offset < 0) {
498 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
499 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
500 spur_subchannel_sd = 1;
502 spur_subchannel_sd = 0;
504 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
507 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
508 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
509 spur_subchannel_sd = 0;
511 spur_subchannel_sd = 1;
513 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
517 spur_delta_phase = (freq_offset << 17) / 5;
520 spur_subchannel_sd = 0;
521 spur_freq_sd = (freq_offset << 9) /11;
522 spur_delta_phase = (freq_offset << 18) / 5;
525 spur_freq_sd = spur_freq_sd & 0x3ff;
526 spur_delta_phase = spur_delta_phase & 0xfffff;
528 ar9003_hw_spur_ofdm(ah,
536 /* Spur mitigation for OFDM */
537 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
538 struct ath9k_channel *chan)
546 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
548 if (IS_CHAN_5GHZ(chan)) {
549 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
553 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
557 if (spurChansPtr[0] == 0)
558 return; /* No spur in the mode */
560 if (IS_CHAN_HT40(chan)) {
562 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
563 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
564 synth_freq = chan->channel - 10;
566 synth_freq = chan->channel + 10;
569 synth_freq = chan->channel;
572 ar9003_hw_spur_ofdm_clear(ah);
574 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
575 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
576 freq_offset -= synth_freq;
577 if (abs(freq_offset) < range) {
578 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
581 if (AR_SREV_9565(ah) && (i < 4)) {
582 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
584 freq_offset -= synth_freq;
585 if (abs(freq_offset) < range)
586 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
594 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
595 struct ath9k_channel *chan)
597 if (!AR_SREV_9565(ah))
598 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
599 ar9003_hw_spur_mitigate_ofdm(ah, chan);
602 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
603 struct ath9k_channel *chan)
607 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
609 if (chan && IS_CHAN_HALF_RATE(chan))
610 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
611 else if (chan && IS_CHAN_QUARTER_RATE(chan))
612 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
614 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
619 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
620 struct ath9k_channel *chan)
624 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
626 if (chan && IS_CHAN_HALF_RATE(chan))
627 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
628 else if (chan && IS_CHAN_QUARTER_RATE(chan))
629 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
631 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
636 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
637 struct ath9k_channel *chan)
640 u32 enableDacFifo = 0;
643 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
645 /* Enable 11n HT, 20 MHz */
646 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
648 if (!AR_SREV_9561(ah))
649 phymode |= AR_PHY_GC_SINGLE_HT_LTF1;
651 /* Configure baseband for dynamic 20/40 operation */
652 if (IS_CHAN_HT40(chan)) {
653 phymode |= AR_PHY_GC_DYN2040_EN;
654 /* Configure control (primary) channel at +-10MHz */
655 if (IS_CHAN_HT40PLUS(chan))
656 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
660 /* make sure we preserve INI settings */
661 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
662 /* turn off Green Field detection for STA for now */
663 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
665 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
667 /* Configure MAC for 20/40 operation */
668 ath9k_hw_set11nmac2040(ah, chan);
670 /* global transmit timeout (25 TUs default)*/
671 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
672 /* carrier sense timeout */
673 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
676 static void ar9003_hw_init_bb(struct ath_hw *ah,
677 struct ath9k_channel *chan)
682 * Wait for the frequency synth to settle (synth goes on
683 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
684 * Value is in 100ns increments.
686 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
688 /* Activate the PHY (includes baseband activate + synthesizer on) */
689 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
690 ath9k_hw_synth_delay(ah, chan, synthDelay);
693 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
695 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
696 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
697 AR_PHY_SWAP_ALT_CHAIN);
699 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
700 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
702 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
705 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
709 * Override INI values with chip specific configuration.
711 static void ar9003_hw_override_ini(struct ath_hw *ah)
716 * Set the RX_ABORT and RX_DIS and clear it only after
717 * RXE is set for MAC. This prevents frames with
718 * corrupted descriptor status.
720 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
723 * For AR9280 and above, there is a new feature that allows
724 * Multicast search based on both MAC Address and Key ID. By default,
725 * this feature is enabled. But since the driver is not using this
726 * feature, we switch it off; otherwise multicast search based on
727 * MAC addr only will fail.
729 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
730 val |= AR_AGG_WEP_ENABLE_FIX |
732 AR_PCU_MISC_MODE2_CFP_IGNORE;
733 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
735 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
736 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
737 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
739 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
740 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
741 ah->enabled_cals |= TX_IQ_CAL;
743 ah->enabled_cals &= ~TX_IQ_CAL;
747 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
748 ah->enabled_cals |= TX_CL_CAL;
750 ah->enabled_cals &= ~TX_CL_CAL;
752 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
754 if (ah->is_clk_25mhz) {
755 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
756 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
757 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
759 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
760 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
761 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
767 static void ar9003_hw_prog_ini(struct ath_hw *ah,
768 struct ar5416IniArray *iniArr,
771 unsigned int i, regWrites = 0;
773 /* New INI format: Array may be undefined (pre, core, post arrays) */
774 if (!iniArr->ia_array)
778 * New INI format: Pre, core, and post arrays for a given subsystem
779 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
780 * the array is non-modal and force the column to 1.
782 if (column >= iniArr->ia_columns)
785 for (i = 0; i < iniArr->ia_rows; i++) {
786 u32 reg = INI_RA(iniArr, i, 0);
787 u32 val = INI_RA(iniArr, i, column);
789 REG_WRITE(ah, reg, val);
795 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
796 struct ath9k_channel *chan)
800 if (IS_CHAN_2GHZ(chan)) {
801 if (IS_CHAN_HT40(chan))
807 if (chan->channel <= 5350)
809 else if ((chan->channel > 5350) && (chan->channel <= 5600))
814 if (IS_CHAN_HT40(chan))
820 static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
821 struct ath9k_channel *chan)
823 if (IS_CHAN_2GHZ(chan)) {
824 if (IS_CHAN_HT40(chan))
833 static void ar9003_doubler_fix(struct ath_hw *ah)
835 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
836 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
837 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
838 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
839 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
840 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
841 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
842 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
843 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
844 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
848 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
849 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
850 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
851 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
852 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
853 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
857 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
858 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
859 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
860 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
861 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
862 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
866 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
867 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
869 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
870 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
871 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
872 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
873 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
874 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
875 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
876 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
877 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
881 static int ar9003_hw_process_ini(struct ath_hw *ah,
882 struct ath9k_channel *chan)
884 unsigned int regWrites = 0, i;
887 if (IS_CHAN_5GHZ(chan))
888 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
890 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
893 * SOC, MAC, BB, RADIO initvals.
895 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
896 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
897 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
898 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
899 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
900 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
901 ar9003_hw_prog_ini(ah,
902 &ah->ini_radio_post_sys2ant,
906 ar9003_doubler_fix(ah);
911 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
913 if (AR_SREV_9462_20_OR_LATER(ah)) {
915 * CUS217 mix LNA mode.
917 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
918 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
920 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
921 modesIndex, regWrites);
927 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
928 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
929 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
930 modesIndex, regWrites);
934 if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
935 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
938 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
939 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
940 modesIndex, regWrites);
944 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
945 int modes_txgain_index = 1;
947 if (AR_SREV_9550(ah))
948 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
950 if (AR_SREV_9561(ah))
952 ar9561_hw_get_modes_txgain_index(ah, chan);
954 if (modes_txgain_index < 0)
957 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
960 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
964 * For 5GHz channels requiring Fast Clock, apply
965 * different modal values.
967 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
968 REG_WRITE_ARRAY(&ah->iniModesFastClock,
969 modesIndex, regWrites);
972 * Clock frequency initvals.
974 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
979 if (chan->channel == 2484)
980 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
982 ah->modes_index = modesIndex;
983 ar9003_hw_override_ini(ah);
984 ar9003_hw_set_channel_regs(ah, chan);
985 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
986 ath9k_hw_apply_txpower(ah, chan, false);
991 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
992 struct ath9k_channel *chan)
999 if (IS_CHAN_2GHZ(chan))
1000 rfMode |= AR_PHY_MODE_DYNAMIC;
1002 rfMode |= AR_PHY_MODE_OFDM;
1004 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1005 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1007 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
1008 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1009 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
1011 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1014 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
1016 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1019 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
1020 struct ath9k_channel *chan)
1022 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1023 u32 clockMhzScaled = 0x64000000;
1024 struct chan_centers centers;
1027 * half and quarter rate can divide the scaled clock by 2 or 4
1028 * scale for selected channel bandwidth
1030 if (IS_CHAN_HALF_RATE(chan))
1031 clockMhzScaled = clockMhzScaled >> 1;
1032 else if (IS_CHAN_QUARTER_RATE(chan))
1033 clockMhzScaled = clockMhzScaled >> 2;
1036 * ALGO -> coef = 1e8/fcarrier*fclock/40;
1037 * scaled coef to provide precision for this floating calculation
1039 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1040 coef_scaled = clockMhzScaled / centers.synth_center;
1042 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1045 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1046 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1047 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1048 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1052 * scaled coeff is 9/10 that of normal coeff
1054 coef_scaled = (9 * coef_scaled) / 10;
1056 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1060 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1061 AR_PHY_SGI_DSC_MAN, ds_coef_man);
1062 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1063 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
1066 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1068 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1069 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1070 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1074 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1075 * Read the phy active delay register. Value is in 100ns increments.
1077 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1079 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1081 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
1083 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1086 static bool ar9003_hw_ani_control(struct ath_hw *ah,
1087 enum ath9k_ani_cmd cmd, int param)
1089 struct ath_common *common = ath9k_hw_common(ah);
1090 struct ath9k_channel *chan = ah->curchan;
1091 struct ar5416AniState *aniState = &ah->ani;
1092 int m1ThreshLow, m2ThreshLow;
1093 int m1Thresh, m2Thresh;
1094 int m2CountThr, m2CountThrLow;
1095 int m1ThreshLowExt, m2ThreshLowExt;
1096 int m1ThreshExt, m2ThreshExt;
1099 switch (cmd & ah->ani_function) {
1100 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1102 * on == 1 means ofdm weak signal detection is ON
1103 * on == 1 is the default, for less noise immunity
1105 * on == 0 means ofdm weak signal detection is OFF
1106 * on == 0 means more noise imm
1108 u32 on = param ? 1 : 0;
1110 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1114 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1116 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1118 aniState->iniDef.m1Thresh : m1Thresh_off;
1120 aniState->iniDef.m2Thresh : m2Thresh_off;
1122 aniState->iniDef.m2CountThr : m2CountThr_off;
1123 m2CountThrLow = on ?
1124 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1125 m1ThreshLowExt = on ?
1126 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1127 m2ThreshLowExt = on ?
1128 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1130 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1132 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1134 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1135 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1137 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1138 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1140 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1141 AR_PHY_SFCORR_M1_THRESH,
1143 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1144 AR_PHY_SFCORR_M2_THRESH,
1146 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1147 AR_PHY_SFCORR_M2COUNT_THR,
1149 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1150 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1152 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1153 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1155 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1156 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1158 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1159 AR_PHY_SFCORR_EXT_M1_THRESH,
1161 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1162 AR_PHY_SFCORR_EXT_M2_THRESH,
1166 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1167 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1169 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1170 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1172 if (on != aniState->ofdmWeakSigDetect) {
1173 ath_dbg(common, ANI,
1174 "** ch %d: ofdm weak signal: %s=>%s\n",
1176 aniState->ofdmWeakSigDetect ?
1180 ah->stats.ast_ani_ofdmon++;
1182 ah->stats.ast_ani_ofdmoff++;
1183 aniState->ofdmWeakSigDetect = on;
1187 case ATH9K_ANI_FIRSTEP_LEVEL:{
1190 if (level >= ARRAY_SIZE(firstep_table)) {
1191 ath_dbg(common, ANI,
1192 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1193 level, ARRAY_SIZE(firstep_table));
1198 * make register setting relative to default
1199 * from INI file & cap value
1201 value = firstep_table[level] -
1202 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1203 aniState->iniDef.firstep;
1204 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1205 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1206 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1207 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1208 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1209 AR_PHY_FIND_SIG_FIRSTEP,
1212 * we need to set first step low register too
1213 * make register setting relative to default
1214 * from INI file & cap value
1216 value2 = firstep_table[level] -
1217 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1218 aniState->iniDef.firstepLow;
1219 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1220 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1221 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1222 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1224 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1225 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1227 if (level != aniState->firstepLevel) {
1228 ath_dbg(common, ANI,
1229 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1231 aniState->firstepLevel,
1233 ATH9K_ANI_FIRSTEP_LVL,
1235 aniState->iniDef.firstep);
1236 ath_dbg(common, ANI,
1237 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1239 aniState->firstepLevel,
1241 ATH9K_ANI_FIRSTEP_LVL,
1243 aniState->iniDef.firstepLow);
1244 if (level > aniState->firstepLevel)
1245 ah->stats.ast_ani_stepup++;
1246 else if (level < aniState->firstepLevel)
1247 ah->stats.ast_ani_stepdown++;
1248 aniState->firstepLevel = level;
1252 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1255 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1256 ath_dbg(common, ANI,
1257 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1258 level, ARRAY_SIZE(cycpwrThr1_table));
1262 * make register setting relative to default
1263 * from INI file & cap value
1265 value = cycpwrThr1_table[level] -
1266 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1267 aniState->iniDef.cycpwrThr1;
1268 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1269 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1270 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1271 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1272 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1273 AR_PHY_TIMING5_CYCPWR_THR1,
1277 * set AR_PHY_EXT_CCA for extension channel
1278 * make register setting relative to default
1279 * from INI file & cap value
1281 value2 = cycpwrThr1_table[level] -
1282 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1283 aniState->iniDef.cycpwrThr1Ext;
1284 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1285 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1286 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1287 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1288 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1289 AR_PHY_EXT_CYCPWR_THR1, value2);
1291 if (level != aniState->spurImmunityLevel) {
1292 ath_dbg(common, ANI,
1293 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1295 aniState->spurImmunityLevel,
1297 ATH9K_ANI_SPUR_IMMUNE_LVL,
1299 aniState->iniDef.cycpwrThr1);
1300 ath_dbg(common, ANI,
1301 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1303 aniState->spurImmunityLevel,
1305 ATH9K_ANI_SPUR_IMMUNE_LVL,
1307 aniState->iniDef.cycpwrThr1Ext);
1308 if (level > aniState->spurImmunityLevel)
1309 ah->stats.ast_ani_spurup++;
1310 else if (level < aniState->spurImmunityLevel)
1311 ah->stats.ast_ani_spurdown++;
1312 aniState->spurImmunityLevel = level;
1316 case ATH9K_ANI_MRC_CCK:{
1318 * is_on == 1 means MRC CCK ON (default, less noise imm)
1319 * is_on == 0 means MRC CCK is OFF (more noise imm)
1321 bool is_on = param ? 1 : 0;
1323 if (ah->caps.rx_chainmask == 1)
1326 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1327 AR_PHY_MRC_CCK_ENABLE, is_on);
1328 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1329 AR_PHY_MRC_CCK_MUX_REG, is_on);
1330 if (is_on != aniState->mrcCCK) {
1331 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1333 aniState->mrcCCK ? "on" : "off",
1334 is_on ? "on" : "off");
1336 ah->stats.ast_ani_ccklow++;
1338 ah->stats.ast_ani_cckhigh++;
1339 aniState->mrcCCK = is_on;
1344 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1348 ath_dbg(common, ANI,
1349 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1350 aniState->spurImmunityLevel,
1351 aniState->ofdmWeakSigDetect ? "on" : "off",
1352 aniState->firstepLevel,
1353 aniState->mrcCCK ? "on" : "off",
1354 aniState->listenTime,
1355 aniState->ofdmPhyErrCount,
1356 aniState->cckPhyErrCount);
1360 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1361 int16_t nfarray[NUM_NF_READINGS])
1363 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1364 #define AR_PHY_CH_MINCCA_PWR_S 20
1365 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1366 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1371 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1372 if (ah->rxchainmask & BIT(i)) {
1373 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1374 AR_PHY_CH_MINCCA_PWR);
1375 nfarray[i] = sign_extend32(nf, 8);
1377 if (IS_CHAN_HT40(ah->curchan)) {
1378 u8 ext_idx = AR9300_MAX_CHAINS + i;
1380 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1381 AR_PHY_CH_EXT_MINCCA_PWR);
1382 nfarray[ext_idx] = sign_extend32(nf, 8);
1388 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1390 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1391 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1392 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1393 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1394 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1395 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1397 if (AR_SREV_9330(ah))
1398 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1400 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1401 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1402 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1403 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1404 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1409 * Initialize the ANI register values with default (ini) values.
1410 * This routine is called during a (full) hardware reset after
1411 * all the registers are initialised from the INI.
1413 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1415 struct ar5416AniState *aniState;
1416 struct ath_common *common = ath9k_hw_common(ah);
1417 struct ath9k_channel *chan = ah->curchan;
1418 struct ath9k_ani_default *iniDef;
1421 aniState = &ah->ani;
1422 iniDef = &aniState->iniDef;
1424 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1425 ah->hw_version.macVersion,
1426 ah->hw_version.macRev,
1430 val = REG_READ(ah, AR_PHY_SFCORR);
1431 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1432 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1433 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1435 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1436 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1437 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1438 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1440 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1441 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1442 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1443 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1444 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1445 iniDef->firstep = REG_READ_FIELD(ah,
1447 AR_PHY_FIND_SIG_FIRSTEP);
1448 iniDef->firstepLow = REG_READ_FIELD(ah,
1449 AR_PHY_FIND_SIG_LOW,
1450 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1451 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1453 AR_PHY_TIMING5_CYCPWR_THR1);
1454 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1456 AR_PHY_EXT_CYCPWR_THR1);
1458 /* these levels just got reset to defaults by the INI */
1459 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1460 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1461 aniState->ofdmWeakSigDetect = true;
1462 aniState->mrcCCK = true;
1465 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1466 struct ath_hw_radar_conf *conf)
1468 unsigned int regWrites = 0;
1469 u32 radar_0 = 0, radar_1;
1472 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1476 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1477 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1478 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1479 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1480 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1481 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1483 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1484 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1485 AR_PHY_RADAR_1_RELPWR_THRESH);
1486 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1487 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1488 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1489 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1490 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1492 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1493 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1494 if (conf->ext_channel)
1495 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1497 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1499 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1500 REG_WRITE_ARRAY(&ah->ini_dfs,
1501 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1505 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1507 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1509 conf->fir_power = -28;
1510 conf->radar_rssi = 0;
1511 conf->pulse_height = 10;
1512 conf->pulse_rssi = 15;
1513 conf->pulse_inband = 8;
1514 conf->pulse_maxlen = 255;
1515 conf->pulse_inband_step = 12;
1516 conf->radar_inband = 8;
1519 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1520 struct ath_hw_antcomb_conf *antconf)
1524 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1525 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1526 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1527 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1528 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1529 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1530 AR_PHY_ANT_FAST_DIV_BIAS_S;
1532 if (AR_SREV_9330_11(ah)) {
1533 antconf->lna1_lna2_switch_delta = -1;
1534 antconf->lna1_lna2_delta = -9;
1535 antconf->div_group = 1;
1536 } else if (AR_SREV_9485(ah)) {
1537 antconf->lna1_lna2_switch_delta = -1;
1538 antconf->lna1_lna2_delta = -9;
1539 antconf->div_group = 2;
1540 } else if (AR_SREV_9565(ah)) {
1541 antconf->lna1_lna2_switch_delta = 3;
1542 antconf->lna1_lna2_delta = -9;
1543 antconf->div_group = 3;
1545 antconf->lna1_lna2_switch_delta = -1;
1546 antconf->lna1_lna2_delta = -3;
1547 antconf->div_group = 0;
1551 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1552 struct ath_hw_antcomb_conf *antconf)
1556 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1557 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1558 AR_PHY_ANT_DIV_ALT_LNACONF |
1559 AR_PHY_ANT_FAST_DIV_BIAS |
1560 AR_PHY_ANT_DIV_MAIN_GAINTB |
1561 AR_PHY_ANT_DIV_ALT_GAINTB);
1562 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1563 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1564 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1565 & AR_PHY_ANT_DIV_ALT_LNACONF);
1566 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1567 & AR_PHY_ANT_FAST_DIV_BIAS);
1568 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1569 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1570 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1571 & AR_PHY_ANT_DIV_ALT_GAINTB);
1573 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1576 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1578 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1580 struct ath9k_hw_capabilities *pCap = &ah->caps;
1584 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1587 if (AR_SREV_9485(ah)) {
1588 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1589 IS_CHAN_2GHZ(ah->curchan));
1591 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1592 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1594 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1595 AR_SWITCH_TABLE_COM2_ALL, regval);
1598 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1601 * Set MAIN/ALT LNA conf.
1602 * Set MAIN/ALT gain_tb.
1604 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1605 regval &= (~AR_ANT_DIV_CTRL_ALL);
1606 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1607 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1609 if (AR_SREV_9485_11_OR_LATER(ah)) {
1611 * Enable LNA diversity.
1613 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1614 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1615 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1617 regval |= AR_ANT_DIV_ENABLE;
1619 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1622 * Enable fast antenna diversity.
1624 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1625 regval &= ~AR_FAST_DIV_ENABLE;
1626 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1628 regval |= AR_FAST_DIV_ENABLE;
1630 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1632 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1633 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1634 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1635 AR_PHY_ANT_DIV_ALT_LNACONF |
1636 AR_PHY_ANT_DIV_ALT_GAINTB |
1637 AR_PHY_ANT_DIV_MAIN_GAINTB));
1639 * Set MAIN to LNA1 and ALT to LNA2 at the
1642 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1643 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1644 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1645 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1646 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1648 } else if (AR_SREV_9565(ah)) {
1650 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1652 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1653 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1654 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1655 AR_FAST_DIV_ENABLE);
1656 REG_SET_BIT(ah, AR_PHY_RESTART,
1657 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1658 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1659 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1661 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1663 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1664 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1665 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1666 AR_FAST_DIV_ENABLE);
1667 REG_CLR_BIT(ah, AR_PHY_RESTART,
1668 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1669 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1670 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1672 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1673 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1674 AR_PHY_ANT_DIV_ALT_LNACONF |
1675 AR_PHY_ANT_DIV_MAIN_GAINTB |
1676 AR_PHY_ANT_DIV_ALT_GAINTB);
1677 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1678 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1679 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1680 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1681 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1688 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1689 struct ath9k_channel *chan,
1692 unsigned int regWrites = 0;
1693 u32 modesIndex, txgain_index;
1695 if (IS_CHAN_5GHZ(chan))
1696 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1698 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1700 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1702 if (modesIndex == ah->modes_index) {
1703 *ini_reloaded = false;
1707 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1708 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1709 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1710 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1712 if (AR_SREV_9462_20_OR_LATER(ah))
1713 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1716 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
1718 if (AR_SREV_9462_20_OR_LATER(ah)) {
1720 * CUS217 mix LNA mode.
1722 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1723 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1725 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1726 modesIndex, regWrites);
1731 * For 5GHz channels requiring Fast Clock, apply
1732 * different modal values.
1734 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1735 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1737 if (AR_SREV_9565(ah))
1738 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1743 if (chan->channel == 2484)
1744 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1746 ah->modes_index = modesIndex;
1747 *ini_reloaded = true;
1750 ar9003_hw_set_rfmode(ah, chan);
1754 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1755 struct ath_spec_scan *param)
1759 if (!param->enabled) {
1760 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1761 AR_PHY_SPECTRAL_SCAN_ENABLE);
1765 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1766 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1768 /* on AR93xx and newer, count = 0 will make the the chip send
1769 * spectral samples endlessly. Check if this really was intended,
1770 * and fix otherwise.
1772 count = param->count;
1775 else if (param->count == 0)
1778 if (param->short_repeat)
1779 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1780 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1782 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1783 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1785 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1786 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1787 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1788 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1789 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1790 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1795 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1797 /* Activate spectral scan */
1798 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1799 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1802 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1804 struct ath_common *common = ath9k_hw_common(ah);
1806 /* Poll for spectral scan complete */
1807 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1808 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1809 0, AH_WAIT_TIMEOUT)) {
1810 ath_err(common, "spectral scan wait failed\n");
1815 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1817 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1818 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1819 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1820 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1821 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1822 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1823 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1824 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1825 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1828 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1830 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1831 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1834 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1836 static s16 p_pwr_array[ar9300RateSize] = { 0 };
1839 if (txpower <= MAX_RATE_POWER) {
1840 for (i = 0; i < ar9300RateSize; i++)
1841 p_pwr_array[i] = txpower;
1843 for (i = 0; i < ar9300RateSize; i++)
1844 p_pwr_array[i] = MAX_RATE_POWER;
1847 REG_WRITE(ah, 0xa458, 0);
1849 REG_WRITE(ah, 0xa3c0,
1850 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1851 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1852 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) |
1853 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1854 REG_WRITE(ah, 0xa3c4,
1855 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) |
1856 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) |
1857 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) |
1858 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1859 REG_WRITE(ah, 0xa3c8,
1860 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1861 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1862 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1863 REG_WRITE(ah, 0xa3cc,
1864 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) |
1865 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) |
1866 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) |
1867 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1868 REG_WRITE(ah, 0xa3d0,
1869 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) |
1870 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) |
1871 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1872 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1873 REG_WRITE(ah, 0xa3d4,
1874 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1875 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1876 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) |
1877 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0));
1878 REG_WRITE(ah, 0xa3e4,
1879 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1880 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1881 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) |
1882 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0));
1883 REG_WRITE(ah, 0xa3e8,
1884 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1885 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1886 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) |
1887 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0));
1888 REG_WRITE(ah, 0xa3d8,
1889 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1890 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1891 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1892 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1893 REG_WRITE(ah, 0xa3dc,
1894 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1895 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1896 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) |
1897 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0));
1898 REG_WRITE(ah, 0xa3ec,
1899 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1900 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1901 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) |
1902 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
1905 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
1907 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1908 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1909 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
1910 rate_array[ALL_TARGET_LEGACY_5S]);
1911 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
1912 rate_array[ALL_TARGET_LEGACY_11S]);
1915 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
1920 for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
1921 /* OFDM rate to power table idx */
1922 j = ofdm2pwr[i - offset];
1923 ah->tx_power[i] = rate_array[j];
1927 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
1928 int ss_offset, int ds_offset,
1929 int ts_offset, bool is_40)
1931 int i, j, mcs_idx = 0;
1932 const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;
1934 for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
1935 j = mcs2pwr[mcs_idx];
1936 ah->tx_power[i] = rate_array[j];
1940 for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
1941 j = mcs2pwr[mcs_idx];
1942 ah->tx_power[i] = rate_array[j];
1946 for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
1947 j = mcs2pwr[mcs_idx];
1948 ah->tx_power[i] = rate_array[j];
1953 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
1954 int ds_offset, int ts_offset)
1956 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
1957 AR9300_HT_SS_RATES);
1958 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
1959 AR9300_HT_DS_RATES);
1960 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
1961 AR9300_HT_TS_RATES);
1964 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1965 struct ath9k_channel *chan)
1967 if (IS_CHAN_5GHZ(chan)) {
1968 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1969 AR9300_11NA_OFDM_SHIFT);
1970 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1971 ar9003_hw_init_txpower_ht(ah, rate_array,
1972 AR9300_11NA_HT_SS_SHIFT,
1973 AR9300_11NA_HT_DS_SHIFT,
1974 AR9300_11NA_HT_TS_SHIFT,
1975 IS_CHAN_HT40(chan));
1976 ar9003_hw_init_txpower_stbc(ah,
1977 AR9300_11NA_HT_SS_SHIFT,
1978 AR9300_11NA_HT_DS_SHIFT,
1979 AR9300_11NA_HT_TS_SHIFT);
1982 ar9003_hw_init_txpower_cck(ah, rate_array);
1983 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1984 AR9300_11NG_OFDM_SHIFT);
1985 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1986 ar9003_hw_init_txpower_ht(ah, rate_array,
1987 AR9300_11NG_HT_SS_SHIFT,
1988 AR9300_11NG_HT_DS_SHIFT,
1989 AR9300_11NG_HT_TS_SHIFT,
1990 IS_CHAN_HT40(chan));
1991 ar9003_hw_init_txpower_stbc(ah,
1992 AR9300_11NG_HT_SS_SHIFT,
1993 AR9300_11NG_HT_DS_SHIFT,
1994 AR9300_11NG_HT_TS_SHIFT);
1999 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
2001 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
2002 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
2003 static const u32 ar9300_cca_regs[6] = {
2012 priv_ops->rf_set_freq = ar9003_hw_set_channel;
2013 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
2015 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
2017 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
2019 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
2021 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
2022 priv_ops->init_bb = ar9003_hw_init_bb;
2023 priv_ops->process_ini = ar9003_hw_process_ini;
2024 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
2025 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
2026 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
2027 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
2028 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
2029 priv_ops->ani_control = ar9003_hw_ani_control;
2030 priv_ops->do_getnf = ar9003_hw_do_getnf;
2031 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
2032 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
2033 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
2035 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
2036 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
2037 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
2038 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
2039 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
2041 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2042 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
2044 ops->tx99_start = ar9003_hw_tx99_start;
2045 ops->tx99_stop = ar9003_hw_tx99_stop;
2046 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
2048 ar9003_hw_set_nf_limits(ah);
2049 ar9003_hw_set_radar_conf(ah);
2050 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
2054 * Baseband Watchdog signatures:
2056 * 0x04000539: BB hang when operating in HT40 DFS Channel.
2057 * Full chip reset is not required, but a recovery
2058 * mechanism is needed.
2060 * 0x1300000a: Related to CAC deafness.
2061 * Chip reset is not required.
2063 * 0x0400000a: Related to CAC deafness.
2064 * Full chip reset is required.
2066 * 0x04000b09: RX state machine gets into an illegal state
2067 * when a packet with unsupported rate is received.
2068 * Full chip reset is required and PHY_RESTART has
2071 * 0x04000409: Packet stuck on receive.
2072 * Full chip reset is required for all chips except AR9340.
2076 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
2078 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
2082 switch(ah->bb_watchdog_last_status) {
2084 val = REG_READ(ah, AR_PHY_RADAR_0);
2085 val &= (~AR_PHY_RADAR_0_FIRPWR);
2086 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
2087 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2089 val = REG_READ(ah, AR_PHY_RADAR_0);
2090 val &= ~AR_PHY_RADAR_0_FIRPWR;
2091 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
2092 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2101 if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
2107 * For any other unknown signatures, do a
2113 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
2115 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
2117 struct ath_common *common = ath9k_hw_common(ah);
2118 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
2119 u32 val, idle_count;
2122 /* disable IRQ, disable chip-reset for BB panic */
2123 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2124 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
2125 ~(AR_PHY_WATCHDOG_RST_ENABLE |
2126 AR_PHY_WATCHDOG_IRQ_ENABLE));
2128 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
2129 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2130 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
2131 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2132 AR_PHY_WATCHDOG_IDLE_ENABLE));
2134 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
2138 /* enable IRQ, disable chip-reset for BB watchdog */
2139 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
2140 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2141 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
2142 ~AR_PHY_WATCHDOG_RST_ENABLE);
2144 /* bound limit to 10 secs */
2145 if (idle_tmo_ms > 10000)
2146 idle_tmo_ms = 10000;
2149 * The time unit for watchdog event is 2^15 44/88MHz cycles.
2151 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
2152 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
2154 * Given we use fast clock now in 5 GHz, these time units should
2155 * be common for both 2 GHz and 5 GHz.
2157 idle_count = (100 * idle_tmo_ms) / 74;
2158 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
2159 idle_count = (100 * idle_tmo_ms) / 37;
2162 * enable watchdog in non-IDLE mode, disable in IDLE mode,
2163 * set idle time-out.
2165 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2166 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2167 AR_PHY_WATCHDOG_IDLE_MASK |
2168 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
2170 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
2174 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
2177 * we want to avoid printing in ISR context so we save the
2178 * watchdog status to be printed later in bottom half context.
2180 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
2183 * the watchdog timer should reset on status read but to be sure
2184 * sure we write 0 to the watchdog status bit.
2186 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
2187 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
2190 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
2192 struct ath_common *common = ath9k_hw_common(ah);
2195 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
2198 status = ah->bb_watchdog_last_status;
2199 ath_dbg(common, RESET,
2200 "\n==== BB update: BB status=0x%08x ====\n", status);
2201 ath_dbg(common, RESET,
2202 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
2203 MS(status, AR_PHY_WATCHDOG_INFO),
2204 MS(status, AR_PHY_WATCHDOG_DET_HANG),
2205 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
2206 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
2207 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
2208 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
2209 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
2210 MS(status, AR_PHY_WATCHDOG_AGC_SM),
2211 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
2213 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
2214 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2215 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
2216 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
2217 REG_READ(ah, AR_PHY_GEN_CTRL));
2219 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
2220 if (common->cc_survey.cycles)
2221 ath_dbg(common, RESET,
2222 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
2223 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
2225 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
2227 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
2229 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2234 /* While receiving unsupported rate frame rx state machine
2235 * gets into a state 0xb and if phy_restart happens in that
2236 * state, BB would go hang. If RXSM is in 0xb state after
2237 * first bb panic, ensure to disable the phy_restart.
2239 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2241 if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2242 ah->bb_hang_rx_ofdm = true;
2243 val = REG_READ(ah, AR_PHY_RESTART);
2244 val &= ~AR_PHY_RESTART_ENA;
2245 REG_WRITE(ah, AR_PHY_RESTART, val);
2248 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);