1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
11 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
28 "host2reo-re-injection",
30 "host2rxdma-monitor-ring3",
31 "host2rxdma-monitor-ring2",
32 "host2rxdma-monitor-ring1",
34 "wbm2host-rx-release",
36 "reo2host-destination-ring4",
37 "reo2host-destination-ring3",
38 "reo2host-destination-ring2",
39 "reo2host-destination-ring1",
40 "rxdma2host-monitor-destination-mac3",
41 "rxdma2host-monitor-destination-mac2",
42 "rxdma2host-monitor-destination-mac1",
43 "ppdu-end-interrupts-mac3",
44 "ppdu-end-interrupts-mac2",
45 "ppdu-end-interrupts-mac1",
46 "rxdma2host-monitor-status-ring-mac3",
47 "rxdma2host-monitor-status-ring-mac2",
48 "rxdma2host-monitor-status-ring-mac1",
49 "host2rxdma-host-buf-ring-mac3",
50 "host2rxdma-host-buf-ring-mac2",
51 "host2rxdma-host-buf-ring-mac1",
52 "rxdma2host-destination-ring-mac3",
53 "rxdma2host-destination-ring-mac2",
54 "rxdma2host-destination-ring-mac1",
55 "host2tcl-input-ring4",
56 "host2tcl-input-ring3",
57 "host2tcl-input-ring2",
58 "host2tcl-input-ring1",
59 "wbm2host-tx-completions-ring3",
60 "wbm2host-tx-completions-ring2",
61 "wbm2host-tx-completions-ring1",
62 "tcl2host-status-ring",
65 static const struct ath11k_msi_config ath11k_msi_config[] = {
69 .users = (struct ath11k_msi_user[]) {
70 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
71 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
72 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
73 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
75 .hw_rev = ATH11K_HW_QCA6390_HW20,
80 .users = (struct ath11k_msi_user[]) {
81 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
82 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
83 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
85 .hw_rev = ATH11K_HW_QCN9074_HW10,
90 .users = (struct ath11k_msi_user[]) {
91 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
92 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
93 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
94 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
96 .hw_rev = ATH11K_HW_WCN6855_HW20,
101 .users = (struct ath11k_msi_user[]) {
102 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
103 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
104 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
105 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
107 .hw_rev = ATH11K_HW_WCN6855_HW21,
112 .users = (struct ath11k_msi_user[]) {
113 { .name = "CE", .num_vectors = 10, .base_vector = 0 },
114 { .name = "DP", .num_vectors = 18, .base_vector = 10 },
116 .hw_rev = ATH11K_HW_WCN6750_HW10,
120 int ath11k_pcic_init_msi_config(struct ath11k_base *ab)
122 const struct ath11k_msi_config *msi_config;
125 for (i = 0; i < ARRAY_SIZE(ath11k_msi_config); i++) {
126 msi_config = &ath11k_msi_config[i];
128 if (msi_config->hw_rev == ab->hw_rev)
132 if (i == ARRAY_SIZE(ath11k_msi_config)) {
133 ath11k_err(ab, "failed to fetch msi config, unsupported hw version: 0x%x\n",
138 ab->pci.msi.config = msi_config;
141 EXPORT_SYMBOL(ath11k_pcic_init_msi_config);
143 static inline u32 ath11k_pcic_get_window_start(struct ath11k_base *ab,
146 u32 window_start = 0;
148 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
149 window_start = ab->hw_params.dp_window_idx * ATH11K_PCI_WINDOW_START;
150 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
151 ATH11K_PCI_WINDOW_RANGE_MASK)
152 window_start = ab->hw_params.ce_window_idx * ATH11K_PCI_WINDOW_START;
157 void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
162 /* for offset beyond BAR + 4K - 32, may
163 * need to wakeup the device to access.
165 if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
166 offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->wakeup)
167 ret = ab->pci.ops->wakeup(ab);
169 if (offset < ATH11K_PCI_WINDOW_START) {
170 iowrite32(value, ab->mem + offset);
171 } else if (ab->hw_params.static_window_map) {
172 window_start = ath11k_pcic_get_window_start(ab, offset);
173 iowrite32(value, ab->mem + window_start +
174 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
175 } else if (ab->pci.ops->window_write32) {
176 ab->pci.ops->window_write32(ab, offset, value);
179 if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
180 offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->release &&
182 ab->pci.ops->release(ab);
184 EXPORT_SYMBOL(ath11k_pcic_write32);
186 u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
192 /* for offset beyond BAR + 4K - 32, may
193 * need to wakeup the device to access.
195 if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
196 offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->wakeup)
197 ret = ab->pci.ops->wakeup(ab);
199 if (offset < ATH11K_PCI_WINDOW_START) {
200 val = ioread32(ab->mem + offset);
201 } else if (ab->hw_params.static_window_map) {
202 window_start = ath11k_pcic_get_window_start(ab, offset);
203 val = ioread32(ab->mem + window_start +
204 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
205 } else if (ab->pci.ops->window_read32) {
206 val = ab->pci.ops->window_read32(ab, offset);
209 if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
210 offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->release &&
212 ab->pci.ops->release(ab);
216 EXPORT_SYMBOL(ath11k_pcic_read32);
218 void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
221 *msi_addr_lo = ab->pci.msi.addr_lo;
222 *msi_addr_hi = ab->pci.msi.addr_hi;
224 EXPORT_SYMBOL(ath11k_pcic_get_msi_address);
226 int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
227 int *num_vectors, u32 *user_base_data,
230 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
233 for (idx = 0; idx < msi_config->total_users; idx++) {
234 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
235 *num_vectors = msi_config->users[idx].num_vectors;
236 *base_vector = msi_config->users[idx].base_vector;
237 *user_base_data = *base_vector + ab->pci.msi.ep_base_data;
239 ath11k_dbg(ab, ATH11K_DBG_PCI,
240 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
241 user_name, *num_vectors, *user_base_data,
248 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
252 EXPORT_SYMBOL(ath11k_pcic_get_user_msi_assignment);
254 void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx)
258 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
259 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
267 *msi_idx = msi_data_idx;
269 EXPORT_SYMBOL(ath11k_pcic_get_ce_msi_idx);
271 static void ath11k_pcic_free_ext_irq(struct ath11k_base *ab)
275 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
276 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
278 for (j = 0; j < irq_grp->num_irq; j++)
279 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
281 netif_napi_del(&irq_grp->napi);
285 void ath11k_pcic_free_irq(struct ath11k_base *ab)
289 for (i = 0; i < ab->hw_params.ce_count; i++) {
290 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
292 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
293 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
296 ath11k_pcic_free_ext_irq(ab);
298 EXPORT_SYMBOL(ath11k_pcic_free_irq);
300 static void ath11k_pcic_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
304 /* In case of one MSI vector, we handle irq enable/disable in a
305 * uniform way since we only have one irq
307 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
310 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
311 enable_irq(ab->irq_num[irq_idx]);
314 static void ath11k_pcic_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
318 /* In case of one MSI vector, we handle irq enable/disable in a
319 * uniform way since we only have one irq
321 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
324 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
325 disable_irq_nosync(ab->irq_num[irq_idx]);
328 static void ath11k_pcic_ce_irqs_disable(struct ath11k_base *ab)
332 clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
334 for (i = 0; i < ab->hw_params.ce_count; i++) {
335 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
337 ath11k_pcic_ce_irq_disable(ab, i);
341 static void ath11k_pcic_sync_ce_irqs(struct ath11k_base *ab)
346 for (i = 0; i < ab->hw_params.ce_count; i++) {
347 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
350 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
351 synchronize_irq(ab->irq_num[irq_idx]);
355 static void ath11k_pcic_ce_tasklet(struct tasklet_struct *t)
357 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
358 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
360 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
362 enable_irq(ce_pipe->ab->irq_num[irq_idx]);
365 static irqreturn_t ath11k_pcic_ce_interrupt_handler(int irq, void *arg)
367 struct ath11k_ce_pipe *ce_pipe = arg;
368 struct ath11k_base *ab = ce_pipe->ab;
369 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
371 if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
374 /* last interrupt received for this CE */
375 ce_pipe->timestamp = jiffies;
377 disable_irq_nosync(ab->irq_num[irq_idx]);
379 tasklet_schedule(&ce_pipe->intr_tq);
384 static void ath11k_pcic_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
386 struct ath11k_base *ab = irq_grp->ab;
389 /* In case of one MSI vector, we handle irq enable/disable
390 * in a uniform way since we only have one irq
392 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
395 for (i = 0; i < irq_grp->num_irq; i++)
396 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
399 static void __ath11k_pcic_ext_irq_disable(struct ath11k_base *sc)
403 clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &sc->dev_flags);
405 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
406 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
408 ath11k_pcic_ext_grp_disable(irq_grp);
410 if (irq_grp->napi_enabled) {
411 napi_synchronize(&irq_grp->napi);
412 napi_disable(&irq_grp->napi);
413 irq_grp->napi_enabled = false;
418 static void ath11k_pcic_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
420 struct ath11k_base *ab = irq_grp->ab;
423 /* In case of one MSI vector, we handle irq enable/disable in a
424 * uniform way since we only have one irq
426 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
429 for (i = 0; i < irq_grp->num_irq; i++)
430 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
433 void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab)
437 set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
439 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
440 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
442 if (!irq_grp->napi_enabled) {
443 napi_enable(&irq_grp->napi);
444 irq_grp->napi_enabled = true;
446 ath11k_pcic_ext_grp_enable(irq_grp);
449 EXPORT_SYMBOL(ath11k_pcic_ext_irq_enable);
451 static void ath11k_pcic_sync_ext_irqs(struct ath11k_base *ab)
455 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
456 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
458 for (j = 0; j < irq_grp->num_irq; j++) {
459 irq_idx = irq_grp->irqs[j];
460 synchronize_irq(ab->irq_num[irq_idx]);
465 void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab)
467 __ath11k_pcic_ext_irq_disable(ab);
468 ath11k_pcic_sync_ext_irqs(ab);
470 EXPORT_SYMBOL(ath11k_pcic_ext_irq_disable);
472 static int ath11k_pcic_ext_grp_napi_poll(struct napi_struct *napi, int budget)
474 struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
475 struct ath11k_ext_irq_grp,
477 struct ath11k_base *ab = irq_grp->ab;
481 work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
482 if (work_done < budget) {
483 napi_complete_done(napi, work_done);
484 for (i = 0; i < irq_grp->num_irq; i++)
485 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
488 if (work_done > budget)
494 static irqreturn_t ath11k_pcic_ext_interrupt_handler(int irq, void *arg)
496 struct ath11k_ext_irq_grp *irq_grp = arg;
497 struct ath11k_base *ab = irq_grp->ab;
500 if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
503 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
505 /* last interrupt received for this group */
506 irq_grp->timestamp = jiffies;
508 for (i = 0; i < irq_grp->num_irq; i++)
509 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
511 napi_schedule(&irq_grp->napi);
517 ath11k_pcic_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
519 if (!ab->pci.ops->get_msi_irq) {
520 WARN_ONCE(1, "get_msi_irq pci op not defined");
524 return ab->pci.ops->get_msi_irq(ab, vector);
527 static int ath11k_pcic_ext_irq_config(struct ath11k_base *ab)
529 int i, j, ret, num_vectors = 0;
530 u32 user_base_data = 0, base_vector = 0;
531 unsigned long irq_flags;
533 ret = ath11k_pcic_get_user_msi_assignment(ab, "DP", &num_vectors,
539 irq_flags = IRQF_SHARED;
540 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
541 irq_flags |= IRQF_NOBALANCING;
543 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
544 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
549 init_dummy_netdev(&irq_grp->napi_ndev);
550 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
551 ath11k_pcic_ext_grp_napi_poll, NAPI_POLL_WEIGHT);
553 if (ab->hw_params.ring_mask->tx[i] ||
554 ab->hw_params.ring_mask->rx[i] ||
555 ab->hw_params.ring_mask->rx_err[i] ||
556 ab->hw_params.ring_mask->rx_wbm_rel[i] ||
557 ab->hw_params.ring_mask->reo_status[i] ||
558 ab->hw_params.ring_mask->rxdma2host[i] ||
559 ab->hw_params.ring_mask->host2rxdma[i] ||
560 ab->hw_params.ring_mask->rx_mon_status[i]) {
564 irq_grp->num_irq = num_irq;
565 irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i;
567 for (j = 0; j < irq_grp->num_irq; j++) {
568 int irq_idx = irq_grp->irqs[j];
569 int vector = (i % num_vectors) + base_vector;
570 int irq = ath11k_pcic_get_msi_irq(ab, vector);
575 ab->irq_num[irq_idx] = irq;
577 ath11k_dbg(ab, ATH11K_DBG_PCI,
578 "irq:%d group:%d\n", irq, i);
580 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
581 ret = request_irq(irq, ath11k_pcic_ext_interrupt_handler,
582 irq_flags, "DP_EXT_IRQ", irq_grp);
584 ath11k_err(ab, "failed request irq %d: %d\n",
589 ath11k_pcic_ext_grp_disable(irq_grp);
595 int ath11k_pcic_config_irq(struct ath11k_base *ab)
597 struct ath11k_ce_pipe *ce_pipe;
599 u32 msi_data_count, msi_data_idx;
601 unsigned int msi_data;
602 int irq, i, ret, irq_idx;
603 unsigned long irq_flags;
605 ret = ath11k_pcic_get_user_msi_assignment(ab, "CE", &msi_data_count,
606 &msi_data_start, &msi_irq_start);
610 irq_flags = IRQF_SHARED;
611 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
612 irq_flags |= IRQF_NOBALANCING;
614 /* Configure CE irqs */
615 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
616 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
619 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
620 irq = ath11k_pcic_get_msi_irq(ab, msi_data);
624 ce_pipe = &ab->ce.ce_pipe[i];
626 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
628 tasklet_setup(&ce_pipe->intr_tq, ath11k_pcic_ce_tasklet);
630 ret = request_irq(irq, ath11k_pcic_ce_interrupt_handler,
631 irq_flags, irq_name[irq_idx], ce_pipe);
633 ath11k_err(ab, "failed to request irq %d: %d\n",
638 ab->irq_num[irq_idx] = irq;
641 ath11k_pcic_ce_irq_disable(ab, i);
644 ret = ath11k_pcic_ext_irq_config(ab);
650 EXPORT_SYMBOL(ath11k_pcic_config_irq);
652 void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab)
656 set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
658 for (i = 0; i < ab->hw_params.ce_count; i++) {
659 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
661 ath11k_pcic_ce_irq_enable(ab, i);
664 EXPORT_SYMBOL(ath11k_pcic_ce_irqs_enable);
666 static void ath11k_pcic_kill_tasklets(struct ath11k_base *ab)
670 for (i = 0; i < ab->hw_params.ce_count; i++) {
671 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
673 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
676 tasklet_kill(&ce_pipe->intr_tq);
680 void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab)
682 ath11k_pcic_ce_irqs_disable(ab);
683 ath11k_pcic_sync_ce_irqs(ab);
684 ath11k_pcic_kill_tasklets(ab);
686 EXPORT_SYMBOL(ath11k_pcic_ce_irq_disable_sync);
688 void ath11k_pcic_stop(struct ath11k_base *ab)
690 ath11k_pcic_ce_irq_disable_sync(ab);
691 ath11k_ce_cleanup_pipes(ab);
693 EXPORT_SYMBOL(ath11k_pcic_stop);
695 int ath11k_pcic_start(struct ath11k_base *ab)
697 set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
699 ath11k_pcic_ce_irqs_enable(ab);
700 ath11k_ce_rx_post_buf(ab);
704 EXPORT_SYMBOL(ath11k_pcic_start);
706 int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
707 u8 *ul_pipe, u8 *dl_pipe)
709 const struct service_to_pipe *entry;
710 bool ul_set = false, dl_set = false;
713 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
714 entry = &ab->hw_params.svc_to_ce_map[i];
716 if (__le32_to_cpu(entry->service_id) != service_id)
719 switch (__le32_to_cpu(entry->pipedir)) {
724 *dl_pipe = __le32_to_cpu(entry->pipenum);
729 *ul_pipe = __le32_to_cpu(entry->pipenum);
735 *dl_pipe = __le32_to_cpu(entry->pipenum);
736 *ul_pipe = __le32_to_cpu(entry->pipenum);
743 if (WARN_ON(!ul_set || !dl_set))
748 EXPORT_SYMBOL(ath11k_pcic_map_service_to_pipe);