1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/module.h>
19 #define ATH11K_PCI_BAR_NUM 0
20 #define ATH11K_PCI_DMA_MASK 32
22 #define TCSR_SOC_HW_VERSION 0x0224
23 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
24 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
26 #define QCA6390_DEVICE_ID 0x1101
27 #define QCN9074_DEVICE_ID 0x1104
28 #define WCN6855_DEVICE_ID 0x1103
30 static const struct pci_device_id ath11k_pci_id_table[] = {
31 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
32 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
33 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
37 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
39 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab)
41 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
43 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
46 static void ath11k_pci_bus_release(struct ath11k_base *ab)
48 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
50 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
53 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
55 struct ath11k_base *ab = ab_pci->ab;
57 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
59 lockdep_assert_held(&ab_pci->window_lock);
61 if (window != ab_pci->register_window) {
62 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
63 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
64 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
65 ab_pci->register_window = window;
70 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
72 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
73 u32 window_start = ATH11K_PCI_WINDOW_START;
75 spin_lock_bh(&ab_pci->window_lock);
76 ath11k_pci_select_window(ab_pci, offset);
77 iowrite32(value, ab->mem + window_start +
78 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
79 spin_unlock_bh(&ab_pci->window_lock);
82 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
84 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
85 u32 window_start = ATH11K_PCI_WINDOW_START;
88 spin_lock_bh(&ab_pci->window_lock);
89 ath11k_pci_select_window(ab_pci, offset);
90 val = ioread32(ab->mem + window_start +
91 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
92 spin_unlock_bh(&ab_pci->window_lock);
97 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
99 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
101 return pci_irq_vector(pci_dev, vector);
104 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
105 .wakeup = ath11k_pci_bus_wake_up,
106 .release = ath11k_pci_bus_release,
107 .get_msi_irq = ath11k_pci_get_msi_irq,
108 .window_write32 = ath11k_pci_window_write32,
109 .window_read32 = ath11k_pci_window_read32,
112 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
113 .get_msi_irq = ath11k_pci_get_msi_irq,
114 .window_write32 = ath11k_pci_window_write32,
115 .window_read32 = ath11k_pci_window_read32,
118 static const struct ath11k_msi_config msi_config_one_msi = {
121 .users = (struct ath11k_msi_user[]) {
122 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
123 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
124 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
125 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
129 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
135 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
136 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
137 window = (umac_window << 12) | (ce_window << 6);
139 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
140 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
143 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
147 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
149 val |= PCIE_SOC_GLOBAL_RESET_V;
151 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
153 /* TODO: exact time to sleep is uncertain */
157 /* Need to toggle V bit back otherwise stuck in reset status */
158 val &= ~PCIE_SOC_GLOBAL_RESET_V;
160 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
164 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
165 if (val == 0xffffffff)
166 ath11k_warn(ab, "link down error during global reset\n");
169 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
174 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
175 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val);
177 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
178 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
180 /* TODO: exact time to sleep is uncertain */
183 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
184 * continuing warm path and entering dead loop.
186 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
189 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
190 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
192 /* A read clear register. clear the register to prevent
193 * Q6 from entering wrong code path.
195 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
196 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val);
199 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
200 u32 offset, u32 value, u32 mask)
205 v = ath11k_pcic_read32(ab, offset);
206 if ((v & mask) == value)
209 for (i = 0; i < 10; i++) {
210 ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
212 v = ath11k_pcic_read32(ab, offset);
213 if ((v & mask) == value)
219 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
220 offset, v & mask, value);
225 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
229 ret = ath11k_pci_set_link_reg(ab,
230 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
231 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
232 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
234 ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
238 ret = ath11k_pci_set_link_reg(ab,
239 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
240 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
241 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
243 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
247 ret = ath11k_pci_set_link_reg(ab,
248 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
249 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
250 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
252 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
256 ret = ath11k_pci_set_link_reg(ab,
257 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
258 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
259 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
261 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
268 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
273 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
275 /* PCIE link seems very unstable after the Hot Reset*/
276 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
277 if (val == 0xffffffff)
280 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
281 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
284 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val);
286 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
287 val |= GCC_GCC_PCIE_HOT_RST_VAL;
288 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
289 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
291 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
296 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
298 /* This is a WAR for PCIE Hotreset.
299 * When target receive Hotreset, but will set the interrupt.
300 * So when download SBL again, SBL will open Interrupt and
301 * receive it, and crash immediately.
303 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
306 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
310 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
311 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
312 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
315 static void ath11k_pci_force_wake(struct ath11k_base *ab)
317 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
321 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
326 ath11k_pci_enable_ltssm(ab);
327 ath11k_pci_clear_all_intrs(ab);
328 ath11k_pci_set_wlaon_pwr_ctrl(ab);
329 if (ab->hw_params.fix_l1ss)
330 ath11k_pci_fix_l1ss(ab);
333 ath11k_mhi_clear_vector(ab);
334 ath11k_pci_clear_dbg_registers(ab);
335 ath11k_pci_soc_global_reset(ab);
336 ath11k_mhi_set_mhictrl_reset(ab);
339 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
341 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
343 cfg->tgt_ce = ab->hw_params.target_ce_config;
344 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
346 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
347 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
348 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
350 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
351 &cfg->shadow_reg_v2_len);
354 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
356 struct pci_dev *dev = ab_pci->pdev;
359 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
362 control |= PCI_MSI_FLAGS_ENABLE;
364 control &= ~PCI_MSI_FLAGS_ENABLE;
366 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
369 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci)
371 ath11k_pci_msi_config(ab_pci, true);
374 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
376 ath11k_pci_msi_config(ab_pci, false);
379 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
381 struct ath11k_base *ab = ab_pci->ab;
382 const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
383 struct pci_dev *pci_dev = ab_pci->pdev;
384 struct msi_desc *msi_desc;
388 num_vectors = pci_alloc_irq_vectors(pci_dev,
389 msi_config->total_vectors,
390 msi_config->total_vectors,
392 if (num_vectors == msi_config->total_vectors) {
393 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
395 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
399 if (num_vectors < 0) {
401 goto reset_msi_config;
403 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
404 ab->pci.msi.config = &msi_config_one_msi;
405 ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n");
407 ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
409 ath11k_pci_msi_disable(ab_pci);
411 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
413 ath11k_err(ab, "msi_desc is NULL!\n");
415 goto free_msi_vector;
418 ab->pci.msi.ep_base_data = msi_desc->msg.data;
420 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
421 &ab->pci.msi.addr_lo);
423 if (msi_desc->pci.msi_attrib.is_64) {
424 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
425 &ab->pci.msi.addr_hi);
427 ab->pci.msi.addr_hi = 0;
430 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data);
435 pci_free_irq_vectors(ab_pci->pdev);
441 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci)
443 pci_free_irq_vectors(ab_pci->pdev);
446 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
448 struct msi_desc *msi_desc;
450 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
452 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n");
453 pci_free_irq_vectors(ab_pci->pdev);
457 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
459 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",
460 ab_pci->ab->pci.msi.ep_base_data);
465 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
467 struct ath11k_base *ab = ab_pci->ab;
471 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
472 if (device_id != ab_pci->dev_id) {
473 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
474 device_id, ab_pci->dev_id);
479 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
481 ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
485 ret = pci_enable_device(pdev);
487 ath11k_err(ab, "failed to enable pci device: %d\n", ret);
491 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
493 ath11k_err(ab, "failed to request pci region: %d\n", ret);
497 ret = dma_set_mask_and_coherent(&pdev->dev,
498 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
500 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
501 ATH11K_PCI_DMA_MASK, ret);
505 pci_set_master(pdev);
507 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
508 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
510 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
515 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
519 pci_clear_master(pdev);
521 pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
523 pci_disable_device(pdev);
528 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
530 struct ath11k_base *ab = ab_pci->ab;
531 struct pci_dev *pci_dev = ab_pci->pdev;
533 pci_iounmap(pci_dev, ab->mem);
535 pci_clear_master(pci_dev);
536 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
537 if (pci_is_enabled(pci_dev))
538 pci_disable_device(pci_dev);
541 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
543 struct ath11k_base *ab = ab_pci->ab;
545 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
548 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
550 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
551 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
553 /* disable L0s and L1 */
554 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
555 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
557 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
560 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
562 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
563 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
567 static int ath11k_pci_power_up(struct ath11k_base *ab)
569 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
572 ab_pci->register_window = 0;
573 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
574 ath11k_pci_sw_reset(ab_pci->ab, true);
576 /* Disable ASPM during firmware download due to problems switching
579 ath11k_pci_aspm_disable(ab_pci);
581 ath11k_pci_msi_enable(ab_pci);
583 ret = ath11k_mhi_start(ab_pci);
585 ath11k_err(ab, "failed to start mhi: %d\n", ret);
589 if (ab->hw_params.static_window_map)
590 ath11k_pci_select_static_window(ab_pci);
595 static void ath11k_pci_power_down(struct ath11k_base *ab)
597 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
599 /* restore aspm in case firmware bootup fails */
600 ath11k_pci_aspm_restore(ab_pci);
602 ath11k_pci_force_wake(ab_pci->ab);
604 ath11k_pci_msi_disable(ab_pci);
606 ath11k_mhi_stop(ab_pci);
607 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
608 ath11k_pci_sw_reset(ab_pci->ab, false);
611 static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
613 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
615 return ath11k_mhi_suspend(ar_pci);
618 static int ath11k_pci_hif_resume(struct ath11k_base *ab)
620 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
622 return ath11k_mhi_resume(ar_pci);
625 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
627 ath11k_pcic_ce_irqs_enable(ab);
630 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
632 ath11k_pcic_ce_irq_disable_sync(ab);
635 static int ath11k_pci_start(struct ath11k_base *ab)
637 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
639 /* TODO: for now don't restore ASPM in case of single MSI
640 * vector as MHI register reading in M2 causes system hang.
642 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
643 ath11k_pci_aspm_restore(ab_pci);
645 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
647 ath11k_pcic_start(ab);
652 static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
653 .start = ath11k_pci_start,
654 .stop = ath11k_pcic_stop,
655 .read32 = ath11k_pcic_read32,
656 .write32 = ath11k_pcic_write32,
657 .power_down = ath11k_pci_power_down,
658 .power_up = ath11k_pci_power_up,
659 .suspend = ath11k_pci_hif_suspend,
660 .resume = ath11k_pci_hif_resume,
661 .irq_enable = ath11k_pcic_ext_irq_enable,
662 .irq_disable = ath11k_pcic_ext_irq_disable,
663 .get_msi_address = ath11k_pcic_get_msi_address,
664 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
665 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
666 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
667 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
668 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx,
671 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
675 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
676 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
678 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
681 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
685 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
686 const struct cpumask *m)
688 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
691 return irq_set_affinity_hint(ab_pci->pdev->irq, m);
694 static int ath11k_pci_probe(struct pci_dev *pdev,
695 const struct pci_device_id *pci_dev)
697 struct ath11k_base *ab;
698 struct ath11k_pci *ab_pci;
699 u32 soc_hw_version_major, soc_hw_version_minor, addr;
702 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
705 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
709 ab->dev = &pdev->dev;
710 pci_set_drvdata(pdev, ab);
711 ab_pci = ath11k_pci_priv(ab);
712 ab_pci->dev_id = pci_dev->device;
715 ab->hif.ops = &ath11k_pci_hif_ops;
716 pci_set_drvdata(pdev, ab);
717 spin_lock_init(&ab_pci->window_lock);
719 /* Set fixed_mem_region to true for platforms support reserved memory
720 * from DT. If memory is reserved from DT for FW, ath11k driver need not
723 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr);
725 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
727 ret = ath11k_pci_claim(ab_pci, pdev);
729 ath11k_err(ab, "failed to claim device: %d\n", ret);
733 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
734 pdev->vendor, pdev->device,
735 pdev->subsystem_vendor, pdev->subsystem_device);
737 ab->id.vendor = pdev->vendor;
738 ab->id.device = pdev->device;
739 ab->id.subsystem_vendor = pdev->subsystem_vendor;
740 ab->id.subsystem_device = pdev->subsystem_device;
742 switch (pci_dev->device) {
743 case QCA6390_DEVICE_ID:
744 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
745 &soc_hw_version_minor);
746 switch (soc_hw_version_major) {
748 ab->hw_rev = ATH11K_HW_QCA6390_HW20;
751 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
752 soc_hw_version_major, soc_hw_version_minor);
754 goto err_pci_free_region;
757 ab->pci.ops = &ath11k_pci_ops_qca6390;
759 case QCN9074_DEVICE_ID:
760 ab->pci.ops = &ath11k_pci_ops_qcn9074;
761 ab->hw_rev = ATH11K_HW_QCN9074_HW10;
763 case WCN6855_DEVICE_ID:
764 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
765 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
766 &soc_hw_version_minor);
767 switch (soc_hw_version_major) {
769 switch (soc_hw_version_minor) {
772 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
776 ab->hw_rev = ATH11K_HW_WCN6855_HW21;
779 goto unsupported_wcn6855_soc;
783 unsupported_wcn6855_soc:
784 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
785 soc_hw_version_major, soc_hw_version_minor);
787 goto err_pci_free_region;
790 ab->pci.ops = &ath11k_pci_ops_qca6390;
793 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
796 goto err_pci_free_region;
799 ret = ath11k_pcic_init_msi_config(ab);
801 ath11k_err(ab, "failed to init msi config: %d\n", ret);
802 goto err_pci_free_region;
805 ret = ath11k_pci_alloc_msi(ab_pci);
807 ath11k_err(ab, "failed to enable msi: %d\n", ret);
808 goto err_pci_free_region;
811 ret = ath11k_core_pre_init(ab);
813 goto err_pci_disable_msi;
815 ret = ath11k_mhi_register(ab_pci);
817 ath11k_err(ab, "failed to register mhi: %d\n", ret);
818 goto err_pci_disable_msi;
821 ret = ath11k_hal_srng_init(ab);
823 goto err_mhi_unregister;
825 ret = ath11k_ce_alloc_pipes(ab);
827 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
828 goto err_hal_srng_deinit;
831 ath11k_pci_init_qmi_ce_config(ab);
833 ret = ath11k_pcic_config_irq(ab);
835 ath11k_err(ab, "failed to config irq: %d\n", ret);
839 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
841 ath11k_err(ab, "failed to set irq affinity %d\n", ret);
845 /* kernel may allocate a dummy vector before request_irq and
846 * then allocate a real vector when request_irq is called.
847 * So get msi_data here again to avoid spurious interrupt
848 * as msi_data will configured to srngs.
850 ret = ath11k_pci_config_msi_data(ab_pci);
852 ath11k_err(ab, "failed to config msi_data: %d\n", ret);
853 goto err_irq_affinity_cleanup;
856 ret = ath11k_core_init(ab);
858 ath11k_err(ab, "failed to init core: %d\n", ret);
859 goto err_irq_affinity_cleanup;
863 err_irq_affinity_cleanup:
864 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
867 ath11k_pcic_free_irq(ab);
870 ath11k_ce_free_pipes(ab);
873 ath11k_hal_srng_deinit(ab);
876 ath11k_mhi_unregister(ab_pci);
879 ath11k_pci_free_msi(ab_pci);
882 ath11k_pci_free_region(ab_pci);
885 ath11k_core_free(ab);
890 static void ath11k_pci_remove(struct pci_dev *pdev)
892 struct ath11k_base *ab = pci_get_drvdata(pdev);
893 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
895 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
897 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
898 ath11k_pci_power_down(ab);
899 ath11k_debugfs_soc_destroy(ab);
900 ath11k_qmi_deinit_service(ab);
904 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
906 ath11k_core_deinit(ab);
909 ath11k_mhi_unregister(ab_pci);
911 ath11k_pcic_free_irq(ab);
912 ath11k_pci_free_msi(ab_pci);
913 ath11k_pci_free_region(ab_pci);
915 ath11k_hal_srng_deinit(ab);
916 ath11k_ce_free_pipes(ab);
917 ath11k_core_free(ab);
920 static void ath11k_pci_shutdown(struct pci_dev *pdev)
922 struct ath11k_base *ab = pci_get_drvdata(pdev);
924 ath11k_pci_power_down(ab);
927 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
929 struct ath11k_base *ab = dev_get_drvdata(dev);
932 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
933 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n");
937 ret = ath11k_core_suspend(ab);
939 ath11k_warn(ab, "failed to suspend core: %d\n", ret);
944 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
946 struct ath11k_base *ab = dev_get_drvdata(dev);
949 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
950 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n");
954 ret = ath11k_core_resume(ab);
956 ath11k_warn(ab, "failed to resume core: %d\n", ret);
961 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops,
962 ath11k_pci_pm_suspend,
963 ath11k_pci_pm_resume);
965 static struct pci_driver ath11k_pci_driver = {
966 .name = "ath11k_pci",
967 .id_table = ath11k_pci_id_table,
968 .probe = ath11k_pci_probe,
969 .remove = ath11k_pci_remove,
970 .shutdown = ath11k_pci_shutdown,
972 .driver.pm = &ath11k_pci_pm_ops,
976 static int ath11k_pci_init(void)
980 ret = pci_register_driver(&ath11k_pci_driver);
982 pr_err("failed to register ath11k pci driver: %d\n",
987 module_init(ath11k_pci_init);
989 static void ath11k_pci_exit(void)
991 pci_unregister_driver(&ath11k_pci_driver);
994 module_exit(ath11k_pci_exit);
996 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices");
997 MODULE_LICENSE("Dual BSD/GPL");
999 /* QCA639x 2.0 firmware files */