1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/firmware.h>
11 #include <linux/of_address.h>
12 #include <linux/ioport.h>
20 #define MHI_TIMEOUT_DEFAULT_MS 20000
21 #define RDDM_DUMP_SIZE 0x420000
23 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
32 .doorbell = MHI_DB_BRST_DISABLE,
34 .offload_channel = false,
35 .doorbell_mode_switch = false,
43 .dir = DMA_FROM_DEVICE,
46 .doorbell = MHI_DB_BRST_DISABLE,
48 .offload_channel = false,
49 .doorbell_mode_switch = false,
60 .doorbell = MHI_DB_BRST_DISABLE,
62 .offload_channel = false,
63 .doorbell_mode_switch = false,
71 .dir = DMA_FROM_DEVICE,
74 .doorbell = MHI_DB_BRST_DISABLE,
76 .offload_channel = false,
77 .doorbell_mode_switch = false,
82 static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
85 .irq_moderation_ms = 0,
87 .mode = MHI_DB_BRST_DISABLE,
88 .data_type = MHI_ER_CTRL,
89 .hardware_event = false,
90 .client_managed = false,
91 .offload_channel = false,
95 .irq_moderation_ms = 1,
97 .mode = MHI_DB_BRST_DISABLE,
99 .hardware_event = false,
100 .client_managed = false,
101 .offload_channel = false,
105 static struct mhi_controller_config ath11k_mhi_config_qca6390 = {
108 .use_bounce_buf = false,
110 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
111 .ch_cfg = ath11k_mhi_channels_qca6390,
112 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
113 .event_cfg = ath11k_mhi_events_qca6390,
116 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
122 .dir = DMA_TO_DEVICE,
125 .doorbell = MHI_DB_BRST_DISABLE,
127 .offload_channel = false,
128 .doorbell_mode_switch = false,
136 .dir = DMA_FROM_DEVICE,
139 .doorbell = MHI_DB_BRST_DISABLE,
141 .offload_channel = false,
142 .doorbell_mode_switch = false,
150 .dir = DMA_TO_DEVICE,
153 .doorbell = MHI_DB_BRST_DISABLE,
155 .offload_channel = false,
156 .doorbell_mode_switch = false,
164 .dir = DMA_FROM_DEVICE,
167 .doorbell = MHI_DB_BRST_DISABLE,
169 .offload_channel = false,
170 .doorbell_mode_switch = false,
175 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
178 .irq_moderation_ms = 0,
180 .data_type = MHI_ER_CTRL,
181 .mode = MHI_DB_BRST_DISABLE,
182 .hardware_event = false,
183 .client_managed = false,
184 .offload_channel = false,
188 .irq_moderation_ms = 1,
190 .mode = MHI_DB_BRST_DISABLE,
192 .hardware_event = false,
193 .client_managed = false,
194 .offload_channel = false,
198 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
201 .use_bounce_buf = false,
203 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
204 .ch_cfg = ath11k_mhi_channels_qcn9074,
205 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
206 .event_cfg = ath11k_mhi_events_qcn9074,
209 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
213 val = ath11k_pcic_read32(ab, MHISTATUS);
215 ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val);
217 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
218 * has SYSERR bit set and thus need to set MHICTRL_RESET
221 ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
226 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab)
228 ath11k_pcic_write32(ab, PCIE_TXVECDB, 0);
231 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab)
233 ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0);
236 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab)
238 ath11k_pcic_write32(ab, PCIE_RXVECDB, 0);
241 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab)
243 ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0);
246 void ath11k_mhi_clear_vector(struct ath11k_base *ab)
248 ath11k_mhi_reset_txvecdb(ab);
249 ath11k_mhi_reset_txvecstatus(ab);
250 ath11k_mhi_reset_rxvecdb(ab);
251 ath11k_mhi_reset_rxvecstatus(ab);
254 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
256 struct ath11k_base *ab = ab_pci->ab;
257 u32 user_base_data, base_vector;
258 int ret, num_vectors, i;
260 unsigned int msi_data;
262 ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors,
263 &user_base_data, &base_vector);
267 ath11k_dbg(ab, ATH11K_DBG_PCI, "num_vectors %d base_vector %d\n",
268 num_vectors, base_vector);
270 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL);
274 for (i = 0; i < num_vectors; i++) {
275 msi_data = base_vector;
277 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
280 irq[i] = ath11k_pci_get_msi_irq(ab, msi_data);
283 ab_pci->mhi_ctrl->irq = irq;
284 ab_pci->mhi_ctrl->nr_irqs = num_vectors;
289 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
294 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
298 static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason)
302 return "MHI_CB_IDLE";
303 case MHI_CB_PENDING_DATA:
304 return "MHI_CB_PENDING_DATA";
305 case MHI_CB_LPM_ENTER:
306 return "MHI_CB_LPM_ENTER";
307 case MHI_CB_LPM_EXIT:
308 return "MHI_CB_LPM_EXIT";
310 return "MHI_CB_EE_RDDM";
311 case MHI_CB_EE_MISSION_MODE:
312 return "MHI_CB_EE_MISSION_MODE";
313 case MHI_CB_SYS_ERROR:
314 return "MHI_CB_SYS_ERROR";
315 case MHI_CB_FATAL_ERROR:
316 return "MHI_CB_FATAL_ERROR";
318 return "MHI_CB_BW_REQ";
324 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
325 enum mhi_callback cb)
327 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
329 ath11k_dbg(ab, ATH11K_DBG_BOOT, "notify status reason %s\n",
330 ath11k_mhi_op_callback_to_str(cb));
333 case MHI_CB_SYS_ERROR:
334 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
337 ath11k_warn(ab, "firmware crashed: MHI_CB_EE_RDDM\n");
338 if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags)))
339 queue_work(ab->workqueue_aux, &ab->reset_work);
346 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
355 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
362 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
364 struct device_node *np;
368 np = of_find_node_by_type(NULL, "memory");
372 ret = of_address_to_resource(np, 0, &res);
377 mhi_ctrl->iova_start = res.start + 0x1000000;
378 mhi_ctrl->iova_stop = res.end;
383 int ath11k_mhi_register(struct ath11k_pci *ab_pci)
385 struct ath11k_base *ab = ab_pci->ab;
386 struct mhi_controller *mhi_ctrl;
387 struct mhi_controller_config *ath11k_mhi_config;
390 mhi_ctrl = mhi_alloc_controller();
394 ab_pci->mhi_ctrl = mhi_ctrl;
395 mhi_ctrl->cntrl_dev = ab->dev;
396 mhi_ctrl->regs = ab->mem;
397 mhi_ctrl->reg_len = ab->mem_len;
399 if (ab->fw.amss_data && ab->fw.amss_len > 0) {
400 /* use MHI firmware file from firmware-N.bin */
401 mhi_ctrl->fw_data = ab->fw.amss_data;
402 mhi_ctrl->fw_sz = ab->fw.amss_len;
404 /* use the old separate mhi.bin MHI firmware file */
405 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE,
407 sizeof(ab_pci->amss_path));
408 mhi_ctrl->fw_image = ab_pci->amss_path;
411 ret = ath11k_mhi_get_msi(ab_pci);
413 ath11k_err(ab, "failed to get msi for mhi\n");
414 goto free_controller;
417 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
418 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
420 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) {
421 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl);
423 goto free_controller;
425 mhi_ctrl->iova_start = 0;
426 mhi_ctrl->iova_stop = 0xFFFFFFFF;
429 mhi_ctrl->rddm_size = RDDM_DUMP_SIZE;
430 mhi_ctrl->sbl_size = SZ_512K;
431 mhi_ctrl->seg_len = SZ_512K;
432 mhi_ctrl->fbc_download = true;
433 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get;
434 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put;
435 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
436 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
437 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
439 switch (ab->hw_rev) {
440 case ATH11K_HW_QCN9074_HW10:
441 ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
443 case ATH11K_HW_QCA6390_HW20:
444 case ATH11K_HW_WCN6855_HW20:
445 case ATH11K_HW_WCN6855_HW21:
446 ath11k_mhi_config = &ath11k_mhi_config_qca6390;
449 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n",
452 goto free_controller;
455 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
457 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
458 goto free_controller;
464 mhi_free_controller(mhi_ctrl);
465 ab_pci->mhi_ctrl = NULL;
469 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci)
471 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
473 mhi_unregister_controller(mhi_ctrl);
474 kfree(mhi_ctrl->irq);
475 mhi_free_controller(mhi_ctrl);
478 int ath11k_mhi_start(struct ath11k_pci *ab_pci)
480 struct ath11k_base *ab = ab_pci->ab;
483 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
485 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
487 ath11k_warn(ab, "failed to prepare mhi: %d", ret);
491 ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
493 ath11k_warn(ab, "failed to power up mhi: %d", ret);
500 void ath11k_mhi_stop(struct ath11k_pci *ab_pci)
502 mhi_power_down(ab_pci->mhi_ctrl, true);
503 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
506 int ath11k_mhi_suspend(struct ath11k_pci *ab_pci)
508 struct ath11k_base *ab = ab_pci->ab;
511 ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
513 ath11k_warn(ab, "failed to suspend mhi: %d", ret);
520 int ath11k_mhi_resume(struct ath11k_pci *ab_pci)
522 struct ath11k_base *ab = ab_pci->ab;
525 /* Do force MHI resume as some devices like QCA6390, WCN6855
526 * are not in M3 state but they are functional. So just ignore
527 * the MHI state while resuming.
529 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl);
531 ath11k_warn(ab, "failed to resume mhi: %d", ret);