1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
15 #define HAL_LINK_DESC_SIZE (32 << 2)
16 #define HAL_LINK_DESC_ALIGN 128
17 #define HAL_NUM_MPDUS_PER_LINK_DESC 6
18 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7
19 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6
20 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12
21 #define HAL_MAX_AVAIL_BLK_RES 3
23 #define HAL_RING_BASE_ALIGN 8
25 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704
26 /* TODO: Check with hw team on the supported scatter buf size */
27 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8
28 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
29 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE)
31 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48
32 #define HAL_DSCP_TID_TBL_SIZE 24
34 /* calculate the register address from bar0 of shadow register x */
35 #define HAL_SHADOW_BASE_ADDR(ab) ab->hw_params.regs->hal_shadow_base_addr
36 #define HAL_SHADOW_NUM_REGS 36
37 #define HAL_HP_OFFSET_IN_REG_START 1
38 #define HAL_OFFSET_FROM_HP_TO_TP 4
40 #define HAL_SHADOW_REG(ab, x) (HAL_SHADOW_BASE_ADDR(ab) + (4 * (x)))
42 /* WCSS Relative address */
43 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
44 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
46 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \
47 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)
48 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) \
49 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)
50 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) \
51 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)
52 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) \
53 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)
54 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
56 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
57 #define HAL_WLAON_REG_BASE 0x01f80000
59 /* SW2TCL(x) R0 ring configuration address */
60 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014
61 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c
62 #define HAL_TCL1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_lsb
63 #define HAL_TCL1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_msb
64 #define HAL_TCL1_RING_ID(ab) ab->hw_params.regs->hal_tcl1_ring_id
65 #define HAL_TCL1_RING_MISC(ab) ab->hw_params.regs->hal_tcl1_ring_misc
66 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \
67 ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb
68 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \
69 ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb
70 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \
71 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0
72 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \
73 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1
74 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \
75 ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb
76 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \
77 ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb
78 #define HAL_TCL1_RING_MSI1_DATA(ab) \
79 ab->hw_params.regs->hal_tcl1_ring_msi1_data
80 #define HAL_TCL2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl2_ring_base_lsb
81 #define HAL_TCL_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl_ring_base_lsb
83 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) \
84 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
85 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) \
86 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
87 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) \
88 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab))
89 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) \
90 (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
91 #define HAL_TCL1_RING_ID_OFFSET(ab) \
92 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab))
93 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) \
94 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab))
95 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \
96 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab))
97 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \
98 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
99 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \
100 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
101 #define HAL_TCL1_RING_MISC_OFFSET(ab) \
102 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab))
104 /* SW2TCL(x) R2 ring pointers (head/tail) address */
105 #define HAL_TCL1_RING_HP 0x00002000
106 #define HAL_TCL1_RING_TP 0x00002004
107 #define HAL_TCL2_RING_HP 0x00002008
108 #define HAL_TCL_RING_HP 0x00002018
110 #define HAL_TCL1_RING_TP_OFFSET \
111 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
113 /* TCL STATUS ring address */
114 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \
115 ab->hw_params.regs->hal_tcl_status_ring_base_lsb
116 #define HAL_TCL_STATUS_RING_HP 0x00002030
118 /* REO2SW(x) R0 ring configuration address */
119 #define HAL_REO1_GEN_ENABLE 0x00000000
120 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004
121 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
122 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
123 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
124 #define HAL_REO1_MISC_CTL(ab) ab->hw_params.regs->hal_reo1_misc_ctl
125 #define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb
126 #define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb
127 #define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id
128 #define HAL_REO1_RING_MISC(ab) ab->hw_params.regs->hal_reo1_ring_misc
129 #define HAL_REO1_RING_HP_ADDR_LSB(ab) \
130 ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb
131 #define HAL_REO1_RING_HP_ADDR_MSB(ab) \
132 ab->hw_params.regs->hal_reo1_ring_hp_addr_msb
133 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \
134 ab->hw_params.regs->hal_reo1_ring_producer_int_setup
135 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \
136 ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb
137 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \
138 ab->hw_params.regs->hal_reo1_ring_msi1_base_msb
139 #define HAL_REO1_RING_MSI1_DATA(ab) \
140 ab->hw_params.regs->hal_reo1_ring_msi1_data
141 #define HAL_REO2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo2_ring_base_lsb
142 #define HAL_REO1_AGING_THRESH_IX_0(ab) \
143 ab->hw_params.regs->hal_reo1_aging_thresh_ix_0
144 #define HAL_REO1_AGING_THRESH_IX_1(ab) \
145 ab->hw_params.regs->hal_reo1_aging_thresh_ix_1
146 #define HAL_REO1_AGING_THRESH_IX_2(ab) \
147 ab->hw_params.regs->hal_reo1_aging_thresh_ix_2
148 #define HAL_REO1_AGING_THRESH_IX_3(ab) \
149 ab->hw_params.regs->hal_reo1_aging_thresh_ix_3
151 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) \
152 (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
153 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) \
154 (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
155 #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) \
156 (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab))
157 #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) \
158 (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
159 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab))
160 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) \
161 (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab))
162 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) \
163 (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
164 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) \
165 (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
166 #define HAL_REO1_RING_MISC_OFFSET(ab) \
167 (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab))
169 /* REO2SW(x) R2 ring pointers (head/tail) address */
170 #define HAL_REO1_RING_HP(ab) ab->hw_params.regs->hal_reo1_ring_hp
171 #define HAL_REO1_RING_TP(ab) ab->hw_params.regs->hal_reo1_ring_tp
172 #define HAL_REO2_RING_HP(ab) ab->hw_params.regs->hal_reo2_ring_hp
174 #define HAL_REO1_RING_TP_OFFSET(ab) (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab))
176 /* REO2TCL R0 ring configuration address */
177 #define HAL_REO_TCL_RING_BASE_LSB(ab) \
178 ab->hw_params.regs->hal_reo_tcl_ring_base_lsb
180 /* REO2TCL R2 ring pointer (head/tail) address */
181 #define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp
183 /* REO CMD R0 address */
184 #define HAL_REO_CMD_RING_BASE_LSB(ab) \
185 ab->hw_params.regs->hal_reo_cmd_ring_base_lsb
187 /* REO CMD R2 address */
188 #define HAL_REO_CMD_HP(ab) ab->hw_params.regs->hal_reo_cmd_ring_hp
190 /* SW2REO R0 address */
191 #define HAL_SW2REO_RING_BASE_LSB(ab) \
192 ab->hw_params.regs->hal_sw2reo_ring_base_lsb
194 /* SW2REO R2 address */
195 #define HAL_SW2REO_RING_HP(ab) ab->hw_params.regs->hal_sw2reo_ring_hp
197 /* CE ring R0 address */
198 #define HAL_CE_DST_RING_BASE_LSB 0x00000000
199 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058
200 #define HAL_CE_DST_RING_CTRL 0x000000b0
202 /* CE ring R2 address */
203 #define HAL_CE_DST_RING_HP 0x00000400
204 #define HAL_CE_DST_STATUS_RING_HP 0x00000408
206 /* REO status address */
207 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \
208 ab->hw_params.regs->hal_reo_status_ring_base_lsb
209 #define HAL_REO_STATUS_HP(ab) ab->hw_params.regs->hal_reo_status_hp
211 /* WBM Idle R0 address */
212 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \
213 (ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)
214 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \
215 (ab->hw_params.regs->hal_wbm_idle_link_ring_misc)
216 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048
217 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c
218 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058
219 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c
220 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068
221 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c
222 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078
223 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c
224 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084
226 /* WBM Idle R2 address */
227 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0
229 /* SW2WBM R0 release address */
230 #define HAL_WBM_RELEASE_RING_BASE_LSB(x) \
231 (ab->hw_params.regs->hal_wbm_release_ring_base_lsb)
233 /* SW2WBM R2 release address */
234 #define HAL_WBM_RELEASE_RING_HP 0x00003018
236 /* WBM2SW R0 release address */
237 #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \
238 (ab->hw_params.regs->hal_wbm0_release_ring_base_lsb)
239 #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \
240 (ab->hw_params.regs->hal_wbm1_release_ring_base_lsb)
242 /* WBM2SW R2 release address */
243 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0
244 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8
246 /* TCL ring field mask and offset */
247 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
248 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
249 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
250 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1)
251 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
252 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4)
253 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5)
254 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6)
255 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16)
256 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
257 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
258 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
259 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
260 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17)
261 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)
262 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)
263 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
264 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)
265 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)
266 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)
267 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)
268 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)
269 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)
271 /* REO ring field mask and offset */
272 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
273 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
274 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)
275 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
276 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
277 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4)
278 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5)
279 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6)
280 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16)
281 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
282 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
283 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
284 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23)
285 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2)
286 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
287 #define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17)
289 /* CE ring bit field mask and shift */
290 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
292 #define HAL_ADDR_LSB_REG_MASK 0xffffffff
294 #define HAL_ADDR_MSB_REG_SHIFT 32
296 /* WBM ring bit field mask and shift */
297 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1)
298 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2)
299 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)
300 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)
301 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8)
303 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8)
304 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8)
306 #define BASE_ADDR_MATCH_TAG_VAL 0x5
308 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff
309 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff
310 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff
311 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff
312 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
313 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff
314 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff
315 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
316 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff
317 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff
318 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
319 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff
320 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff
321 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
322 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff
324 /* IPQ5018 ce registers */
325 #define HAL_IPQ5018_CE_WFSS_REG_BASE 0x08400000
326 #define HAL_IPQ5018_CE_SIZE 0x200000
328 /* Add any other errors here and return them in
329 * ath11k_hal_rx_desc_get_err().
332 enum hal_srng_ring_id {
333 HAL_SRNG_RING_ID_REO2SW1 = 0,
334 HAL_SRNG_RING_ID_REO2SW2,
335 HAL_SRNG_RING_ID_REO2SW3,
336 HAL_SRNG_RING_ID_REO2SW4,
337 HAL_SRNG_RING_ID_REO2TCL,
338 HAL_SRNG_RING_ID_SW2REO,
340 HAL_SRNG_RING_ID_REO_CMD = 8,
341 HAL_SRNG_RING_ID_REO_STATUS,
343 HAL_SRNG_RING_ID_SW2TCL1 = 16,
344 HAL_SRNG_RING_ID_SW2TCL2,
345 HAL_SRNG_RING_ID_SW2TCL3,
346 HAL_SRNG_RING_ID_SW2TCL4,
348 HAL_SRNG_RING_ID_SW2TCL_CMD = 24,
349 HAL_SRNG_RING_ID_TCL_STATUS,
351 HAL_SRNG_RING_ID_CE0_SRC = 32,
352 HAL_SRNG_RING_ID_CE1_SRC,
353 HAL_SRNG_RING_ID_CE2_SRC,
354 HAL_SRNG_RING_ID_CE3_SRC,
355 HAL_SRNG_RING_ID_CE4_SRC,
356 HAL_SRNG_RING_ID_CE5_SRC,
357 HAL_SRNG_RING_ID_CE6_SRC,
358 HAL_SRNG_RING_ID_CE7_SRC,
359 HAL_SRNG_RING_ID_CE8_SRC,
360 HAL_SRNG_RING_ID_CE9_SRC,
361 HAL_SRNG_RING_ID_CE10_SRC,
362 HAL_SRNG_RING_ID_CE11_SRC,
364 HAL_SRNG_RING_ID_CE0_DST = 56,
365 HAL_SRNG_RING_ID_CE1_DST,
366 HAL_SRNG_RING_ID_CE2_DST,
367 HAL_SRNG_RING_ID_CE3_DST,
368 HAL_SRNG_RING_ID_CE4_DST,
369 HAL_SRNG_RING_ID_CE5_DST,
370 HAL_SRNG_RING_ID_CE6_DST,
371 HAL_SRNG_RING_ID_CE7_DST,
372 HAL_SRNG_RING_ID_CE8_DST,
373 HAL_SRNG_RING_ID_CE9_DST,
374 HAL_SRNG_RING_ID_CE10_DST,
375 HAL_SRNG_RING_ID_CE11_DST,
377 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80,
378 HAL_SRNG_RING_ID_CE1_DST_STATUS,
379 HAL_SRNG_RING_ID_CE2_DST_STATUS,
380 HAL_SRNG_RING_ID_CE3_DST_STATUS,
381 HAL_SRNG_RING_ID_CE4_DST_STATUS,
382 HAL_SRNG_RING_ID_CE5_DST_STATUS,
383 HAL_SRNG_RING_ID_CE6_DST_STATUS,
384 HAL_SRNG_RING_ID_CE7_DST_STATUS,
385 HAL_SRNG_RING_ID_CE8_DST_STATUS,
386 HAL_SRNG_RING_ID_CE9_DST_STATUS,
387 HAL_SRNG_RING_ID_CE10_DST_STATUS,
388 HAL_SRNG_RING_ID_CE11_DST_STATUS,
390 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104,
391 HAL_SRNG_RING_ID_WBM_SW_RELEASE,
392 HAL_SRNG_RING_ID_WBM2SW0_RELEASE,
393 HAL_SRNG_RING_ID_WBM2SW1_RELEASE,
394 HAL_SRNG_RING_ID_WBM2SW2_RELEASE,
395 HAL_SRNG_RING_ID_WBM2SW3_RELEASE,
396 HAL_SRNG_RING_ID_WBM2SW4_RELEASE,
398 HAL_SRNG_RING_ID_UMAC_ID_END = 127,
399 HAL_SRNG_RING_ID_LMAC1_ID_START,
401 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START,
402 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF,
403 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF,
404 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF,
405 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF,
406 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
407 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1,
408 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC,
409 HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
411 HAL_SRNG_RING_ID_LMAC1_ID_END = 143
414 /* SRNG registers are split into two groups R0 and R2 */
415 #define HAL_SRNG_REG_GRP_R0 0
416 #define HAL_SRNG_REG_GRP_R2 1
417 #define HAL_SRNG_NUM_REG_GRP 2
419 #define HAL_SRNG_NUM_LMACS 3
420 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1
421 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \
422 HAL_SRNG_RING_ID_LMAC1_ID_START)
423 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC)
424 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \
425 HAL_SRNG_NUM_LMAC_RINGS)
444 HAL_RXDMA_MONITOR_BUF,
445 HAL_RXDMA_MONITOR_STATUS,
446 HAL_RXDMA_MONITOR_DST,
447 HAL_RXDMA_MONITOR_DESC,
452 #define HAL_RX_MAX_BA_WINDOW 256
454 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000)
457 * enum hal_reo_cmd_type: Enum for REO command type
458 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats
459 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue
460 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache
461 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked
462 * earlier with a 'REO_FLUSH_CACHE' command
463 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
464 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings
466 enum hal_reo_cmd_type {
467 HAL_REO_CMD_GET_QUEUE_STATS = 0,
468 HAL_REO_CMD_FLUSH_QUEUE = 1,
469 HAL_REO_CMD_FLUSH_CACHE = 2,
470 HAL_REO_CMD_UNBLOCK_CACHE = 3,
471 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4,
472 HAL_REO_CMD_UPDATE_RX_QUEUE = 5,
476 * enum hal_reo_cmd_status: Enum for execution status of REO command
477 * @HAL_REO_CMD_SUCCESS: Command has successfully executed
478 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue
479 * or cache was blocked
480 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to
482 * @HAL_REO_CMD_RESOURCE_BLOCKED:
483 * @HAL_REO_CMD_DRAIN:
485 enum hal_reo_cmd_status {
486 HAL_REO_CMD_SUCCESS = 0,
487 HAL_REO_CMD_BLOCKED = 1,
488 HAL_REO_CMD_FAILED = 2,
489 HAL_REO_CMD_RESOURCE_BLOCKED = 3,
490 HAL_REO_CMD_DRAIN = 0xff,
493 struct hal_wbm_idle_scatter_list {
495 struct hal_wbm_link_desc *vaddr;
498 struct hal_srng_params {
499 dma_addr_t ring_base_paddr;
500 u32 *ring_base_vaddr;
502 u32 intr_batch_cntr_thres_entries;
503 u32 intr_timer_thres_us;
510 /* Add more params as needed */
519 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008
520 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010
521 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020
522 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000
523 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000
524 #define HAL_SRNG_FLAGS_CACHED 0x20000000
525 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000
526 #define HAL_SRNG_FLAGS_REMAP_CE_RING 0x10000000
528 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
529 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
531 /* Common SRNG ring structure for source and destination rings */
533 /* Unique SRNG ring ID */
536 /* Ring initialization done */
539 /* Interrupt/MSI value assigned to this ring */
542 /* Physical base address of the ring */
543 dma_addr_t ring_base_paddr;
545 /* Virtual base address of the ring */
546 u32 *ring_base_vaddr;
548 /* Number of entries in ring */
557 /* Size of ring entry */
560 /* Interrupt timer threshold - in micro seconds */
561 u32 intr_timer_thres_us;
563 /* Interrupt batch counter threshold - in number of ring entries */
564 u32 intr_batch_cntr_thres_entries;
575 /* Lock for serializing ring index updates */
578 /* Start offset of SRNG register groups for this ring
579 * TBD: See if this is required - register address can be derived
582 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP];
586 /* Source or Destination ring */
587 enum hal_srng_dir ring_dir;
591 /* SW tail pointer */
594 /* Shadow head pointer location to be updated by HW */
595 volatile u32 *hp_addr;
597 /* Cached head pointer */
600 /* Tail pointer location to be updated by SW - This
601 * will be a register address and need not be
602 * accessed through SW structure
606 /* Current SW loop cnt */
609 /* max transfer size */
610 u16 max_buffer_length;
612 /* head pointer at access end */
617 /* SW head pointer */
620 /* SW reap head pointer */
623 /* Shadow tail pointer location to be updated by HW */
626 /* Cached tail pointer */
629 /* Head pointer location to be updated by SW - This
630 * will be a register address and need not be accessed
631 * through SW structure
635 /* Low threshold - in number of ring entries */
638 /* tail pointer at access end */
644 /* Interrupt mitigation - Batch threshold in terms of number of frames */
645 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256
646 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128
647 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1
649 /* Interrupt mitigation - timer threshold in us */
650 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000
651 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500
652 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256
654 /* HW SRNG configuration table */
655 struct hal_srng_config {
659 u32 reg_start[HAL_SRNG_NUM_REG_GRP];
660 u16 reg_size[HAL_SRNG_NUM_REG_GRP];
662 enum hal_srng_dir ring_dir;
667 * enum hal_rx_buf_return_buf_manager
669 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
670 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
672 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
673 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
674 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
675 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
676 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
679 enum hal_rx_buf_return_buf_manager {
680 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST,
681 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST,
682 HAL_RX_BUF_RBM_FW_BM,
683 HAL_RX_BUF_RBM_SW0_BM,
684 HAL_RX_BUF_RBM_SW1_BM,
685 HAL_RX_BUF_RBM_SW2_BM,
686 HAL_RX_BUF_RBM_SW3_BM,
687 HAL_RX_BUF_RBM_SW4_BM,
690 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000
692 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0)
693 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1)
694 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2)
695 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
696 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4)
697 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5)
698 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6)
699 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7)
700 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8)
702 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */
703 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8)
704 #define HAL_REO_CMD_UPD0_VLD BIT(9)
705 #define HAL_REO_CMD_UPD0_ALDC BIT(10)
706 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11)
707 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12)
708 #define HAL_REO_CMD_UPD0_AC BIT(13)
709 #define HAL_REO_CMD_UPD0_BAR BIT(14)
710 #define HAL_REO_CMD_UPD0_RETRY BIT(15)
711 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16)
712 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17)
713 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18)
714 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19)
715 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20)
716 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21)
717 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22)
718 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23)
719 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24)
720 #define HAL_REO_CMD_UPD0_SVLD BIT(25)
721 #define HAL_REO_CMD_UPD0_SSN BIT(26)
722 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27)
723 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28)
724 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29)
725 #define HAL_REO_CMD_UPD0_PN BIT(30)
727 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */
728 #define HAL_REO_CMD_UPD1_VLD BIT(16)
729 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)
730 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19)
731 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20)
732 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)
733 #define HAL_REO_CMD_UPD1_BAR BIT(23)
734 #define HAL_REO_CMD_UPD1_RETRY BIT(24)
735 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25)
736 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26)
737 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27)
738 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28)
739 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29)
740 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30)
741 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31)
743 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */
744 #define HAL_REO_CMD_UPD2_SVLD BIT(10)
745 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)
746 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23)
747 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24)
749 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8)
751 struct ath11k_hal_reo_cmd {
771 HAL_PN_TYPE_WAPI_EVEN,
772 HAL_PN_TYPE_WAPI_UNEVEN,
778 HAL_CE_DESC_DST_STATUS,
781 #define HAL_HASH_ROUTING_RING_TCL 0
782 #define HAL_HASH_ROUTING_RING_SW1 1
783 #define HAL_HASH_ROUTING_RING_SW2 2
784 #define HAL_HASH_ROUTING_RING_SW3 3
785 #define HAL_HASH_ROUTING_RING_SW4 4
786 #define HAL_HASH_ROUTING_RING_REL 5
787 #define HAL_HASH_ROUTING_RING_FW 6
789 struct hal_reo_status_header {
791 enum hal_reo_cmd_status cmd_status;
796 struct hal_reo_status_queue_stats {
800 u32 last_rx_queue_ts;
801 u32 last_rx_dequeue_ts;
802 u32 rx_bitmap[8]; /* Bitmap from 0-255 */
805 u16 fwd_due_to_bar_cnt;
807 u32 frames_in_order_cnt;
808 u32 num_mpdu_processed_cnt;
809 u32 num_msdu_processed_cnt;
810 u32 total_num_processed_byte_cnt;
811 u32 late_rx_mpdu_cnt;
812 u32 reorder_hole_cnt;
815 u8 num_window_2k_jump_cnt;
818 struct hal_reo_status_flush_queue {
822 enum hal_reo_status_flush_cache_err_code {
823 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS,
824 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE,
825 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND,
828 struct hal_reo_status_flush_cache {
830 enum hal_reo_status_flush_cache_err_code err_code;
831 bool cache_controller_flush_status_hit;
832 u8 cache_controller_flush_status_desc_type;
833 u8 cache_controller_flush_status_client_id;
834 u8 cache_controller_flush_status_err;
835 u8 cache_controller_flush_status_cnt;
838 enum hal_reo_status_unblock_cache_type {
839 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE,
840 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE,
843 struct hal_reo_status_unblock_cache {
845 enum hal_reo_status_unblock_cache_type unblock_type;
848 struct hal_reo_status_flush_timeout_list {
851 u16 release_desc_cnt;
855 enum hal_reo_threshold_idx {
856 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0,
857 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1,
858 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2,
859 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM,
862 struct hal_reo_status_desc_thresh_reached {
863 enum hal_reo_threshold_idx threshold_idx;
864 u32 link_desc_counter0;
865 u32 link_desc_counter1;
866 u32 link_desc_counter2;
867 u32 link_desc_counter_sum;
870 struct hal_reo_status {
871 struct hal_reo_status_header uniform_hdr;
874 struct hal_reo_status_queue_stats queue_stats;
875 struct hal_reo_status_flush_queue flush_queue;
876 struct hal_reo_status_flush_cache flush_cache;
877 struct hal_reo_status_unblock_cache unblock_cache;
878 struct hal_reo_status_flush_timeout_list timeout_list;
879 struct hal_reo_status_desc_thresh_reached desc_thresh_reached;
883 /* HAL context to be used to access SRNG APIs (currently used by data path
884 * and transport (CE) modules)
887 /* HAL internal state for all SRNG rings.
889 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX];
891 /* SRNG configuration table */
892 struct hal_srng_config *srng_config;
894 /* Remote pointer memory for HW/FW updates */
900 /* Shared memory for ring pointer updates from host to FW */
906 /* Available REO blocking resources bitmap */
907 u8 avail_blk_resource;
909 u8 current_blk_index;
911 /* shadow register configuration */
912 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS];
913 int num_shadow_reg_configured;
915 struct lock_class_key srng_key[HAL_SRNG_RING_ID_MAX];
918 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid);
919 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
920 u32 start_seq, enum hal_pn_type type);
921 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
922 struct hal_srng *srng);
923 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
924 struct hal_wbm_idle_scatter_list *sbuf,
925 u32 nsbufs, u32 tot_link_desc,
928 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab,
929 struct hal_srng *srng);
930 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab,
931 struct hal_srng *srng);
932 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie,
934 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type);
935 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id,
937 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr);
938 u32 ath11k_hal_ce_dst_status_get_length(void *buf);
939 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type);
940 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type);
941 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng,
942 struct hal_srng_params *params);
943 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab,
944 struct hal_srng *srng);
945 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng);
946 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng,
948 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng);
949 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab,
950 struct hal_srng *srng);
951 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab,
952 struct hal_srng *srng);
953 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab,
954 struct hal_srng *srng);
955 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng,
957 void ath11k_hal_srng_access_begin(struct ath11k_base *ab,
958 struct hal_srng *srng);
959 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng);
960 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
961 int ring_num, int mac_id,
962 struct hal_srng_params *params);
963 int ath11k_hal_srng_init(struct ath11k_base *ath11k);
964 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k);
965 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab);
966 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab,
967 u32 **cfg, u32 *len);
968 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab,
969 enum hal_ring_type ring_type,
971 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab);
972 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab,
973 struct hal_srng *srng);