drivers/net/wireless/ath/ath10k/snoc.c

   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Copyright (c) 2018 The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bits.h>
   7 #include <linux/clk.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/property.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/remoteproc/qcom_rproc.h>
  16 #include <linux/of_address.h>
  17 #include <linux/iommu.h>
  18
  19 #include "ce.h"
  20 #include "coredump.h"
  21 #include "debug.h"
  22 #include "hif.h"
  23 #include "htc.h"
  24 #include "snoc.h"
  25
  26 #define ATH10K_SNOC_RX_POST_RETRY_MS 50
  27 #define CE_POLL_PIPE 4
  28 #define ATH10K_SNOC_WAKE_IRQ 2
  29
  30 static char *const ce_name[] = {
  31         "WLAN_CE_0",
  32         "WLAN_CE_1",
  33         "WLAN_CE_2",
  34         "WLAN_CE_3",
  35         "WLAN_CE_4",
  36         "WLAN_CE_5",
  37         "WLAN_CE_6",
  38         "WLAN_CE_7",
  39         "WLAN_CE_8",
  40         "WLAN_CE_9",
  41         "WLAN_CE_10",
  42         "WLAN_CE_11",
  43 };
  44
  45 static const char * const ath10k_regulators[] = {
  46         "vdd-0.8-cx-mx",
  47         "vdd-1.8-xo",
  48         "vdd-1.3-rfa",
  49         "vdd-3.3-ch0",
  50         "vdd-3.3-ch1",
  51 };
  52
  53 static const char * const ath10k_clocks[] = {
  54         "cxo_ref_clk_pin", "qdss",
  55 };
  56
  57 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
  58 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
  59 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
  60 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
  61 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
  62 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
  63
  64 static const struct ath10k_snoc_drv_priv drv_priv = {
  65         .hw_rev = ATH10K_HW_WCN3990,
  66         .dma_mask = DMA_BIT_MASK(35),
  67         .msa_size = 0x100000,
  68 };
  69
  70 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C
  71 #define WCN3990_DST_WR_IDX_OFFSET 0x40
  72
  73 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = {
  74                 {
  75                         .ce_id = __cpu_to_le16(0),
  76                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  77                 },
  78
  79                 {
  80                         .ce_id = __cpu_to_le16(3),
  81                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  82                 },
  83
  84                 {
  85                         .ce_id = __cpu_to_le16(4),
  86                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  87                 },
  88
  89                 {
  90                         .ce_id = __cpu_to_le16(5),
  91                         .reg_offset =  __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  92                 },
  93
  94                 {
  95                         .ce_id = __cpu_to_le16(7),
  96                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  97                 },
  98
  99                 {
 100                         .ce_id = __cpu_to_le16(1),
 101                         .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 102                 },
 103
 104                 {
 105                         .ce_id = __cpu_to_le16(2),
 106                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 107                 },
 108
 109                 {
 110                         .ce_id = __cpu_to_le16(7),
 111                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 112                 },
 113
 114                 {
 115                         .ce_id = __cpu_to_le16(8),
 116                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 117                 },
 118
 119                 {
 120                         .ce_id = __cpu_to_le16(9),
 121                         .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 122                 },
 123
 124                 {
 125                         .ce_id = __cpu_to_le16(10),
 126                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 127                 },
 128
 129                 {
 130                         .ce_id = __cpu_to_le16(11),
 131                         .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 132                 },
 133 };
 134
 135 static struct ce_attr host_ce_config_wlan[] = {
 136         /* CE0: host->target HTC control streams */
 137         {
 138                 .flags = CE_ATTR_FLAGS,
 139                 .src_nentries = 16,
 140                 .src_sz_max = 2048,
 141                 .dest_nentries = 0,
 142                 .send_cb = ath10k_snoc_htc_tx_cb,
 143         },
 144
 145         /* CE1: target->host HTT + HTC control */
 146         {
 147                 .flags = CE_ATTR_FLAGS,
 148                 .src_nentries = 0,
 149                 .src_sz_max = 2048,
 150                 .dest_nentries = 512,
 151                 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
 152         },
 153
 154         /* CE2: target->host WMI */
 155         {
 156                 .flags = CE_ATTR_FLAGS,
 157                 .src_nentries = 0,
 158                 .src_sz_max = 2048,
 159                 .dest_nentries = 64,
 160                 .recv_cb = ath10k_snoc_htc_rx_cb,
 161         },
 162
 163         /* CE3: host->target WMI */
 164         {
 165                 .flags = CE_ATTR_FLAGS,
 166                 .src_nentries = 32,
 167                 .src_sz_max = 2048,
 168                 .dest_nentries = 0,
 169                 .send_cb = ath10k_snoc_htc_tx_cb,
 170         },
 171
 172         /* CE4: host->target HTT */
 173         {
 174                 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
 175                 .src_nentries = 2048,
 176                 .src_sz_max = 256,
 177                 .dest_nentries = 0,
 178                 .send_cb = ath10k_snoc_htt_tx_cb,
 179         },
 180
 181         /* CE5: target->host HTT (ipa_uc->target ) */
 182         {
 183                 .flags = CE_ATTR_FLAGS,
 184                 .src_nentries = 0,
 185                 .src_sz_max = 512,
 186                 .dest_nentries = 512,
 187                 .recv_cb = ath10k_snoc_htt_rx_cb,
 188         },
 189
 190         /* CE6: target autonomous hif_memcpy */
 191         {
 192                 .flags = CE_ATTR_FLAGS,
 193                 .src_nentries = 0,
 194                 .src_sz_max = 0,
 195                 .dest_nentries = 0,
 196         },
 197
 198         /* CE7: ce_diag, the Diagnostic Window */
 199         {
 200                 .flags = CE_ATTR_FLAGS,
 201                 .src_nentries = 2,
 202                 .src_sz_max = 2048,
 203                 .dest_nentries = 2,
 204         },
 205
 206         /* CE8: Target to uMC */
 207         {
 208                 .flags = CE_ATTR_FLAGS,
 209                 .src_nentries = 0,
 210                 .src_sz_max = 2048,
 211                 .dest_nentries = 128,
 212         },
 213
 214         /* CE9 target->host HTT */
 215         {
 216                 .flags = CE_ATTR_FLAGS,
 217                 .src_nentries = 0,
 218                 .src_sz_max = 2048,
 219                 .dest_nentries = 512,
 220                 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
 221         },
 222
 223         /* CE10: target->host HTT */
 224         {
 225                 .flags = CE_ATTR_FLAGS,
 226                 .src_nentries = 0,
 227                 .src_sz_max = 2048,
 228                 .dest_nentries = 512,
 229                 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
 230         },
 231
 232         /* CE11: target -> host PKTLOG */
 233         {
 234                 .flags = CE_ATTR_FLAGS,
 235                 .src_nentries = 0,
 236                 .src_sz_max = 2048,
 237                 .dest_nentries = 512,
 238                 .recv_cb = ath10k_snoc_pktlog_rx_cb,
 239         },
 240 };
 241
 242 static struct ce_pipe_config target_ce_config_wlan[] = {
 243         /* CE0: host->target HTC control and raw streams */
 244         {
 245                 .pipenum = __cpu_to_le32(0),
 246                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 247                 .nentries = __cpu_to_le32(32),
 248                 .nbytes_max = __cpu_to_le32(2048),
 249                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 250                 .reserved = __cpu_to_le32(0),
 251         },
 252
 253         /* CE1: target->host HTT + HTC control */
 254         {
 255                 .pipenum = __cpu_to_le32(1),
 256                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 257                 .nentries = __cpu_to_le32(32),
 258                 .nbytes_max = __cpu_to_le32(2048),
 259                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 260                 .reserved = __cpu_to_le32(0),
 261         },
 262
 263         /* CE2: target->host WMI */
 264         {
 265                 .pipenum = __cpu_to_le32(2),
 266                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 267                 .nentries = __cpu_to_le32(64),
 268                 .nbytes_max = __cpu_to_le32(2048),
 269                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 270                 .reserved = __cpu_to_le32(0),
 271         },
 272
 273         /* CE3: host->target WMI */
 274         {
 275                 .pipenum = __cpu_to_le32(3),
 276                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 277                 .nentries = __cpu_to_le32(32),
 278                 .nbytes_max = __cpu_to_le32(2048),
 279                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 280                 .reserved = __cpu_to_le32(0),
 281         },
 282
 283         /* CE4: host->target HTT */
 284         {
 285                 .pipenum = __cpu_to_le32(4),
 286                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 287                 .nentries = __cpu_to_le32(256),
 288                 .nbytes_max = __cpu_to_le32(256),
 289                 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
 290                 .reserved = __cpu_to_le32(0),
 291         },
 292
 293         /* CE5: target->host HTT (HIF->HTT) */
 294         {
 295                 .pipenum = __cpu_to_le32(5),
 296                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 297                 .nentries = __cpu_to_le32(1024),
 298                 .nbytes_max = __cpu_to_le32(64),
 299                 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
 300                 .reserved = __cpu_to_le32(0),
 301         },
 302
 303         /* CE6: Reserved for target autonomous hif_memcpy */
 304         {
 305                 .pipenum = __cpu_to_le32(6),
 306                 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
 307                 .nentries = __cpu_to_le32(32),
 308                 .nbytes_max = __cpu_to_le32(16384),
 309                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 310                 .reserved = __cpu_to_le32(0),
 311         },
 312
 313         /* CE7 used only by Host */
 314         {
 315                 .pipenum = __cpu_to_le32(7),
 316                 .pipedir = __cpu_to_le32(4),
 317                 .nentries = __cpu_to_le32(0),
 318                 .nbytes_max = __cpu_to_le32(0),
 319                 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
 320                 .reserved = __cpu_to_le32(0),
 321         },
 322
 323         /* CE8 Target to uMC */
 324         {
 325                 .pipenum = __cpu_to_le32(8),
 326                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 327                 .nentries = __cpu_to_le32(32),
 328                 .nbytes_max = __cpu_to_le32(2048),
 329                 .flags = __cpu_to_le32(0),
 330                 .reserved = __cpu_to_le32(0),
 331         },
 332
 333         /* CE9 target->host HTT */
 334         {
 335                 .pipenum = __cpu_to_le32(9),
 336                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 337                 .nentries = __cpu_to_le32(32),
 338                 .nbytes_max = __cpu_to_le32(2048),
 339                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 340                 .reserved = __cpu_to_le32(0),
 341         },
 342
 343         /* CE10 target->host HTT */
 344         {
 345                 .pipenum = __cpu_to_le32(10),
 346                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 347                 .nentries = __cpu_to_le32(32),
 348                 .nbytes_max = __cpu_to_le32(2048),
 349                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 350                 .reserved = __cpu_to_le32(0),
 351         },
 352
 353         /* CE11 target autonomous qcache memcpy */
 354         {
 355                 .pipenum = __cpu_to_le32(11),
 356                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 357                 .nentries = __cpu_to_le32(32),
 358                 .nbytes_max = __cpu_to_le32(2048),
 359                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 360                 .reserved = __cpu_to_le32(0),
 361         },
 362 };
 363
 364 static struct ce_service_to_pipe target_service_to_ce_map_wlan[] = {
 365         {
 366                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
 367                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 368                 __cpu_to_le32(3),
 369         },
 370         {
 371                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
 372                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 373                 __cpu_to_le32(2),
 374         },
 375         {
 376                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
 377                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 378                 __cpu_to_le32(3),
 379         },
 380         {
 381                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
 382                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 383                 __cpu_to_le32(2),
 384         },
 385         {
 386                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
 387                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 388                 __cpu_to_le32(3),
 389         },
 390         {
 391                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
 392                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 393                 __cpu_to_le32(2),
 394         },
 395         {
 396                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
 397                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 398                 __cpu_to_le32(3),
 399         },
 400         {
 401                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
 402                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 403                 __cpu_to_le32(2),
 404         },
 405         {
 406                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
 407                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 408                 __cpu_to_le32(3),
 409         },
 410         {
 411                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
 412                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 413                 __cpu_to_le32(2),
 414         },
 415         {
 416                 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
 417                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 418                 __cpu_to_le32(0),
 419         },
 420         {
 421                 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
 422                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 423                 __cpu_to_le32(2),
 424         },
 425         { /* not used */
 426                 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
 427                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 428                 __cpu_to_le32(0),
 429         },
 430         { /* not used */
 431                 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
 432                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 433                 __cpu_to_le32(2),
 434         },
 435         {
 436                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
 437                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 438                 __cpu_to_le32(4),
 439         },
 440         {
 441                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
 442                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 443                 __cpu_to_le32(1),
 444         },
 445         { /* not used */
 446                 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
 447                 __cpu_to_le32(PIPEDIR_OUT),
 448                 __cpu_to_le32(5),
 449         },
 450         { /* in = DL = target -> host */
 451                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG),
 452                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 453                 __cpu_to_le32(9),
 454         },
 455         { /* in = DL = target -> host */
 456                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG),
 457                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 458                 __cpu_to_le32(10),
 459         },
 460         { /* in = DL = target -> host pktlog */
 461                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG),
 462                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 463                 __cpu_to_le32(11),
 464         },
 465         /* (Additions here) */
 466
 467         { /* must be last */
 468                 __cpu_to_le32(0),
 469                 __cpu_to_le32(0),
 470                 __cpu_to_le32(0),
 471         },
 472 };
 473
 474 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value)
 475 {
 476         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 477
 478         iowrite32(value, ar_snoc->mem + offset);
 479 }
 480
 481 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset)
 482 {
 483         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 484         u32 val;
 485
 486         val = ioread32(ar_snoc->mem + offset);
 487
 488         return val;
 489 }
 490
 491 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe)
 492 {
 493         struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
 494         struct ath10k *ar = pipe->hif_ce_state;
 495         struct ath10k_ce *ce = ath10k_ce_priv(ar);
 496         struct sk_buff *skb;
 497         dma_addr_t paddr;
 498         int ret;
 499
 500         skb = dev_alloc_skb(pipe->buf_sz);
 501         if (!skb)
 502                 return -ENOMEM;
 503
 504         WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
 505
 506         paddr = dma_map_single(ar->dev, skb->data,
 507                                skb->len + skb_tailroom(skb),
 508                                DMA_FROM_DEVICE);
 509         if (unlikely(dma_mapping_error(ar->dev, paddr))) {
 510                 ath10k_warn(ar, "failed to dma map snoc rx buf\n");
 511                 dev_kfree_skb_any(skb);
 512                 return -EIO;
 513         }
 514
 515         ATH10K_SKB_RXCB(skb)->paddr = paddr;
 516
 517         spin_lock_bh(&ce->ce_lock);
 518         ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
 519         spin_unlock_bh(&ce->ce_lock);
 520         if (ret) {
 521                 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
 522                                  DMA_FROM_DEVICE);
 523                 dev_kfree_skb_any(skb);
 524                 return ret;
 525         }
 526
 527         return 0;
 528 }
 529
 530 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe)
 531 {
 532         struct ath10k *ar = pipe->hif_ce_state;
 533         struct ath10k_ce *ce = ath10k_ce_priv(ar);
 534         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 535         struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
 536         int ret, num;
 537
 538         if (pipe->buf_sz == 0)
 539                 return;
 540
 541         if (!ce_pipe->dest_ring)
 542                 return;
 543
 544         spin_lock_bh(&ce->ce_lock);
 545         num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
 546         spin_unlock_bh(&ce->ce_lock);
 547         while (num--) {
 548                 ret = __ath10k_snoc_rx_post_buf(pipe);
 549                 if (ret) {
 550                         if (ret == -ENOSPC)
 551                                 break;
 552                         ath10k_warn(ar, "failed to post rx buf: %d\n", ret);
 553                         mod_timer(&ar_snoc->rx_post_retry, jiffies +
 554                                   ATH10K_SNOC_RX_POST_RETRY_MS);
 555                         break;
 556                 }
 557         }
 558 }
 559
 560 static void ath10k_snoc_rx_post(struct ath10k *ar)
 561 {
 562         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 563         int i;
 564
 565         for (i = 0; i < CE_COUNT; i++)
 566                 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]);
 567 }
 568
 569 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state,
 570                                       void (*callback)(struct ath10k *ar,
 571                                                        struct sk_buff *skb))
 572 {
 573         struct ath10k *ar = ce_state->ar;
 574         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 575         struct ath10k_snoc_pipe *pipe_info =  &ar_snoc->pipe_info[ce_state->id];
 576         struct sk_buff *skb;
 577         struct sk_buff_head list;
 578         void *transfer_context;
 579         unsigned int nbytes, max_nbytes;
 580
 581         __skb_queue_head_init(&list);
 582         while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
 583                                              &nbytes) == 0) {
 584                 skb = transfer_context;
 585                 max_nbytes = skb->len + skb_tailroom(skb);
 586                 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
 587                                  max_nbytes, DMA_FROM_DEVICE);
 588
 589                 if (unlikely(max_nbytes < nbytes)) {
 590                         ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)\n",
 591                                     nbytes, max_nbytes);
 592                         dev_kfree_skb_any(skb);
 593                         continue;
 594                 }
 595
 596                 skb_put(skb, nbytes);
 597                 __skb_queue_tail(&list, skb);
 598         }
 599
 600         while ((skb = __skb_dequeue(&list))) {
 601                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n",
 602                            ce_state->id, skb->len);
 603
 604                 callback(ar, skb);
 605         }
 606
 607         ath10k_snoc_rx_post_pipe(pipe_info);
 608 }
 609
 610 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
 611 {
 612         ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
 613 }
 614
 615 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
 616 {
 617         /* CE4 polling needs to be done whenever CE pipe which transports
 618          * HTT Rx (target->host) is processed.
 619          */
 620         ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
 621
 622         ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
 623 }
 624
 625 /* Called by lower (CE) layer when data is received from the Target.
 626  * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data.
 627  */
 628 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
 629 {
 630         ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
 631 }
 632
 633 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
 634 {
 635         skb_pull(skb, sizeof(struct ath10k_htc_hdr));
 636         ath10k_htt_t2h_msg_handler(ar, skb);
 637 }
 638
 639 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
 640 {
 641         ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
 642         ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver);
 643 }
 644
 645 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
 646 {
 647         struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
 648         struct ath10k *ar = ar_snoc->ar;
 649
 650         ath10k_snoc_rx_post(ar);
 651 }
 652
 653 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
 654 {
 655         struct ath10k *ar = ce_state->ar;
 656         struct sk_buff_head list;
 657         struct sk_buff *skb;
 658
 659         __skb_queue_head_init(&list);
 660         while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
 661                 if (!skb)
 662                         continue;
 663
 664                 __skb_queue_tail(&list, skb);
 665         }
 666
 667         while ((skb = __skb_dequeue(&list)))
 668                 ath10k_htc_tx_completion_handler(ar, skb);
 669 }
 670
 671 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
 672 {
 673         struct ath10k *ar = ce_state->ar;
 674         struct sk_buff *skb;
 675
 676         while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
 677                 if (!skb)
 678                         continue;
 679
 680                 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
 681                                  skb->len, DMA_TO_DEVICE);
 682                 ath10k_htt_hif_tx_complete(ar, skb);
 683         }
 684 }
 685
 686 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
 687                                  struct ath10k_hif_sg_item *items, int n_items)
 688 {
 689         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 690         struct ath10k_ce *ce = ath10k_ce_priv(ar);
 691         struct ath10k_snoc_pipe *snoc_pipe;
 692         struct ath10k_ce_pipe *ce_pipe;
 693         int err, i = 0;
 694
 695         snoc_pipe = &ar_snoc->pipe_info[pipe_id];
 696         ce_pipe = snoc_pipe->ce_hdl;
 697         spin_lock_bh(&ce->ce_lock);
 698
 699         for (i = 0; i < n_items - 1; i++) {
 700                 ath10k_dbg(ar, ATH10K_DBG_SNOC,
 701                            "snoc tx item %d paddr %pad len %d n_items %d\n",
 702                            i, &items[i].paddr, items[i].len, n_items);
 703
 704                 err = ath10k_ce_send_nolock(ce_pipe,
 705                                             items[i].transfer_context,
 706                                             items[i].paddr,
 707                                             items[i].len,
 708                                             items[i].transfer_id,
 709                                             CE_SEND_FLAG_GATHER);
 710                 if (err)
 711                         goto err;
 712         }
 713
 714         ath10k_dbg(ar, ATH10K_DBG_SNOC,
 715                    "snoc tx item %d paddr %pad len %d n_items %d\n",
 716                    i, &items[i].paddr, items[i].len, n_items);
 717
 718         err = ath10k_ce_send_nolock(ce_pipe,
 719                                     items[i].transfer_context,
 720                                     items[i].paddr,
 721                                     items[i].len,
 722                                     items[i].transfer_id,
 723                                     0);
 724         if (err)
 725                 goto err;
 726
 727         spin_unlock_bh(&ce->ce_lock);
 728
 729         return 0;
 730
 731 err:
 732         for (; i > 0; i--)
 733                 __ath10k_ce_send_revert(ce_pipe);
 734
 735         spin_unlock_bh(&ce->ce_lock);
 736         return err;
 737 }
 738
 739 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar,
 740                                            struct bmi_target_info *target_info)
 741 {
 742         target_info->version = ATH10K_HW_WCN3990;
 743         target_info->type = ATH10K_HW_WCN3990;
 744
 745         return 0;
 746 }
 747
 748 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
 749 {
 750         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 751
 752         ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n");
 753
 754         return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl);
 755 }
 756
 757 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe,
 758                                                 int force)
 759 {
 760         int resources;
 761
 762         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n");
 763
 764         if (!force) {
 765                 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe);
 766
 767                 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
 768                         return;
 769         }
 770         ath10k_ce_per_engine_service(ar, pipe);
 771 }
 772
 773 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar,
 774                                                u16 service_id,
 775                                                u8 *ul_pipe, u8 *dl_pipe)
 776 {
 777         const struct ce_service_to_pipe *entry;
 778         bool ul_set = false, dl_set = false;
 779         int i;
 780
 781         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n");
 782
 783         for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
 784                 entry = &target_service_to_ce_map_wlan[i];
 785
 786                 if (__le32_to_cpu(entry->service_id) != service_id)
 787                         continue;
 788
 789                 switch (__le32_to_cpu(entry->pipedir)) {
 790                 case PIPEDIR_NONE:
 791                         break;
 792                 case PIPEDIR_IN:
 793                         WARN_ON(dl_set);
 794                         *dl_pipe = __le32_to_cpu(entry->pipenum);
 795                         dl_set = true;
 796                         break;
 797                 case PIPEDIR_OUT:
 798                         WARN_ON(ul_set);
 799                         *ul_pipe = __le32_to_cpu(entry->pipenum);
 800                         ul_set = true;
 801                         break;
 802                 case PIPEDIR_INOUT:
 803                         WARN_ON(dl_set);
 804                         WARN_ON(ul_set);
 805                         *dl_pipe = __le32_to_cpu(entry->pipenum);
 806                         *ul_pipe = __le32_to_cpu(entry->pipenum);
 807                         dl_set = true;
 808                         ul_set = true;
 809                         break;
 810                 }
 811         }
 812
 813         if (!ul_set || !dl_set)
 814                 return -ENOENT;
 815
 816         return 0;
 817 }
 818
 819 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar,
 820                                              u8 *ul_pipe, u8 *dl_pipe)
 821 {
 822         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n");
 823
 824         (void)ath10k_snoc_hif_map_service_to_pipe(ar,
 825                                                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
 826                                                  ul_pipe, dl_pipe);
 827 }
 828
 829 static inline void ath10k_snoc_irq_disable(struct ath10k *ar)
 830 {
 831         ath10k_ce_disable_interrupts(ar);
 832 }
 833
 834 static inline void ath10k_snoc_irq_enable(struct ath10k *ar)
 835 {
 836         ath10k_ce_enable_interrupts(ar);
 837 }
 838
 839 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
 840 {
 841         struct ath10k_ce_pipe *ce_pipe;
 842         struct ath10k_ce_ring *ce_ring;
 843         struct sk_buff *skb;
 844         struct ath10k *ar;
 845         int i;
 846
 847         ar = snoc_pipe->hif_ce_state;
 848         ce_pipe = snoc_pipe->ce_hdl;
 849         ce_ring = ce_pipe->dest_ring;
 850
 851         if (!ce_ring)
 852                 return;
 853
 854         if (!snoc_pipe->buf_sz)
 855                 return;
 856
 857         for (i = 0; i < ce_ring->nentries; i++) {
 858                 skb = ce_ring->per_transfer_context[i];
 859                 if (!skb)
 860                         continue;
 861
 862                 ce_ring->per_transfer_context[i] = NULL;
 863
 864                 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
 865                                  skb->len + skb_tailroom(skb),
 866                                  DMA_FROM_DEVICE);
 867                 dev_kfree_skb_any(skb);
 868         }
 869 }
 870
 871 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
 872 {
 873         struct ath10k_ce_pipe *ce_pipe;
 874         struct ath10k_ce_ring *ce_ring;
 875         struct sk_buff *skb;
 876         struct ath10k *ar;
 877         int i;
 878
 879         ar = snoc_pipe->hif_ce_state;
 880         ce_pipe = snoc_pipe->ce_hdl;
 881         ce_ring = ce_pipe->src_ring;
 882
 883         if (!ce_ring)
 884                 return;
 885
 886         if (!snoc_pipe->buf_sz)
 887                 return;
 888
 889         for (i = 0; i < ce_ring->nentries; i++) {
 890                 skb = ce_ring->per_transfer_context[i];
 891                 if (!skb)
 892                         continue;
 893
 894                 ce_ring->per_transfer_context[i] = NULL;
 895
 896                 ath10k_htc_tx_completion_handler(ar, skb);
 897         }
 898 }
 899
 900 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar)
 901 {
 902         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 903         struct ath10k_snoc_pipe *pipe_info;
 904         int pipe_num;
 905
 906         del_timer_sync(&ar_snoc->rx_post_retry);
 907         for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
 908                 pipe_info = &ar_snoc->pipe_info[pipe_num];
 909                 ath10k_snoc_rx_pipe_cleanup(pipe_info);
 910                 ath10k_snoc_tx_pipe_cleanup(pipe_info);
 911         }
 912 }
 913
 914 static void ath10k_snoc_hif_stop(struct ath10k *ar)
 915 {
 916         if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags))
 917                 ath10k_snoc_irq_disable(ar);
 918
 919         ath10k_core_napi_sync_disable(ar);
 920         ath10k_snoc_buffer_cleanup(ar);
 921         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
 922 }
 923
 924 static int ath10k_snoc_hif_start(struct ath10k *ar)
 925 {
 926         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 927
 928         bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX);
 929
 930         ath10k_core_napi_enable(ar);
 931         ath10k_snoc_irq_enable(ar);
 932         ath10k_snoc_rx_post(ar);
 933
 934         clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
 935
 936         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
 937
 938         return 0;
 939 }
 940
 941 static int ath10k_snoc_init_pipes(struct ath10k *ar)
 942 {
 943         int i, ret;
 944
 945         for (i = 0; i < CE_COUNT; i++) {
 946                 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
 947                 if (ret) {
 948                         ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
 949                                    i, ret);
 950                         return ret;
 951                 }
 952         }
 953
 954         return 0;
 955 }
 956
 957 static int ath10k_snoc_wlan_enable(struct ath10k *ar,
 958                                    enum ath10k_firmware_mode fw_mode)
 959 {
 960         struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX];
 961         struct ath10k_qmi_wlan_enable_cfg cfg;
 962         enum wlfw_driver_mode_enum_v01 mode;
 963         int pipe_num;
 964
 965         for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) {
 966                 tgt_cfg[pipe_num].pipe_num =
 967                                 target_ce_config_wlan[pipe_num].pipenum;
 968                 tgt_cfg[pipe_num].pipe_dir =
 969                                 target_ce_config_wlan[pipe_num].pipedir;
 970                 tgt_cfg[pipe_num].nentries =
 971                                 target_ce_config_wlan[pipe_num].nentries;
 972                 tgt_cfg[pipe_num].nbytes_max =
 973                                 target_ce_config_wlan[pipe_num].nbytes_max;
 974                 tgt_cfg[pipe_num].flags =
 975                                 target_ce_config_wlan[pipe_num].flags;
 976                 tgt_cfg[pipe_num].reserved = 0;
 977         }
 978
 979         cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) /
 980                                 sizeof(struct ath10k_tgt_pipe_cfg);
 981         cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *)
 982                 &tgt_cfg;
 983         cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) /
 984                                   sizeof(struct ath10k_svc_pipe_cfg);
 985         cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *)
 986                 &target_service_to_ce_map_wlan;
 987         cfg.num_shadow_reg_cfg = ARRAY_SIZE(target_shadow_reg_cfg_map);
 988         cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *)
 989                 &target_shadow_reg_cfg_map;
 990
 991         switch (fw_mode) {
 992         case ATH10K_FIRMWARE_MODE_NORMAL:
 993                 mode = QMI_WLFW_MISSION_V01;
 994                 break;
 995         case ATH10K_FIRMWARE_MODE_UTF:
 996                 mode = QMI_WLFW_FTM_V01;
 997                 break;
 998         default:
 999                 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode);
1000                 return -EINVAL;
1001         }
1002
1003         return ath10k_qmi_wlan_enable(ar, &cfg, mode,
1004                                        NULL);
1005 }
1006
1007 static int ath10k_hw_power_on(struct ath10k *ar)
1008 {
1009         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1010         int ret;
1011
1012         ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n");
1013
1014         ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs);
1015         if (ret)
1016                 return ret;
1017
1018         ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks);
1019         if (ret)
1020                 goto vreg_off;
1021
1022         return ret;
1023
1024 vreg_off:
1025         regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1026         return ret;
1027 }
1028
1029 static int ath10k_hw_power_off(struct ath10k *ar)
1030 {
1031         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1032
1033         ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n");
1034
1035         clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks);
1036
1037         return regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1038 }
1039
1040 static void ath10k_snoc_wlan_disable(struct ath10k *ar)
1041 {
1042         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1043
1044         /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY
1045          * flags are not set, it means that the driver has restarted
1046          * due to a crash inject via debugfs. In this case, the driver
1047          * needs to restart the firmware and hence send qmi wlan disable,
1048          * during the driver restart sequence.
1049          */
1050         if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) ||
1051             !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1052                 ath10k_qmi_wlan_disable(ar);
1053 }
1054
1055 static void ath10k_snoc_hif_power_down(struct ath10k *ar)
1056 {
1057         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
1058
1059         ath10k_snoc_wlan_disable(ar);
1060         ath10k_ce_free_rri(ar);
1061         ath10k_hw_power_off(ar);
1062 }
1063
1064 static int ath10k_snoc_hif_power_up(struct ath10k *ar,
1065                                     enum ath10k_firmware_mode fw_mode)
1066 {
1067         int ret;
1068
1069         ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n",
1070                    __func__, ar->state);
1071
1072         ret = ath10k_hw_power_on(ar);
1073         if (ret) {
1074                 ath10k_err(ar, "failed to power on device: %d\n", ret);
1075                 return ret;
1076         }
1077
1078         ret = ath10k_snoc_wlan_enable(ar, fw_mode);
1079         if (ret) {
1080                 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret);
1081                 goto err_hw_power_off;
1082         }
1083
1084         ath10k_ce_alloc_rri(ar);
1085
1086         ret = ath10k_snoc_init_pipes(ar);
1087         if (ret) {
1088                 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1089                 goto err_free_rri;
1090         }
1091
1092         return 0;
1093
1094 err_free_rri:
1095         ath10k_ce_free_rri(ar);
1096         ath10k_snoc_wlan_disable(ar);
1097
1098 err_hw_power_off:
1099         ath10k_hw_power_off(ar);
1100
1101         return ret;
1102 }
1103
1104 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar,
1105                                                u8 fw_log_mode)
1106 {
1107         u8 fw_dbg_mode;
1108
1109         if (fw_log_mode)
1110                 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE;
1111         else
1112                 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG;
1113
1114         return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode);
1115 }
1116
1117 #ifdef CONFIG_PM
1118 static int ath10k_snoc_hif_suspend(struct ath10k *ar)
1119 {
1120         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1121         int ret;
1122
1123         if (!device_may_wakeup(ar->dev))
1124                 return -EPERM;
1125
1126         ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1127         if (ret) {
1128                 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret);
1129                 return ret;
1130         }
1131
1132         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n");
1133
1134         return ret;
1135 }
1136
1137 static int ath10k_snoc_hif_resume(struct ath10k *ar)
1138 {
1139         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1140         int ret;
1141
1142         if (!device_may_wakeup(ar->dev))
1143                 return -EPERM;
1144
1145         ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1146         if (ret) {
1147                 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret);
1148                 return ret;
1149         }
1150
1151         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n");
1152
1153         return ret;
1154 }
1155 #endif
1156
1157 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = {
1158         .read32         = ath10k_snoc_read32,
1159         .write32        = ath10k_snoc_write32,
1160         .start          = ath10k_snoc_hif_start,
1161         .stop           = ath10k_snoc_hif_stop,
1162         .map_service_to_pipe    = ath10k_snoc_hif_map_service_to_pipe,
1163         .get_default_pipe       = ath10k_snoc_hif_get_default_pipe,
1164         .power_up               = ath10k_snoc_hif_power_up,
1165         .power_down             = ath10k_snoc_hif_power_down,
1166         .tx_sg                  = ath10k_snoc_hif_tx_sg,
1167         .send_complete_check    = ath10k_snoc_hif_send_complete_check,
1168         .get_free_queue_number  = ath10k_snoc_hif_get_free_queue_number,
1169         .get_target_info        = ath10k_snoc_hif_get_target_info,
1170         .set_target_log_mode    = ath10k_snoc_hif_set_target_log_mode,
1171
1172 #ifdef CONFIG_PM
1173         .suspend                = ath10k_snoc_hif_suspend,
1174         .resume                 = ath10k_snoc_hif_resume,
1175 #endif
1176 };
1177
1178 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = {
1179         .read32         = ath10k_snoc_read32,
1180         .write32        = ath10k_snoc_write32,
1181 };
1182
1183 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
1184 {
1185         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1186         int i;
1187
1188         for (i = 0; i < CE_COUNT_MAX; i++) {
1189                 if (ar_snoc->ce_irqs[i].irq_line == irq)
1190                         return i;
1191         }
1192         ath10k_err(ar, "No matching CE id for irq %d\n", irq);
1193
1194         return -EINVAL;
1195 }
1196
1197 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg)
1198 {
1199         struct ath10k *ar = arg;
1200         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1201         int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq);
1202
1203         if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) {
1204                 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
1205                             ce_id);
1206                 return IRQ_HANDLED;
1207         }
1208
1209         ath10k_ce_disable_interrupt(ar, ce_id);
1210         set_bit(ce_id, ar_snoc->pending_ce_irqs);
1211
1212         napi_schedule(&ar->napi);
1213
1214         return IRQ_HANDLED;
1215 }
1216
1217 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget)
1218 {
1219         struct ath10k *ar = container_of(ctx, struct ath10k, napi);
1220         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1221         int done = 0;
1222         int ce_id;
1223
1224         if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) {
1225                 napi_complete(ctx);
1226                 return done;
1227         }
1228
1229         for (ce_id = 0; ce_id < CE_COUNT; ce_id++)
1230                 if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) {
1231                         ath10k_ce_per_engine_service(ar, ce_id);
1232                         ath10k_ce_enable_interrupt(ar, ce_id);
1233                 }
1234
1235         done = ath10k_htt_txrx_compl_task(ar, budget);
1236
1237         if (done < budget)
1238                 napi_complete(ctx);
1239
1240         return done;
1241 }
1242
1243 static void ath10k_snoc_init_napi(struct ath10k *ar)
1244 {
1245         netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll,
1246                        NAPI_POLL_WEIGHT);
1247 }
1248
1249 static int ath10k_snoc_request_irq(struct ath10k *ar)
1250 {
1251         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1252         int irqflags = IRQF_TRIGGER_RISING;
1253         int ret, id;
1254
1255         for (id = 0; id < CE_COUNT_MAX; id++) {
1256                 ret = request_irq(ar_snoc->ce_irqs[id].irq_line,
1257                                   ath10k_snoc_per_engine_handler,
1258                                   irqflags, ce_name[id], ar);
1259                 if (ret) {
1260                         ath10k_err(ar,
1261                                    "failed to register IRQ handler for CE %d: %d\n",
1262                                    id, ret);
1263                         goto err_irq;
1264                 }
1265         }
1266
1267         return 0;
1268
1269 err_irq:
1270         for (id -= 1; id >= 0; id--)
1271                 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1272
1273         return ret;
1274 }
1275
1276 static void ath10k_snoc_free_irq(struct ath10k *ar)
1277 {
1278         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1279         int id;
1280
1281         for (id = 0; id < CE_COUNT_MAX; id++)
1282                 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1283 }
1284
1285 static int ath10k_snoc_resource_init(struct ath10k *ar)
1286 {
1287         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1288         struct platform_device *pdev;
1289         struct resource *res;
1290         int i, ret = 0;
1291
1292         pdev = ar_snoc->dev;
1293         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
1294         if (!res) {
1295                 ath10k_err(ar, "Memory base not found in DT\n");
1296                 return -EINVAL;
1297         }
1298
1299         ar_snoc->mem_pa = res->start;
1300         ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa,
1301                                     resource_size(res));
1302         if (!ar_snoc->mem) {
1303                 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n",
1304                            &ar_snoc->mem_pa);
1305                 return -EINVAL;
1306         }
1307
1308         for (i = 0; i < CE_COUNT; i++) {
1309                 ret = platform_get_irq(ar_snoc->dev, i);
1310                 if (ret < 0)
1311                         return ret;
1312                 ar_snoc->ce_irqs[i].irq_line = ret;
1313         }
1314
1315         ret = device_property_read_u32(&pdev->dev, "qcom,xo-cal-data",
1316                                        &ar_snoc->xo_cal_data);
1317         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc xo-cal-data return %d\n", ret);
1318         if (ret == 0) {
1319                 ar_snoc->xo_cal_supported = true;
1320                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "xo cal data %x\n",
1321                            ar_snoc->xo_cal_data);
1322         }
1323
1324         return 0;
1325 }
1326
1327 static void ath10k_snoc_quirks_init(struct ath10k *ar)
1328 {
1329         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1330         struct device *dev = &ar_snoc->dev->dev;
1331
1332         if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-8bit-quirk"))
1333                 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags);
1334 }
1335
1336 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type)
1337 {
1338         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1339         struct ath10k_bus_params bus_params = {};
1340         int ret;
1341
1342         if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags))
1343                 return 0;
1344
1345         switch (type) {
1346         case ATH10K_QMI_EVENT_FW_READY_IND:
1347                 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) {
1348                         ath10k_core_start_recovery(ar);
1349                         break;
1350                 }
1351
1352                 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
1353                 bus_params.chip_id = ar_snoc->target_info.soc_version;
1354                 ret = ath10k_core_register(ar, &bus_params);
1355                 if (ret) {
1356                         ath10k_err(ar, "Failed to register driver core: %d\n",
1357                                    ret);
1358                         return ret;
1359                 }
1360                 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags);
1361                 break;
1362         case ATH10K_QMI_EVENT_FW_DOWN_IND:
1363                 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1364                 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1365                 break;
1366         default:
1367                 ath10k_err(ar, "invalid fw indication: %llx\n", type);
1368                 return -EINVAL;
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int ath10k_snoc_setup_resource(struct ath10k *ar)
1375 {
1376         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1377         struct ath10k_ce *ce = ath10k_ce_priv(ar);
1378         struct ath10k_snoc_pipe *pipe;
1379         int i, ret;
1380
1381         timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0);
1382         spin_lock_init(&ce->ce_lock);
1383         for (i = 0; i < CE_COUNT; i++) {
1384                 pipe = &ar_snoc->pipe_info[i];
1385                 pipe->ce_hdl = &ce->ce_states[i];
1386                 pipe->pipe_num = i;
1387                 pipe->hif_ce_state = ar;
1388
1389                 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1390                 if (ret) {
1391                         ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1392                                    i, ret);
1393                         return ret;
1394                 }
1395
1396                 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max;
1397         }
1398         ath10k_snoc_init_napi(ar);
1399
1400         return 0;
1401 }
1402
1403 static void ath10k_snoc_release_resource(struct ath10k *ar)
1404 {
1405         int i;
1406
1407         netif_napi_del(&ar->napi);
1408         for (i = 0; i < CE_COUNT; i++)
1409                 ath10k_ce_free_pipe(ar, i);
1410 }
1411
1412 static void ath10k_msa_dump_memory(struct ath10k *ar,
1413                                    struct ath10k_fw_crash_data *crash_data)
1414 {
1415         const struct ath10k_hw_mem_layout *mem_layout;
1416         const struct ath10k_mem_region *current_region;
1417         struct ath10k_dump_ram_data_hdr *hdr;
1418         size_t buf_len;
1419         u8 *buf;
1420
1421         if (!crash_data || !crash_data->ramdump_buf)
1422                 return;
1423
1424         mem_layout = ath10k_coredump_get_mem_layout(ar);
1425         if (!mem_layout)
1426                 return;
1427
1428         current_region = &mem_layout->region_table.regions[0];
1429
1430         buf = crash_data->ramdump_buf;
1431         buf_len = crash_data->ramdump_buf_len;
1432         memset(buf, 0, buf_len);
1433
1434         /* Reserve space for the header. */
1435         hdr = (void *)buf;
1436         buf += sizeof(*hdr);
1437         buf_len -= sizeof(*hdr);
1438
1439         hdr->region_type = cpu_to_le32(current_region->type);
1440         hdr->start = cpu_to_le32((unsigned long)ar->msa.vaddr);
1441         hdr->length = cpu_to_le32(ar->msa.mem_size);
1442
1443         if (current_region->len < ar->msa.mem_size) {
1444                 memcpy(buf, ar->msa.vaddr, current_region->len);
1445                 ath10k_warn(ar, "msa dump length is less than msa size %x, %x\n",
1446                             current_region->len, ar->msa.mem_size);
1447         } else {
1448                 memcpy(buf, ar->msa.vaddr, ar->msa.mem_size);
1449         }
1450 }
1451
1452 void ath10k_snoc_fw_crashed_dump(struct ath10k *ar)
1453 {
1454         struct ath10k_fw_crash_data *crash_data;
1455         char guid[UUID_STRING_LEN + 1];
1456
1457         mutex_lock(&ar->dump_mutex);
1458
1459         spin_lock_bh(&ar->data_lock);
1460         ar->stats.fw_crash_counter++;
1461         spin_unlock_bh(&ar->data_lock);
1462
1463         crash_data = ath10k_coredump_new(ar);
1464
1465         if (crash_data)
1466                 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1467         else
1468                 scnprintf(guid, sizeof(guid), "n/a");
1469
1470         ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1471         ath10k_print_driver_info(ar);
1472         ath10k_msa_dump_memory(ar, crash_data);
1473         mutex_unlock(&ar->dump_mutex);
1474 }
1475
1476 static int ath10k_snoc_modem_notify(struct notifier_block *nb, unsigned long action,
1477                                     void *data)
1478 {
1479         struct ath10k_snoc *ar_snoc = container_of(nb, struct ath10k_snoc, nb);
1480         struct ath10k *ar = ar_snoc->ar;
1481         struct qcom_ssr_notify_data *notify_data = data;
1482
1483         switch (action) {
1484         case QCOM_SSR_BEFORE_POWERUP:
1485                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem starting event\n");
1486                 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1487                 break;
1488
1489         case QCOM_SSR_AFTER_POWERUP:
1490                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem running event\n");
1491                 break;
1492
1493         case QCOM_SSR_BEFORE_SHUTDOWN:
1494                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem %s event\n",
1495                            notify_data->crashed ? "crashed" : "stopping");
1496                 if (!notify_data->crashed)
1497                         set_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1498                 else
1499                         clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1500                 break;
1501
1502         case QCOM_SSR_AFTER_SHUTDOWN:
1503                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem offline event\n");
1504                 break;
1505
1506         default:
1507                 ath10k_err(ar, "received unrecognized event %lu\n", action);
1508                 break;
1509         }
1510
1511         return NOTIFY_OK;
1512 }
1513
1514 static int ath10k_modem_init(struct ath10k *ar)
1515 {
1516         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1517         void *notifier;
1518         int ret;
1519
1520         ar_snoc->nb.notifier_call = ath10k_snoc_modem_notify;
1521
1522         notifier = qcom_register_ssr_notifier("mpss", &ar_snoc->nb);
1523         if (IS_ERR(notifier)) {
1524                 ret = PTR_ERR(notifier);
1525                 ath10k_err(ar, "failed to initialize modem notifier: %d\n", ret);
1526                 return ret;
1527         }
1528
1529         ar_snoc->notifier = notifier;
1530
1531         return 0;
1532 }
1533
1534 static void ath10k_modem_deinit(struct ath10k *ar)
1535 {
1536         int ret;
1537         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1538
1539         ret = qcom_unregister_ssr_notifier(ar_snoc->notifier, &ar_snoc->nb);
1540         if (ret)
1541                 ath10k_err(ar, "error %d unregistering notifier\n", ret);
1542 }
1543
1544 static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size)
1545 {
1546         struct device *dev = ar->dev;
1547         struct device_node *node;
1548         struct resource r;
1549         int ret;
1550
1551         node = of_parse_phandle(dev->of_node, "memory-region", 0);
1552         if (node) {
1553                 ret = of_address_to_resource(node, 0, &r);
1554                 of_node_put(node);
1555                 if (ret) {
1556                         dev_err(dev, "failed to resolve msa fixed region\n");
1557                         return ret;
1558                 }
1559
1560                 ar->msa.paddr = r.start;
1561                 ar->msa.mem_size = resource_size(&r);
1562                 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr,
1563                                               ar->msa.mem_size,
1564                                               MEMREMAP_WT);
1565                 if (IS_ERR(ar->msa.vaddr)) {
1566                         dev_err(dev, "failed to map memory region: %pa\n",
1567                                 &r.start);
1568                         return PTR_ERR(ar->msa.vaddr);
1569                 }
1570         } else {
1571                 ar->msa.vaddr = dmam_alloc_coherent(dev, msa_size,
1572                                                     &ar->msa.paddr,
1573                                                     GFP_KERNEL);
1574                 if (!ar->msa.vaddr) {
1575                         ath10k_err(ar, "failed to allocate dma memory for msa region\n");
1576                         return -ENOMEM;
1577                 }
1578                 ar->msa.mem_size = msa_size;
1579         }
1580
1581         ath10k_dbg(ar, ATH10K_DBG_QMI, "qmi msa.paddr: %pad , msa.vaddr: 0x%p\n",
1582                    &ar->msa.paddr,
1583                    ar->msa.vaddr);
1584
1585         return 0;
1586 }
1587
1588 static int ath10k_fw_init(struct ath10k *ar)
1589 {
1590         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1591         struct device *host_dev = &ar_snoc->dev->dev;
1592         struct platform_device_info info;
1593         struct iommu_domain *iommu_dom;
1594         struct platform_device *pdev;
1595         struct device_node *node;
1596         int ret;
1597
1598         node = of_get_child_by_name(host_dev->of_node, "wifi-firmware");
1599         if (!node) {
1600                 ar_snoc->use_tz = true;
1601                 return 0;
1602         }
1603
1604         memset(&info, 0, sizeof(info));
1605         info.fwnode = &node->fwnode;
1606         info.parent = host_dev;
1607         info.name = node->name;
1608         info.dma_mask = DMA_BIT_MASK(32);
1609
1610         pdev = platform_device_register_full(&info);
1611         if (IS_ERR(pdev)) {
1612                 of_node_put(node);
1613                 return PTR_ERR(pdev);
1614         }
1615
1616         pdev->dev.of_node = node;
1617
1618         ret = of_dma_configure(&pdev->dev, node, true);
1619         if (ret) {
1620                 ath10k_err(ar, "dma configure fail: %d\n", ret);
1621                 goto err_unregister;
1622         }
1623
1624         ar_snoc->fw.dev = &pdev->dev;
1625
1626         iommu_dom = iommu_domain_alloc(&platform_bus_type);
1627         if (!iommu_dom) {
1628                 ath10k_err(ar, "failed to allocate iommu domain\n");
1629                 ret = -ENOMEM;
1630                 goto err_unregister;
1631         }
1632
1633         ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev);
1634         if (ret) {
1635                 ath10k_err(ar, "could not attach device: %d\n", ret);
1636                 goto err_iommu_free;
1637         }
1638
1639         ar_snoc->fw.iommu_domain = iommu_dom;
1640         ar_snoc->fw.fw_start_addr = ar->msa.paddr;
1641
1642         ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr,
1643                         ar->msa.paddr, ar->msa.mem_size,
1644                         IOMMU_READ | IOMMU_WRITE);
1645         if (ret) {
1646                 ath10k_err(ar, "failed to map firmware region: %d\n", ret);
1647                 goto err_iommu_detach;
1648         }
1649
1650         of_node_put(node);
1651
1652         return 0;
1653
1654 err_iommu_detach:
1655         iommu_detach_device(iommu_dom, ar_snoc->fw.dev);
1656
1657 err_iommu_free:
1658         iommu_domain_free(iommu_dom);
1659
1660 err_unregister:
1661         platform_device_unregister(pdev);
1662         of_node_put(node);
1663
1664         return ret;
1665 }
1666
1667 static int ath10k_fw_deinit(struct ath10k *ar)
1668 {
1669         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1670         const size_t mapped_size = ar_snoc->fw.mapped_mem_size;
1671         struct iommu_domain *iommu;
1672         size_t unmapped_size;
1673
1674         if (ar_snoc->use_tz)
1675                 return 0;
1676
1677         iommu = ar_snoc->fw.iommu_domain;
1678
1679         unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr,
1680                                     mapped_size);
1681         if (unmapped_size != mapped_size)
1682                 ath10k_err(ar, "failed to unmap firmware: %zu\n",
1683                            unmapped_size);
1684
1685         iommu_detach_device(iommu, ar_snoc->fw.dev);
1686         iommu_domain_free(iommu);
1687
1688         platform_device_unregister(to_platform_device(ar_snoc->fw.dev));
1689
1690         return 0;
1691 }
1692
1693 static const struct of_device_id ath10k_snoc_dt_match[] = {
1694         { .compatible = "qcom,wcn3990-wifi",
1695          .data = &drv_priv,
1696         },
1697         { }
1698 };
1699 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match);
1700
1701 static int ath10k_snoc_probe(struct platform_device *pdev)
1702 {
1703         const struct ath10k_snoc_drv_priv *drv_data;
1704         struct ath10k_snoc *ar_snoc;
1705         struct device *dev;
1706         struct ath10k *ar;
1707         u32 msa_size;
1708         int ret;
1709         u32 i;
1710
1711         dev = &pdev->dev;
1712         drv_data = device_get_match_data(dev);
1713         if (!drv_data) {
1714                 dev_err(dev, "failed to find matching device tree id\n");
1715                 return -EINVAL;
1716         }
1717
1718         ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask);
1719         if (ret) {
1720                 dev_err(dev, "failed to set dma mask: %d\n", ret);
1721                 return ret;
1722         }
1723
1724         ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC,
1725                                 drv_data->hw_rev, &ath10k_snoc_hif_ops);
1726         if (!ar) {
1727                 dev_err(dev, "failed to allocate core\n");
1728                 return -ENOMEM;
1729         }
1730
1731         ar_snoc = ath10k_snoc_priv(ar);
1732         ar_snoc->dev = pdev;
1733         platform_set_drvdata(pdev, ar);
1734         ar_snoc->ar = ar;
1735         ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
1736         ar->ce_priv = &ar_snoc->ce;
1737         msa_size = drv_data->msa_size;
1738
1739         ath10k_snoc_quirks_init(ar);
1740
1741         ret = ath10k_snoc_resource_init(ar);
1742         if (ret) {
1743                 ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
1744                 goto err_core_destroy;
1745         }
1746
1747         ret = ath10k_snoc_setup_resource(ar);
1748         if (ret) {
1749                 ath10k_warn(ar, "failed to setup resource: %d\n", ret);
1750                 goto err_core_destroy;
1751         }
1752         ret = ath10k_snoc_request_irq(ar);
1753         if (ret) {
1754                 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
1755                 goto err_release_resource;
1756         }
1757
1758         ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators);
1759         ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs,
1760                                       sizeof(*ar_snoc->vregs), GFP_KERNEL);
1761         if (!ar_snoc->vregs) {
1762                 ret = -ENOMEM;
1763                 goto err_free_irq;
1764         }
1765         for (i = 0; i < ar_snoc->num_vregs; i++)
1766                 ar_snoc->vregs[i].supply = ath10k_regulators[i];
1767
1768         ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs,
1769                                       ar_snoc->vregs);
1770         if (ret < 0)
1771                 goto err_free_irq;
1772
1773         ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks);
1774         ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks,
1775                                      sizeof(*ar_snoc->clks), GFP_KERNEL);
1776         if (!ar_snoc->clks) {
1777                 ret = -ENOMEM;
1778                 goto err_free_irq;
1779         }
1780
1781         for (i = 0; i < ar_snoc->num_clks; i++)
1782                 ar_snoc->clks[i].id = ath10k_clocks[i];
1783
1784         ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks,
1785                                          ar_snoc->clks);
1786         if (ret)
1787                 goto err_free_irq;
1788
1789         ret = ath10k_setup_msa_resources(ar, msa_size);
1790         if (ret) {
1791                 ath10k_warn(ar, "failed to setup msa resources: %d\n", ret);
1792                 goto err_free_irq;
1793         }
1794
1795         ret = ath10k_fw_init(ar);
1796         if (ret) {
1797                 ath10k_err(ar, "failed to initialize firmware: %d\n", ret);
1798                 goto err_free_irq;
1799         }
1800
1801         ret = ath10k_qmi_init(ar, msa_size);
1802         if (ret) {
1803                 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret);
1804                 goto err_fw_deinit;
1805         }
1806
1807         ret = ath10k_modem_init(ar);
1808         if (ret)
1809                 goto err_qmi_deinit;
1810
1811         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n");
1812
1813         return 0;
1814
1815 err_qmi_deinit:
1816         ath10k_qmi_deinit(ar);
1817
1818 err_fw_deinit:
1819         ath10k_fw_deinit(ar);
1820
1821 err_free_irq:
1822         ath10k_snoc_free_irq(ar);
1823
1824 err_release_resource:
1825         ath10k_snoc_release_resource(ar);
1826
1827 err_core_destroy:
1828         ath10k_core_destroy(ar);
1829
1830         return ret;
1831 }
1832
1833 static int ath10k_snoc_free_resources(struct ath10k *ar)
1834 {
1835         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1836
1837         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc free resources\n");
1838
1839         set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags);
1840
1841         ath10k_core_unregister(ar);
1842         ath10k_fw_deinit(ar);
1843         ath10k_snoc_free_irq(ar);
1844         ath10k_snoc_release_resource(ar);
1845         ath10k_modem_deinit(ar);
1846         ath10k_qmi_deinit(ar);
1847         ath10k_core_destroy(ar);
1848
1849         return 0;
1850 }
1851
1852 static int ath10k_snoc_remove(struct platform_device *pdev)
1853 {
1854         struct ath10k *ar = platform_get_drvdata(pdev);
1855         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1856
1857         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n");
1858
1859         reinit_completion(&ar->driver_recovery);
1860
1861         if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1862                 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ);
1863
1864         ath10k_snoc_free_resources(ar);
1865
1866         return 0;
1867 }
1868
1869 static void ath10k_snoc_shutdown(struct platform_device *pdev)
1870 {
1871         struct ath10k *ar = platform_get_drvdata(pdev);
1872
1873         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc shutdown\n");
1874         ath10k_snoc_free_resources(ar);
1875 }
1876
1877 static struct platform_driver ath10k_snoc_driver = {
1878         .probe  = ath10k_snoc_probe,
1879         .remove = ath10k_snoc_remove,
1880         .shutdown =  ath10k_snoc_shutdown,
1881         .driver = {
1882                 .name   = "ath10k_snoc",
1883                 .of_match_table = ath10k_snoc_dt_match,
1884         },
1885 };
1886 module_platform_driver(ath10k_snoc_driver);
1887
1888 MODULE_AUTHOR("Qualcomm");
1889 MODULE_LICENSE("Dual BSD/GPL");
1890 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");