2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012,2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include <linux/module.h>
20 #include <linux/mmc/card.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/sdio_func.h>
24 #include <linux/mmc/sdio_ids.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sd.h>
27 #include <linux/bitfield.h>
34 #include "targaddrs.h"
38 /* inlined helper functions */
40 static inline int ath10k_sdio_calc_txrx_padded_len(struct ath10k_sdio *ar_sdio,
43 return __ALIGN_MASK((len), ar_sdio->mbox_info.block_mask);
46 static inline enum ath10k_htc_ep_id pipe_id_to_eid(u8 pipe_id)
48 return (enum ath10k_htc_ep_id)pipe_id;
51 static inline void ath10k_sdio_mbox_free_rx_pkt(struct ath10k_sdio_rx_data *pkt)
53 dev_kfree_skb(pkt->skb);
57 pkt->trailer_only = false;
60 static inline int ath10k_sdio_mbox_alloc_rx_pkt(struct ath10k_sdio_rx_data *pkt,
61 size_t act_len, size_t full_len,
65 pkt->skb = dev_alloc_skb(full_len);
69 pkt->act_len = act_len;
70 pkt->alloc_len = full_len;
71 pkt->part_of_bundle = part_of_bundle;
72 pkt->last_in_bundle = last_in_bundle;
73 pkt->trailer_only = false;
78 static inline bool is_trailer_only_msg(struct ath10k_sdio_rx_data *pkt)
80 bool trailer_only = false;
81 struct ath10k_htc_hdr *htc_hdr =
82 (struct ath10k_htc_hdr *)pkt->skb->data;
83 u16 len = __le16_to_cpu(htc_hdr->len);
85 if (len == htc_hdr->trailer_len)
91 /* sdio/mmc functions */
93 static inline void ath10k_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
97 *arg = FIELD_PREP(BIT(31), write) |
98 FIELD_PREP(BIT(27), raw) |
99 FIELD_PREP(BIT(26), 1) |
100 FIELD_PREP(GENMASK(25, 9), address) |
101 FIELD_PREP(BIT(8), 1) |
102 FIELD_PREP(GENMASK(7, 0), val);
105 static int ath10k_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
106 unsigned int address,
109 struct mmc_command io_cmd;
111 memset(&io_cmd, 0, sizeof(io_cmd));
112 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
113 io_cmd.opcode = SD_IO_RW_DIRECT;
114 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
116 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
119 static int ath10k_sdio_func0_cmd52_rd_byte(struct mmc_card *card,
120 unsigned int address,
123 struct mmc_command io_cmd;
126 memset(&io_cmd, 0, sizeof(io_cmd));
127 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 0, 0, address, 0);
128 io_cmd.opcode = SD_IO_RW_DIRECT;
129 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
131 ret = mmc_wait_for_cmd(card->host, &io_cmd, 0);
133 *byte = io_cmd.resp[0];
138 static int ath10k_sdio_config(struct ath10k *ar)
140 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
141 struct sdio_func *func = ar_sdio->func;
142 unsigned char byte, asyncintdelay = 2;
145 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio configuration\n");
147 sdio_claim_host(func);
150 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
151 SDIO_CCCR_DRIVE_STRENGTH,
154 byte &= ~ATH10K_SDIO_DRIVE_DTSX_MASK;
155 byte |= FIELD_PREP(ATH10K_SDIO_DRIVE_DTSX_MASK,
156 ATH10K_SDIO_DRIVE_DTSX_TYPE_D);
158 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
159 SDIO_CCCR_DRIVE_STRENGTH,
163 ret = ath10k_sdio_func0_cmd52_rd_byte(
165 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
168 byte |= (CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A |
169 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C |
170 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D);
172 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
173 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
176 ath10k_warn(ar, "failed to enable driver strength: %d\n", ret);
181 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
182 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
185 byte |= SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3;
187 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
188 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
191 ath10k_warn(ar, "failed to enable 4-bit async irq mode: %d\n",
197 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
198 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
201 byte &= ~CCCR_SDIO_ASYNC_INT_DELAY_MASK;
202 byte |= FIELD_PREP(CCCR_SDIO_ASYNC_INT_DELAY_MASK, asyncintdelay);
204 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
205 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
208 /* give us some time to enable, in ms */
209 func->enable_timeout = 100;
211 ret = sdio_set_block_size(func, ar_sdio->mbox_info.block_size);
213 ath10k_warn(ar, "failed to set sdio block size to %d: %d\n",
214 ar_sdio->mbox_info.block_size, ret);
219 sdio_release_host(func);
223 static int ath10k_sdio_write32(struct ath10k *ar, u32 addr, u32 val)
225 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
226 struct sdio_func *func = ar_sdio->func;
229 sdio_claim_host(func);
231 sdio_writel(func, val, addr, &ret);
233 ath10k_warn(ar, "failed to write 0x%x to address 0x%x: %d\n",
238 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write32 addr 0x%x val 0x%x\n",
242 sdio_release_host(func);
247 static int ath10k_sdio_writesb32(struct ath10k *ar, u32 addr, u32 val)
249 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
250 struct sdio_func *func = ar_sdio->func;
254 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
258 *buf = cpu_to_le32(val);
260 sdio_claim_host(func);
262 ret = sdio_writesb(func, addr, buf, sizeof(*buf));
264 ath10k_warn(ar, "failed to write value 0x%x to fixed sb address 0x%x: %d\n",
269 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio writesb32 addr 0x%x val 0x%x\n",
273 sdio_release_host(func);
280 static int ath10k_sdio_read32(struct ath10k *ar, u32 addr, u32 *val)
282 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
283 struct sdio_func *func = ar_sdio->func;
286 sdio_claim_host(func);
287 *val = sdio_readl(func, addr, &ret);
289 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
294 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read32 addr 0x%x val 0x%x\n",
298 sdio_release_host(func);
303 static int ath10k_sdio_read(struct ath10k *ar, u32 addr, void *buf, size_t len)
305 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
306 struct sdio_func *func = ar_sdio->func;
309 sdio_claim_host(func);
311 ret = sdio_memcpy_fromio(func, buf, addr, len);
313 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
318 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read addr 0x%x buf 0x%p len %zu\n",
320 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio read ", buf, len);
323 sdio_release_host(func);
328 static int ath10k_sdio_write(struct ath10k *ar, u32 addr, const void *buf, size_t len)
330 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
331 struct sdio_func *func = ar_sdio->func;
334 sdio_claim_host(func);
336 /* For some reason toio() doesn't have const for the buffer, need
337 * an ugly hack to workaround that.
339 ret = sdio_memcpy_toio(func, addr, (void *)buf, len);
341 ath10k_warn(ar, "failed to write to address 0x%x: %d\n",
346 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write addr 0x%x buf 0x%p len %zu\n",
348 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio write ", buf, len);
351 sdio_release_host(func);
356 static int ath10k_sdio_readsb(struct ath10k *ar, u32 addr, void *buf, size_t len)
358 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
359 struct sdio_func *func = ar_sdio->func;
362 sdio_claim_host(func);
364 len = round_down(len, ar_sdio->mbox_info.block_size);
366 ret = sdio_readsb(func, buf, addr, len);
368 ath10k_warn(ar, "failed to read from fixed (sb) address 0x%x: %d\n",
373 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio readsb addr 0x%x buf 0x%p len %zu\n",
375 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio readsb ", buf, len);
378 sdio_release_host(func);
383 /* HIF mbox functions */
385 static int ath10k_sdio_mbox_rx_process_packet(struct ath10k *ar,
386 struct ath10k_sdio_rx_data *pkt,
390 struct ath10k_htc *htc = &ar->htc;
391 struct sk_buff *skb = pkt->skb;
392 struct ath10k_htc_hdr *htc_hdr = (struct ath10k_htc_hdr *)skb->data;
393 bool trailer_present = htc_hdr->flags & ATH10K_HTC_FLAG_TRAILER_PRESENT;
394 enum ath10k_htc_ep_id eid;
398 if (trailer_present) {
399 trailer = skb->data + skb->len - htc_hdr->trailer_len;
401 eid = pipe_id_to_eid(htc_hdr->eid);
403 ret = ath10k_htc_process_trailer(htc,
405 htc_hdr->trailer_len,
412 if (is_trailer_only_msg(pkt))
413 pkt->trailer_only = true;
415 skb_trim(skb, skb->len - htc_hdr->trailer_len);
418 skb_pull(skb, sizeof(*htc_hdr));
423 static int ath10k_sdio_mbox_rx_process_packets(struct ath10k *ar,
427 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
428 struct ath10k_htc *htc = &ar->htc;
429 struct ath10k_sdio_rx_data *pkt;
430 struct ath10k_htc_ep *ep;
431 enum ath10k_htc_ep_id id;
432 int ret, i, *n_lookahead_local;
433 u32 *lookaheads_local;
434 int lookahead_idx = 0;
436 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
437 lookaheads_local = lookaheads;
438 n_lookahead_local = n_lookahead;
440 id = ((struct ath10k_htc_hdr *)
441 &lookaheads[lookahead_idx++])->eid;
443 if (id >= ATH10K_HTC_EP_COUNT) {
444 ath10k_warn(ar, "invalid endpoint in look-ahead: %d\n",
450 ep = &htc->endpoint[id];
452 if (ep->service_id == 0) {
453 ath10k_warn(ar, "ep %d is not connected\n", id);
458 pkt = &ar_sdio->rx_pkts[i];
460 if (pkt->part_of_bundle && !pkt->last_in_bundle) {
461 /* Only read lookahead's from RX trailers
462 * for the last packet in a bundle.
465 lookaheads_local = NULL;
466 n_lookahead_local = NULL;
469 ret = ath10k_sdio_mbox_rx_process_packet(ar,
476 if (!pkt->trailer_only)
477 ep->ep_ops.ep_rx_complete(ar_sdio->ar, pkt->skb);
481 /* The RX complete handler now owns the skb...*/
489 /* Free all packets that was not passed on to the RX completion
492 for (; i < ar_sdio->n_rx_pkts; i++)
493 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
498 static int ath10k_sdio_mbox_alloc_pkt_bundle(struct ath10k *ar,
499 struct ath10k_sdio_rx_data *rx_pkts,
500 struct ath10k_htc_hdr *htc_hdr,
501 size_t full_len, size_t act_len,
506 *bndl_cnt = FIELD_GET(ATH10K_HTC_FLAG_BUNDLE_MASK, htc_hdr->flags);
508 if (*bndl_cnt > HTC_HOST_MAX_MSG_PER_BUNDLE) {
510 "HTC bundle length %u exceeds maximum %u\n",
511 le16_to_cpu(htc_hdr->len),
512 HTC_HOST_MAX_MSG_PER_BUNDLE);
516 /* Allocate bndl_cnt extra skb's for the bundle.
517 * The package containing the
518 * ATH10K_HTC_FLAG_BUNDLE_MASK flag is not included
519 * in bndl_cnt. The skb for that packet will be
520 * allocated separately.
522 for (i = 0; i < *bndl_cnt; i++) {
523 ret = ath10k_sdio_mbox_alloc_rx_pkt(&rx_pkts[i],
535 static int ath10k_sdio_mbox_rx_alloc(struct ath10k *ar,
536 u32 lookaheads[], int n_lookaheads)
538 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
539 struct ath10k_htc_hdr *htc_hdr;
540 size_t full_len, act_len;
544 if (n_lookaheads > ATH10K_SDIO_MAX_RX_MSGS) {
546 "the total number of pkgs to be fetched (%u) exceeds maximum %u\n",
548 ATH10K_SDIO_MAX_RX_MSGS);
553 for (i = 0; i < n_lookaheads; i++) {
554 htc_hdr = (struct ath10k_htc_hdr *)&lookaheads[i];
555 last_in_bundle = false;
557 if (le16_to_cpu(htc_hdr->len) >
558 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH) {
560 "payload length %d exceeds max htc length: %zu\n",
561 le16_to_cpu(htc_hdr->len),
562 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH);
565 queue_work(ar->workqueue, &ar->restart_work);
566 ath10k_warn(ar, "exceeds length, start recovery\n");
571 act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr);
572 full_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio, act_len);
574 if (full_len > ATH10K_SDIO_MAX_BUFFER_SIZE) {
576 "rx buffer requested with invalid htc_hdr length (%d, 0x%x): %d\n",
577 htc_hdr->eid, htc_hdr->flags,
578 le16_to_cpu(htc_hdr->len));
583 if (htc_hdr->flags & ATH10K_HTC_FLAG_BUNDLE_MASK) {
584 /* HTC header indicates that every packet to follow
585 * has the same padded length so that it can be
586 * optimally fetched as a full bundle.
590 ret = ath10k_sdio_mbox_alloc_pkt_bundle(ar,
591 &ar_sdio->rx_pkts[i],
597 n_lookaheads += bndl_cnt;
599 /*Next buffer will be the last in the bundle */
600 last_in_bundle = true;
603 /* Allocate skb for packet. If the packet had the
604 * ATH10K_HTC_FLAG_BUNDLE_MASK flag set, all bundled
605 * packet skb's have been allocated in the previous step.
607 ret = ath10k_sdio_mbox_alloc_rx_pkt(&ar_sdio->rx_pkts[i],
613 ath10k_warn(ar, "alloc_rx_pkt error %d\n", ret);
618 ar_sdio->n_rx_pkts = i;
623 for (i = 0; i < ATH10K_SDIO_MAX_RX_MSGS; i++) {
624 if (!ar_sdio->rx_pkts[i].alloc_len)
626 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
632 static int ath10k_sdio_mbox_rx_packet(struct ath10k *ar,
633 struct ath10k_sdio_rx_data *pkt)
635 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
636 struct sk_buff *skb = pkt->skb;
637 struct ath10k_htc_hdr *htc_hdr;
640 ret = ath10k_sdio_readsb(ar, ar_sdio->mbox_info.htc_addr,
641 skb->data, pkt->alloc_len);
645 /* Update actual length. The original length may be incorrect,
646 * as the FW will bundle multiple packets as long as their sizes
647 * fit within the same aligned length (pkt->alloc_len).
649 htc_hdr = (struct ath10k_htc_hdr *)skb->data;
650 pkt->act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr);
651 if (pkt->act_len > pkt->alloc_len) {
652 ath10k_warn(ar, "rx packet too large (%zu > %zu)\n",
653 pkt->act_len, pkt->alloc_len);
658 skb_put(skb, pkt->act_len);
666 static int ath10k_sdio_mbox_rx_fetch(struct ath10k *ar)
668 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
671 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
672 ret = ath10k_sdio_mbox_rx_packet(ar,
673 &ar_sdio->rx_pkts[i]);
681 /* Free all packets that was not successfully fetched. */
682 for (; i < ar_sdio->n_rx_pkts; i++)
683 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
688 /* This is the timeout for mailbox processing done in the sdio irq
689 * handler. The timeout is deliberately set quite high since SDIO dump logs
690 * over serial port can/will add a substantial overhead to the processing
693 #define SDIO_MBOX_PROCESSING_TIMEOUT_HZ (20 * HZ)
695 static int ath10k_sdio_mbox_rxmsg_pending_handler(struct ath10k *ar,
696 u32 msg_lookahead, bool *done)
698 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
699 u32 lookaheads[ATH10K_SDIO_MAX_RX_MSGS];
700 int n_lookaheads = 1;
701 unsigned long timeout;
706 /* Copy the lookahead obtained from the HTC register table into our
707 * temp array as a start value.
709 lookaheads[0] = msg_lookahead;
711 timeout = jiffies + SDIO_MBOX_PROCESSING_TIMEOUT_HZ;
713 /* Try to allocate as many HTC RX packets indicated by
716 ret = ath10k_sdio_mbox_rx_alloc(ar, lookaheads,
721 if (ar_sdio->n_rx_pkts >= 2)
722 /* A recv bundle was detected, force IRQ status
727 ret = ath10k_sdio_mbox_rx_fetch(ar);
729 /* Process fetched packets. This will potentially update
730 * n_lookaheads depending on if the packets contain lookahead
734 ret = ath10k_sdio_mbox_rx_process_packets(ar,
738 if (!n_lookaheads || ret)
741 /* For SYNCH processing, if we get here, we are running
742 * through the loop again due to updated lookaheads. Set
743 * flag that we should re-check IRQ status registers again
744 * before leaving IRQ processing, this can net better
745 * performance in high throughput situations.
748 } while (time_before(jiffies, timeout));
750 if (ret && (ret != -ECANCELED))
751 ath10k_warn(ar, "failed to get pending recv messages: %d\n",
757 static int ath10k_sdio_mbox_proc_dbg_intr(struct ath10k *ar)
762 /* TODO: Add firmware crash handling */
763 ath10k_warn(ar, "firmware crashed\n");
765 /* read counter to clear the interrupt, the debug error interrupt is
768 ret = ath10k_sdio_read32(ar, MBOX_COUNT_DEC_ADDRESS, &val);
770 ath10k_warn(ar, "failed to clear debug interrupt: %d\n", ret);
775 static int ath10k_sdio_mbox_proc_counter_intr(struct ath10k *ar)
777 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
778 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
779 u8 counter_int_status;
782 mutex_lock(&irq_data->mtx);
783 counter_int_status = irq_data->irq_proc_reg->counter_int_status &
784 irq_data->irq_en_reg->cntr_int_status_en;
786 /* NOTE: other modules like GMBOX may use the counter interrupt for
787 * credit flow control on other counters, we only need to check for
788 * the debug assertion counter interrupt.
790 if (counter_int_status & ATH10K_SDIO_TARGET_DEBUG_INTR_MASK)
791 ret = ath10k_sdio_mbox_proc_dbg_intr(ar);
795 mutex_unlock(&irq_data->mtx);
800 static int ath10k_sdio_mbox_proc_err_intr(struct ath10k *ar)
802 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
803 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
807 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio error interrupt\n");
809 error_int_status = irq_data->irq_proc_reg->error_int_status & 0x0F;
810 if (!error_int_status) {
811 ath10k_warn(ar, "invalid error interrupt status: 0x%x\n",
816 ath10k_dbg(ar, ATH10K_DBG_SDIO,
817 "sdio error_int_status 0x%x\n", error_int_status);
819 if (FIELD_GET(MBOX_ERROR_INT_STATUS_WAKEUP_MASK,
821 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio interrupt error wakeup\n");
823 if (FIELD_GET(MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
825 ath10k_warn(ar, "rx underflow interrupt error\n");
827 if (FIELD_GET(MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
829 ath10k_warn(ar, "tx overflow interrupt error\n");
831 /* Clear the interrupt */
832 irq_data->irq_proc_reg->error_int_status &= ~error_int_status;
834 /* set W1C value to clear the interrupt, this hits the register first */
835 ret = ath10k_sdio_writesb32(ar, MBOX_ERROR_INT_STATUS_ADDRESS,
838 ath10k_warn(ar, "unable to write to error int status address: %d\n",
846 static int ath10k_sdio_mbox_proc_cpu_intr(struct ath10k *ar)
848 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
849 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
853 mutex_lock(&irq_data->mtx);
854 cpu_int_status = irq_data->irq_proc_reg->cpu_int_status &
855 irq_data->irq_en_reg->cpu_int_status_en;
856 if (!cpu_int_status) {
857 ath10k_warn(ar, "CPU interrupt status is zero\n");
862 /* Clear the interrupt */
863 irq_data->irq_proc_reg->cpu_int_status &= ~cpu_int_status;
865 /* Set up the register transfer buffer to hit the register 4 times,
866 * this is done to make the access 4-byte aligned to mitigate issues
867 * with host bus interconnects that restrict bus transfer lengths to
868 * be a multiple of 4-bytes.
870 * Set W1C value to clear the interrupt, this hits the register first.
872 ret = ath10k_sdio_writesb32(ar, MBOX_CPU_INT_STATUS_ADDRESS,
875 ath10k_warn(ar, "unable to write to cpu interrupt status address: %d\n",
881 mutex_unlock(&irq_data->mtx);
885 static int ath10k_sdio_mbox_read_int_status(struct ath10k *ar,
889 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
890 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
891 struct ath10k_sdio_irq_proc_regs *irq_proc_reg = irq_data->irq_proc_reg;
892 struct ath10k_sdio_irq_enable_regs *irq_en_reg = irq_data->irq_en_reg;
893 u8 htc_mbox = FIELD_PREP(ATH10K_HTC_MAILBOX_MASK, 1);
896 mutex_lock(&irq_data->mtx);
899 *host_int_status = 0;
901 /* int_status_en is supposed to be non zero, otherwise interrupts
902 * shouldn't be enabled. There is however a short time frame during
903 * initialization between the irq register and int_status_en init
904 * where this can happen.
905 * We silently ignore this condition.
907 if (!irq_en_reg->int_status_en) {
912 /* Read the first sizeof(struct ath10k_irq_proc_registers)
913 * bytes of the HTC register table. This
914 * will yield us the value of different int status
915 * registers and the lookahead registers.
917 ret = ath10k_sdio_read(ar, MBOX_HOST_INT_STATUS_ADDRESS,
918 irq_proc_reg, sizeof(*irq_proc_reg));
922 /* Update only those registers that are enabled */
923 *host_int_status = irq_proc_reg->host_int_status &
924 irq_en_reg->int_status_en;
926 /* Look at mbox status */
927 if (!(*host_int_status & htc_mbox)) {
933 /* Mask out pending mbox value, we use look ahead as
934 * the real flag for mbox processing.
936 *host_int_status &= ~htc_mbox;
937 if (irq_proc_reg->rx_lookahead_valid & htc_mbox) {
938 *lookahead = le32_to_cpu(
939 irq_proc_reg->rx_lookahead[ATH10K_HTC_MAILBOX]);
941 ath10k_warn(ar, "sdio mbox lookahead is zero\n");
945 mutex_unlock(&irq_data->mtx);
949 static int ath10k_sdio_mbox_proc_pending_irqs(struct ath10k *ar,
956 /* NOTE: HIF implementation guarantees that the context of this
957 * call allows us to perform SYNCHRONOUS I/O, that is we can block,
958 * sleep or call any API that can block or switch thread/task
959 * contexts. This is a fully schedulable context.
962 ret = ath10k_sdio_mbox_read_int_status(ar,
970 if (!host_int_status && !lookahead) {
977 ath10k_dbg(ar, ATH10K_DBG_SDIO,
978 "sdio pending mailbox msg lookahead 0x%08x\n",
981 ret = ath10k_sdio_mbox_rxmsg_pending_handler(ar,
988 /* now, handle the rest of the interrupts */
989 ath10k_dbg(ar, ATH10K_DBG_SDIO,
990 "sdio host_int_status 0x%x\n", host_int_status);
992 if (FIELD_GET(MBOX_HOST_INT_STATUS_CPU_MASK, host_int_status)) {
994 ret = ath10k_sdio_mbox_proc_cpu_intr(ar);
999 if (FIELD_GET(MBOX_HOST_INT_STATUS_ERROR_MASK, host_int_status)) {
1000 /* Error Interrupt */
1001 ret = ath10k_sdio_mbox_proc_err_intr(ar);
1006 if (FIELD_GET(MBOX_HOST_INT_STATUS_COUNTER_MASK, host_int_status))
1007 /* Counter Interrupt */
1008 ret = ath10k_sdio_mbox_proc_counter_intr(ar);
1013 /* An optimization to bypass reading the IRQ status registers
1014 * unecessarily which can re-wake the target, if upper layers
1015 * determine that we are in a low-throughput mode, we can rely on
1016 * taking another interrupt rather than re-checking the status
1017 * registers which can re-wake the target.
1019 * NOTE : for host interfaces that makes use of detecting pending
1020 * mbox messages at hif can not use this optimization due to
1021 * possible side effects, SPI requires the host to drain all
1022 * messages from the mailbox before exiting the ISR routine.
1025 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1026 "sdio pending irqs done %d status %d",
1032 static void ath10k_sdio_set_mbox_info(struct ath10k *ar)
1034 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1035 struct ath10k_mbox_info *mbox_info = &ar_sdio->mbox_info;
1036 u16 device = ar_sdio->func->device, dev_id_base, dev_id_chiprev;
1038 mbox_info->htc_addr = ATH10K_HIF_MBOX_BASE_ADDR;
1039 mbox_info->block_size = ATH10K_HIF_MBOX_BLOCK_SIZE;
1040 mbox_info->block_mask = ATH10K_HIF_MBOX_BLOCK_SIZE - 1;
1041 mbox_info->gmbox_addr = ATH10K_HIF_GMBOX_BASE_ADDR;
1042 mbox_info->gmbox_sz = ATH10K_HIF_GMBOX_WIDTH;
1044 mbox_info->ext_info[0].htc_ext_addr = ATH10K_HIF_MBOX0_EXT_BASE_ADDR;
1046 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, device);
1047 dev_id_chiprev = FIELD_GET(QCA_MANUFACTURER_ID_REV_MASK, device);
1048 switch (dev_id_base) {
1049 case QCA_MANUFACTURER_ID_AR6005_BASE:
1050 if (dev_id_chiprev < 4)
1051 mbox_info->ext_info[0].htc_ext_sz =
1052 ATH10K_HIF_MBOX0_EXT_WIDTH;
1054 /* from QCA6174 2.0(0x504), the width has been extended
1057 mbox_info->ext_info[0].htc_ext_sz =
1058 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1060 case QCA_MANUFACTURER_ID_QCA9377_BASE:
1061 mbox_info->ext_info[0].htc_ext_sz =
1062 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1065 mbox_info->ext_info[0].htc_ext_sz =
1066 ATH10K_HIF_MBOX0_EXT_WIDTH;
1069 mbox_info->ext_info[1].htc_ext_addr =
1070 mbox_info->ext_info[0].htc_ext_addr +
1071 mbox_info->ext_info[0].htc_ext_sz +
1072 ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE;
1073 mbox_info->ext_info[1].htc_ext_sz = ATH10K_HIF_MBOX1_EXT_WIDTH;
1078 static int ath10k_sdio_bmi_credits(struct ath10k *ar)
1080 u32 addr, cmd_credits;
1081 unsigned long timeout;
1084 /* Read the counter register to get the command credits */
1085 addr = MBOX_COUNT_DEC_ADDRESS + ATH10K_HIF_MBOX_NUM_MAX * 4;
1086 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1089 while (time_before(jiffies, timeout) && !cmd_credits) {
1090 /* Hit the credit counter with a 4-byte access, the first byte
1091 * read will hit the counter and cause a decrement, while the
1092 * remaining 3 bytes has no effect. The rationale behind this
1093 * is to make all HIF accesses 4-byte aligned.
1095 ret = ath10k_sdio_read32(ar, addr, &cmd_credits);
1098 "unable to decrement the command credit count register: %d\n",
1103 /* The counter is only 8 bits.
1104 * Ignore anything in the upper 3 bytes
1106 cmd_credits &= 0xFF;
1110 ath10k_warn(ar, "bmi communication timeout\n");
1117 static int ath10k_sdio_bmi_get_rx_lookahead(struct ath10k *ar)
1119 unsigned long timeout;
1123 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1126 while ((time_before(jiffies, timeout)) && !rx_word) {
1127 ret = ath10k_sdio_read32(ar,
1128 MBOX_HOST_INT_STATUS_ADDRESS,
1131 ath10k_warn(ar, "unable to read RX_LOOKAHEAD_VALID: %d\n", ret);
1135 /* all we really want is one bit */
1140 ath10k_warn(ar, "bmi_recv_buf FIFO empty\n");
1147 static int ath10k_sdio_bmi_exchange_msg(struct ath10k *ar,
1148 void *req, u32 req_len,
1149 void *resp, u32 *resp_len)
1151 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1156 ret = ath10k_sdio_bmi_credits(ar);
1160 addr = ar_sdio->mbox_info.htc_addr;
1162 memcpy(ar_sdio->bmi_buf, req, req_len);
1163 ret = ath10k_sdio_write(ar, addr, ar_sdio->bmi_buf, req_len);
1166 "unable to send the bmi data to the device: %d\n",
1172 if (!resp || !resp_len)
1173 /* No response expected */
1176 /* During normal bootup, small reads may be required.
1177 * Rather than issue an HIF Read and then wait as the Target
1178 * adds successive bytes to the FIFO, we wait here until
1179 * we know that response data is available.
1181 * This allows us to cleanly timeout on an unexpected
1182 * Target failure rather than risk problems at the HIF level.
1183 * In particular, this avoids SDIO timeouts and possibly garbage
1184 * data on some host controllers. And on an interconnect
1185 * such as Compact Flash (as well as some SDIO masters) which
1186 * does not provide any indication on data timeout, it avoids
1187 * a potential hang or garbage response.
1189 * Synchronization is more difficult for reads larger than the
1190 * size of the MBOX FIFO (128B), because the Target is unable
1191 * to push the 129th byte of data until AFTER the Host posts an
1192 * HIF Read and removes some FIFO data. So for large reads the
1193 * Host proceeds to post an HIF Read BEFORE all the data is
1194 * actually available to read. Fortunately, large BMI reads do
1195 * not occur in practice -- they're supported for debug/development.
1197 * So Host/Target BMI synchronization is divided into these cases:
1198 * CASE 1: length < 4
1201 * CASE 2: 4 <= length <= 128
1202 * Wait for first 4 bytes to be in FIFO
1203 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1204 * a BMI command credit, which indicates that the ENTIRE
1205 * response is available in the the FIFO
1207 * CASE 3: length > 128
1208 * Wait for the first 4 bytes to be in FIFO
1210 * For most uses, a small timeout should be sufficient and we will
1211 * usually see a response quickly; but there may be some unusual
1212 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1213 * For now, we use an unbounded busy loop while waiting for
1216 * If BMI_EXECUTE ever needs to support longer-latency execution,
1217 * especially in production, this code needs to be enhanced to sleep
1218 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1219 * a function of Host processor speed.
1221 ret = ath10k_sdio_bmi_get_rx_lookahead(ar);
1225 /* We always read from the start of the mbox address */
1226 addr = ar_sdio->mbox_info.htc_addr;
1227 ret = ath10k_sdio_read(ar, addr, ar_sdio->bmi_buf, *resp_len);
1230 "unable to read the bmi data from the device: %d\n",
1235 memcpy(resp, ar_sdio->bmi_buf, *resp_len);
1240 /* sdio async handling functions */
1242 static struct ath10k_sdio_bus_request
1243 *ath10k_sdio_alloc_busreq(struct ath10k *ar)
1245 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1246 struct ath10k_sdio_bus_request *bus_req;
1248 spin_lock_bh(&ar_sdio->lock);
1250 if (list_empty(&ar_sdio->bus_req_freeq)) {
1255 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
1256 struct ath10k_sdio_bus_request, list);
1257 list_del(&bus_req->list);
1260 spin_unlock_bh(&ar_sdio->lock);
1264 static void ath10k_sdio_free_bus_req(struct ath10k *ar,
1265 struct ath10k_sdio_bus_request *bus_req)
1267 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1269 memset(bus_req, 0, sizeof(*bus_req));
1271 spin_lock_bh(&ar_sdio->lock);
1272 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
1273 spin_unlock_bh(&ar_sdio->lock);
1276 static void __ath10k_sdio_write_async(struct ath10k *ar,
1277 struct ath10k_sdio_bus_request *req)
1279 struct ath10k_htc_ep *ep;
1280 struct sk_buff *skb;
1284 ret = ath10k_sdio_write(ar, req->address, skb->data, skb->len);
1286 ath10k_warn(ar, "failed to write skb to 0x%x asynchronously: %d",
1290 ep = &ar->htc.endpoint[req->eid];
1291 ath10k_htc_notify_tx_completion(ep, skb);
1292 } else if (req->comp) {
1293 complete(req->comp);
1296 ath10k_sdio_free_bus_req(ar, req);
1299 static void ath10k_sdio_write_async_work(struct work_struct *work)
1301 struct ath10k_sdio *ar_sdio = container_of(work, struct ath10k_sdio,
1303 struct ath10k *ar = ar_sdio->ar;
1304 struct ath10k_sdio_bus_request *req, *tmp_req;
1306 spin_lock_bh(&ar_sdio->wr_async_lock);
1308 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1309 list_del(&req->list);
1310 spin_unlock_bh(&ar_sdio->wr_async_lock);
1311 __ath10k_sdio_write_async(ar, req);
1312 spin_lock_bh(&ar_sdio->wr_async_lock);
1315 spin_unlock_bh(&ar_sdio->wr_async_lock);
1318 static int ath10k_sdio_prep_async_req(struct ath10k *ar, u32 addr,
1319 struct sk_buff *skb,
1320 struct completion *comp,
1321 bool htc_msg, enum ath10k_htc_ep_id eid)
1323 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1324 struct ath10k_sdio_bus_request *bus_req;
1326 /* Allocate a bus request for the message and queue it on the
1329 bus_req = ath10k_sdio_alloc_busreq(ar);
1332 "unable to allocate bus request for async request\n");
1338 bus_req->address = addr;
1339 bus_req->htc_msg = htc_msg;
1340 bus_req->comp = comp;
1342 spin_lock_bh(&ar_sdio->wr_async_lock);
1343 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
1344 spin_unlock_bh(&ar_sdio->wr_async_lock);
1351 static void ath10k_sdio_irq_handler(struct sdio_func *func)
1353 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
1354 struct ath10k *ar = ar_sdio->ar;
1355 unsigned long timeout;
1359 /* Release the host during interrupts so we can pick it back up when
1360 * we process commands.
1362 sdio_release_host(ar_sdio->func);
1364 timeout = jiffies + ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ;
1366 ret = ath10k_sdio_mbox_proc_pending_irqs(ar, &done);
1369 } while (time_before(jiffies, timeout) && !done);
1371 ath10k_mac_tx_push_pending(ar);
1373 sdio_claim_host(ar_sdio->func);
1375 if (ret && ret != -ECANCELED)
1376 ath10k_warn(ar, "failed to process pending SDIO interrupts: %d\n",
1380 /* sdio HIF functions */
1382 static int ath10k_sdio_hif_disable_intrs(struct ath10k *ar)
1384 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1385 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1386 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1389 mutex_lock(&irq_data->mtx);
1391 memset(regs, 0, sizeof(*regs));
1392 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1393 ®s->int_status_en, sizeof(*regs));
1395 ath10k_warn(ar, "unable to disable sdio interrupts: %d\n", ret);
1397 mutex_unlock(&irq_data->mtx);
1402 static int ath10k_sdio_hif_power_up(struct ath10k *ar)
1404 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1405 struct sdio_func *func = ar_sdio->func;
1408 if (!ar_sdio->is_disabled)
1411 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power on\n");
1413 sdio_claim_host(func);
1415 ret = sdio_enable_func(func);
1417 ath10k_warn(ar, "unable to enable sdio function: %d)\n", ret);
1418 sdio_release_host(func);
1422 sdio_release_host(func);
1424 /* Wait for hardware to initialise. It should take a lot less than
1425 * 20 ms but let's be conservative here.
1429 ar_sdio->is_disabled = false;
1431 ret = ath10k_sdio_hif_disable_intrs(ar);
1438 static void ath10k_sdio_hif_power_down(struct ath10k *ar)
1440 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1443 if (ar_sdio->is_disabled)
1446 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power off\n");
1448 /* Disable the card */
1449 sdio_claim_host(ar_sdio->func);
1450 ret = sdio_disable_func(ar_sdio->func);
1451 sdio_release_host(ar_sdio->func);
1454 ath10k_warn(ar, "unable to disable sdio function: %d\n", ret);
1456 ar_sdio->is_disabled = true;
1459 static int ath10k_sdio_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1460 struct ath10k_hif_sg_item *items, int n_items)
1462 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1463 enum ath10k_htc_ep_id eid;
1464 struct sk_buff *skb;
1467 eid = pipe_id_to_eid(pipe_id);
1469 for (i = 0; i < n_items; i++) {
1473 skb = items[i].transfer_context;
1474 padded_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio,
1476 skb_trim(skb, padded_len);
1478 /* Write TX data to the end of the mbox address space */
1479 address = ar_sdio->mbox_addr[eid] + ar_sdio->mbox_size[eid] -
1481 ret = ath10k_sdio_prep_async_req(ar, address, skb,
1487 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1492 static int ath10k_sdio_hif_enable_intrs(struct ath10k *ar)
1494 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1495 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1496 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1499 mutex_lock(&irq_data->mtx);
1501 /* Enable all but CPU interrupts */
1502 regs->int_status_en = FIELD_PREP(MBOX_INT_STATUS_ENABLE_ERROR_MASK, 1) |
1503 FIELD_PREP(MBOX_INT_STATUS_ENABLE_CPU_MASK, 1) |
1504 FIELD_PREP(MBOX_INT_STATUS_ENABLE_COUNTER_MASK, 1);
1506 /* NOTE: There are some cases where HIF can do detection of
1507 * pending mbox messages which is disabled now.
1509 regs->int_status_en |=
1510 FIELD_PREP(MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK, 1);
1512 /* Set up the CPU Interrupt status Register */
1513 regs->cpu_int_status_en = 0;
1515 /* Set up the Error Interrupt status Register */
1516 regs->err_int_status_en =
1517 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 1) |
1518 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 1);
1520 /* Enable Counter interrupt status register to get fatal errors for
1523 regs->cntr_int_status_en =
1524 FIELD_PREP(MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
1525 ATH10K_SDIO_TARGET_DEBUG_INTR_MASK);
1527 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1528 ®s->int_status_en, sizeof(*regs));
1531 "failed to update mbox interrupt status register : %d\n",
1534 mutex_unlock(&irq_data->mtx);
1538 static int ath10k_sdio_hif_set_mbox_sleep(struct ath10k *ar, bool enable_sleep)
1543 ret = ath10k_sdio_read32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, &val);
1545 ath10k_warn(ar, "failed to read fifo/chip control register: %d\n",
1551 val &= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF;
1553 val |= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON;
1555 ret = ath10k_sdio_write32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, val);
1557 ath10k_warn(ar, "failed to write to FIFO_TIMEOUT_AND_CHIP_CONTROL: %d",
1565 /* HIF diagnostics */
1567 static int ath10k_sdio_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1573 mem = kzalloc(buf_len, GFP_KERNEL);
1577 /* set window register to start read cycle */
1578 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_READ_ADDR_ADDRESS, address);
1580 ath10k_warn(ar, "failed to set mbox window read address: %d", ret);
1585 ret = ath10k_sdio_read(ar, MBOX_WINDOW_DATA_ADDRESS, mem, buf_len);
1587 ath10k_warn(ar, "failed to read from mbox window data address: %d\n",
1592 memcpy(buf, mem, buf_len);
1600 static int ath10k_sdio_hif_diag_read32(struct ath10k *ar, u32 address,
1606 val = kzalloc(sizeof(*val), GFP_KERNEL);
1610 ret = ath10k_sdio_hif_diag_read(ar, address, val, sizeof(*val));
1614 *value = __le32_to_cpu(*val);
1622 static int ath10k_sdio_hif_diag_write_mem(struct ath10k *ar, u32 address,
1623 const void *data, int nbytes)
1627 /* set write data */
1628 ret = ath10k_sdio_write(ar, MBOX_WINDOW_DATA_ADDRESS, data, nbytes);
1631 "failed to write 0x%p to mbox window data address: %d\n",
1636 /* set window register, which starts the write cycle */
1637 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_WRITE_ADDR_ADDRESS, address);
1639 ath10k_warn(ar, "failed to set mbox window write address: %d", ret);
1646 /* HIF start/stop */
1648 static int ath10k_sdio_hif_start(struct ath10k *ar)
1650 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1654 /* Sleep 20 ms before HIF interrupts are disabled.
1655 * This will give target plenty of time to process the BMI done
1656 * request before interrupts are disabled.
1659 ret = ath10k_sdio_hif_disable_intrs(ar);
1663 /* eid 0 always uses the lower part of the extended mailbox address
1664 * space (ext_info[0].htc_ext_addr).
1666 ar_sdio->mbox_addr[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1667 ar_sdio->mbox_size[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1669 sdio_claim_host(ar_sdio->func);
1671 /* Register the isr */
1672 ret = sdio_claim_irq(ar_sdio->func, ath10k_sdio_irq_handler);
1674 ath10k_warn(ar, "failed to claim sdio interrupt: %d\n", ret);
1675 sdio_release_host(ar_sdio->func);
1679 sdio_release_host(ar_sdio->func);
1681 ret = ath10k_sdio_hif_enable_intrs(ar);
1683 ath10k_warn(ar, "failed to enable sdio interrupts: %d\n", ret);
1685 addr = host_interest_item_address(HI_ITEM(hi_acs_flags));
1687 ret = ath10k_sdio_hif_diag_read32(ar, addr, &val);
1689 ath10k_warn(ar, "unable to read hi_acs_flags address: %d\n", ret);
1693 if (val & HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK) {
1694 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1695 "sdio mailbox swap service enabled\n");
1696 ar_sdio->swap_mbox = true;
1699 /* Enable sleep and then disable it again */
1700 ret = ath10k_sdio_hif_set_mbox_sleep(ar, true);
1704 /* Wait for 20ms for the written value to take effect */
1707 ret = ath10k_sdio_hif_set_mbox_sleep(ar, false);
1714 #define SDIO_IRQ_DISABLE_TIMEOUT_HZ (3 * HZ)
1716 static void ath10k_sdio_irq_disable(struct ath10k *ar)
1718 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1719 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1720 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1721 struct sk_buff *skb;
1722 struct completion irqs_disabled_comp;
1725 skb = dev_alloc_skb(sizeof(*regs));
1729 mutex_lock(&irq_data->mtx);
1731 memset(regs, 0, sizeof(*regs)); /* disable all interrupts */
1732 memcpy(skb->data, regs, sizeof(*regs));
1733 skb_put(skb, sizeof(*regs));
1735 mutex_unlock(&irq_data->mtx);
1737 init_completion(&irqs_disabled_comp);
1738 ret = ath10k_sdio_prep_async_req(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1739 skb, &irqs_disabled_comp, false, 0);
1743 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1745 /* Wait for the completion of the IRQ disable request.
1746 * If there is a timeout we will try to disable irq's anyway.
1748 ret = wait_for_completion_timeout(&irqs_disabled_comp,
1749 SDIO_IRQ_DISABLE_TIMEOUT_HZ);
1751 ath10k_warn(ar, "sdio irq disable request timed out\n");
1753 sdio_claim_host(ar_sdio->func);
1755 ret = sdio_release_irq(ar_sdio->func);
1757 ath10k_warn(ar, "failed to release sdio interrupt: %d\n", ret);
1759 sdio_release_host(ar_sdio->func);
1765 static void ath10k_sdio_hif_stop(struct ath10k *ar)
1767 struct ath10k_sdio_bus_request *req, *tmp_req;
1768 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1770 ath10k_sdio_irq_disable(ar);
1772 cancel_work_sync(&ar_sdio->wr_async_work);
1774 spin_lock_bh(&ar_sdio->wr_async_lock);
1776 /* Free all bus requests that have not been handled */
1777 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1778 struct ath10k_htc_ep *ep;
1780 list_del(&req->list);
1783 ep = &ar->htc.endpoint[req->eid];
1784 ath10k_htc_notify_tx_completion(ep, req->skb);
1785 } else if (req->skb) {
1786 kfree_skb(req->skb);
1788 ath10k_sdio_free_bus_req(ar, req);
1791 spin_unlock_bh(&ar_sdio->wr_async_lock);
1796 static int ath10k_sdio_hif_suspend(struct ath10k *ar)
1801 static int ath10k_sdio_hif_resume(struct ath10k *ar)
1803 switch (ar->state) {
1804 case ATH10K_STATE_OFF:
1805 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1806 "sdio resume configuring sdio\n");
1808 /* need to set sdio settings after power is cut from sdio */
1809 ath10k_sdio_config(ar);
1812 case ATH10K_STATE_ON:
1821 static int ath10k_sdio_hif_map_service_to_pipe(struct ath10k *ar,
1823 u8 *ul_pipe, u8 *dl_pipe)
1825 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1826 struct ath10k_htc *htc = &ar->htc;
1827 u32 htt_addr, wmi_addr, htt_mbox_size, wmi_mbox_size;
1828 enum ath10k_htc_ep_id eid;
1829 bool ep_found = false;
1832 /* For sdio, we are interested in the mapping between eid
1833 * and pipeid rather than service_id to pipe_id.
1834 * First we find out which eid has been allocated to the
1837 for (i = 0; i < ATH10K_HTC_EP_COUNT; i++) {
1838 if (htc->endpoint[i].service_id == service_id) {
1839 eid = htc->endpoint[i].eid;
1848 /* Then we create the simplest mapping possible between pipeid
1851 *ul_pipe = *dl_pipe = (u8)eid;
1853 /* Normally, HTT will use the upper part of the extended
1854 * mailbox address space (ext_info[1].htc_ext_addr) and WMI ctrl
1855 * the lower part (ext_info[0].htc_ext_addr).
1856 * If fw wants swapping of mailbox addresses, the opposite is true.
1858 if (ar_sdio->swap_mbox) {
1859 htt_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1860 wmi_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1861 htt_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1862 wmi_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1864 htt_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1865 wmi_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1866 htt_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1867 wmi_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1870 switch (service_id) {
1871 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1872 /* HTC ctrl ep mbox address has already been setup in
1873 * ath10k_sdio_hif_start
1876 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1877 ar_sdio->mbox_addr[eid] = wmi_addr;
1878 ar_sdio->mbox_size[eid] = wmi_mbox_size;
1879 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1880 "sdio wmi ctrl mbox_addr 0x%x mbox_size %d\n",
1881 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1883 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1884 ar_sdio->mbox_addr[eid] = htt_addr;
1885 ar_sdio->mbox_size[eid] = htt_mbox_size;
1886 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1887 "sdio htt data mbox_addr 0x%x mbox_size %d\n",
1888 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1891 ath10k_warn(ar, "unsupported HTC service id: %d\n",
1899 static void ath10k_sdio_hif_get_default_pipe(struct ath10k *ar,
1900 u8 *ul_pipe, u8 *dl_pipe)
1902 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio hif get default pipe\n");
1904 /* HTC ctrl ep (SVC id 1) always has eid (and pipe_id in our
1911 /* This op is currently only used by htc_wait_target if the HTC ready
1912 * message times out. It is not applicable for SDIO since there is nothing
1913 * we can do if the HTC ready message does not arrive in time.
1914 * TODO: Make this op non mandatory by introducing a NULL check in the
1917 static void ath10k_sdio_hif_send_complete_check(struct ath10k *ar,
1922 static const struct ath10k_hif_ops ath10k_sdio_hif_ops = {
1923 .tx_sg = ath10k_sdio_hif_tx_sg,
1924 .diag_read = ath10k_sdio_hif_diag_read,
1925 .diag_write = ath10k_sdio_hif_diag_write_mem,
1926 .exchange_bmi_msg = ath10k_sdio_bmi_exchange_msg,
1927 .start = ath10k_sdio_hif_start,
1928 .stop = ath10k_sdio_hif_stop,
1929 .map_service_to_pipe = ath10k_sdio_hif_map_service_to_pipe,
1930 .get_default_pipe = ath10k_sdio_hif_get_default_pipe,
1931 .send_complete_check = ath10k_sdio_hif_send_complete_check,
1932 .power_up = ath10k_sdio_hif_power_up,
1933 .power_down = ath10k_sdio_hif_power_down,
1935 .suspend = ath10k_sdio_hif_suspend,
1936 .resume = ath10k_sdio_hif_resume,
1940 #ifdef CONFIG_PM_SLEEP
1942 /* Empty handlers so that mmc subsystem doesn't remove us entirely during
1943 * suspend. We instead follow cfg80211 suspend/resume handlers.
1945 static int ath10k_sdio_pm_suspend(struct device *device)
1950 static int ath10k_sdio_pm_resume(struct device *device)
1955 static SIMPLE_DEV_PM_OPS(ath10k_sdio_pm_ops, ath10k_sdio_pm_suspend,
1956 ath10k_sdio_pm_resume);
1958 #define ATH10K_SDIO_PM_OPS (&ath10k_sdio_pm_ops)
1962 #define ATH10K_SDIO_PM_OPS NULL
1964 #endif /* CONFIG_PM_SLEEP */
1966 static int ath10k_sdio_probe(struct sdio_func *func,
1967 const struct sdio_device_id *id)
1969 struct ath10k_sdio *ar_sdio;
1971 enum ath10k_hw_rev hw_rev;
1972 u32 chip_id, dev_id_base;
1975 /* Assumption: All SDIO based chipsets (so far) are QCA6174 based.
1976 * If there will be newer chipsets that does not use the hw reg
1977 * setup as defined in qca6174_regs and qca6174_values, this
1978 * assumption is no longer valid and hw_rev must be setup differently
1979 * depending on chipset.
1981 hw_rev = ATH10K_HW_QCA6174;
1983 ar = ath10k_core_create(sizeof(*ar_sdio), &func->dev, ATH10K_BUS_SDIO,
1984 hw_rev, &ath10k_sdio_hif_ops);
1986 dev_err(&func->dev, "failed to allocate core\n");
1990 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1991 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1992 func->num, func->vendor, func->device,
1993 func->max_blksize, func->cur_blksize);
1995 ar_sdio = ath10k_sdio_priv(ar);
1997 ar_sdio->irq_data.irq_proc_reg =
1998 kzalloc(sizeof(struct ath10k_sdio_irq_proc_regs),
2000 if (!ar_sdio->irq_data.irq_proc_reg) {
2002 goto err_core_destroy;
2005 ar_sdio->irq_data.irq_en_reg =
2006 kzalloc(sizeof(struct ath10k_sdio_irq_enable_regs),
2008 if (!ar_sdio->irq_data.irq_en_reg) {
2010 goto err_free_proc_reg;
2013 ar_sdio->bmi_buf = kzalloc(BMI_MAX_CMDBUF_SIZE, GFP_KERNEL);
2014 if (!ar_sdio->bmi_buf) {
2016 goto err_free_en_reg;
2019 ar_sdio->func = func;
2020 sdio_set_drvdata(func, ar_sdio);
2022 ar_sdio->is_disabled = true;
2025 spin_lock_init(&ar_sdio->lock);
2026 spin_lock_init(&ar_sdio->wr_async_lock);
2027 mutex_init(&ar_sdio->irq_data.mtx);
2029 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
2030 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
2032 INIT_WORK(&ar_sdio->wr_async_work, ath10k_sdio_write_async_work);
2033 ar_sdio->workqueue = create_singlethread_workqueue("ath10k_sdio_wq");
2034 if (!ar_sdio->workqueue) {
2036 goto err_free_bmi_buf;
2039 for (i = 0; i < ATH10K_SDIO_BUS_REQUEST_MAX_NUM; i++)
2040 ath10k_sdio_free_bus_req(ar, &ar_sdio->bus_req[i]);
2042 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, id->device);
2043 switch (dev_id_base) {
2044 case QCA_MANUFACTURER_ID_AR6005_BASE:
2045 case QCA_MANUFACTURER_ID_QCA9377_BASE:
2046 ar->dev_id = QCA9377_1_0_DEVICE_ID;
2050 ath10k_err(ar, "unsupported device id %u (0x%x)\n",
2051 dev_id_base, id->device);
2052 goto err_free_bmi_buf;
2055 ar->id.vendor = id->vendor;
2056 ar->id.device = id->device;
2058 ath10k_sdio_set_mbox_info(ar);
2060 ret = ath10k_sdio_config(ar);
2062 ath10k_err(ar, "failed to config sdio: %d\n", ret);
2066 /* TODO: don't know yet how to get chip_id with SDIO */
2068 ret = ath10k_core_register(ar, chip_id);
2070 ath10k_err(ar, "failed to register driver core: %d\n", ret);
2074 /* TODO: remove this once SDIO support is fully implemented */
2075 ath10k_warn(ar, "WARNING: ath10k SDIO support is incomplete, don't expect anything to work!\n");
2080 destroy_workqueue(ar_sdio->workqueue);
2082 kfree(ar_sdio->bmi_buf);
2084 kfree(ar_sdio->irq_data.irq_en_reg);
2086 kfree(ar_sdio->irq_data.irq_proc_reg);
2088 ath10k_core_destroy(ar);
2093 static void ath10k_sdio_remove(struct sdio_func *func)
2095 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
2096 struct ath10k *ar = ar_sdio->ar;
2098 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2099 "sdio removed func %d vendor 0x%x device 0x%x\n",
2100 func->num, func->vendor, func->device);
2102 (void)ath10k_sdio_hif_disable_intrs(ar);
2103 cancel_work_sync(&ar_sdio->wr_async_work);
2104 ath10k_core_unregister(ar);
2105 ath10k_core_destroy(ar);
2107 flush_workqueue(ar_sdio->workqueue);
2108 destroy_workqueue(ar_sdio->workqueue);
2111 static const struct sdio_device_id ath10k_sdio_devices[] = {
2112 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2113 (QCA_SDIO_ID_AR6005_BASE | 0xA))},
2114 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2115 (QCA_SDIO_ID_QCA9377_BASE | 0x1))},
2119 MODULE_DEVICE_TABLE(sdio, ath10k_sdio_devices);
2121 static struct sdio_driver ath10k_sdio_driver = {
2122 .name = "ath10k_sdio",
2123 .id_table = ath10k_sdio_devices,
2124 .probe = ath10k_sdio_probe,
2125 .remove = ath10k_sdio_remove,
2126 .drv.pm = ATH10K_SDIO_PM_OPS,
2129 static int __init ath10k_sdio_init(void)
2133 ret = sdio_register_driver(&ath10k_sdio_driver);
2135 pr_err("sdio driver registration failed: %d\n", ret);
2140 static void __exit ath10k_sdio_exit(void)
2142 sdio_unregister_driver(&ath10k_sdio_driver);
2145 module_init(ath10k_sdio_init);
2146 module_exit(ath10k_sdio_exit);
2148 MODULE_AUTHOR("Qualcomm Atheros");
2149 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN SDIO devices");
2150 MODULE_LICENSE("Dual BSD/GPL");