2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012,2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include <linux/module.h>
20 #include <linux/mmc/card.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/sdio_func.h>
24 #include <linux/mmc/sdio_ids.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sd.h>
27 #include <linux/bitfield.h>
34 #include "targaddrs.h"
38 /* inlined helper functions */
40 static inline int ath10k_sdio_calc_txrx_padded_len(struct ath10k_sdio *ar_sdio,
43 return __ALIGN_MASK((len), ar_sdio->mbox_info.block_mask);
46 static inline enum ath10k_htc_ep_id pipe_id_to_eid(u8 pipe_id)
48 return (enum ath10k_htc_ep_id)pipe_id;
51 static inline void ath10k_sdio_mbox_free_rx_pkt(struct ath10k_sdio_rx_data *pkt)
53 dev_kfree_skb(pkt->skb);
57 pkt->trailer_only = false;
60 static inline int ath10k_sdio_mbox_alloc_rx_pkt(struct ath10k_sdio_rx_data *pkt,
61 size_t act_len, size_t full_len,
65 pkt->skb = dev_alloc_skb(full_len);
69 pkt->act_len = act_len;
70 pkt->alloc_len = full_len;
71 pkt->part_of_bundle = part_of_bundle;
72 pkt->last_in_bundle = last_in_bundle;
73 pkt->trailer_only = false;
78 static inline bool is_trailer_only_msg(struct ath10k_sdio_rx_data *pkt)
80 bool trailer_only = false;
81 struct ath10k_htc_hdr *htc_hdr =
82 (struct ath10k_htc_hdr *)pkt->skb->data;
83 u16 len = __le16_to_cpu(htc_hdr->len);
85 if (len == htc_hdr->trailer_len)
91 /* sdio/mmc functions */
93 static inline void ath10k_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
97 *arg = FIELD_PREP(BIT(31), write) |
98 FIELD_PREP(BIT(27), raw) |
99 FIELD_PREP(BIT(26), 1) |
100 FIELD_PREP(GENMASK(25, 9), address) |
101 FIELD_PREP(BIT(8), 1) |
102 FIELD_PREP(GENMASK(7, 0), val);
105 static int ath10k_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
106 unsigned int address,
109 struct mmc_command io_cmd;
111 memset(&io_cmd, 0, sizeof(io_cmd));
112 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
113 io_cmd.opcode = SD_IO_RW_DIRECT;
114 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
116 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
119 static int ath10k_sdio_func0_cmd52_rd_byte(struct mmc_card *card,
120 unsigned int address,
123 struct mmc_command io_cmd;
126 memset(&io_cmd, 0, sizeof(io_cmd));
127 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 0, 0, address, 0);
128 io_cmd.opcode = SD_IO_RW_DIRECT;
129 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
131 ret = mmc_wait_for_cmd(card->host, &io_cmd, 0);
133 *byte = io_cmd.resp[0];
138 static int ath10k_sdio_config(struct ath10k *ar)
140 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
141 struct sdio_func *func = ar_sdio->func;
142 unsigned char byte, asyncintdelay = 2;
145 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio configuration\n");
147 sdio_claim_host(func);
150 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
151 SDIO_CCCR_DRIVE_STRENGTH,
154 byte &= ~ATH10K_SDIO_DRIVE_DTSX_MASK;
155 byte |= FIELD_PREP(ATH10K_SDIO_DRIVE_DTSX_MASK,
156 ATH10K_SDIO_DRIVE_DTSX_TYPE_D);
158 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
159 SDIO_CCCR_DRIVE_STRENGTH,
163 ret = ath10k_sdio_func0_cmd52_rd_byte(
165 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
168 byte |= (CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A |
169 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C |
170 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D);
172 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
173 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
176 ath10k_warn(ar, "failed to enable driver strength: %d\n", ret);
181 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
182 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
185 byte |= SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3;
187 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
188 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
191 ath10k_warn(ar, "failed to enable 4-bit async irq mode: %d\n",
197 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
198 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
201 byte &= ~CCCR_SDIO_ASYNC_INT_DELAY_MASK;
202 byte |= FIELD_PREP(CCCR_SDIO_ASYNC_INT_DELAY_MASK, asyncintdelay);
204 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
205 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
208 /* give us some time to enable, in ms */
209 func->enable_timeout = 100;
211 ret = sdio_set_block_size(func, ar_sdio->mbox_info.block_size);
213 ath10k_warn(ar, "failed to set sdio block size to %d: %d\n",
214 ar_sdio->mbox_info.block_size, ret);
219 sdio_release_host(func);
223 static int ath10k_sdio_write32(struct ath10k *ar, u32 addr, u32 val)
225 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
226 struct sdio_func *func = ar_sdio->func;
229 sdio_claim_host(func);
231 sdio_writel(func, val, addr, &ret);
233 ath10k_warn(ar, "failed to write 0x%x to address 0x%x: %d\n",
238 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write32 addr 0x%x val 0x%x\n",
242 sdio_release_host(func);
247 static int ath10k_sdio_writesb32(struct ath10k *ar, u32 addr, u32 val)
249 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
250 struct sdio_func *func = ar_sdio->func;
254 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
258 *buf = cpu_to_le32(val);
260 sdio_claim_host(func);
262 ret = sdio_writesb(func, addr, buf, sizeof(*buf));
264 ath10k_warn(ar, "failed to write value 0x%x to fixed sb address 0x%x: %d\n",
269 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio writesb32 addr 0x%x val 0x%x\n",
273 sdio_release_host(func);
280 static int ath10k_sdio_read32(struct ath10k *ar, u32 addr, u32 *val)
282 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
283 struct sdio_func *func = ar_sdio->func;
286 sdio_claim_host(func);
287 *val = sdio_readl(func, addr, &ret);
289 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
294 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read32 addr 0x%x val 0x%x\n",
298 sdio_release_host(func);
303 static int ath10k_sdio_read(struct ath10k *ar, u32 addr, void *buf, size_t len)
305 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
306 struct sdio_func *func = ar_sdio->func;
309 sdio_claim_host(func);
311 ret = sdio_memcpy_fromio(func, buf, addr, len);
313 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
318 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read addr 0x%x buf 0x%p len %zu\n",
320 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio read ", buf, len);
323 sdio_release_host(func);
328 static int ath10k_sdio_write(struct ath10k *ar, u32 addr, const void *buf, size_t len)
330 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
331 struct sdio_func *func = ar_sdio->func;
334 sdio_claim_host(func);
336 /* For some reason toio() doesn't have const for the buffer, need
337 * an ugly hack to workaround that.
339 ret = sdio_memcpy_toio(func, addr, (void *)buf, len);
341 ath10k_warn(ar, "failed to write to address 0x%x: %d\n",
346 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write addr 0x%x buf 0x%p len %zu\n",
348 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio write ", buf, len);
351 sdio_release_host(func);
356 static int ath10k_sdio_readsb(struct ath10k *ar, u32 addr, void *buf, size_t len)
358 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
359 struct sdio_func *func = ar_sdio->func;
362 sdio_claim_host(func);
364 len = round_down(len, ar_sdio->mbox_info.block_size);
366 ret = sdio_readsb(func, buf, addr, len);
368 ath10k_warn(ar, "failed to read from fixed (sb) address 0x%x: %d\n",
373 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio readsb addr 0x%x buf 0x%p len %zu\n",
375 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio readsb ", buf, len);
378 sdio_release_host(func);
383 /* HIF mbox functions */
385 static int ath10k_sdio_mbox_rx_process_packet(struct ath10k *ar,
386 struct ath10k_sdio_rx_data *pkt,
390 struct ath10k_htc *htc = &ar->htc;
391 struct sk_buff *skb = pkt->skb;
392 struct ath10k_htc_hdr *htc_hdr = (struct ath10k_htc_hdr *)skb->data;
393 bool trailer_present = htc_hdr->flags & ATH10K_HTC_FLAG_TRAILER_PRESENT;
394 enum ath10k_htc_ep_id eid;
398 if (trailer_present) {
399 trailer = skb->data + skb->len - htc_hdr->trailer_len;
401 eid = pipe_id_to_eid(htc_hdr->eid);
403 ret = ath10k_htc_process_trailer(htc,
405 htc_hdr->trailer_len,
412 if (is_trailer_only_msg(pkt))
413 pkt->trailer_only = true;
415 skb_trim(skb, skb->len - htc_hdr->trailer_len);
418 skb_pull(skb, sizeof(*htc_hdr));
423 static int ath10k_sdio_mbox_rx_process_packets(struct ath10k *ar,
427 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
428 struct ath10k_htc *htc = &ar->htc;
429 struct ath10k_sdio_rx_data *pkt;
430 struct ath10k_htc_ep *ep;
431 enum ath10k_htc_ep_id id;
432 int ret, i, *n_lookahead_local;
433 u32 *lookaheads_local;
434 int lookahead_idx = 0;
436 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
437 lookaheads_local = lookaheads;
438 n_lookahead_local = n_lookahead;
440 id = ((struct ath10k_htc_hdr *)
441 &lookaheads[lookahead_idx++])->eid;
443 if (id >= ATH10K_HTC_EP_COUNT) {
444 ath10k_warn(ar, "invalid endpoint in look-ahead: %d\n",
450 ep = &htc->endpoint[id];
452 if (ep->service_id == 0) {
453 ath10k_warn(ar, "ep %d is not connected\n", id);
458 pkt = &ar_sdio->rx_pkts[i];
460 if (pkt->part_of_bundle && !pkt->last_in_bundle) {
461 /* Only read lookahead's from RX trailers
462 * for the last packet in a bundle.
465 lookaheads_local = NULL;
466 n_lookahead_local = NULL;
469 ret = ath10k_sdio_mbox_rx_process_packet(ar,
476 if (!pkt->trailer_only)
477 ep->ep_ops.ep_rx_complete(ar_sdio->ar, pkt->skb);
481 /* The RX complete handler now owns the skb...*/
489 /* Free all packets that was not passed on to the RX completion
492 for (; i < ar_sdio->n_rx_pkts; i++)
493 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
498 static int ath10k_sdio_mbox_alloc_pkt_bundle(struct ath10k *ar,
499 struct ath10k_sdio_rx_data *rx_pkts,
500 struct ath10k_htc_hdr *htc_hdr,
501 size_t full_len, size_t act_len,
506 *bndl_cnt = FIELD_GET(ATH10K_HTC_FLAG_BUNDLE_MASK, htc_hdr->flags);
508 if (*bndl_cnt > HTC_HOST_MAX_MSG_PER_RX_BUNDLE) {
510 "HTC bundle length %u exceeds maximum %u\n",
511 le16_to_cpu(htc_hdr->len),
512 HTC_HOST_MAX_MSG_PER_RX_BUNDLE);
516 /* Allocate bndl_cnt extra skb's for the bundle.
517 * The package containing the
518 * ATH10K_HTC_FLAG_BUNDLE_MASK flag is not included
519 * in bndl_cnt. The skb for that packet will be
520 * allocated separately.
522 for (i = 0; i < *bndl_cnt; i++) {
523 ret = ath10k_sdio_mbox_alloc_rx_pkt(&rx_pkts[i],
535 static int ath10k_sdio_mbox_rx_alloc(struct ath10k *ar,
536 u32 lookaheads[], int n_lookaheads)
538 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
539 struct ath10k_htc_hdr *htc_hdr;
540 size_t full_len, act_len;
544 if (n_lookaheads > ATH10K_SDIO_MAX_RX_MSGS) {
546 "the total number of pkgs to be fetched (%u) exceeds maximum %u\n",
548 ATH10K_SDIO_MAX_RX_MSGS);
553 for (i = 0; i < n_lookaheads; i++) {
554 htc_hdr = (struct ath10k_htc_hdr *)&lookaheads[i];
555 last_in_bundle = false;
557 if (le16_to_cpu(htc_hdr->len) >
558 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH) {
560 "payload length %d exceeds max htc length: %zu\n",
561 le16_to_cpu(htc_hdr->len),
562 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH);
565 queue_work(ar->workqueue, &ar->restart_work);
566 ath10k_warn(ar, "exceeds length, start recovery\n");
571 act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr);
572 full_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio, act_len);
574 if (full_len > ATH10K_SDIO_MAX_BUFFER_SIZE) {
576 "rx buffer requested with invalid htc_hdr length (%d, 0x%x): %d\n",
577 htc_hdr->eid, htc_hdr->flags,
578 le16_to_cpu(htc_hdr->len));
583 if (htc_hdr->flags & ATH10K_HTC_FLAG_BUNDLE_MASK) {
584 /* HTC header indicates that every packet to follow
585 * has the same padded length so that it can be
586 * optimally fetched as a full bundle.
590 ret = ath10k_sdio_mbox_alloc_pkt_bundle(ar,
591 &ar_sdio->rx_pkts[i],
597 n_lookaheads += bndl_cnt;
599 /*Next buffer will be the last in the bundle */
600 last_in_bundle = true;
603 /* Allocate skb for packet. If the packet had the
604 * ATH10K_HTC_FLAG_BUNDLE_MASK flag set, all bundled
605 * packet skb's have been allocated in the previous step.
607 if (htc_hdr->flags & ATH10K_HTC_FLAGS_RECV_1MORE_BLOCK)
608 full_len += ATH10K_HIF_MBOX_BLOCK_SIZE;
610 ret = ath10k_sdio_mbox_alloc_rx_pkt(&ar_sdio->rx_pkts[i],
616 ath10k_warn(ar, "alloc_rx_pkt error %d\n", ret);
621 ar_sdio->n_rx_pkts = i;
626 for (i = 0; i < ATH10K_SDIO_MAX_RX_MSGS; i++) {
627 if (!ar_sdio->rx_pkts[i].alloc_len)
629 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
635 static int ath10k_sdio_mbox_rx_packet(struct ath10k *ar,
636 struct ath10k_sdio_rx_data *pkt)
638 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
639 struct sk_buff *skb = pkt->skb;
640 struct ath10k_htc_hdr *htc_hdr;
643 ret = ath10k_sdio_readsb(ar, ar_sdio->mbox_info.htc_addr,
644 skb->data, pkt->alloc_len);
648 /* Update actual length. The original length may be incorrect,
649 * as the FW will bundle multiple packets as long as their sizes
650 * fit within the same aligned length (pkt->alloc_len).
652 htc_hdr = (struct ath10k_htc_hdr *)skb->data;
653 pkt->act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr);
654 if (pkt->act_len > pkt->alloc_len) {
655 ath10k_warn(ar, "rx packet too large (%zu > %zu)\n",
656 pkt->act_len, pkt->alloc_len);
661 skb_put(skb, pkt->act_len);
669 static int ath10k_sdio_mbox_rx_fetch(struct ath10k *ar)
671 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
674 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
675 ret = ath10k_sdio_mbox_rx_packet(ar,
676 &ar_sdio->rx_pkts[i]);
684 /* Free all packets that was not successfully fetched. */
685 for (; i < ar_sdio->n_rx_pkts; i++)
686 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
691 /* This is the timeout for mailbox processing done in the sdio irq
692 * handler. The timeout is deliberately set quite high since SDIO dump logs
693 * over serial port can/will add a substantial overhead to the processing
696 #define SDIO_MBOX_PROCESSING_TIMEOUT_HZ (20 * HZ)
698 static int ath10k_sdio_mbox_rxmsg_pending_handler(struct ath10k *ar,
699 u32 msg_lookahead, bool *done)
701 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
702 u32 lookaheads[ATH10K_SDIO_MAX_RX_MSGS];
703 int n_lookaheads = 1;
704 unsigned long timeout;
709 /* Copy the lookahead obtained from the HTC register table into our
710 * temp array as a start value.
712 lookaheads[0] = msg_lookahead;
714 timeout = jiffies + SDIO_MBOX_PROCESSING_TIMEOUT_HZ;
716 /* Try to allocate as many HTC RX packets indicated by
719 ret = ath10k_sdio_mbox_rx_alloc(ar, lookaheads,
724 if (ar_sdio->n_rx_pkts >= 2)
725 /* A recv bundle was detected, force IRQ status
730 ret = ath10k_sdio_mbox_rx_fetch(ar);
732 /* Process fetched packets. This will potentially update
733 * n_lookaheads depending on if the packets contain lookahead
737 ret = ath10k_sdio_mbox_rx_process_packets(ar,
741 if (!n_lookaheads || ret)
744 /* For SYNCH processing, if we get here, we are running
745 * through the loop again due to updated lookaheads. Set
746 * flag that we should re-check IRQ status registers again
747 * before leaving IRQ processing, this can net better
748 * performance in high throughput situations.
751 } while (time_before(jiffies, timeout));
753 if (ret && (ret != -ECANCELED))
754 ath10k_warn(ar, "failed to get pending recv messages: %d\n",
760 static int ath10k_sdio_mbox_proc_dbg_intr(struct ath10k *ar)
765 /* TODO: Add firmware crash handling */
766 ath10k_warn(ar, "firmware crashed\n");
768 /* read counter to clear the interrupt, the debug error interrupt is
771 ret = ath10k_sdio_read32(ar, MBOX_COUNT_DEC_ADDRESS, &val);
773 ath10k_warn(ar, "failed to clear debug interrupt: %d\n", ret);
778 static int ath10k_sdio_mbox_proc_counter_intr(struct ath10k *ar)
780 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
781 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
782 u8 counter_int_status;
785 mutex_lock(&irq_data->mtx);
786 counter_int_status = irq_data->irq_proc_reg->counter_int_status &
787 irq_data->irq_en_reg->cntr_int_status_en;
789 /* NOTE: other modules like GMBOX may use the counter interrupt for
790 * credit flow control on other counters, we only need to check for
791 * the debug assertion counter interrupt.
793 if (counter_int_status & ATH10K_SDIO_TARGET_DEBUG_INTR_MASK)
794 ret = ath10k_sdio_mbox_proc_dbg_intr(ar);
798 mutex_unlock(&irq_data->mtx);
803 static int ath10k_sdio_mbox_proc_err_intr(struct ath10k *ar)
805 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
806 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
810 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio error interrupt\n");
812 error_int_status = irq_data->irq_proc_reg->error_int_status & 0x0F;
813 if (!error_int_status) {
814 ath10k_warn(ar, "invalid error interrupt status: 0x%x\n",
819 ath10k_dbg(ar, ATH10K_DBG_SDIO,
820 "sdio error_int_status 0x%x\n", error_int_status);
822 if (FIELD_GET(MBOX_ERROR_INT_STATUS_WAKEUP_MASK,
824 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio interrupt error wakeup\n");
826 if (FIELD_GET(MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
828 ath10k_warn(ar, "rx underflow interrupt error\n");
830 if (FIELD_GET(MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
832 ath10k_warn(ar, "tx overflow interrupt error\n");
834 /* Clear the interrupt */
835 irq_data->irq_proc_reg->error_int_status &= ~error_int_status;
837 /* set W1C value to clear the interrupt, this hits the register first */
838 ret = ath10k_sdio_writesb32(ar, MBOX_ERROR_INT_STATUS_ADDRESS,
841 ath10k_warn(ar, "unable to write to error int status address: %d\n",
849 static int ath10k_sdio_mbox_proc_cpu_intr(struct ath10k *ar)
851 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
852 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
856 mutex_lock(&irq_data->mtx);
857 cpu_int_status = irq_data->irq_proc_reg->cpu_int_status &
858 irq_data->irq_en_reg->cpu_int_status_en;
859 if (!cpu_int_status) {
860 ath10k_warn(ar, "CPU interrupt status is zero\n");
865 /* Clear the interrupt */
866 irq_data->irq_proc_reg->cpu_int_status &= ~cpu_int_status;
868 /* Set up the register transfer buffer to hit the register 4 times,
869 * this is done to make the access 4-byte aligned to mitigate issues
870 * with host bus interconnects that restrict bus transfer lengths to
871 * be a multiple of 4-bytes.
873 * Set W1C value to clear the interrupt, this hits the register first.
875 ret = ath10k_sdio_writesb32(ar, MBOX_CPU_INT_STATUS_ADDRESS,
878 ath10k_warn(ar, "unable to write to cpu interrupt status address: %d\n",
884 mutex_unlock(&irq_data->mtx);
888 static int ath10k_sdio_mbox_read_int_status(struct ath10k *ar,
892 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
893 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
894 struct ath10k_sdio_irq_proc_regs *irq_proc_reg = irq_data->irq_proc_reg;
895 struct ath10k_sdio_irq_enable_regs *irq_en_reg = irq_data->irq_en_reg;
896 u8 htc_mbox = FIELD_PREP(ATH10K_HTC_MAILBOX_MASK, 1);
899 mutex_lock(&irq_data->mtx);
902 *host_int_status = 0;
904 /* int_status_en is supposed to be non zero, otherwise interrupts
905 * shouldn't be enabled. There is however a short time frame during
906 * initialization between the irq register and int_status_en init
907 * where this can happen.
908 * We silently ignore this condition.
910 if (!irq_en_reg->int_status_en) {
915 /* Read the first sizeof(struct ath10k_irq_proc_registers)
916 * bytes of the HTC register table. This
917 * will yield us the value of different int status
918 * registers and the lookahead registers.
920 ret = ath10k_sdio_read(ar, MBOX_HOST_INT_STATUS_ADDRESS,
921 irq_proc_reg, sizeof(*irq_proc_reg));
925 /* Update only those registers that are enabled */
926 *host_int_status = irq_proc_reg->host_int_status &
927 irq_en_reg->int_status_en;
929 /* Look at mbox status */
930 if (!(*host_int_status & htc_mbox)) {
936 /* Mask out pending mbox value, we use look ahead as
937 * the real flag for mbox processing.
939 *host_int_status &= ~htc_mbox;
940 if (irq_proc_reg->rx_lookahead_valid & htc_mbox) {
941 *lookahead = le32_to_cpu(
942 irq_proc_reg->rx_lookahead[ATH10K_HTC_MAILBOX]);
944 ath10k_warn(ar, "sdio mbox lookahead is zero\n");
948 mutex_unlock(&irq_data->mtx);
952 static int ath10k_sdio_mbox_proc_pending_irqs(struct ath10k *ar,
959 /* NOTE: HIF implementation guarantees that the context of this
960 * call allows us to perform SYNCHRONOUS I/O, that is we can block,
961 * sleep or call any API that can block or switch thread/task
962 * contexts. This is a fully schedulable context.
965 ret = ath10k_sdio_mbox_read_int_status(ar,
973 if (!host_int_status && !lookahead) {
980 ath10k_dbg(ar, ATH10K_DBG_SDIO,
981 "sdio pending mailbox msg lookahead 0x%08x\n",
984 ret = ath10k_sdio_mbox_rxmsg_pending_handler(ar,
991 /* now, handle the rest of the interrupts */
992 ath10k_dbg(ar, ATH10K_DBG_SDIO,
993 "sdio host_int_status 0x%x\n", host_int_status);
995 if (FIELD_GET(MBOX_HOST_INT_STATUS_CPU_MASK, host_int_status)) {
997 ret = ath10k_sdio_mbox_proc_cpu_intr(ar);
1002 if (FIELD_GET(MBOX_HOST_INT_STATUS_ERROR_MASK, host_int_status)) {
1003 /* Error Interrupt */
1004 ret = ath10k_sdio_mbox_proc_err_intr(ar);
1009 if (FIELD_GET(MBOX_HOST_INT_STATUS_COUNTER_MASK, host_int_status))
1010 /* Counter Interrupt */
1011 ret = ath10k_sdio_mbox_proc_counter_intr(ar);
1016 /* An optimization to bypass reading the IRQ status registers
1017 * unecessarily which can re-wake the target, if upper layers
1018 * determine that we are in a low-throughput mode, we can rely on
1019 * taking another interrupt rather than re-checking the status
1020 * registers which can re-wake the target.
1022 * NOTE : for host interfaces that makes use of detecting pending
1023 * mbox messages at hif can not use this optimization due to
1024 * possible side effects, SPI requires the host to drain all
1025 * messages from the mailbox before exiting the ISR routine.
1028 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1029 "sdio pending irqs done %d status %d",
1035 static void ath10k_sdio_set_mbox_info(struct ath10k *ar)
1037 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1038 struct ath10k_mbox_info *mbox_info = &ar_sdio->mbox_info;
1039 u16 device = ar_sdio->func->device, dev_id_base, dev_id_chiprev;
1041 mbox_info->htc_addr = ATH10K_HIF_MBOX_BASE_ADDR;
1042 mbox_info->block_size = ATH10K_HIF_MBOX_BLOCK_SIZE;
1043 mbox_info->block_mask = ATH10K_HIF_MBOX_BLOCK_SIZE - 1;
1044 mbox_info->gmbox_addr = ATH10K_HIF_GMBOX_BASE_ADDR;
1045 mbox_info->gmbox_sz = ATH10K_HIF_GMBOX_WIDTH;
1047 mbox_info->ext_info[0].htc_ext_addr = ATH10K_HIF_MBOX0_EXT_BASE_ADDR;
1049 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, device);
1050 dev_id_chiprev = FIELD_GET(QCA_MANUFACTURER_ID_REV_MASK, device);
1051 switch (dev_id_base) {
1052 case QCA_MANUFACTURER_ID_AR6005_BASE:
1053 if (dev_id_chiprev < 4)
1054 mbox_info->ext_info[0].htc_ext_sz =
1055 ATH10K_HIF_MBOX0_EXT_WIDTH;
1057 /* from QCA6174 2.0(0x504), the width has been extended
1060 mbox_info->ext_info[0].htc_ext_sz =
1061 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1063 case QCA_MANUFACTURER_ID_QCA9377_BASE:
1064 mbox_info->ext_info[0].htc_ext_sz =
1065 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1068 mbox_info->ext_info[0].htc_ext_sz =
1069 ATH10K_HIF_MBOX0_EXT_WIDTH;
1072 mbox_info->ext_info[1].htc_ext_addr =
1073 mbox_info->ext_info[0].htc_ext_addr +
1074 mbox_info->ext_info[0].htc_ext_sz +
1075 ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE;
1076 mbox_info->ext_info[1].htc_ext_sz = ATH10K_HIF_MBOX1_EXT_WIDTH;
1081 static int ath10k_sdio_bmi_credits(struct ath10k *ar)
1083 u32 addr, cmd_credits;
1084 unsigned long timeout;
1087 /* Read the counter register to get the command credits */
1088 addr = MBOX_COUNT_DEC_ADDRESS + ATH10K_HIF_MBOX_NUM_MAX * 4;
1089 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1092 while (time_before(jiffies, timeout) && !cmd_credits) {
1093 /* Hit the credit counter with a 4-byte access, the first byte
1094 * read will hit the counter and cause a decrement, while the
1095 * remaining 3 bytes has no effect. The rationale behind this
1096 * is to make all HIF accesses 4-byte aligned.
1098 ret = ath10k_sdio_read32(ar, addr, &cmd_credits);
1101 "unable to decrement the command credit count register: %d\n",
1106 /* The counter is only 8 bits.
1107 * Ignore anything in the upper 3 bytes
1109 cmd_credits &= 0xFF;
1113 ath10k_warn(ar, "bmi communication timeout\n");
1120 static int ath10k_sdio_bmi_get_rx_lookahead(struct ath10k *ar)
1122 unsigned long timeout;
1126 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1129 while ((time_before(jiffies, timeout)) && !rx_word) {
1130 ret = ath10k_sdio_read32(ar,
1131 MBOX_HOST_INT_STATUS_ADDRESS,
1134 ath10k_warn(ar, "unable to read RX_LOOKAHEAD_VALID: %d\n", ret);
1138 /* all we really want is one bit */
1143 ath10k_warn(ar, "bmi_recv_buf FIFO empty\n");
1150 static int ath10k_sdio_bmi_exchange_msg(struct ath10k *ar,
1151 void *req, u32 req_len,
1152 void *resp, u32 *resp_len)
1154 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1159 ret = ath10k_sdio_bmi_credits(ar);
1163 addr = ar_sdio->mbox_info.htc_addr;
1165 memcpy(ar_sdio->bmi_buf, req, req_len);
1166 ret = ath10k_sdio_write(ar, addr, ar_sdio->bmi_buf, req_len);
1169 "unable to send the bmi data to the device: %d\n",
1175 if (!resp || !resp_len)
1176 /* No response expected */
1179 /* During normal bootup, small reads may be required.
1180 * Rather than issue an HIF Read and then wait as the Target
1181 * adds successive bytes to the FIFO, we wait here until
1182 * we know that response data is available.
1184 * This allows us to cleanly timeout on an unexpected
1185 * Target failure rather than risk problems at the HIF level.
1186 * In particular, this avoids SDIO timeouts and possibly garbage
1187 * data on some host controllers. And on an interconnect
1188 * such as Compact Flash (as well as some SDIO masters) which
1189 * does not provide any indication on data timeout, it avoids
1190 * a potential hang or garbage response.
1192 * Synchronization is more difficult for reads larger than the
1193 * size of the MBOX FIFO (128B), because the Target is unable
1194 * to push the 129th byte of data until AFTER the Host posts an
1195 * HIF Read and removes some FIFO data. So for large reads the
1196 * Host proceeds to post an HIF Read BEFORE all the data is
1197 * actually available to read. Fortunately, large BMI reads do
1198 * not occur in practice -- they're supported for debug/development.
1200 * So Host/Target BMI synchronization is divided into these cases:
1201 * CASE 1: length < 4
1204 * CASE 2: 4 <= length <= 128
1205 * Wait for first 4 bytes to be in FIFO
1206 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1207 * a BMI command credit, which indicates that the ENTIRE
1208 * response is available in the the FIFO
1210 * CASE 3: length > 128
1211 * Wait for the first 4 bytes to be in FIFO
1213 * For most uses, a small timeout should be sufficient and we will
1214 * usually see a response quickly; but there may be some unusual
1215 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1216 * For now, we use an unbounded busy loop while waiting for
1219 * If BMI_EXECUTE ever needs to support longer-latency execution,
1220 * especially in production, this code needs to be enhanced to sleep
1221 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1222 * a function of Host processor speed.
1224 ret = ath10k_sdio_bmi_get_rx_lookahead(ar);
1228 /* We always read from the start of the mbox address */
1229 addr = ar_sdio->mbox_info.htc_addr;
1230 ret = ath10k_sdio_read(ar, addr, ar_sdio->bmi_buf, *resp_len);
1233 "unable to read the bmi data from the device: %d\n",
1238 memcpy(resp, ar_sdio->bmi_buf, *resp_len);
1243 /* sdio async handling functions */
1245 static struct ath10k_sdio_bus_request
1246 *ath10k_sdio_alloc_busreq(struct ath10k *ar)
1248 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1249 struct ath10k_sdio_bus_request *bus_req;
1251 spin_lock_bh(&ar_sdio->lock);
1253 if (list_empty(&ar_sdio->bus_req_freeq)) {
1258 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
1259 struct ath10k_sdio_bus_request, list);
1260 list_del(&bus_req->list);
1263 spin_unlock_bh(&ar_sdio->lock);
1267 static void ath10k_sdio_free_bus_req(struct ath10k *ar,
1268 struct ath10k_sdio_bus_request *bus_req)
1270 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1272 memset(bus_req, 0, sizeof(*bus_req));
1274 spin_lock_bh(&ar_sdio->lock);
1275 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
1276 spin_unlock_bh(&ar_sdio->lock);
1279 static void __ath10k_sdio_write_async(struct ath10k *ar,
1280 struct ath10k_sdio_bus_request *req)
1282 struct ath10k_htc_ep *ep;
1283 struct sk_buff *skb;
1287 ret = ath10k_sdio_write(ar, req->address, skb->data, skb->len);
1289 ath10k_warn(ar, "failed to write skb to 0x%x asynchronously: %d",
1293 ep = &ar->htc.endpoint[req->eid];
1294 ath10k_htc_notify_tx_completion(ep, skb);
1295 } else if (req->comp) {
1296 complete(req->comp);
1299 ath10k_sdio_free_bus_req(ar, req);
1302 static void ath10k_sdio_write_async_work(struct work_struct *work)
1304 struct ath10k_sdio *ar_sdio = container_of(work, struct ath10k_sdio,
1306 struct ath10k *ar = ar_sdio->ar;
1307 struct ath10k_sdio_bus_request *req, *tmp_req;
1309 spin_lock_bh(&ar_sdio->wr_async_lock);
1311 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1312 list_del(&req->list);
1313 spin_unlock_bh(&ar_sdio->wr_async_lock);
1314 __ath10k_sdio_write_async(ar, req);
1315 spin_lock_bh(&ar_sdio->wr_async_lock);
1318 spin_unlock_bh(&ar_sdio->wr_async_lock);
1321 static int ath10k_sdio_prep_async_req(struct ath10k *ar, u32 addr,
1322 struct sk_buff *skb,
1323 struct completion *comp,
1324 bool htc_msg, enum ath10k_htc_ep_id eid)
1326 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1327 struct ath10k_sdio_bus_request *bus_req;
1329 /* Allocate a bus request for the message and queue it on the
1332 bus_req = ath10k_sdio_alloc_busreq(ar);
1335 "unable to allocate bus request for async request\n");
1341 bus_req->address = addr;
1342 bus_req->htc_msg = htc_msg;
1343 bus_req->comp = comp;
1345 spin_lock_bh(&ar_sdio->wr_async_lock);
1346 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
1347 spin_unlock_bh(&ar_sdio->wr_async_lock);
1354 static void ath10k_sdio_irq_handler(struct sdio_func *func)
1356 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
1357 struct ath10k *ar = ar_sdio->ar;
1358 unsigned long timeout;
1362 /* Release the host during interrupts so we can pick it back up when
1363 * we process commands.
1365 sdio_release_host(ar_sdio->func);
1367 timeout = jiffies + ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ;
1369 ret = ath10k_sdio_mbox_proc_pending_irqs(ar, &done);
1372 } while (time_before(jiffies, timeout) && !done);
1374 ath10k_mac_tx_push_pending(ar);
1376 sdio_claim_host(ar_sdio->func);
1378 if (ret && ret != -ECANCELED)
1379 ath10k_warn(ar, "failed to process pending SDIO interrupts: %d\n",
1383 /* sdio HIF functions */
1385 static int ath10k_sdio_hif_disable_intrs(struct ath10k *ar)
1387 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1388 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1389 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1392 mutex_lock(&irq_data->mtx);
1394 memset(regs, 0, sizeof(*regs));
1395 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1396 ®s->int_status_en, sizeof(*regs));
1398 ath10k_warn(ar, "unable to disable sdio interrupts: %d\n", ret);
1400 mutex_unlock(&irq_data->mtx);
1405 static int ath10k_sdio_hif_power_up(struct ath10k *ar)
1407 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1408 struct sdio_func *func = ar_sdio->func;
1411 if (!ar_sdio->is_disabled)
1414 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power on\n");
1416 sdio_claim_host(func);
1418 ret = sdio_enable_func(func);
1420 ath10k_warn(ar, "unable to enable sdio function: %d)\n", ret);
1421 sdio_release_host(func);
1425 sdio_release_host(func);
1427 /* Wait for hardware to initialise. It should take a lot less than
1428 * 20 ms but let's be conservative here.
1432 ar_sdio->is_disabled = false;
1434 ret = ath10k_sdio_hif_disable_intrs(ar);
1441 static void ath10k_sdio_hif_power_down(struct ath10k *ar)
1443 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1446 if (ar_sdio->is_disabled)
1449 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power off\n");
1451 /* Disable the card */
1452 sdio_claim_host(ar_sdio->func);
1453 ret = sdio_disable_func(ar_sdio->func);
1454 sdio_release_host(ar_sdio->func);
1457 ath10k_warn(ar, "unable to disable sdio function: %d\n", ret);
1459 ar_sdio->is_disabled = true;
1462 static int ath10k_sdio_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1463 struct ath10k_hif_sg_item *items, int n_items)
1465 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1466 enum ath10k_htc_ep_id eid;
1467 struct sk_buff *skb;
1470 eid = pipe_id_to_eid(pipe_id);
1472 for (i = 0; i < n_items; i++) {
1476 skb = items[i].transfer_context;
1477 padded_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio,
1479 skb_trim(skb, padded_len);
1481 /* Write TX data to the end of the mbox address space */
1482 address = ar_sdio->mbox_addr[eid] + ar_sdio->mbox_size[eid] -
1484 ret = ath10k_sdio_prep_async_req(ar, address, skb,
1490 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1495 static int ath10k_sdio_hif_enable_intrs(struct ath10k *ar)
1497 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1498 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1499 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1502 mutex_lock(&irq_data->mtx);
1504 /* Enable all but CPU interrupts */
1505 regs->int_status_en = FIELD_PREP(MBOX_INT_STATUS_ENABLE_ERROR_MASK, 1) |
1506 FIELD_PREP(MBOX_INT_STATUS_ENABLE_CPU_MASK, 1) |
1507 FIELD_PREP(MBOX_INT_STATUS_ENABLE_COUNTER_MASK, 1);
1509 /* NOTE: There are some cases where HIF can do detection of
1510 * pending mbox messages which is disabled now.
1512 regs->int_status_en |=
1513 FIELD_PREP(MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK, 1);
1515 /* Set up the CPU Interrupt status Register */
1516 regs->cpu_int_status_en = 0;
1518 /* Set up the Error Interrupt status Register */
1519 regs->err_int_status_en =
1520 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 1) |
1521 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 1);
1523 /* Enable Counter interrupt status register to get fatal errors for
1526 regs->cntr_int_status_en =
1527 FIELD_PREP(MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
1528 ATH10K_SDIO_TARGET_DEBUG_INTR_MASK);
1530 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1531 ®s->int_status_en, sizeof(*regs));
1534 "failed to update mbox interrupt status register : %d\n",
1537 mutex_unlock(&irq_data->mtx);
1541 static int ath10k_sdio_hif_set_mbox_sleep(struct ath10k *ar, bool enable_sleep)
1546 ret = ath10k_sdio_read32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, &val);
1548 ath10k_warn(ar, "failed to read fifo/chip control register: %d\n",
1554 val &= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF;
1556 val |= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON;
1558 ret = ath10k_sdio_write32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, val);
1560 ath10k_warn(ar, "failed to write to FIFO_TIMEOUT_AND_CHIP_CONTROL: %d",
1568 /* HIF diagnostics */
1570 static int ath10k_sdio_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1576 mem = kzalloc(buf_len, GFP_KERNEL);
1580 /* set window register to start read cycle */
1581 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_READ_ADDR_ADDRESS, address);
1583 ath10k_warn(ar, "failed to set mbox window read address: %d", ret);
1588 ret = ath10k_sdio_read(ar, MBOX_WINDOW_DATA_ADDRESS, mem, buf_len);
1590 ath10k_warn(ar, "failed to read from mbox window data address: %d\n",
1595 memcpy(buf, mem, buf_len);
1603 static int ath10k_sdio_hif_diag_read32(struct ath10k *ar, u32 address,
1609 val = kzalloc(sizeof(*val), GFP_KERNEL);
1613 ret = ath10k_sdio_hif_diag_read(ar, address, val, sizeof(*val));
1617 *value = __le32_to_cpu(*val);
1625 static int ath10k_sdio_hif_diag_write_mem(struct ath10k *ar, u32 address,
1626 const void *data, int nbytes)
1630 /* set write data */
1631 ret = ath10k_sdio_write(ar, MBOX_WINDOW_DATA_ADDRESS, data, nbytes);
1634 "failed to write 0x%p to mbox window data address: %d\n",
1639 /* set window register, which starts the write cycle */
1640 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_WRITE_ADDR_ADDRESS, address);
1642 ath10k_warn(ar, "failed to set mbox window write address: %d", ret);
1649 /* HIF start/stop */
1651 static int ath10k_sdio_hif_start(struct ath10k *ar)
1653 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1657 /* Sleep 20 ms before HIF interrupts are disabled.
1658 * This will give target plenty of time to process the BMI done
1659 * request before interrupts are disabled.
1662 ret = ath10k_sdio_hif_disable_intrs(ar);
1666 /* eid 0 always uses the lower part of the extended mailbox address
1667 * space (ext_info[0].htc_ext_addr).
1669 ar_sdio->mbox_addr[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1670 ar_sdio->mbox_size[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1672 sdio_claim_host(ar_sdio->func);
1674 /* Register the isr */
1675 ret = sdio_claim_irq(ar_sdio->func, ath10k_sdio_irq_handler);
1677 ath10k_warn(ar, "failed to claim sdio interrupt: %d\n", ret);
1678 sdio_release_host(ar_sdio->func);
1682 sdio_release_host(ar_sdio->func);
1684 ret = ath10k_sdio_hif_enable_intrs(ar);
1686 ath10k_warn(ar, "failed to enable sdio interrupts: %d\n", ret);
1688 addr = host_interest_item_address(HI_ITEM(hi_acs_flags));
1690 ret = ath10k_sdio_hif_diag_read32(ar, addr, &val);
1692 ath10k_warn(ar, "unable to read hi_acs_flags address: %d\n", ret);
1696 if (val & HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK) {
1697 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1698 "sdio mailbox swap service enabled\n");
1699 ar_sdio->swap_mbox = true;
1702 /* Enable sleep and then disable it again */
1703 ret = ath10k_sdio_hif_set_mbox_sleep(ar, true);
1707 /* Wait for 20ms for the written value to take effect */
1710 ret = ath10k_sdio_hif_set_mbox_sleep(ar, false);
1717 #define SDIO_IRQ_DISABLE_TIMEOUT_HZ (3 * HZ)
1719 static void ath10k_sdio_irq_disable(struct ath10k *ar)
1721 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1722 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1723 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1724 struct sk_buff *skb;
1725 struct completion irqs_disabled_comp;
1728 skb = dev_alloc_skb(sizeof(*regs));
1732 mutex_lock(&irq_data->mtx);
1734 memset(regs, 0, sizeof(*regs)); /* disable all interrupts */
1735 memcpy(skb->data, regs, sizeof(*regs));
1736 skb_put(skb, sizeof(*regs));
1738 mutex_unlock(&irq_data->mtx);
1740 init_completion(&irqs_disabled_comp);
1741 ret = ath10k_sdio_prep_async_req(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1742 skb, &irqs_disabled_comp, false, 0);
1746 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1748 /* Wait for the completion of the IRQ disable request.
1749 * If there is a timeout we will try to disable irq's anyway.
1751 ret = wait_for_completion_timeout(&irqs_disabled_comp,
1752 SDIO_IRQ_DISABLE_TIMEOUT_HZ);
1754 ath10k_warn(ar, "sdio irq disable request timed out\n");
1756 sdio_claim_host(ar_sdio->func);
1758 ret = sdio_release_irq(ar_sdio->func);
1760 ath10k_warn(ar, "failed to release sdio interrupt: %d\n", ret);
1762 sdio_release_host(ar_sdio->func);
1768 static void ath10k_sdio_hif_stop(struct ath10k *ar)
1770 struct ath10k_sdio_bus_request *req, *tmp_req;
1771 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1773 ath10k_sdio_irq_disable(ar);
1775 cancel_work_sync(&ar_sdio->wr_async_work);
1777 spin_lock_bh(&ar_sdio->wr_async_lock);
1779 /* Free all bus requests that have not been handled */
1780 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1781 struct ath10k_htc_ep *ep;
1783 list_del(&req->list);
1786 ep = &ar->htc.endpoint[req->eid];
1787 ath10k_htc_notify_tx_completion(ep, req->skb);
1788 } else if (req->skb) {
1789 kfree_skb(req->skb);
1791 ath10k_sdio_free_bus_req(ar, req);
1794 spin_unlock_bh(&ar_sdio->wr_async_lock);
1799 static int ath10k_sdio_hif_suspend(struct ath10k *ar)
1804 static int ath10k_sdio_hif_resume(struct ath10k *ar)
1806 switch (ar->state) {
1807 case ATH10K_STATE_OFF:
1808 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1809 "sdio resume configuring sdio\n");
1811 /* need to set sdio settings after power is cut from sdio */
1812 ath10k_sdio_config(ar);
1815 case ATH10K_STATE_ON:
1824 static int ath10k_sdio_hif_map_service_to_pipe(struct ath10k *ar,
1826 u8 *ul_pipe, u8 *dl_pipe)
1828 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1829 struct ath10k_htc *htc = &ar->htc;
1830 u32 htt_addr, wmi_addr, htt_mbox_size, wmi_mbox_size;
1831 enum ath10k_htc_ep_id eid;
1832 bool ep_found = false;
1835 /* For sdio, we are interested in the mapping between eid
1836 * and pipeid rather than service_id to pipe_id.
1837 * First we find out which eid has been allocated to the
1840 for (i = 0; i < ATH10K_HTC_EP_COUNT; i++) {
1841 if (htc->endpoint[i].service_id == service_id) {
1842 eid = htc->endpoint[i].eid;
1851 /* Then we create the simplest mapping possible between pipeid
1854 *ul_pipe = *dl_pipe = (u8)eid;
1856 /* Normally, HTT will use the upper part of the extended
1857 * mailbox address space (ext_info[1].htc_ext_addr) and WMI ctrl
1858 * the lower part (ext_info[0].htc_ext_addr).
1859 * If fw wants swapping of mailbox addresses, the opposite is true.
1861 if (ar_sdio->swap_mbox) {
1862 htt_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1863 wmi_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1864 htt_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1865 wmi_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1867 htt_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1868 wmi_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1869 htt_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1870 wmi_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1873 switch (service_id) {
1874 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1875 /* HTC ctrl ep mbox address has already been setup in
1876 * ath10k_sdio_hif_start
1879 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1880 ar_sdio->mbox_addr[eid] = wmi_addr;
1881 ar_sdio->mbox_size[eid] = wmi_mbox_size;
1882 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1883 "sdio wmi ctrl mbox_addr 0x%x mbox_size %d\n",
1884 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1886 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1887 ar_sdio->mbox_addr[eid] = htt_addr;
1888 ar_sdio->mbox_size[eid] = htt_mbox_size;
1889 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1890 "sdio htt data mbox_addr 0x%x mbox_size %d\n",
1891 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1894 ath10k_warn(ar, "unsupported HTC service id: %d\n",
1902 static void ath10k_sdio_hif_get_default_pipe(struct ath10k *ar,
1903 u8 *ul_pipe, u8 *dl_pipe)
1905 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio hif get default pipe\n");
1907 /* HTC ctrl ep (SVC id 1) always has eid (and pipe_id in our
1914 /* This op is currently only used by htc_wait_target if the HTC ready
1915 * message times out. It is not applicable for SDIO since there is nothing
1916 * we can do if the HTC ready message does not arrive in time.
1917 * TODO: Make this op non mandatory by introducing a NULL check in the
1920 static void ath10k_sdio_hif_send_complete_check(struct ath10k *ar,
1925 static const struct ath10k_hif_ops ath10k_sdio_hif_ops = {
1926 .tx_sg = ath10k_sdio_hif_tx_sg,
1927 .diag_read = ath10k_sdio_hif_diag_read,
1928 .diag_write = ath10k_sdio_hif_diag_write_mem,
1929 .exchange_bmi_msg = ath10k_sdio_bmi_exchange_msg,
1930 .start = ath10k_sdio_hif_start,
1931 .stop = ath10k_sdio_hif_stop,
1932 .map_service_to_pipe = ath10k_sdio_hif_map_service_to_pipe,
1933 .get_default_pipe = ath10k_sdio_hif_get_default_pipe,
1934 .send_complete_check = ath10k_sdio_hif_send_complete_check,
1935 .power_up = ath10k_sdio_hif_power_up,
1936 .power_down = ath10k_sdio_hif_power_down,
1938 .suspend = ath10k_sdio_hif_suspend,
1939 .resume = ath10k_sdio_hif_resume,
1943 #ifdef CONFIG_PM_SLEEP
1945 /* Empty handlers so that mmc subsystem doesn't remove us entirely during
1946 * suspend. We instead follow cfg80211 suspend/resume handlers.
1948 static int ath10k_sdio_pm_suspend(struct device *device)
1953 static int ath10k_sdio_pm_resume(struct device *device)
1958 static SIMPLE_DEV_PM_OPS(ath10k_sdio_pm_ops, ath10k_sdio_pm_suspend,
1959 ath10k_sdio_pm_resume);
1961 #define ATH10K_SDIO_PM_OPS (&ath10k_sdio_pm_ops)
1965 #define ATH10K_SDIO_PM_OPS NULL
1967 #endif /* CONFIG_PM_SLEEP */
1969 static int ath10k_sdio_probe(struct sdio_func *func,
1970 const struct sdio_device_id *id)
1972 struct ath10k_sdio *ar_sdio;
1974 enum ath10k_hw_rev hw_rev;
1975 u32 chip_id, dev_id_base;
1978 /* Assumption: All SDIO based chipsets (so far) are QCA6174 based.
1979 * If there will be newer chipsets that does not use the hw reg
1980 * setup as defined in qca6174_regs and qca6174_values, this
1981 * assumption is no longer valid and hw_rev must be setup differently
1982 * depending on chipset.
1984 hw_rev = ATH10K_HW_QCA6174;
1986 ar = ath10k_core_create(sizeof(*ar_sdio), &func->dev, ATH10K_BUS_SDIO,
1987 hw_rev, &ath10k_sdio_hif_ops);
1989 dev_err(&func->dev, "failed to allocate core\n");
1993 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1994 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1995 func->num, func->vendor, func->device,
1996 func->max_blksize, func->cur_blksize);
1998 ar_sdio = ath10k_sdio_priv(ar);
2000 ar_sdio->irq_data.irq_proc_reg =
2001 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_proc_regs),
2003 if (!ar_sdio->irq_data.irq_proc_reg) {
2005 goto err_core_destroy;
2008 ar_sdio->irq_data.irq_en_reg =
2009 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_enable_regs),
2011 if (!ar_sdio->irq_data.irq_en_reg) {
2013 goto err_core_destroy;
2016 ar_sdio->bmi_buf = devm_kzalloc(ar->dev, BMI_MAX_CMDBUF_SIZE, GFP_KERNEL);
2017 if (!ar_sdio->bmi_buf) {
2019 goto err_core_destroy;
2022 ar_sdio->func = func;
2023 sdio_set_drvdata(func, ar_sdio);
2025 ar_sdio->is_disabled = true;
2028 spin_lock_init(&ar_sdio->lock);
2029 spin_lock_init(&ar_sdio->wr_async_lock);
2030 mutex_init(&ar_sdio->irq_data.mtx);
2032 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
2033 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
2035 INIT_WORK(&ar_sdio->wr_async_work, ath10k_sdio_write_async_work);
2036 ar_sdio->workqueue = create_singlethread_workqueue("ath10k_sdio_wq");
2037 if (!ar_sdio->workqueue) {
2039 goto err_core_destroy;
2042 for (i = 0; i < ATH10K_SDIO_BUS_REQUEST_MAX_NUM; i++)
2043 ath10k_sdio_free_bus_req(ar, &ar_sdio->bus_req[i]);
2045 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, id->device);
2046 switch (dev_id_base) {
2047 case QCA_MANUFACTURER_ID_AR6005_BASE:
2048 case QCA_MANUFACTURER_ID_QCA9377_BASE:
2049 ar->dev_id = QCA9377_1_0_DEVICE_ID;
2053 ath10k_err(ar, "unsupported device id %u (0x%x)\n",
2054 dev_id_base, id->device);
2058 ar->id.vendor = id->vendor;
2059 ar->id.device = id->device;
2061 ath10k_sdio_set_mbox_info(ar);
2063 ret = ath10k_sdio_config(ar);
2065 ath10k_err(ar, "failed to config sdio: %d\n", ret);
2069 /* TODO: don't know yet how to get chip_id with SDIO */
2071 ret = ath10k_core_register(ar, chip_id);
2073 ath10k_err(ar, "failed to register driver core: %d\n", ret);
2077 /* TODO: remove this once SDIO support is fully implemented */
2078 ath10k_warn(ar, "WARNING: ath10k SDIO support is incomplete, don't expect anything to work!\n");
2083 destroy_workqueue(ar_sdio->workqueue);
2085 ath10k_core_destroy(ar);
2090 static void ath10k_sdio_remove(struct sdio_func *func)
2092 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
2093 struct ath10k *ar = ar_sdio->ar;
2095 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2096 "sdio removed func %d vendor 0x%x device 0x%x\n",
2097 func->num, func->vendor, func->device);
2099 (void)ath10k_sdio_hif_disable_intrs(ar);
2100 cancel_work_sync(&ar_sdio->wr_async_work);
2101 ath10k_core_unregister(ar);
2102 ath10k_core_destroy(ar);
2104 flush_workqueue(ar_sdio->workqueue);
2105 destroy_workqueue(ar_sdio->workqueue);
2108 static const struct sdio_device_id ath10k_sdio_devices[] = {
2109 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2110 (QCA_SDIO_ID_AR6005_BASE | 0xA))},
2111 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2112 (QCA_SDIO_ID_QCA9377_BASE | 0x1))},
2116 MODULE_DEVICE_TABLE(sdio, ath10k_sdio_devices);
2118 static struct sdio_driver ath10k_sdio_driver = {
2119 .name = "ath10k_sdio",
2120 .id_table = ath10k_sdio_devices,
2121 .probe = ath10k_sdio_probe,
2122 .remove = ath10k_sdio_remove,
2123 .drv.pm = ATH10K_SDIO_PM_OPS,
2126 static int __init ath10k_sdio_init(void)
2130 ret = sdio_register_driver(&ath10k_sdio_driver);
2132 pr_err("sdio driver registration failed: %d\n", ret);
2137 static void __exit ath10k_sdio_exit(void)
2139 sdio_unregister_driver(&ath10k_sdio_driver);
2142 module_init(ath10k_sdio_init);
2143 module_exit(ath10k_sdio_exit);
2145 MODULE_AUTHOR("Qualcomm Atheros");
2146 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN SDIO devices");
2147 MODULE_LICENSE("Dual BSD/GPL");