2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_reset_mode {
37 ATH10K_PCI_RESET_AUTO = 0,
38 ATH10K_PCI_RESET_WARM_ONLY = 1,
41 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
42 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
44 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
45 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
47 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
48 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
50 /* how long wait to wait for target to initialise, in ms */
51 #define ATH10K_PCI_TARGET_WAIT 3000
52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
54 static const struct pci_device_id ath10k_pci_id_table[] = {
55 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
56 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
57 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
58 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
59 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
60 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
61 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
62 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
66 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
67 /* QCA988X pre 2.0 chips are not supported because they need some nasty
68 * hacks. ath10k doesn't have them and these devices crash horribly
71 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
73 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
74 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
75 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
79 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
80 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
81 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
85 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
87 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
89 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
92 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
94 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
97 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
98 static int ath10k_pci_cold_reset(struct ath10k *ar);
99 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
100 static int ath10k_pci_init_irq(struct ath10k *ar);
101 static int ath10k_pci_deinit_irq(struct ath10k *ar);
102 static int ath10k_pci_request_irq(struct ath10k *ar);
103 static void ath10k_pci_free_irq(struct ath10k *ar);
104 static int ath10k_pci_bmi_wait(struct ath10k *ar,
105 struct ath10k_ce_pipe *tx_pipe,
106 struct ath10k_ce_pipe *rx_pipe,
107 struct bmi_xfer *xfer);
108 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
109 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
110 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
111 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
112 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
113 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
114 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
116 static struct ce_attr host_ce_config_wlan[] = {
117 /* CE0: host->target HTC control and raw streams */
119 .flags = CE_ATTR_FLAGS,
123 .send_cb = ath10k_pci_htc_tx_cb,
126 /* CE1: target->host HTT + HTC control */
128 .flags = CE_ATTR_FLAGS,
131 .dest_nentries = 512,
132 .recv_cb = ath10k_pci_htt_htc_rx_cb,
135 /* CE2: target->host WMI */
137 .flags = CE_ATTR_FLAGS,
140 .dest_nentries = 128,
141 .recv_cb = ath10k_pci_htc_rx_cb,
144 /* CE3: host->target WMI */
146 .flags = CE_ATTR_FLAGS,
150 .send_cb = ath10k_pci_htc_tx_cb,
153 /* CE4: host->target HTT */
155 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
156 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
159 .send_cb = ath10k_pci_htt_tx_cb,
162 /* CE5: target->host HTT (HIF->HTT) */
164 .flags = CE_ATTR_FLAGS,
167 .dest_nentries = 512,
168 .recv_cb = ath10k_pci_htt_rx_cb,
171 /* CE6: target autonomous hif_memcpy */
173 .flags = CE_ATTR_FLAGS,
179 /* CE7: ce_diag, the Diagnostic Window */
181 .flags = CE_ATTR_FLAGS,
183 .src_sz_max = DIAG_TRANSFER_LIMIT,
187 /* CE8: target->host pktlog */
189 .flags = CE_ATTR_FLAGS,
192 .dest_nentries = 128,
193 .recv_cb = ath10k_pci_pktlog_rx_cb,
196 /* CE9 target autonomous qcache memcpy */
198 .flags = CE_ATTR_FLAGS,
204 /* CE10: target autonomous hif memcpy */
206 .flags = CE_ATTR_FLAGS,
212 /* CE11: target autonomous hif memcpy */
214 .flags = CE_ATTR_FLAGS,
221 /* Target firmware's Copy Engine configuration. */
222 static struct ce_pipe_config target_ce_config_wlan[] = {
223 /* CE0: host->target HTC control and raw streams */
225 .pipenum = __cpu_to_le32(0),
226 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
227 .nentries = __cpu_to_le32(32),
228 .nbytes_max = __cpu_to_le32(256),
229 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
230 .reserved = __cpu_to_le32(0),
233 /* CE1: target->host HTT + HTC control */
235 .pipenum = __cpu_to_le32(1),
236 .pipedir = __cpu_to_le32(PIPEDIR_IN),
237 .nentries = __cpu_to_le32(32),
238 .nbytes_max = __cpu_to_le32(2048),
239 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
240 .reserved = __cpu_to_le32(0),
243 /* CE2: target->host WMI */
245 .pipenum = __cpu_to_le32(2),
246 .pipedir = __cpu_to_le32(PIPEDIR_IN),
247 .nentries = __cpu_to_le32(64),
248 .nbytes_max = __cpu_to_le32(2048),
249 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
250 .reserved = __cpu_to_le32(0),
253 /* CE3: host->target WMI */
255 .pipenum = __cpu_to_le32(3),
256 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
257 .nentries = __cpu_to_le32(32),
258 .nbytes_max = __cpu_to_le32(2048),
259 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
260 .reserved = __cpu_to_le32(0),
263 /* CE4: host->target HTT */
265 .pipenum = __cpu_to_le32(4),
266 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
267 .nentries = __cpu_to_le32(256),
268 .nbytes_max = __cpu_to_le32(256),
269 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
270 .reserved = __cpu_to_le32(0),
273 /* NB: 50% of src nentries, since tx has 2 frags */
275 /* CE5: target->host HTT (HIF->HTT) */
277 .pipenum = __cpu_to_le32(5),
278 .pipedir = __cpu_to_le32(PIPEDIR_IN),
279 .nentries = __cpu_to_le32(32),
280 .nbytes_max = __cpu_to_le32(512),
281 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
282 .reserved = __cpu_to_le32(0),
285 /* CE6: Reserved for target autonomous hif_memcpy */
287 .pipenum = __cpu_to_le32(6),
288 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
289 .nentries = __cpu_to_le32(32),
290 .nbytes_max = __cpu_to_le32(4096),
291 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
292 .reserved = __cpu_to_le32(0),
295 /* CE7 used only by Host */
297 .pipenum = __cpu_to_le32(7),
298 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
299 .nentries = __cpu_to_le32(0),
300 .nbytes_max = __cpu_to_le32(0),
301 .flags = __cpu_to_le32(0),
302 .reserved = __cpu_to_le32(0),
305 /* CE8 target->host packtlog */
307 .pipenum = __cpu_to_le32(8),
308 .pipedir = __cpu_to_le32(PIPEDIR_IN),
309 .nentries = __cpu_to_le32(64),
310 .nbytes_max = __cpu_to_le32(2048),
311 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
312 .reserved = __cpu_to_le32(0),
315 /* CE9 target autonomous qcache memcpy */
317 .pipenum = __cpu_to_le32(9),
318 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
319 .nentries = __cpu_to_le32(32),
320 .nbytes_max = __cpu_to_le32(2048),
321 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
322 .reserved = __cpu_to_le32(0),
325 /* It not necessary to send target wlan configuration for CE10 & CE11
326 * as these CEs are not actively used in target.
331 * Map from service/endpoint to Copy Engine.
332 * This table is derived from the CE_PCI TABLE, above.
333 * It is passed to the Target at startup for use by firmware.
335 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
337 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
338 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
342 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
343 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
348 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
353 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
358 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
363 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
368 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
373 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
377 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
378 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
382 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
383 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
387 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
388 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
392 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
393 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
397 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
398 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
402 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
403 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
407 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
408 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
412 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
413 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
417 /* (Additions here) */
426 static bool ath10k_pci_is_awake(struct ath10k *ar)
428 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
429 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
432 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
435 static void __ath10k_pci_wake(struct ath10k *ar)
437 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
439 lockdep_assert_held(&ar_pci->ps_lock);
441 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
442 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
444 iowrite32(PCIE_SOC_WAKE_V_MASK,
445 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
446 PCIE_SOC_WAKE_ADDRESS);
449 static void __ath10k_pci_sleep(struct ath10k *ar)
451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
453 lockdep_assert_held(&ar_pci->ps_lock);
455 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
456 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
458 iowrite32(PCIE_SOC_WAKE_RESET,
459 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
460 PCIE_SOC_WAKE_ADDRESS);
461 ar_pci->ps_awake = false;
464 static int ath10k_pci_wake_wait(struct ath10k *ar)
469 while (tot_delay < PCIE_WAKE_TIMEOUT) {
470 if (ath10k_pci_is_awake(ar)) {
471 if (tot_delay > PCIE_WAKE_LATE_US)
472 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
478 tot_delay += curr_delay;
487 static int ath10k_pci_force_wake(struct ath10k *ar)
489 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
496 spin_lock_irqsave(&ar_pci->ps_lock, flags);
498 if (!ar_pci->ps_awake) {
499 iowrite32(PCIE_SOC_WAKE_V_MASK,
500 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
501 PCIE_SOC_WAKE_ADDRESS);
503 ret = ath10k_pci_wake_wait(ar);
505 ar_pci->ps_awake = true;
508 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
513 static void ath10k_pci_force_sleep(struct ath10k *ar)
515 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
518 spin_lock_irqsave(&ar_pci->ps_lock, flags);
520 iowrite32(PCIE_SOC_WAKE_RESET,
521 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
522 PCIE_SOC_WAKE_ADDRESS);
523 ar_pci->ps_awake = false;
525 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
528 static int ath10k_pci_wake(struct ath10k *ar)
530 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
534 if (ar_pci->pci_ps == 0)
537 spin_lock_irqsave(&ar_pci->ps_lock, flags);
539 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
540 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
542 /* This function can be called very frequently. To avoid excessive
543 * CPU stalls for MMIO reads use a cache var to hold the device state.
545 if (!ar_pci->ps_awake) {
546 __ath10k_pci_wake(ar);
548 ret = ath10k_pci_wake_wait(ar);
550 ar_pci->ps_awake = true;
554 ar_pci->ps_wake_refcount++;
555 WARN_ON(ar_pci->ps_wake_refcount == 0);
558 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
563 static void ath10k_pci_sleep(struct ath10k *ar)
565 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
568 if (ar_pci->pci_ps == 0)
571 spin_lock_irqsave(&ar_pci->ps_lock, flags);
573 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
574 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
576 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
579 ar_pci->ps_wake_refcount--;
581 mod_timer(&ar_pci->ps_timer, jiffies +
582 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
585 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
588 static void ath10k_pci_ps_timer(unsigned long ptr)
590 struct ath10k *ar = (void *)ptr;
591 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
594 spin_lock_irqsave(&ar_pci->ps_lock, flags);
596 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
597 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
599 if (ar_pci->ps_wake_refcount > 0)
602 __ath10k_pci_sleep(ar);
605 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
608 static void ath10k_pci_sleep_sync(struct ath10k *ar)
610 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
613 if (ar_pci->pci_ps == 0) {
614 ath10k_pci_force_sleep(ar);
618 del_timer_sync(&ar_pci->ps_timer);
620 spin_lock_irqsave(&ar_pci->ps_lock, flags);
621 WARN_ON(ar_pci->ps_wake_refcount > 0);
622 __ath10k_pci_sleep(ar);
623 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
626 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
628 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
631 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
632 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
633 offset, offset + sizeof(value), ar_pci->mem_len);
637 ret = ath10k_pci_wake(ar);
639 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
644 iowrite32(value, ar_pci->mem + offset);
645 ath10k_pci_sleep(ar);
648 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
650 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
654 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
655 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
656 offset, offset + sizeof(val), ar_pci->mem_len);
660 ret = ath10k_pci_wake(ar);
662 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
667 val = ioread32(ar_pci->mem + offset);
668 ath10k_pci_sleep(ar);
673 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
675 struct ath10k_ce *ce = ath10k_ce_priv(ar);
677 ce->bus_ops->write32(ar, offset, value);
680 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
682 struct ath10k_ce *ce = ath10k_ce_priv(ar);
684 return ce->bus_ops->read32(ar, offset);
687 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
689 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
692 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
694 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
697 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
699 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
702 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
704 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
707 bool ath10k_pci_irq_pending(struct ath10k *ar)
711 /* Check if the shared legacy irq is for us */
712 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
713 PCIE_INTR_CAUSE_ADDRESS);
714 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
720 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
722 /* IMPORTANT: INTR_CLR register has to be set after
723 * INTR_ENABLE is set to 0, otherwise interrupt can not be
726 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
728 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
729 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
731 /* IMPORTANT: this extra read transaction is required to
732 * flush the posted write buffer.
734 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
735 PCIE_INTR_ENABLE_ADDRESS);
738 void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
740 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
741 PCIE_INTR_ENABLE_ADDRESS,
742 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
744 /* IMPORTANT: this extra read transaction is required to
745 * flush the posted write buffer.
747 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
748 PCIE_INTR_ENABLE_ADDRESS);
751 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
753 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
755 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
761 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
763 struct ath10k *ar = pipe->hif_ce_state;
764 struct ath10k_ce *ce = ath10k_ce_priv(ar);
765 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
770 skb = dev_alloc_skb(pipe->buf_sz);
774 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
776 paddr = dma_map_single(ar->dev, skb->data,
777 skb->len + skb_tailroom(skb),
779 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
780 ath10k_warn(ar, "failed to dma map pci rx buf\n");
781 dev_kfree_skb_any(skb);
785 ATH10K_SKB_RXCB(skb)->paddr = paddr;
787 spin_lock_bh(&ce->ce_lock);
788 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
789 spin_unlock_bh(&ce->ce_lock);
791 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
793 dev_kfree_skb_any(skb);
800 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
802 struct ath10k *ar = pipe->hif_ce_state;
803 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
804 struct ath10k_ce *ce = ath10k_ce_priv(ar);
805 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
808 if (pipe->buf_sz == 0)
811 if (!ce_pipe->dest_ring)
814 spin_lock_bh(&ce->ce_lock);
815 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
816 spin_unlock_bh(&ce->ce_lock);
819 ret = __ath10k_pci_rx_post_buf(pipe);
823 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
824 mod_timer(&ar_pci->rx_post_retry, jiffies +
825 ATH10K_PCI_RX_POST_RETRY_MS);
832 void ath10k_pci_rx_post(struct ath10k *ar)
834 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
837 for (i = 0; i < CE_COUNT; i++)
838 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
841 void ath10k_pci_rx_replenish_retry(unsigned long ptr)
843 struct ath10k *ar = (void *)ptr;
845 ath10k_pci_rx_post(ar);
848 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
850 u32 val = 0, region = addr & 0xfffff;
852 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
854 val |= 0x100000 | region;
858 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
860 u32 val = 0, region = addr & 0xfffff;
862 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
863 val |= 0x100000 | region;
867 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
869 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
871 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
874 return ar_pci->targ_cpu_to_ce_addr(ar, addr);
878 * Diagnostic read/write access is provided for startup/config/debug usage.
879 * Caller must guarantee proper alignment, when applicable, and single user
882 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
885 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
886 struct ath10k_ce *ce = ath10k_ce_priv(ar);
889 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
890 struct ath10k_ce_pipe *ce_diag;
891 /* Host buffer address in CE space */
893 dma_addr_t ce_data_base = 0;
894 void *data_buf = NULL;
897 spin_lock_bh(&ce->ce_lock);
899 ce_diag = ar_pci->ce_diag;
902 * Allocate a temporary bounce buffer to hold caller's data
903 * to be DMA'ed from Target. This guarantees
904 * 1) 4-byte alignment
905 * 2) Buffer in DMA-able space
907 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
909 data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev,
919 remaining_bytes = nbytes;
920 ce_data = ce_data_base;
921 while (remaining_bytes) {
922 nbytes = min_t(unsigned int, remaining_bytes,
923 DIAG_TRANSFER_LIMIT);
925 ret = __ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data);
929 /* Request CE to send from Target(!) address to Host buffer */
931 * The address supplied by the caller is in the
932 * Target CPU virtual address space.
934 * In order to use this address with the diagnostic CE,
935 * convert it from Target CPU virtual address space
936 * to CE address space
938 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
940 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
946 while (ath10k_ce_completed_send_next_nolock(ce_diag,
949 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
956 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
962 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
968 if (nbytes != completed_nbytes) {
973 if (*buf != ce_data) {
978 remaining_bytes -= nbytes;
979 memcpy(data, data_buf, nbytes);
988 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
991 spin_unlock_bh(&ce->ce_lock);
996 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
1001 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1002 *value = __le32_to_cpu(val);
1007 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1010 u32 host_addr, addr;
1013 host_addr = host_interest_item_address(src);
1015 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1017 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1022 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1024 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1032 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1033 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1035 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1036 const void *data, int nbytes)
1038 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1039 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1042 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
1043 struct ath10k_ce_pipe *ce_diag;
1044 void *data_buf = NULL;
1045 dma_addr_t ce_data_base = 0;
1048 spin_lock_bh(&ce->ce_lock);
1050 ce_diag = ar_pci->ce_diag;
1053 * Allocate a temporary bounce buffer to hold caller's data
1054 * to be DMA'ed to Target. This guarantees
1055 * 1) 4-byte alignment
1056 * 2) Buffer in DMA-able space
1058 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
1060 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1070 * The address supplied by the caller is in the
1071 * Target CPU virtual address space.
1073 * In order to use this address with the diagnostic CE,
1075 * Target CPU virtual address space
1079 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1081 remaining_bytes = nbytes;
1082 while (remaining_bytes) {
1083 /* FIXME: check cast */
1084 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1086 /* Copy caller's data to allocated DMA buf */
1087 memcpy(data_buf, data, nbytes);
1089 /* Set up to receive directly into Target(!) address */
1090 ret = __ath10k_ce_rx_post_buf(ce_diag, &address, address);
1095 * Request CE to send caller-supplied data that
1096 * was copied to bounce buffer to Target(!) address.
1098 ret = ath10k_ce_send_nolock(ce_diag, NULL, ce_data_base,
1104 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1108 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1115 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
1121 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1127 if (nbytes != completed_nbytes) {
1132 if (*buf != address) {
1137 remaining_bytes -= nbytes;
1144 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1149 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1152 spin_unlock_bh(&ce->ce_lock);
1157 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1159 __le32 val = __cpu_to_le32(value);
1161 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1164 /* Called by lower (CE) layer when a send to Target completes. */
1165 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1167 struct ath10k *ar = ce_state->ar;
1168 struct sk_buff_head list;
1169 struct sk_buff *skb;
1171 __skb_queue_head_init(&list);
1172 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1173 /* no need to call tx completion for NULL pointers */
1177 __skb_queue_tail(&list, skb);
1180 while ((skb = __skb_dequeue(&list)))
1181 ath10k_htc_tx_completion_handler(ar, skb);
1184 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1185 void (*callback)(struct ath10k *ar,
1186 struct sk_buff *skb))
1188 struct ath10k *ar = ce_state->ar;
1189 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1190 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1191 struct sk_buff *skb;
1192 struct sk_buff_head list;
1193 void *transfer_context;
1194 unsigned int nbytes, max_nbytes;
1196 __skb_queue_head_init(&list);
1197 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1199 skb = transfer_context;
1200 max_nbytes = skb->len + skb_tailroom(skb);
1201 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1202 max_nbytes, DMA_FROM_DEVICE);
1204 if (unlikely(max_nbytes < nbytes)) {
1205 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1206 nbytes, max_nbytes);
1207 dev_kfree_skb_any(skb);
1211 skb_put(skb, nbytes);
1212 __skb_queue_tail(&list, skb);
1215 while ((skb = __skb_dequeue(&list))) {
1216 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1217 ce_state->id, skb->len);
1218 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1219 skb->data, skb->len);
1224 ath10k_pci_rx_post_pipe(pipe_info);
1227 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1228 void (*callback)(struct ath10k *ar,
1229 struct sk_buff *skb))
1231 struct ath10k *ar = ce_state->ar;
1232 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1233 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1234 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1235 struct sk_buff *skb;
1236 struct sk_buff_head list;
1237 void *transfer_context;
1238 unsigned int nbytes, max_nbytes, nentries;
1241 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1242 * is processed other than init and deinit. Before releasing CE5
1243 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1245 __skb_queue_head_init(&list);
1246 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1248 skb = transfer_context;
1249 max_nbytes = skb->len + skb_tailroom(skb);
1251 if (unlikely(max_nbytes < nbytes)) {
1252 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1253 nbytes, max_nbytes);
1257 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1258 max_nbytes, DMA_FROM_DEVICE);
1259 skb_put(skb, nbytes);
1260 __skb_queue_tail(&list, skb);
1263 nentries = skb_queue_len(&list);
1264 while ((skb = __skb_dequeue(&list))) {
1265 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1266 ce_state->id, skb->len);
1267 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1268 skb->data, skb->len);
1270 orig_len = skb->len;
1272 skb_push(skb, orig_len - skb->len);
1273 skb_reset_tail_pointer(skb);
1276 /*let device gain the buffer again*/
1277 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1278 skb->len + skb_tailroom(skb),
1281 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1284 /* Called by lower (CE) layer when data is received from the Target. */
1285 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1287 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1290 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1292 /* CE4 polling needs to be done whenever CE pipe which transports
1293 * HTT Rx (target->host) is processed.
1295 ath10k_ce_per_engine_service(ce_state->ar, 4);
1297 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1300 /* Called by lower (CE) layer when data is received from the Target.
1301 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1303 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1305 ath10k_pci_process_rx_cb(ce_state,
1306 ath10k_htt_rx_pktlog_completion_handler);
1309 /* Called by lower (CE) layer when a send to HTT Target completes. */
1310 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1312 struct ath10k *ar = ce_state->ar;
1313 struct sk_buff *skb;
1315 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1316 /* no need to call tx completion for NULL pointers */
1320 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1321 skb->len, DMA_TO_DEVICE);
1322 ath10k_htt_hif_tx_complete(ar, skb);
1326 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1328 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1329 ath10k_htt_t2h_msg_handler(ar, skb);
1332 /* Called by lower (CE) layer when HTT data is received from the Target. */
1333 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1335 /* CE4 polling needs to be done whenever CE pipe which transports
1336 * HTT Rx (target->host) is processed.
1338 ath10k_ce_per_engine_service(ce_state->ar, 4);
1340 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1343 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1344 struct ath10k_hif_sg_item *items, int n_items)
1346 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1347 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1348 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1349 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1350 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1351 unsigned int nentries_mask;
1352 unsigned int sw_index;
1353 unsigned int write_index;
1356 spin_lock_bh(&ce->ce_lock);
1358 nentries_mask = src_ring->nentries_mask;
1359 sw_index = src_ring->sw_index;
1360 write_index = src_ring->write_index;
1362 if (unlikely(CE_RING_DELTA(nentries_mask,
1363 write_index, sw_index - 1) < n_items)) {
1368 for (i = 0; i < n_items - 1; i++) {
1369 ath10k_dbg(ar, ATH10K_DBG_PCI,
1370 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1371 i, items[i].paddr, items[i].len, n_items);
1372 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1373 items[i].vaddr, items[i].len);
1375 err = ath10k_ce_send_nolock(ce_pipe,
1376 items[i].transfer_context,
1379 items[i].transfer_id,
1380 CE_SEND_FLAG_GATHER);
1385 /* `i` is equal to `n_items -1` after for() */
1387 ath10k_dbg(ar, ATH10K_DBG_PCI,
1388 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1389 i, items[i].paddr, items[i].len, n_items);
1390 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1391 items[i].vaddr, items[i].len);
1393 err = ath10k_ce_send_nolock(ce_pipe,
1394 items[i].transfer_context,
1397 items[i].transfer_id,
1402 spin_unlock_bh(&ce->ce_lock);
1407 __ath10k_ce_send_revert(ce_pipe);
1409 spin_unlock_bh(&ce->ce_lock);
1413 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1416 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1419 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1421 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1423 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1425 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1428 static void ath10k_pci_dump_registers(struct ath10k *ar,
1429 struct ath10k_fw_crash_data *crash_data)
1431 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1434 lockdep_assert_held(&ar->data_lock);
1436 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1438 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1440 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1444 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1446 ath10k_err(ar, "firmware register dump:\n");
1447 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1448 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1450 __le32_to_cpu(reg_dump_values[i]),
1451 __le32_to_cpu(reg_dump_values[i + 1]),
1452 __le32_to_cpu(reg_dump_values[i + 2]),
1453 __le32_to_cpu(reg_dump_values[i + 3]));
1458 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1459 crash_data->registers[i] = reg_dump_values[i];
1462 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1464 struct ath10k_fw_crash_data *crash_data;
1465 char guid[UUID_STRING_LEN + 1];
1467 spin_lock_bh(&ar->data_lock);
1469 ar->stats.fw_crash_counter++;
1471 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1474 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1476 scnprintf(guid, sizeof(guid), "n/a");
1478 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1479 ath10k_print_driver_info(ar);
1480 ath10k_pci_dump_registers(ar, crash_data);
1481 ath10k_ce_dump_registers(ar, crash_data);
1483 spin_unlock_bh(&ar->data_lock);
1485 queue_work(ar->workqueue, &ar->restart_work);
1488 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1491 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1496 * Decide whether to actually poll for completions, or just
1497 * wait for a later chance.
1498 * If there seem to be plenty of resources left, then just wait
1499 * since checking involves reading a CE register, which is a
1500 * relatively expensive operation.
1502 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1505 * If at least 50% of the total resources are still available,
1506 * don't bother checking again yet.
1508 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1511 ath10k_ce_per_engine_service(ar, pipe);
1514 static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1516 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1518 del_timer_sync(&ar_pci->rx_post_retry);
1521 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1522 u8 *ul_pipe, u8 *dl_pipe)
1524 const struct service_to_pipe *entry;
1525 bool ul_set = false, dl_set = false;
1528 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1530 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1531 entry = &target_service_to_ce_map_wlan[i];
1533 if (__le32_to_cpu(entry->service_id) != service_id)
1536 switch (__le32_to_cpu(entry->pipedir)) {
1541 *dl_pipe = __le32_to_cpu(entry->pipenum);
1546 *ul_pipe = __le32_to_cpu(entry->pipenum);
1552 *dl_pipe = __le32_to_cpu(entry->pipenum);
1553 *ul_pipe = __le32_to_cpu(entry->pipenum);
1560 if (WARN_ON(!ul_set || !dl_set))
1566 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1567 u8 *ul_pipe, u8 *dl_pipe)
1569 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1571 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1572 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1576 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1580 switch (ar->hw_rev) {
1581 case ATH10K_HW_QCA988X:
1582 case ATH10K_HW_QCA9887:
1583 case ATH10K_HW_QCA6174:
1584 case ATH10K_HW_QCA9377:
1585 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1587 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1588 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1589 CORE_CTRL_ADDRESS, val);
1591 case ATH10K_HW_QCA99X0:
1592 case ATH10K_HW_QCA9984:
1593 case ATH10K_HW_QCA9888:
1594 case ATH10K_HW_QCA4019:
1595 /* TODO: Find appropriate register configuration for QCA99X0
1599 case ATH10K_HW_WCN3990:
1604 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1608 switch (ar->hw_rev) {
1609 case ATH10K_HW_QCA988X:
1610 case ATH10K_HW_QCA9887:
1611 case ATH10K_HW_QCA6174:
1612 case ATH10K_HW_QCA9377:
1613 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1615 val |= CORE_CTRL_PCIE_REG_31_MASK;
1616 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1617 CORE_CTRL_ADDRESS, val);
1619 case ATH10K_HW_QCA99X0:
1620 case ATH10K_HW_QCA9984:
1621 case ATH10K_HW_QCA9888:
1622 case ATH10K_HW_QCA4019:
1623 /* TODO: Find appropriate register configuration for QCA99X0
1624 * to unmask irq/MSI.
1627 case ATH10K_HW_WCN3990:
1632 static void ath10k_pci_irq_disable(struct ath10k *ar)
1634 ath10k_ce_disable_interrupts(ar);
1635 ath10k_pci_disable_and_clear_legacy_irq(ar);
1636 ath10k_pci_irq_msi_fw_mask(ar);
1639 static void ath10k_pci_irq_sync(struct ath10k *ar)
1641 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1643 synchronize_irq(ar_pci->pdev->irq);
1646 static void ath10k_pci_irq_enable(struct ath10k *ar)
1648 ath10k_ce_enable_interrupts(ar);
1649 ath10k_pci_enable_legacy_irq(ar);
1650 ath10k_pci_irq_msi_fw_unmask(ar);
1653 static int ath10k_pci_hif_start(struct ath10k *ar)
1655 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1657 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1659 napi_enable(&ar->napi);
1661 ath10k_pci_irq_enable(ar);
1662 ath10k_pci_rx_post(ar);
1664 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1670 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1673 struct ath10k_ce_pipe *ce_pipe;
1674 struct ath10k_ce_ring *ce_ring;
1675 struct sk_buff *skb;
1678 ar = pci_pipe->hif_ce_state;
1679 ce_pipe = pci_pipe->ce_hdl;
1680 ce_ring = ce_pipe->dest_ring;
1685 if (!pci_pipe->buf_sz)
1688 for (i = 0; i < ce_ring->nentries; i++) {
1689 skb = ce_ring->per_transfer_context[i];
1693 ce_ring->per_transfer_context[i] = NULL;
1695 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1696 skb->len + skb_tailroom(skb),
1698 dev_kfree_skb_any(skb);
1702 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1705 struct ath10k_ce_pipe *ce_pipe;
1706 struct ath10k_ce_ring *ce_ring;
1707 struct sk_buff *skb;
1710 ar = pci_pipe->hif_ce_state;
1711 ce_pipe = pci_pipe->ce_hdl;
1712 ce_ring = ce_pipe->src_ring;
1717 if (!pci_pipe->buf_sz)
1720 for (i = 0; i < ce_ring->nentries; i++) {
1721 skb = ce_ring->per_transfer_context[i];
1725 ce_ring->per_transfer_context[i] = NULL;
1727 ath10k_htc_tx_completion_handler(ar, skb);
1732 * Cleanup residual buffers for device shutdown:
1733 * buffers that were enqueued for receive
1734 * buffers that were to be sent
1735 * Note: Buffers that had completed but which were
1736 * not yet processed are on a completion queue. They
1737 * are handled when the completion thread shuts down.
1739 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1741 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1744 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1745 struct ath10k_pci_pipe *pipe_info;
1747 pipe_info = &ar_pci->pipe_info[pipe_num];
1748 ath10k_pci_rx_pipe_cleanup(pipe_info);
1749 ath10k_pci_tx_pipe_cleanup(pipe_info);
1753 void ath10k_pci_ce_deinit(struct ath10k *ar)
1757 for (i = 0; i < CE_COUNT; i++)
1758 ath10k_ce_deinit_pipe(ar, i);
1761 void ath10k_pci_flush(struct ath10k *ar)
1763 ath10k_pci_rx_retry_sync(ar);
1764 ath10k_pci_buffer_cleanup(ar);
1767 static void ath10k_pci_hif_stop(struct ath10k *ar)
1769 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1770 unsigned long flags;
1772 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1774 ath10k_pci_irq_disable(ar);
1775 ath10k_pci_irq_sync(ar);
1776 napi_synchronize(&ar->napi);
1777 napi_disable(&ar->napi);
1779 /* Most likely the device has HTT Rx ring configured. The only way to
1780 * prevent the device from accessing (and possible corrupting) host
1781 * memory is to reset the chip now.
1783 * There's also no known way of masking MSI interrupts on the device.
1784 * For ranged MSI the CE-related interrupts can be masked. However
1785 * regardless how many MSI interrupts are assigned the first one
1786 * is always used for firmware indications (crashes) and cannot be
1787 * masked. To prevent the device from asserting the interrupt reset it
1788 * before proceeding with cleanup.
1790 ath10k_pci_safe_chip_reset(ar);
1792 ath10k_pci_flush(ar);
1794 spin_lock_irqsave(&ar_pci->ps_lock, flags);
1795 WARN_ON(ar_pci->ps_wake_refcount > 0);
1796 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
1799 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1800 void *req, u32 req_len,
1801 void *resp, u32 *resp_len)
1803 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1804 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1805 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1806 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1807 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1808 dma_addr_t req_paddr = 0;
1809 dma_addr_t resp_paddr = 0;
1810 struct bmi_xfer xfer = {};
1811 void *treq, *tresp = NULL;
1816 if (resp && !resp_len)
1819 if (resp && resp_len && *resp_len == 0)
1822 treq = kmemdup(req, req_len, GFP_KERNEL);
1826 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1827 ret = dma_mapping_error(ar->dev, req_paddr);
1833 if (resp && resp_len) {
1834 tresp = kzalloc(*resp_len, GFP_KERNEL);
1840 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1842 ret = dma_mapping_error(ar->dev, resp_paddr);
1848 xfer.wait_for_resp = true;
1851 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1854 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1858 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
1861 unsigned int unused_nbytes;
1862 unsigned int unused_id;
1864 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1865 &unused_nbytes, &unused_id);
1867 /* non-zero means we did not time out */
1875 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1876 dma_unmap_single(ar->dev, resp_paddr,
1877 *resp_len, DMA_FROM_DEVICE);
1880 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1882 if (ret == 0 && resp_len) {
1883 *resp_len = min(*resp_len, xfer.resp_len);
1884 memcpy(resp, tresp, xfer.resp_len);
1893 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1895 struct bmi_xfer *xfer;
1897 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
1900 xfer->tx_done = true;
1903 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1905 struct ath10k *ar = ce_state->ar;
1906 struct bmi_xfer *xfer;
1907 unsigned int nbytes;
1909 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
1913 if (WARN_ON_ONCE(!xfer))
1916 if (!xfer->wait_for_resp) {
1917 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1921 xfer->resp_len = nbytes;
1922 xfer->rx_done = true;
1925 static int ath10k_pci_bmi_wait(struct ath10k *ar,
1926 struct ath10k_ce_pipe *tx_pipe,
1927 struct ath10k_ce_pipe *rx_pipe,
1928 struct bmi_xfer *xfer)
1930 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1931 unsigned long started = jiffies;
1935 while (time_before_eq(jiffies, timeout)) {
1936 ath10k_pci_bmi_send_done(tx_pipe);
1937 ath10k_pci_bmi_recv_data(rx_pipe);
1939 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
1950 dur = jiffies - started;
1952 ath10k_dbg(ar, ATH10K_DBG_BMI,
1953 "bmi cmd took %lu jiffies hz %d ret %d\n",
1959 * Send an interrupt to the device to wake up the Target CPU
1960 * so it has an opportunity to notice any changed state.
1962 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1966 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
1967 val = ath10k_pci_read32(ar, addr);
1968 val |= CORE_CTRL_CPU_INTR_MASK;
1969 ath10k_pci_write32(ar, addr, val);
1974 static int ath10k_pci_get_num_banks(struct ath10k *ar)
1976 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1978 switch (ar_pci->pdev->device) {
1979 case QCA988X_2_0_DEVICE_ID:
1980 case QCA99X0_2_0_DEVICE_ID:
1981 case QCA9888_2_0_DEVICE_ID:
1982 case QCA9984_1_0_DEVICE_ID:
1983 case QCA9887_1_0_DEVICE_ID:
1985 case QCA6164_2_1_DEVICE_ID:
1986 case QCA6174_2_1_DEVICE_ID:
1987 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
1988 case QCA6174_HW_1_0_CHIP_ID_REV:
1989 case QCA6174_HW_1_1_CHIP_ID_REV:
1990 case QCA6174_HW_2_1_CHIP_ID_REV:
1991 case QCA6174_HW_2_2_CHIP_ID_REV:
1993 case QCA6174_HW_1_3_CHIP_ID_REV:
1995 case QCA6174_HW_3_0_CHIP_ID_REV:
1996 case QCA6174_HW_3_1_CHIP_ID_REV:
1997 case QCA6174_HW_3_2_CHIP_ID_REV:
2001 case QCA9377_1_0_DEVICE_ID:
2005 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
2009 static int ath10k_bus_get_num_banks(struct ath10k *ar)
2011 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2013 return ce->bus_ops->get_num_banks(ar);
2016 int ath10k_pci_init_config(struct ath10k *ar)
2018 u32 interconnect_targ_addr;
2019 u32 pcie_state_targ_addr = 0;
2020 u32 pipe_cfg_targ_addr = 0;
2021 u32 svc_to_pipe_map = 0;
2022 u32 pcie_config_flags = 0;
2024 u32 ealloc_targ_addr;
2026 u32 flag2_targ_addr;
2029 /* Download to Target the CE Config and the service-to-CE map */
2030 interconnect_targ_addr =
2031 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2033 /* Supply Target-side CE configuration */
2034 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2035 &pcie_state_targ_addr);
2037 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2041 if (pcie_state_targ_addr == 0) {
2043 ath10k_err(ar, "Invalid pcie state addr\n");
2047 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2048 offsetof(struct pcie_state,
2050 &pipe_cfg_targ_addr);
2052 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2056 if (pipe_cfg_targ_addr == 0) {
2058 ath10k_err(ar, "Invalid pipe cfg addr\n");
2062 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2063 target_ce_config_wlan,
2064 sizeof(struct ce_pipe_config) *
2065 NUM_TARGET_CE_CONFIG_WLAN);
2068 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2072 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2073 offsetof(struct pcie_state,
2077 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2081 if (svc_to_pipe_map == 0) {
2083 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2087 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2088 target_service_to_ce_map_wlan,
2089 sizeof(target_service_to_ce_map_wlan));
2091 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2095 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2096 offsetof(struct pcie_state,
2098 &pcie_config_flags);
2100 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2104 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2106 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2107 offsetof(struct pcie_state,
2111 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2115 /* configure early allocation */
2116 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2118 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2120 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2124 /* first bank is switched to IRAM */
2125 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2126 HI_EARLY_ALLOC_MAGIC_MASK);
2127 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2128 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2129 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2131 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2133 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2137 /* Tell Target to proceed with initialization */
2138 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2140 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2142 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2146 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2148 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2150 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2157 static void ath10k_pci_override_ce_config(struct ath10k *ar)
2159 struct ce_attr *attr;
2160 struct ce_pipe_config *config;
2162 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2163 * since it is currently used for other feature.
2166 /* Override Host's Copy Engine 5 configuration */
2167 attr = &host_ce_config_wlan[5];
2168 attr->src_sz_max = 0;
2169 attr->dest_nentries = 0;
2171 /* Override Target firmware's Copy Engine configuration */
2172 config = &target_ce_config_wlan[5];
2173 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2174 config->nbytes_max = __cpu_to_le32(2048);
2176 /* Map from service/endpoint to Copy Engine */
2177 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2180 int ath10k_pci_alloc_pipes(struct ath10k *ar)
2182 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2183 struct ath10k_pci_pipe *pipe;
2184 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2187 for (i = 0; i < CE_COUNT; i++) {
2188 pipe = &ar_pci->pipe_info[i];
2189 pipe->ce_hdl = &ce->ce_states[i];
2191 pipe->hif_ce_state = ar;
2193 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2195 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2200 /* Last CE is Diagnostic Window */
2201 if (i == CE_DIAG_PIPE) {
2202 ar_pci->ce_diag = pipe->ce_hdl;
2206 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2212 void ath10k_pci_free_pipes(struct ath10k *ar)
2216 for (i = 0; i < CE_COUNT; i++)
2217 ath10k_ce_free_pipe(ar, i);
2220 int ath10k_pci_init_pipes(struct ath10k *ar)
2224 for (i = 0; i < CE_COUNT; i++) {
2225 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2227 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2236 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2238 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2239 FW_IND_EVENT_PENDING;
2242 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2246 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2247 val &= ~FW_IND_EVENT_PENDING;
2248 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2251 static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2255 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2256 return (val == 0xffffffff);
2259 /* this function effectively clears target memory controller assert line */
2260 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2264 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2265 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2266 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2267 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2271 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2272 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2273 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2274 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2279 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2283 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2285 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2286 SOC_RESET_CONTROL_ADDRESS);
2287 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2288 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2291 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2295 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2296 SOC_RESET_CONTROL_ADDRESS);
2298 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2299 val | SOC_RESET_CONTROL_CE_RST_MASK);
2301 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2302 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2305 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2309 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2310 SOC_LF_TIMER_CONTROL0_ADDRESS);
2311 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2312 SOC_LF_TIMER_CONTROL0_ADDRESS,
2313 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2316 static int ath10k_pci_warm_reset(struct ath10k *ar)
2320 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2322 spin_lock_bh(&ar->data_lock);
2323 ar->stats.fw_warm_reset_counter++;
2324 spin_unlock_bh(&ar->data_lock);
2326 ath10k_pci_irq_disable(ar);
2328 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2329 * were to access copy engine while host performs copy engine reset
2330 * then it is possible for the device to confuse pci-e controller to
2331 * the point of bringing host system to a complete stop (i.e. hang).
2333 ath10k_pci_warm_reset_si0(ar);
2334 ath10k_pci_warm_reset_cpu(ar);
2335 ath10k_pci_init_pipes(ar);
2336 ath10k_pci_wait_for_target_init(ar);
2338 ath10k_pci_warm_reset_clear_lf(ar);
2339 ath10k_pci_warm_reset_ce(ar);
2340 ath10k_pci_warm_reset_cpu(ar);
2341 ath10k_pci_init_pipes(ar);
2343 ret = ath10k_pci_wait_for_target_init(ar);
2345 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2349 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2354 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2356 ath10k_pci_irq_disable(ar);
2357 return ath10k_pci_qca99x0_chip_reset(ar);
2360 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2362 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2364 if (!ar_pci->pci_soft_reset)
2367 return ar_pci->pci_soft_reset(ar);
2370 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2375 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2377 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2378 * It is thus preferred to use warm reset which is safer but may not be
2379 * able to recover the device from all possible fail scenarios.
2381 * Warm reset doesn't always work on first try so attempt it a few
2382 * times before giving up.
2384 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2385 ret = ath10k_pci_warm_reset(ar);
2387 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2388 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2393 /* FIXME: Sometimes copy engine doesn't recover after warm
2394 * reset. In most cases this needs cold reset. In some of these
2395 * cases the device is in such a state that a cold reset may
2398 * Reading any host interest register via copy engine is
2399 * sufficient to verify if device is capable of booting
2402 ret = ath10k_pci_init_pipes(ar);
2404 ath10k_warn(ar, "failed to init copy engine: %d\n",
2409 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2412 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2417 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2421 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2422 ath10k_warn(ar, "refusing cold reset as requested\n");
2426 ret = ath10k_pci_cold_reset(ar);
2428 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2432 ret = ath10k_pci_wait_for_target_init(ar);
2434 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2439 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2444 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2448 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2450 /* FIXME: QCA6174 requires cold + warm reset to work. */
2452 ret = ath10k_pci_cold_reset(ar);
2454 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2458 ret = ath10k_pci_wait_for_target_init(ar);
2460 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2465 ret = ath10k_pci_warm_reset(ar);
2467 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2471 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2476 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2480 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2482 ret = ath10k_pci_cold_reset(ar);
2484 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2488 ret = ath10k_pci_wait_for_target_init(ar);
2490 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2495 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2500 static int ath10k_pci_chip_reset(struct ath10k *ar)
2502 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2504 if (WARN_ON(!ar_pci->pci_hard_reset))
2507 return ar_pci->pci_hard_reset(ar);
2510 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2512 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2515 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2517 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2519 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2520 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2523 * Bring the target up cleanly.
2525 * The target may be in an undefined state with an AUX-powered Target
2526 * and a Host in WoW mode. If the Host crashes, loses power, or is
2527 * restarted (without unloading the driver) then the Target is left
2528 * (aux) powered and running. On a subsequent driver load, the Target
2529 * is in an unexpected state. We try to catch that here in order to
2530 * reset the Target and retry the probe.
2532 ret = ath10k_pci_chip_reset(ar);
2534 if (ath10k_pci_has_fw_crashed(ar)) {
2535 ath10k_warn(ar, "firmware crashed during chip reset\n");
2536 ath10k_pci_fw_crashed_clear(ar);
2537 ath10k_pci_fw_crashed_dump(ar);
2540 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2544 ret = ath10k_pci_init_pipes(ar);
2546 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2550 ret = ath10k_pci_init_config(ar);
2552 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2556 ret = ath10k_pci_wake_target_cpu(ar);
2558 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2565 ath10k_pci_ce_deinit(ar);
2571 void ath10k_pci_hif_power_down(struct ath10k *ar)
2573 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2575 /* Currently hif_power_up performs effectively a reset and hif_stop
2576 * resets the chip as well so there's no point in resetting here.
2580 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2582 /* Nothing to do; the important stuff is in the driver suspend. */
2586 static int ath10k_pci_suspend(struct ath10k *ar)
2588 /* The grace timer can still be counting down and ar->ps_awake be true.
2589 * It is known that the device may be asleep after resuming regardless
2590 * of the SoC powersave state before suspending. Hence make sure the
2591 * device is asleep before proceeding.
2593 ath10k_pci_sleep_sync(ar);
2598 static int ath10k_pci_hif_resume(struct ath10k *ar)
2600 /* Nothing to do; the important stuff is in the driver resume. */
2604 static int ath10k_pci_resume(struct ath10k *ar)
2606 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2607 struct pci_dev *pdev = ar_pci->pdev;
2611 ret = ath10k_pci_force_wake(ar);
2613 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2617 /* Suspend/Resume resets the PCI configuration space, so we have to
2618 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2619 * from interfering with C3 CPU state. pci_restore_state won't help
2620 * here since it only restores the first 64 bytes pci config header.
2622 pci_read_config_dword(pdev, 0x40, &val);
2623 if ((val & 0x0000ff00) != 0)
2624 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2629 static bool ath10k_pci_validate_cal(void *data, size_t size)
2631 __le16 *cal_words = data;
2638 for (i = 0; i < size / 2; i++)
2639 checksum ^= le16_to_cpu(cal_words[i]);
2641 return checksum == 0xffff;
2644 static void ath10k_pci_enable_eeprom(struct ath10k *ar)
2646 /* Enable SI clock */
2647 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
2649 /* Configure GPIOs for I2C operation */
2650 ath10k_pci_write32(ar,
2651 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2652 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
2653 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
2655 SM(1, GPIO_PIN0_PAD_PULL));
2657 ath10k_pci_write32(ar,
2658 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2659 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
2660 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
2661 SM(1, GPIO_PIN0_PAD_PULL));
2663 ath10k_pci_write32(ar,
2665 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
2666 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
2668 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2669 ath10k_pci_write32(ar,
2670 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
2671 SM(1, SI_CONFIG_ERR_INT) |
2672 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
2673 SM(1, SI_CONFIG_I2C) |
2674 SM(1, SI_CONFIG_POS_SAMPLE) |
2675 SM(1, SI_CONFIG_INACTIVE_DATA) |
2676 SM(1, SI_CONFIG_INACTIVE_CLK) |
2677 SM(8, SI_CONFIG_DIVIDER));
2680 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
2685 /* set device select byte and for the read operation */
2686 reg = QCA9887_EEPROM_SELECT_READ |
2687 SM(addr, QCA9887_EEPROM_ADDR_LO) |
2688 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
2689 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
2691 /* write transmit data, transfer length, and START bit */
2692 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
2693 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
2694 SM(4, SI_CS_TX_CNT));
2696 /* wait max 1 sec */
2697 wait_limit = 100000;
2699 /* wait for SI_CS_DONE_INT */
2701 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
2702 if (MS(reg, SI_CS_DONE_INT))
2707 } while (wait_limit > 0);
2709 if (!MS(reg, SI_CS_DONE_INT)) {
2710 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
2715 /* clear SI_CS_DONE_INT */
2716 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
2718 if (MS(reg, SI_CS_DONE_ERR)) {
2719 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
2723 /* extract receive data */
2724 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
2730 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
2737 if (!QCA_REV_9887(ar))
2740 calsize = ar->hw_params.cal_data_len;
2741 caldata = kmalloc(calsize, GFP_KERNEL);
2745 ath10k_pci_enable_eeprom(ar);
2747 for (i = 0; i < calsize; i++) {
2748 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
2753 if (!ath10k_pci_validate_cal(caldata, calsize))
2757 *data_len = calsize;
2767 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2768 .tx_sg = ath10k_pci_hif_tx_sg,
2769 .diag_read = ath10k_pci_hif_diag_read,
2770 .diag_write = ath10k_pci_diag_write_mem,
2771 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2772 .start = ath10k_pci_hif_start,
2773 .stop = ath10k_pci_hif_stop,
2774 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2775 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2776 .send_complete_check = ath10k_pci_hif_send_complete_check,
2777 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2778 .power_up = ath10k_pci_hif_power_up,
2779 .power_down = ath10k_pci_hif_power_down,
2780 .read32 = ath10k_pci_read32,
2781 .write32 = ath10k_pci_write32,
2782 .suspend = ath10k_pci_hif_suspend,
2783 .resume = ath10k_pci_hif_resume,
2784 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
2788 * Top-level interrupt handler for all PCI interrupts from a Target.
2789 * When a block of MSI interrupts is allocated, this top-level handler
2790 * is not used; instead, we directly call the correct sub-handler.
2792 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2794 struct ath10k *ar = arg;
2795 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2798 if (ath10k_pci_has_device_gone(ar))
2801 ret = ath10k_pci_force_wake(ar);
2803 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
2807 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) &&
2808 !ath10k_pci_irq_pending(ar))
2811 ath10k_pci_disable_and_clear_legacy_irq(ar);
2812 ath10k_pci_irq_msi_fw_mask(ar);
2813 napi_schedule(&ar->napi);
2818 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
2820 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
2823 if (ath10k_pci_has_fw_crashed(ar)) {
2824 ath10k_pci_fw_crashed_clear(ar);
2825 ath10k_pci_fw_crashed_dump(ar);
2830 ath10k_ce_per_engine_service_any(ar);
2832 done = ath10k_htt_txrx_compl_task(ar, budget);
2834 if (done < budget) {
2835 napi_complete_done(ctx, done);
2836 /* In case of MSI, it is possible that interrupts are received
2837 * while NAPI poll is inprogress. So pending interrupts that are
2838 * received after processing all copy engine pipes by NAPI poll
2839 * will not be handled again. This is causing failure to
2840 * complete boot sequence in x86 platform. So before enabling
2841 * interrupts safer to check for pending interrupts for
2842 * immediate servicing.
2844 if (ath10k_ce_interrupt_summary(ar)) {
2845 napi_reschedule(ctx);
2848 ath10k_pci_enable_legacy_irq(ar);
2849 ath10k_pci_irq_msi_fw_unmask(ar);
2856 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2858 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2861 ret = request_irq(ar_pci->pdev->irq,
2862 ath10k_pci_interrupt_handler,
2863 IRQF_SHARED, "ath10k_pci", ar);
2865 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2866 ar_pci->pdev->irq, ret);
2873 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2875 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2878 ret = request_irq(ar_pci->pdev->irq,
2879 ath10k_pci_interrupt_handler,
2880 IRQF_SHARED, "ath10k_pci", ar);
2882 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2883 ar_pci->pdev->irq, ret);
2890 static int ath10k_pci_request_irq(struct ath10k *ar)
2892 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2894 switch (ar_pci->oper_irq_mode) {
2895 case ATH10K_PCI_IRQ_LEGACY:
2896 return ath10k_pci_request_irq_legacy(ar);
2897 case ATH10K_PCI_IRQ_MSI:
2898 return ath10k_pci_request_irq_msi(ar);
2904 static void ath10k_pci_free_irq(struct ath10k *ar)
2906 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2908 free_irq(ar_pci->pdev->irq, ar);
2911 void ath10k_pci_init_napi(struct ath10k *ar)
2913 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll,
2914 ATH10K_NAPI_BUDGET);
2917 static int ath10k_pci_init_irq(struct ath10k *ar)
2919 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2922 ath10k_pci_init_napi(ar);
2924 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2925 ath10k_info(ar, "limiting irq mode to: %d\n",
2926 ath10k_pci_irq_mode);
2929 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2930 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
2931 ret = pci_enable_msi(ar_pci->pdev);
2940 * A potential race occurs here: The CORE_BASE write
2941 * depends on target correctly decoding AXI address but
2942 * host won't know when target writes BAR to CORE_CTRL.
2943 * This write might get lost if target has NOT written BAR.
2944 * For now, fix the race by repeating the write in below
2945 * synchronization checking.
2947 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
2949 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2950 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2955 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2957 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2961 static int ath10k_pci_deinit_irq(struct ath10k *ar)
2963 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2965 switch (ar_pci->oper_irq_mode) {
2966 case ATH10K_PCI_IRQ_LEGACY:
2967 ath10k_pci_deinit_irq_legacy(ar);
2970 pci_disable_msi(ar_pci->pdev);
2977 int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2979 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2980 unsigned long timeout;
2983 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2985 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2988 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2990 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2993 /* target should never return this */
2994 if (val == 0xffffffff)
2997 /* the device has crashed so don't bother trying anymore */
2998 if (val & FW_IND_EVENT_PENDING)
3001 if (val & FW_IND_INITIALIZED)
3004 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
3005 /* Fix potential race by repeating CORE_BASE writes */
3006 ath10k_pci_enable_legacy_irq(ar);
3009 } while (time_before(jiffies, timeout));
3011 ath10k_pci_disable_and_clear_legacy_irq(ar);
3012 ath10k_pci_irq_msi_fw_mask(ar);
3014 if (val == 0xffffffff) {
3015 ath10k_err(ar, "failed to read device register, device is gone\n");
3019 if (val & FW_IND_EVENT_PENDING) {
3020 ath10k_warn(ar, "device has crashed during init\n");
3024 if (!(val & FW_IND_INITIALIZED)) {
3025 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3030 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3034 static int ath10k_pci_cold_reset(struct ath10k *ar)
3038 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3040 spin_lock_bh(&ar->data_lock);
3042 ar->stats.fw_cold_reset_counter++;
3044 spin_unlock_bh(&ar->data_lock);
3046 /* Put Target, including PCIe, into RESET. */
3047 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3049 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3051 /* After writing into SOC_GLOBAL_RESET to put device into
3052 * reset and pulling out of reset pcie may not be stable
3053 * for any immediate pcie register access and cause bus error,
3054 * add delay before any pcie access request to fix this issue.
3058 /* Pull Target, including PCIe, out of RESET. */
3060 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3064 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3069 static int ath10k_pci_claim(struct ath10k *ar)
3071 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3072 struct pci_dev *pdev = ar_pci->pdev;
3075 pci_set_drvdata(pdev, ar);
3077 ret = pci_enable_device(pdev);
3079 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3083 ret = pci_request_region(pdev, BAR_NUM, "ath");
3085 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3090 /* Target expects 32 bit DMA. Enforce it. */
3091 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3093 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3097 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3099 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
3104 pci_set_master(pdev);
3106 /* Arrange for access to Target SoC registers. */
3107 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3108 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3110 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3115 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem);
3119 pci_clear_master(pdev);
3122 pci_release_region(pdev, BAR_NUM);
3125 pci_disable_device(pdev);
3130 static void ath10k_pci_release(struct ath10k *ar)
3132 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3133 struct pci_dev *pdev = ar_pci->pdev;
3135 pci_iounmap(pdev, ar_pci->mem);
3136 pci_release_region(pdev, BAR_NUM);
3137 pci_clear_master(pdev);
3138 pci_disable_device(pdev);
3141 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3143 const struct ath10k_pci_supp_chip *supp_chip;
3145 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3147 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3148 supp_chip = &ath10k_pci_supp_chips[i];
3150 if (supp_chip->dev_id == dev_id &&
3151 supp_chip->rev_id == rev_id)
3158 int ath10k_pci_setup_resource(struct ath10k *ar)
3160 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3161 struct ath10k_ce *ce = ath10k_ce_priv(ar);
3164 spin_lock_init(&ce->ce_lock);
3165 spin_lock_init(&ar_pci->ps_lock);
3167 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
3170 if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3171 ath10k_pci_override_ce_config(ar);
3173 ret = ath10k_pci_alloc_pipes(ar);
3175 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3183 void ath10k_pci_release_resource(struct ath10k *ar)
3185 ath10k_pci_rx_retry_sync(ar);
3186 netif_napi_del(&ar->napi);
3187 ath10k_pci_ce_deinit(ar);
3188 ath10k_pci_free_pipes(ar);
3191 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3192 .read32 = ath10k_bus_pci_read32,
3193 .write32 = ath10k_bus_pci_write32,
3194 .get_num_banks = ath10k_pci_get_num_banks,
3197 static int ath10k_pci_probe(struct pci_dev *pdev,
3198 const struct pci_device_id *pci_dev)
3202 struct ath10k_pci *ar_pci;
3203 enum ath10k_hw_rev hw_rev;
3206 int (*pci_soft_reset)(struct ath10k *ar);
3207 int (*pci_hard_reset)(struct ath10k *ar);
3208 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3210 switch (pci_dev->device) {
3211 case QCA988X_2_0_DEVICE_ID:
3212 hw_rev = ATH10K_HW_QCA988X;
3214 pci_soft_reset = ath10k_pci_warm_reset;
3215 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3216 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3218 case QCA9887_1_0_DEVICE_ID:
3219 hw_rev = ATH10K_HW_QCA9887;
3221 pci_soft_reset = ath10k_pci_warm_reset;
3222 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3223 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3225 case QCA6164_2_1_DEVICE_ID:
3226 case QCA6174_2_1_DEVICE_ID:
3227 hw_rev = ATH10K_HW_QCA6174;
3229 pci_soft_reset = ath10k_pci_warm_reset;
3230 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3231 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3233 case QCA99X0_2_0_DEVICE_ID:
3234 hw_rev = ATH10K_HW_QCA99X0;
3236 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3237 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3238 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3240 case QCA9984_1_0_DEVICE_ID:
3241 hw_rev = ATH10K_HW_QCA9984;
3243 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3244 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3245 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3247 case QCA9888_2_0_DEVICE_ID:
3248 hw_rev = ATH10K_HW_QCA9888;
3250 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3251 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3252 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3254 case QCA9377_1_0_DEVICE_ID:
3255 hw_rev = ATH10K_HW_QCA9377;
3257 pci_soft_reset = NULL;
3258 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3259 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3266 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3267 hw_rev, &ath10k_pci_hif_ops);
3269 dev_err(&pdev->dev, "failed to allocate core\n");
3273 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3274 pdev->vendor, pdev->device,
3275 pdev->subsystem_vendor, pdev->subsystem_device);
3277 ar_pci = ath10k_pci_priv(ar);
3278 ar_pci->pdev = pdev;
3279 ar_pci->dev = &pdev->dev;
3281 ar->dev_id = pci_dev->device;
3282 ar_pci->pci_ps = pci_ps;
3283 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3284 ar_pci->pci_soft_reset = pci_soft_reset;
3285 ar_pci->pci_hard_reset = pci_hard_reset;
3286 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3287 ar->ce_priv = &ar_pci->ce;
3289 ar->id.vendor = pdev->vendor;
3290 ar->id.device = pdev->device;
3291 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3292 ar->id.subsystem_device = pdev->subsystem_device;
3294 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
3297 ret = ath10k_pci_setup_resource(ar);
3299 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3300 goto err_core_destroy;
3303 ret = ath10k_pci_claim(ar);
3305 ath10k_err(ar, "failed to claim device: %d\n", ret);
3306 goto err_free_pipes;
3309 ret = ath10k_pci_force_wake(ar);
3311 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3315 ath10k_pci_ce_deinit(ar);
3316 ath10k_pci_irq_disable(ar);
3318 ret = ath10k_pci_init_irq(ar);
3320 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3324 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3325 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3326 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3328 ret = ath10k_pci_request_irq(ar);
3330 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3331 goto err_deinit_irq;
3334 ret = ath10k_pci_chip_reset(ar);
3336 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3340 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3341 if (chip_id == 0xffffffff) {
3342 ath10k_err(ar, "failed to get chip id\n");
3346 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3347 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3348 pdev->device, chip_id);
3352 ret = ath10k_core_register(ar, chip_id);
3354 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3361 ath10k_pci_free_irq(ar);
3362 ath10k_pci_rx_retry_sync(ar);
3365 ath10k_pci_deinit_irq(ar);
3368 ath10k_pci_sleep_sync(ar);
3369 ath10k_pci_release(ar);
3372 ath10k_pci_free_pipes(ar);
3375 ath10k_core_destroy(ar);
3380 static void ath10k_pci_remove(struct pci_dev *pdev)
3382 struct ath10k *ar = pci_get_drvdata(pdev);
3383 struct ath10k_pci *ar_pci;
3385 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3390 ar_pci = ath10k_pci_priv(ar);
3395 ath10k_core_unregister(ar);
3396 ath10k_pci_free_irq(ar);
3397 ath10k_pci_deinit_irq(ar);
3398 ath10k_pci_release_resource(ar);
3399 ath10k_pci_sleep_sync(ar);
3400 ath10k_pci_release(ar);
3401 ath10k_core_destroy(ar);
3404 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3406 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
3408 struct ath10k *ar = dev_get_drvdata(dev);
3411 ret = ath10k_pci_suspend(ar);
3413 ath10k_warn(ar, "failed to suspend hif: %d\n", ret);
3418 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
3420 struct ath10k *ar = dev_get_drvdata(dev);
3423 ret = ath10k_pci_resume(ar);
3425 ath10k_warn(ar, "failed to resume hif: %d\n", ret);
3430 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
3431 ath10k_pci_pm_suspend,
3432 ath10k_pci_pm_resume);
3434 static struct pci_driver ath10k_pci_driver = {
3435 .name = "ath10k_pci",
3436 .id_table = ath10k_pci_id_table,
3437 .probe = ath10k_pci_probe,
3438 .remove = ath10k_pci_remove,
3440 .driver.pm = &ath10k_pci_pm_ops,
3444 static int __init ath10k_pci_init(void)
3448 ret = pci_register_driver(&ath10k_pci_driver);
3450 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3453 ret = ath10k_ahb_init();
3455 printk(KERN_ERR "ahb init failed: %d\n", ret);
3459 module_init(ath10k_pci_init);
3461 static void __exit ath10k_pci_exit(void)
3463 pci_unregister_driver(&ath10k_pci_driver);
3467 module_exit(ath10k_pci_exit);
3469 MODULE_AUTHOR("Qualcomm Atheros");
3470 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3471 MODULE_LICENSE("Dual BSD/GPL");
3473 /* QCA988x 2.0 firmware files */
3476 /* QCA9887 1.0 firmware files */
3479 /* QCA6174 2.1 firmware files */
3482 /* QCA6174 3.1 firmware files */
3485 /* QCA9377 1.0 firmware files */