1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <linux/etherdevice.h>
15 static u8 ath10k_htt_tx_txq_calc_size(size_t count)
23 while (factor >= 64 && exp < 4) {
32 factor = max(1, factor);
34 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) |
35 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR);
38 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
39 struct ieee80211_txq *txq)
41 struct ath10k *ar = hw->priv;
42 struct ath10k_sta *arsta;
43 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv;
44 unsigned long byte_cnt;
51 lockdep_assert_held(&ar->htt.tx_lock);
53 if (!ar->htt.tx_q_state.enabled)
56 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
60 arsta = (void *)txq->sta->drv_priv;
61 peer_id = arsta->peer_id;
63 peer_id = arvif->peer_id;
67 bit = BIT(peer_id % 32);
70 ieee80211_txq_get_depth(txq, NULL, &byte_cnt);
71 count = ath10k_htt_tx_txq_calc_size(byte_cnt);
73 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) ||
74 unlikely(tid >= ar->htt.tx_q_state.num_tids)) {
75 ath10k_warn(ar, "refusing to update txq for peer_id %u tid %u due to out of bounds\n",
80 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count;
81 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit;
82 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0;
84 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %u tid %u count %u\n",
88 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar)
93 lockdep_assert_held(&ar->htt.tx_lock);
95 if (!ar->htt.tx_q_state.enabled)
98 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
101 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq);
103 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq);
105 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n",
108 size = sizeof(*ar->htt.tx_q_state.vaddr);
109 dma_sync_single_for_device(ar->dev,
110 ar->htt.tx_q_state.paddr,
115 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
116 struct ieee80211_txq *txq)
118 struct ath10k *ar = hw->priv;
120 spin_lock_bh(&ar->htt.tx_lock);
121 __ath10k_htt_tx_txq_recalc(hw, txq);
122 spin_unlock_bh(&ar->htt.tx_lock);
125 void ath10k_htt_tx_txq_sync(struct ath10k *ar)
127 spin_lock_bh(&ar->htt.tx_lock);
128 __ath10k_htt_tx_txq_sync(ar);
129 spin_unlock_bh(&ar->htt.tx_lock);
132 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
133 struct ieee80211_txq *txq)
135 struct ath10k *ar = hw->priv;
137 spin_lock_bh(&ar->htt.tx_lock);
138 __ath10k_htt_tx_txq_recalc(hw, txq);
139 __ath10k_htt_tx_txq_sync(ar);
140 spin_unlock_bh(&ar->htt.tx_lock);
143 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
145 lockdep_assert_held(&htt->tx_lock);
147 htt->num_pending_tx--;
148 if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
149 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
151 if (htt->num_pending_tx == 0)
152 wake_up(&htt->empty_tx_wq);
155 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
157 lockdep_assert_held(&htt->tx_lock);
159 if (htt->num_pending_tx >= htt->max_num_pending_tx)
162 htt->num_pending_tx++;
163 if (htt->num_pending_tx == htt->max_num_pending_tx)
164 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
169 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
172 struct ath10k *ar = htt->ar;
174 lockdep_assert_held(&htt->tx_lock);
176 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres)
180 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx)
183 htt->num_pending_mgmt_tx++;
188 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt)
190 lockdep_assert_held(&htt->tx_lock);
192 if (!htt->ar->hw_params.max_probe_resp_desc_thres)
195 htt->num_pending_mgmt_tx--;
198 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb)
200 struct ath10k *ar = htt->ar;
203 spin_lock_bh(&htt->tx_lock);
204 ret = idr_alloc(&htt->pending_tx, skb, 0,
205 htt->max_num_pending_tx, GFP_ATOMIC);
206 spin_unlock_bh(&htt->tx_lock);
208 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);
213 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
215 struct ath10k *ar = htt->ar;
217 lockdep_assert_held(&htt->tx_lock);
219 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %u\n", msdu_id);
221 idr_remove(&htt->pending_tx, msdu_id);
224 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt)
226 struct ath10k *ar = htt->ar;
229 if (!htt->txbuf.vaddr_txbuff_32)
232 size = htt->txbuf.size;
233 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32,
235 htt->txbuf.vaddr_txbuff_32 = NULL;
238 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt)
240 struct ath10k *ar = htt->ar;
243 size = htt->max_num_pending_tx *
244 sizeof(struct ath10k_htt_txbuf_32);
246 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size,
249 if (!htt->txbuf.vaddr_txbuff_32)
252 htt->txbuf.size = size;
257 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt)
259 struct ath10k *ar = htt->ar;
262 if (!htt->txbuf.vaddr_txbuff_64)
265 size = htt->txbuf.size;
266 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64,
268 htt->txbuf.vaddr_txbuff_64 = NULL;
271 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt)
273 struct ath10k *ar = htt->ar;
276 size = htt->max_num_pending_tx *
277 sizeof(struct ath10k_htt_txbuf_64);
279 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size,
282 if (!htt->txbuf.vaddr_txbuff_64)
285 htt->txbuf.size = size;
290 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt)
294 if (!htt->frag_desc.vaddr_desc_32)
297 size = htt->max_num_pending_tx *
298 sizeof(struct htt_msdu_ext_desc);
300 dma_free_coherent(htt->ar->dev,
302 htt->frag_desc.vaddr_desc_32,
303 htt->frag_desc.paddr);
305 htt->frag_desc.vaddr_desc_32 = NULL;
308 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt)
310 struct ath10k *ar = htt->ar;
313 if (!ar->hw_params.continuous_frag_desc)
316 size = htt->max_num_pending_tx *
317 sizeof(struct htt_msdu_ext_desc);
318 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size,
319 &htt->frag_desc.paddr,
321 if (!htt->frag_desc.vaddr_desc_32) {
322 ath10k_err(ar, "failed to alloc fragment desc memory\n");
325 htt->frag_desc.size = size;
330 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt)
334 if (!htt->frag_desc.vaddr_desc_64)
337 size = htt->max_num_pending_tx *
338 sizeof(struct htt_msdu_ext_desc_64);
340 dma_free_coherent(htt->ar->dev,
342 htt->frag_desc.vaddr_desc_64,
343 htt->frag_desc.paddr);
345 htt->frag_desc.vaddr_desc_64 = NULL;
348 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt)
350 struct ath10k *ar = htt->ar;
353 if (!ar->hw_params.continuous_frag_desc)
356 size = htt->max_num_pending_tx *
357 sizeof(struct htt_msdu_ext_desc_64);
359 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size,
360 &htt->frag_desc.paddr,
362 if (!htt->frag_desc.vaddr_desc_64) {
363 ath10k_err(ar, "failed to alloc fragment desc memory\n");
366 htt->frag_desc.size = size;
371 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt)
373 struct ath10k *ar = htt->ar;
376 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
377 ar->running_fw->fw_file.fw_features))
380 size = sizeof(*htt->tx_q_state.vaddr);
382 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE);
383 kfree(htt->tx_q_state.vaddr);
386 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt)
388 struct ath10k *ar = htt->ar;
392 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
393 ar->running_fw->fw_file.fw_features))
396 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS;
397 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS;
398 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES;
400 size = sizeof(*htt->tx_q_state.vaddr);
401 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL);
402 if (!htt->tx_q_state.vaddr)
405 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr,
406 size, DMA_TO_DEVICE);
407 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr);
409 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret);
410 kfree(htt->tx_q_state.vaddr);
417 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt)
419 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo));
420 kfifo_free(&htt->txdone_fifo);
423 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt)
428 size = roundup_pow_of_two(htt->max_num_pending_tx);
429 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL);
433 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt)
435 struct ath10k *ar = htt->ar;
438 ret = ath10k_htt_alloc_txbuff(htt);
440 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret);
444 ret = ath10k_htt_alloc_frag_desc(htt);
446 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret);
450 ret = ath10k_htt_tx_alloc_txq(htt);
452 ath10k_err(ar, "failed to alloc txq: %d\n", ret);
456 ret = ath10k_htt_tx_alloc_txdone_fifo(htt);
458 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret);
465 ath10k_htt_tx_free_txq(htt);
468 ath10k_htt_free_frag_desc(htt);
471 ath10k_htt_free_txbuff(htt);
476 int ath10k_htt_tx_start(struct ath10k_htt *htt)
478 struct ath10k *ar = htt->ar;
481 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
482 htt->max_num_pending_tx);
484 spin_lock_init(&htt->tx_lock);
485 idr_init(&htt->pending_tx);
487 if (htt->tx_mem_allocated)
490 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
493 ret = ath10k_htt_tx_alloc_buf(htt);
495 goto free_idr_pending_tx;
497 htt->tx_mem_allocated = true;
502 idr_destroy(&htt->pending_tx);
507 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx)
509 struct ath10k *ar = ctx;
510 struct ath10k_htt *htt = &ar->htt;
511 struct htt_tx_done tx_done = {0};
513 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %u\n", msdu_id);
515 tx_done.msdu_id = msdu_id;
516 tx_done.status = HTT_TX_COMPL_STATE_DISCARD;
518 ath10k_txrx_tx_unref(htt, &tx_done);
523 void ath10k_htt_tx_destroy(struct ath10k_htt *htt)
525 if (!htt->tx_mem_allocated)
528 ath10k_htt_free_txbuff(htt);
529 ath10k_htt_tx_free_txq(htt);
530 ath10k_htt_free_frag_desc(htt);
531 ath10k_htt_tx_free_txdone_fifo(htt);
532 htt->tx_mem_allocated = false;
535 static void ath10k_htt_flush_tx_queue(struct ath10k_htt *htt)
537 ath10k_htc_stop_hl(htt->ar);
538 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
541 void ath10k_htt_tx_stop(struct ath10k_htt *htt)
543 ath10k_htt_flush_tx_queue(htt);
544 idr_destroy(&htt->pending_tx);
547 void ath10k_htt_tx_free(struct ath10k_htt *htt)
549 ath10k_htt_tx_stop(htt);
550 ath10k_htt_tx_destroy(htt);
553 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar)
555 queue_work(ar->workqueue, &ar->bundle_tx_work);
558 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
560 struct ath10k_htt *htt = &ar->htt;
561 struct htt_tx_done tx_done = {0};
562 struct htt_cmd_hdr *htt_hdr;
563 struct htt_data_tx_desc *desc_hdr = NULL;
567 if (htt->disable_tx_comp) {
568 htt_hdr = (struct htt_cmd_hdr *)skb->data;
569 msg_type = htt_hdr->msg_type;
571 if (msg_type == HTT_H2T_MSG_TYPE_TX_FRM) {
572 desc_hdr = (struct htt_data_tx_desc *)
573 (skb->data + sizeof(*htt_hdr));
574 flags1 = __le16_to_cpu(desc_hdr->flags1);
575 skb_pull(skb, sizeof(struct htt_cmd_hdr));
576 skb_pull(skb, sizeof(struct htt_data_tx_desc));
580 dev_kfree_skb_any(skb);
582 if ((!htt->disable_tx_comp) || (msg_type != HTT_H2T_MSG_TYPE_TX_FRM))
585 ath10k_dbg(ar, ATH10K_DBG_HTT,
586 "htt tx complete msdu id:%u ,flags1:%x\n",
587 __le16_to_cpu(desc_hdr->id), flags1);
589 if (flags1 & HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE)
592 tx_done.status = HTT_TX_COMPL_STATE_ACK;
593 tx_done.msdu_id = __le16_to_cpu(desc_hdr->id);
594 ath10k_txrx_tx_unref(&ar->htt, &tx_done);
597 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb)
599 dev_kfree_skb_any(skb);
601 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete);
603 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
605 struct ath10k *ar = htt->ar;
611 len += sizeof(cmd->hdr);
612 len += sizeof(cmd->ver_req);
614 skb = ath10k_htc_alloc_skb(ar, len);
619 cmd = (struct htt_cmd *)skb->data;
620 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
622 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
624 dev_kfree_skb_any(skb);
631 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask,
634 struct ath10k *ar = htt->ar;
635 struct htt_stats_req *req;
640 len += sizeof(cmd->hdr);
641 len += sizeof(cmd->stats_req);
643 skb = ath10k_htc_alloc_skb(ar, len);
648 cmd = (struct htt_cmd *)skb->data;
649 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
651 req = &cmd->stats_req;
653 memset(req, 0, sizeof(*req));
655 /* currently we support only max 24 bit masks so no need to worry
656 * about endian support
658 memcpy(req->upload_types, &mask, 3);
659 memcpy(req->reset_types, &reset_mask, 3);
660 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
661 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
662 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
664 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
666 ath10k_warn(ar, "failed to send htt type stats request: %d",
668 dev_kfree_skb_any(skb);
675 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt)
677 struct ath10k *ar = htt->ar;
680 struct htt_frag_desc_bank_cfg32 *cfg;
684 if (!ar->hw_params.continuous_frag_desc)
687 if (!htt->frag_desc.paddr) {
688 ath10k_warn(ar, "invalid frag desc memory\n");
692 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32);
693 skb = ath10k_htc_alloc_skb(ar, size);
698 cmd = (struct htt_cmd *)skb->data;
699 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;
702 info |= SM(htt->tx_q_state.type,
703 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE);
705 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
706 ar->running_fw->fw_file.fw_features))
707 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;
709 cfg = &cmd->frag_desc_bank_cfg32;
712 cfg->desc_size = sizeof(struct htt_msdu_ext_desc);
713 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr);
714 cfg->bank_id[0].bank_min_id = 0;
715 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx -
718 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr);
719 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers);
720 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids);
721 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE;
722 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER;
724 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n");
726 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
728 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",
730 dev_kfree_skb_any(skb);
737 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt)
739 struct ath10k *ar = htt->ar;
742 struct htt_frag_desc_bank_cfg64 *cfg;
746 if (!ar->hw_params.continuous_frag_desc)
749 if (!htt->frag_desc.paddr) {
750 ath10k_warn(ar, "invalid frag desc memory\n");
754 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64);
755 skb = ath10k_htc_alloc_skb(ar, size);
760 cmd = (struct htt_cmd *)skb->data;
761 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;
764 info |= SM(htt->tx_q_state.type,
765 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE);
767 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
768 ar->running_fw->fw_file.fw_features))
769 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;
771 cfg = &cmd->frag_desc_bank_cfg64;
774 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64);
775 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr);
776 cfg->bank_id[0].bank_min_id = 0;
777 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx -
780 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr);
781 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers);
782 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids);
783 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE;
784 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER;
786 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n");
788 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
790 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",
792 dev_kfree_skb_any(skb);
799 static void ath10k_htt_fill_rx_desc_offset_32(struct ath10k_hw_params *hw,
800 struct htt_rx_ring_setup_ring32 *rx_ring)
802 ath10k_htt_rx_desc_get_offsets(hw, &rx_ring->offsets);
805 static void ath10k_htt_fill_rx_desc_offset_64(struct ath10k_hw_params *hw,
806 struct htt_rx_ring_setup_ring64 *rx_ring)
808 ath10k_htt_rx_desc_get_offsets(hw, &rx_ring->offsets);
811 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt)
813 struct ath10k *ar = htt->ar;
814 struct ath10k_hw_params *hw = &ar->hw_params;
817 struct htt_rx_ring_setup_ring32 *ring;
818 const int num_rx_ring = 1;
825 * the HW expects the buffer to be an integral number of 4-byte
828 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
829 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
831 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr)
832 + (sizeof(*ring) * num_rx_ring);
833 skb = ath10k_htc_alloc_skb(ar, len);
839 cmd = (struct htt_cmd *)skb->data;
840 ring = &cmd->rx_setup_32.rings[0];
842 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
843 cmd->rx_setup_32.hdr.num_rings = 1;
845 /* FIXME: do we need all of this? */
847 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
848 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
849 flags |= HTT_RX_RING_FLAGS_PPDU_START;
850 flags |= HTT_RX_RING_FLAGS_PPDU_END;
851 flags |= HTT_RX_RING_FLAGS_MPDU_START;
852 flags |= HTT_RX_RING_FLAGS_MPDU_END;
853 flags |= HTT_RX_RING_FLAGS_MSDU_START;
854 flags |= HTT_RX_RING_FLAGS_MSDU_END;
855 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
856 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
857 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
858 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
859 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
860 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
861 flags |= HTT_RX_RING_FLAGS_NULL_RX;
862 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
864 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
866 ring->fw_idx_shadow_reg_paddr =
867 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
868 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
869 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
870 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
871 ring->flags = __cpu_to_le16(flags);
872 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
874 ath10k_htt_fill_rx_desc_offset_32(hw, ring);
875 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
877 dev_kfree_skb_any(skb);
884 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt)
886 struct ath10k *ar = htt->ar;
887 struct ath10k_hw_params *hw = &ar->hw_params;
890 struct htt_rx_ring_setup_ring64 *ring;
891 const int num_rx_ring = 1;
897 /* HW expects the buffer to be an integral number of 4-byte
900 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
901 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
903 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr)
904 + (sizeof(*ring) * num_rx_ring);
905 skb = ath10k_htc_alloc_skb(ar, len);
911 cmd = (struct htt_cmd *)skb->data;
912 ring = &cmd->rx_setup_64.rings[0];
914 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
915 cmd->rx_setup_64.hdr.num_rings = 1;
918 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
919 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
920 flags |= HTT_RX_RING_FLAGS_PPDU_START;
921 flags |= HTT_RX_RING_FLAGS_PPDU_END;
922 flags |= HTT_RX_RING_FLAGS_MPDU_START;
923 flags |= HTT_RX_RING_FLAGS_MPDU_END;
924 flags |= HTT_RX_RING_FLAGS_MSDU_START;
925 flags |= HTT_RX_RING_FLAGS_MSDU_END;
926 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
927 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
928 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
929 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
930 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
931 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
932 flags |= HTT_RX_RING_FLAGS_NULL_RX;
933 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
935 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
937 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr);
938 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr);
939 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
940 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
941 ring->flags = __cpu_to_le16(flags);
942 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
944 ath10k_htt_fill_rx_desc_offset_64(hw, ring);
945 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
947 dev_kfree_skb_any(skb);
954 static int ath10k_htt_send_rx_ring_cfg_hl(struct ath10k_htt *htt)
956 struct ath10k *ar = htt->ar;
959 struct htt_rx_ring_setup_ring32 *ring;
960 const int num_rx_ring = 1;
966 * the HW expects the buffer to be an integral number of 4-byte
969 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
970 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
972 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr)
973 + (sizeof(*ring) * num_rx_ring);
974 skb = ath10k_htc_alloc_skb(ar, len);
980 cmd = (struct htt_cmd *)skb->data;
981 ring = &cmd->rx_setup_32.rings[0];
983 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
984 cmd->rx_setup_32.hdr.num_rings = 1;
987 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
988 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
989 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
991 memset(ring, 0, sizeof(*ring));
992 ring->rx_ring_len = __cpu_to_le16(HTT_RX_RING_SIZE_MIN);
993 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
994 ring->flags = __cpu_to_le16(flags);
996 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
998 dev_kfree_skb_any(skb);
1005 static int ath10k_htt_h2t_aggr_cfg_msg_32(struct ath10k_htt *htt,
1006 u8 max_subfrms_ampdu,
1007 u8 max_subfrms_amsdu)
1009 struct ath10k *ar = htt->ar;
1010 struct htt_aggr_conf *aggr_conf;
1011 struct sk_buff *skb;
1012 struct htt_cmd *cmd;
1016 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
1018 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
1021 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
1024 len = sizeof(cmd->hdr);
1025 len += sizeof(cmd->aggr_conf);
1027 skb = ath10k_htc_alloc_skb(ar, len);
1032 cmd = (struct htt_cmd *)skb->data;
1033 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
1035 aggr_conf = &cmd->aggr_conf;
1036 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
1037 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
1039 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
1040 aggr_conf->max_num_amsdu_subframes,
1041 aggr_conf->max_num_ampdu_subframes);
1043 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
1045 dev_kfree_skb_any(skb);
1052 static int ath10k_htt_h2t_aggr_cfg_msg_v2(struct ath10k_htt *htt,
1053 u8 max_subfrms_ampdu,
1054 u8 max_subfrms_amsdu)
1056 struct ath10k *ar = htt->ar;
1057 struct htt_aggr_conf_v2 *aggr_conf;
1058 struct sk_buff *skb;
1059 struct htt_cmd *cmd;
1063 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
1065 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
1068 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
1071 len = sizeof(cmd->hdr);
1072 len += sizeof(cmd->aggr_conf_v2);
1074 skb = ath10k_htc_alloc_skb(ar, len);
1079 cmd = (struct htt_cmd *)skb->data;
1080 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
1082 aggr_conf = &cmd->aggr_conf_v2;
1083 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
1084 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
1086 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
1087 aggr_conf->max_num_amsdu_subframes,
1088 aggr_conf->max_num_ampdu_subframes);
1090 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
1092 dev_kfree_skb_any(skb);
1099 int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
1101 __le16 fetch_seq_num,
1102 struct htt_tx_fetch_record *records,
1105 struct sk_buff *skb;
1106 struct htt_cmd *cmd;
1107 const u16 resp_id = 0;
1111 /* Response IDs are echo-ed back only for host driver convenience
1112 * purposes. They aren't used for anything in the driver yet so use 0.
1115 len += sizeof(cmd->hdr);
1116 len += sizeof(cmd->tx_fetch_resp);
1117 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records;
1119 skb = ath10k_htc_alloc_skb(ar, len);
1124 cmd = (struct htt_cmd *)skb->data;
1125 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP;
1126 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id);
1127 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num;
1128 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records);
1129 cmd->tx_fetch_resp.token = token;
1131 memcpy(cmd->tx_fetch_resp.records, records,
1132 sizeof(records[0]) * num_records);
1134 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb);
1136 ath10k_warn(ar, "failed to submit htc command: %d\n", ret);
1143 dev_kfree_skb_any(skb);
1148 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb)
1150 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1151 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
1152 struct ath10k_vif *arvif;
1154 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) {
1155 return ar->scan.vdev_id;
1156 } else if (cb->vif) {
1157 arvif = (void *)cb->vif->drv_priv;
1158 return arvif->vdev_id;
1159 } else if (ar->monitor_started) {
1160 return ar->monitor_vdev_id;
1166 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth)
1168 struct ieee80211_hdr *hdr = (void *)skb->data;
1169 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
1171 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control))
1172 return HTT_DATA_TX_EXT_TID_MGMT;
1173 else if (cb->flags & ATH10K_SKB_F_QOS)
1174 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
1176 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST;
1179 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
1181 struct ath10k *ar = htt->ar;
1182 struct device *dev = ar->dev;
1183 struct sk_buff *txdesc = NULL;
1184 struct htt_cmd *cmd;
1185 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
1186 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
1190 const u8 *peer_addr;
1191 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
1193 len += sizeof(cmd->hdr);
1194 len += sizeof(cmd->mgmt_tx);
1196 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
1202 if ((ieee80211_is_action(hdr->frame_control) ||
1203 ieee80211_is_deauth(hdr->frame_control) ||
1204 ieee80211_is_disassoc(hdr->frame_control)) &&
1205 ieee80211_has_protected(hdr->frame_control)) {
1206 peer_addr = hdr->addr1;
1207 if (is_multicast_ether_addr(peer_addr)) {
1208 skb_put(msdu, sizeof(struct ieee80211_mmie_16));
1210 if (skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP ||
1211 skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP_256)
1212 skb_put(msdu, IEEE80211_GCMP_MIC_LEN);
1214 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1218 txdesc = ath10k_htc_alloc_skb(ar, len);
1221 goto err_free_msdu_id;
1224 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
1226 res = dma_mapping_error(dev, skb_cb->paddr);
1229 goto err_free_txdesc;
1232 skb_put(txdesc, len);
1233 cmd = (struct htt_cmd *)txdesc->data;
1234 memset(cmd, 0, len);
1236 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
1237 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
1238 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
1239 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
1240 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
1241 memcpy(cmd->mgmt_tx.hdr, msdu->data,
1242 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
1244 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
1246 goto err_unmap_msdu;
1251 if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL)
1252 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1254 dev_kfree_skb_any(txdesc);
1256 spin_lock_bh(&htt->tx_lock);
1257 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
1258 spin_unlock_bh(&htt->tx_lock);
1263 #define HTT_TX_HL_NEEDED_HEADROOM \
1264 (unsigned int)(sizeof(struct htt_cmd_hdr) + \
1265 sizeof(struct htt_data_tx_desc) + \
1266 sizeof(struct ath10k_htc_hdr))
1268 static int ath10k_htt_tx_hl(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
1269 struct sk_buff *msdu)
1271 struct ath10k *ar = htt->ar;
1273 struct htt_cmd_hdr *cmd_hdr;
1274 struct htt_data_tx_desc *tx_desc;
1275 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
1276 struct sk_buff *tmp_skb;
1277 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
1278 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
1279 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
1285 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
1287 if ((ieee80211_is_action(hdr->frame_control) ||
1288 ieee80211_is_deauth(hdr->frame_control) ||
1289 ieee80211_is_disassoc(hdr->frame_control)) &&
1290 ieee80211_has_protected(hdr->frame_control)) {
1291 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1295 data_len = msdu->len;
1298 case ATH10K_HW_TXRX_RAW:
1299 case ATH10K_HW_TXRX_NATIVE_WIFI:
1300 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1302 case ATH10K_HW_TXRX_ETHERNET:
1303 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1305 case ATH10K_HW_TXRX_MGMT:
1306 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
1307 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1308 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1310 if (htt->disable_tx_comp)
1311 flags1 |= HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE;
1315 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
1316 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
1318 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
1319 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
1320 if (msdu->ip_summed == CHECKSUM_PARTIAL &&
1321 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
1322 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
1323 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
1326 /* Prepend the HTT header and TX desc struct to the data message
1327 * and realloc the skb if it does not have enough headroom.
1329 if (skb_headroom(msdu) < HTT_TX_HL_NEEDED_HEADROOM) {
1332 ath10k_dbg(htt->ar, ATH10K_DBG_HTT,
1333 "Not enough headroom in skb. Current headroom: %u, needed: %u. Reallocating...\n",
1334 skb_headroom(msdu), HTT_TX_HL_NEEDED_HEADROOM);
1335 msdu = skb_realloc_headroom(msdu, HTT_TX_HL_NEEDED_HEADROOM);
1338 ath10k_warn(htt->ar, "htt hl tx: Unable to realloc skb!\n");
1344 if (ar->bus_param.hl_msdu_ids) {
1345 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
1346 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
1348 ath10k_err(ar, "msdu_id allocation failed %d\n", res);
1354 /* As msdu is freed by mac80211 (in ieee80211_tx_status()) and by
1355 * ath10k (in ath10k_htt_htc_tx_complete()) we have to increase
1356 * reference by one to avoid a use-after-free case and a double
1361 skb_push(msdu, sizeof(*cmd_hdr));
1362 skb_push(msdu, sizeof(*tx_desc));
1363 cmd_hdr = (struct htt_cmd_hdr *)msdu->data;
1364 tx_desc = (struct htt_data_tx_desc *)(msdu->data + sizeof(*cmd_hdr));
1366 cmd_hdr->msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
1367 tx_desc->flags0 = flags0;
1368 tx_desc->flags1 = __cpu_to_le16(flags1);
1369 tx_desc->len = __cpu_to_le16(data_len);
1370 tx_desc->id = __cpu_to_le16(msdu_id);
1371 tx_desc->frags_paddr = 0; /* always zero */
1372 /* Initialize peer_id to INVALID_PEER because this is NOT
1375 tx_desc->peerid = __cpu_to_le32(HTT_INVALID_PEERID);
1377 res = ath10k_htc_send_hl(&htt->ar->htc, htt->eid, msdu);
1383 static int ath10k_htt_tx_32(struct ath10k_htt *htt,
1384 enum ath10k_hw_txrx_mode txmode,
1385 struct sk_buff *msdu)
1387 struct ath10k *ar = htt->ar;
1388 struct device *dev = ar->dev;
1389 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
1390 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
1391 struct ath10k_hif_sg_item sg_items[2];
1392 struct ath10k_htt_txbuf_32 *txbuf;
1393 struct htt_data_tx_desc_frag *frags;
1394 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
1395 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
1396 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
1400 u16 msdu_id, flags1 = 0;
1402 u32 frags_paddr = 0;
1404 struct htt_msdu_ext_desc *ext_desc = NULL;
1405 struct htt_msdu_ext_desc *ext_desc_t = NULL;
1407 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
1413 prefetch_len = min(htt->prefetch_len, msdu->len);
1414 prefetch_len = roundup(prefetch_len, 4);
1416 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id;
1417 txbuf_paddr = htt->txbuf.paddr +
1418 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id);
1421 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
1423 if ((ieee80211_is_action(hdr->frame_control) ||
1424 ieee80211_is_deauth(hdr->frame_control) ||
1425 ieee80211_is_disassoc(hdr->frame_control)) &&
1426 ieee80211_has_protected(hdr->frame_control)) {
1427 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1428 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) &&
1429 txmode == ATH10K_HW_TXRX_RAW &&
1430 ieee80211_has_protected(hdr->frame_control)) {
1431 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1435 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
1437 res = dma_mapping_error(dev, skb_cb->paddr);
1440 goto err_free_msdu_id;
1443 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))
1444 freq = ar->scan.roc_freq;
1447 case ATH10K_HW_TXRX_RAW:
1448 case ATH10K_HW_TXRX_NATIVE_WIFI:
1449 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1451 case ATH10K_HW_TXRX_ETHERNET:
1452 if (ar->hw_params.continuous_frag_desc) {
1453 ext_desc_t = htt->frag_desc.vaddr_desc_32;
1454 memset(&ext_desc_t[msdu_id], 0,
1455 sizeof(struct htt_msdu_ext_desc));
1456 frags = (struct htt_data_tx_desc_frag *)
1457 &ext_desc_t[msdu_id].frags;
1458 ext_desc = &ext_desc_t[msdu_id];
1459 frags[0].tword_addr.paddr_lo =
1460 __cpu_to_le32(skb_cb->paddr);
1461 frags[0].tword_addr.paddr_hi = 0;
1462 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
1464 frags_paddr = htt->frag_desc.paddr +
1465 (sizeof(struct htt_msdu_ext_desc) * msdu_id);
1467 frags = txbuf->frags;
1468 frags[0].dword_addr.paddr =
1469 __cpu_to_le32(skb_cb->paddr);
1470 frags[0].dword_addr.len = __cpu_to_le32(msdu->len);
1471 frags[1].dword_addr.paddr = 0;
1472 frags[1].dword_addr.len = 0;
1474 frags_paddr = txbuf_paddr;
1476 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1478 case ATH10K_HW_TXRX_MGMT:
1479 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
1480 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1481 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1483 frags_paddr = skb_cb->paddr;
1487 /* Normally all commands go through HTC which manages tx credits for
1488 * each endpoint and notifies when tx is completed.
1490 * HTT endpoint is creditless so there's no need to care about HTC
1491 * flags. In that case it is trivial to fill the HTC header here.
1493 * MSDU transmission is considered completed upon HTT event. This
1494 * implies no relevant resources can be freed until after the event is
1495 * received. That's why HTC tx completion handler itself is ignored by
1496 * setting NULL to transfer_context for all sg items.
1498 * There is simply no point in pushing HTT TX_FRM through HTC tx path
1499 * as it's a waste of resources. By bypassing HTC it is possible to
1500 * avoid extra memory allocations, compress data structures and thus
1501 * improve performance.
1504 txbuf->htc_hdr.eid = htt->eid;
1505 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) +
1506 sizeof(txbuf->cmd_tx) +
1508 txbuf->htc_hdr.flags = 0;
1510 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
1511 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
1513 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
1514 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
1515 if (msdu->ip_summed == CHECKSUM_PARTIAL &&
1516 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
1517 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
1518 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
1519 if (ar->hw_params.continuous_frag_desc)
1520 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE;
1523 /* Prevent firmware from sending up tx inspection requests. There's
1524 * nothing ath10k can do with frames requested for inspection so force
1525 * it to simply rely a regular tx completion with discard status.
1527 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
1529 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
1530 txbuf->cmd_tx.flags0 = flags0;
1531 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
1532 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
1533 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
1534 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
1535 if (ath10k_mac_tx_frm_has_freq(ar)) {
1536 txbuf->cmd_tx.offchan_tx.peerid =
1537 __cpu_to_le16(HTT_INVALID_PEERID);
1538 txbuf->cmd_tx.offchan_tx.freq =
1539 __cpu_to_le16(freq);
1541 txbuf->cmd_tx.peerid =
1542 __cpu_to_le32(HTT_INVALID_PEERID);
1545 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
1546 ath10k_dbg(ar, ATH10K_DBG_HTT,
1547 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n",
1548 flags0, flags1, msdu->len, msdu_id, &frags_paddr,
1549 &skb_cb->paddr, vdev_id, tid, freq);
1550 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
1551 msdu->data, msdu->len);
1552 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
1553 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
1555 sg_items[0].transfer_id = 0;
1556 sg_items[0].transfer_context = NULL;
1557 sg_items[0].vaddr = &txbuf->htc_hdr;
1558 sg_items[0].paddr = txbuf_paddr +
1559 sizeof(txbuf->frags);
1560 sg_items[0].len = sizeof(txbuf->htc_hdr) +
1561 sizeof(txbuf->cmd_hdr) +
1562 sizeof(txbuf->cmd_tx);
1564 sg_items[1].transfer_id = 0;
1565 sg_items[1].transfer_context = NULL;
1566 sg_items[1].vaddr = msdu->data;
1567 sg_items[1].paddr = skb_cb->paddr;
1568 sg_items[1].len = prefetch_len;
1570 res = ath10k_hif_tx_sg(htt->ar,
1571 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
1572 sg_items, ARRAY_SIZE(sg_items));
1574 goto err_unmap_msdu;
1579 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1581 spin_lock_bh(&htt->tx_lock);
1582 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
1583 spin_unlock_bh(&htt->tx_lock);
1588 static int ath10k_htt_tx_64(struct ath10k_htt *htt,
1589 enum ath10k_hw_txrx_mode txmode,
1590 struct sk_buff *msdu)
1592 struct ath10k *ar = htt->ar;
1593 struct device *dev = ar->dev;
1594 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
1595 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
1596 struct ath10k_hif_sg_item sg_items[2];
1597 struct ath10k_htt_txbuf_64 *txbuf;
1598 struct htt_data_tx_desc_frag *frags;
1599 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
1600 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
1601 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
1605 u16 msdu_id, flags1 = 0;
1607 dma_addr_t frags_paddr = 0;
1608 dma_addr_t txbuf_paddr;
1609 struct htt_msdu_ext_desc_64 *ext_desc = NULL;
1610 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL;
1612 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
1618 prefetch_len = min(htt->prefetch_len, msdu->len);
1619 prefetch_len = roundup(prefetch_len, 4);
1621 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id;
1622 txbuf_paddr = htt->txbuf.paddr +
1623 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id);
1626 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
1628 if ((ieee80211_is_action(hdr->frame_control) ||
1629 ieee80211_is_deauth(hdr->frame_control) ||
1630 ieee80211_is_disassoc(hdr->frame_control)) &&
1631 ieee80211_has_protected(hdr->frame_control)) {
1632 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1633 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) &&
1634 txmode == ATH10K_HW_TXRX_RAW &&
1635 ieee80211_has_protected(hdr->frame_control)) {
1636 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
1640 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
1642 res = dma_mapping_error(dev, skb_cb->paddr);
1645 goto err_free_msdu_id;
1648 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))
1649 freq = ar->scan.roc_freq;
1652 case ATH10K_HW_TXRX_RAW:
1653 case ATH10K_HW_TXRX_NATIVE_WIFI:
1654 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1656 case ATH10K_HW_TXRX_ETHERNET:
1657 if (ar->hw_params.continuous_frag_desc) {
1658 ext_desc_t = htt->frag_desc.vaddr_desc_64;
1659 memset(&ext_desc_t[msdu_id], 0,
1660 sizeof(struct htt_msdu_ext_desc_64));
1661 frags = (struct htt_data_tx_desc_frag *)
1662 &ext_desc_t[msdu_id].frags;
1663 ext_desc = &ext_desc_t[msdu_id];
1664 frags[0].tword_addr.paddr_lo =
1665 __cpu_to_le32(skb_cb->paddr);
1666 frags[0].tword_addr.paddr_hi =
1667 __cpu_to_le16(upper_32_bits(skb_cb->paddr));
1668 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
1670 frags_paddr = htt->frag_desc.paddr +
1671 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id);
1673 frags = txbuf->frags;
1674 frags[0].tword_addr.paddr_lo =
1675 __cpu_to_le32(skb_cb->paddr);
1676 frags[0].tword_addr.paddr_hi =
1677 __cpu_to_le16(upper_32_bits(skb_cb->paddr));
1678 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
1679 frags[1].tword_addr.paddr_lo = 0;
1680 frags[1].tword_addr.paddr_hi = 0;
1681 frags[1].tword_addr.len_16 = 0;
1683 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1685 case ATH10K_HW_TXRX_MGMT:
1686 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
1687 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
1688 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
1690 frags_paddr = skb_cb->paddr;
1694 /* Normally all commands go through HTC which manages tx credits for
1695 * each endpoint and notifies when tx is completed.
1697 * HTT endpoint is creditless so there's no need to care about HTC
1698 * flags. In that case it is trivial to fill the HTC header here.
1700 * MSDU transmission is considered completed upon HTT event. This
1701 * implies no relevant resources can be freed until after the event is
1702 * received. That's why HTC tx completion handler itself is ignored by
1703 * setting NULL to transfer_context for all sg items.
1705 * There is simply no point in pushing HTT TX_FRM through HTC tx path
1706 * as it's a waste of resources. By bypassing HTC it is possible to
1707 * avoid extra memory allocations, compress data structures and thus
1708 * improve performance.
1711 txbuf->htc_hdr.eid = htt->eid;
1712 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) +
1713 sizeof(txbuf->cmd_tx) +
1715 txbuf->htc_hdr.flags = 0;
1717 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
1718 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
1720 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
1721 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
1722 if (msdu->ip_summed == CHECKSUM_PARTIAL &&
1723 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
1724 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
1725 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
1726 if (ar->hw_params.continuous_frag_desc) {
1727 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag));
1728 ext_desc->tso_flag[3] |=
1729 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64);
1733 /* Prevent firmware from sending up tx inspection requests. There's
1734 * nothing ath10k can do with frames requested for inspection so force
1735 * it to simply rely a regular tx completion with discard status.
1737 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
1739 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
1740 txbuf->cmd_tx.flags0 = flags0;
1741 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
1742 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
1743 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
1745 /* fill fragment descriptor */
1746 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr);
1747 if (ath10k_mac_tx_frm_has_freq(ar)) {
1748 txbuf->cmd_tx.offchan_tx.peerid =
1749 __cpu_to_le16(HTT_INVALID_PEERID);
1750 txbuf->cmd_tx.offchan_tx.freq =
1751 __cpu_to_le16(freq);
1753 txbuf->cmd_tx.peerid =
1754 __cpu_to_le32(HTT_INVALID_PEERID);
1757 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
1758 ath10k_dbg(ar, ATH10K_DBG_HTT,
1759 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n",
1760 flags0, flags1, msdu->len, msdu_id, &frags_paddr,
1761 &skb_cb->paddr, vdev_id, tid, freq);
1762 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
1763 msdu->data, msdu->len);
1764 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
1765 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
1767 sg_items[0].transfer_id = 0;
1768 sg_items[0].transfer_context = NULL;
1769 sg_items[0].vaddr = &txbuf->htc_hdr;
1770 sg_items[0].paddr = txbuf_paddr +
1771 sizeof(txbuf->frags);
1772 sg_items[0].len = sizeof(txbuf->htc_hdr) +
1773 sizeof(txbuf->cmd_hdr) +
1774 sizeof(txbuf->cmd_tx);
1776 sg_items[1].transfer_id = 0;
1777 sg_items[1].transfer_context = NULL;
1778 sg_items[1].vaddr = msdu->data;
1779 sg_items[1].paddr = skb_cb->paddr;
1780 sg_items[1].len = prefetch_len;
1782 res = ath10k_hif_tx_sg(htt->ar,
1783 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
1784 sg_items, ARRAY_SIZE(sg_items));
1786 goto err_unmap_msdu;
1791 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1793 spin_lock_bh(&htt->tx_lock);
1794 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
1795 spin_unlock_bh(&htt->tx_lock);
1800 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = {
1801 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32,
1802 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32,
1803 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32,
1804 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32,
1805 .htt_tx = ath10k_htt_tx_32,
1806 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32,
1807 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32,
1808 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32,
1811 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = {
1812 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64,
1813 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64,
1814 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64,
1815 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64,
1816 .htt_tx = ath10k_htt_tx_64,
1817 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64,
1818 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64,
1819 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_v2,
1822 static const struct ath10k_htt_tx_ops htt_tx_ops_hl = {
1823 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_hl,
1824 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32,
1825 .htt_tx = ath10k_htt_tx_hl,
1826 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32,
1827 .htt_flush_tx = ath10k_htt_flush_tx_queue,
1830 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt)
1832 struct ath10k *ar = htt->ar;
1834 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL)
1835 htt->tx_ops = &htt_tx_ops_hl;
1836 else if (ar->hw_params.target_64bit)
1837 htt->tx_ops = &htt_tx_ops_64;
1839 htt->tx_ops = &htt_tx_ops_32;