2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/etherdevice.h>
25 static u8 ath10k_htt_tx_txq_calc_size(size_t count)
33 while (factor >= 64 && exp < 4) {
42 factor = max(1, factor);
44 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) |
45 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR);
48 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
49 struct ieee80211_txq *txq)
51 struct ath10k *ar = hw->priv;
52 struct ath10k_sta *arsta;
53 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv;
54 unsigned long frame_cnt;
55 unsigned long byte_cnt;
62 lockdep_assert_held(&ar->htt.tx_lock);
64 if (!ar->htt.tx_q_state.enabled)
67 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
71 arsta = (void *)txq->sta->drv_priv;
72 peer_id = arsta->peer_id;
74 peer_id = arvif->peer_id;
78 bit = BIT(peer_id % 32);
81 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
82 count = ath10k_htt_tx_txq_calc_size(byte_cnt);
84 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) ||
85 unlikely(tid >= ar->htt.tx_q_state.num_tids)) {
86 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n",
91 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count;
92 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit;
93 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0;
95 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n",
99 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar)
104 lockdep_assert_held(&ar->htt.tx_lock);
106 if (!ar->htt.tx_q_state.enabled)
109 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL)
112 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq);
114 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq);
116 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n",
119 size = sizeof(*ar->htt.tx_q_state.vaddr);
120 dma_sync_single_for_device(ar->dev,
121 ar->htt.tx_q_state.paddr,
126 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
127 struct ieee80211_txq *txq)
129 struct ath10k *ar = hw->priv;
131 spin_lock_bh(&ar->htt.tx_lock);
132 __ath10k_htt_tx_txq_recalc(hw, txq);
133 spin_unlock_bh(&ar->htt.tx_lock);
136 void ath10k_htt_tx_txq_sync(struct ath10k *ar)
138 spin_lock_bh(&ar->htt.tx_lock);
139 __ath10k_htt_tx_txq_sync(ar);
140 spin_unlock_bh(&ar->htt.tx_lock);
143 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
144 struct ieee80211_txq *txq)
146 struct ath10k *ar = hw->priv;
148 spin_lock_bh(&ar->htt.tx_lock);
149 __ath10k_htt_tx_txq_recalc(hw, txq);
150 __ath10k_htt_tx_txq_sync(ar);
151 spin_unlock_bh(&ar->htt.tx_lock);
154 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
156 lockdep_assert_held(&htt->tx_lock);
158 htt->num_pending_tx--;
159 if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
160 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
163 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
165 lockdep_assert_held(&htt->tx_lock);
167 if (htt->num_pending_tx >= htt->max_num_pending_tx)
170 htt->num_pending_tx++;
171 if (htt->num_pending_tx == htt->max_num_pending_tx)
172 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
177 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
180 struct ath10k *ar = htt->ar;
182 lockdep_assert_held(&htt->tx_lock);
184 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres)
188 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx)
191 htt->num_pending_mgmt_tx++;
196 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt)
198 lockdep_assert_held(&htt->tx_lock);
200 if (!htt->ar->hw_params.max_probe_resp_desc_thres)
203 htt->num_pending_mgmt_tx--;
206 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb)
208 struct ath10k *ar = htt->ar;
211 lockdep_assert_held(&htt->tx_lock);
213 ret = idr_alloc(&htt->pending_tx, skb, 0,
214 htt->max_num_pending_tx, GFP_ATOMIC);
216 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);
221 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
223 struct ath10k *ar = htt->ar;
225 lockdep_assert_held(&htt->tx_lock);
227 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
229 idr_remove(&htt->pending_tx, msdu_id);
232 static void ath10k_htt_tx_free_cont_txbuf(struct ath10k_htt *htt)
234 struct ath10k *ar = htt->ar;
237 if (!htt->txbuf.vaddr)
240 size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf);
241 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr, htt->txbuf.paddr);
242 htt->txbuf.vaddr = NULL;
245 static int ath10k_htt_tx_alloc_cont_txbuf(struct ath10k_htt *htt)
247 struct ath10k *ar = htt->ar;
250 size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf);
251 htt->txbuf.vaddr = dma_alloc_coherent(ar->dev, size, &htt->txbuf.paddr,
253 if (!htt->txbuf.vaddr)
259 static void ath10k_htt_tx_free_cont_frag_desc(struct ath10k_htt *htt)
263 if (!htt->frag_desc.vaddr)
266 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc);
268 dma_free_coherent(htt->ar->dev,
270 htt->frag_desc.vaddr,
271 htt->frag_desc.paddr);
272 htt->frag_desc.vaddr = NULL;
275 static int ath10k_htt_tx_alloc_cont_frag_desc(struct ath10k_htt *htt)
277 struct ath10k *ar = htt->ar;
280 if (!ar->hw_params.continuous_frag_desc)
283 size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc);
284 htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size,
285 &htt->frag_desc.paddr,
287 if (!htt->frag_desc.vaddr)
293 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt)
295 struct ath10k *ar = htt->ar;
298 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
299 ar->running_fw->fw_file.fw_features))
302 size = sizeof(*htt->tx_q_state.vaddr);
304 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE);
305 kfree(htt->tx_q_state.vaddr);
308 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt)
310 struct ath10k *ar = htt->ar;
314 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
315 ar->running_fw->fw_file.fw_features))
318 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS;
319 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS;
320 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES;
322 size = sizeof(*htt->tx_q_state.vaddr);
323 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL);
324 if (!htt->tx_q_state.vaddr)
327 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr,
328 size, DMA_TO_DEVICE);
329 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr);
331 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret);
332 kfree(htt->tx_q_state.vaddr);
339 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt)
341 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo));
342 kfifo_free(&htt->txdone_fifo);
345 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt)
350 size = roundup_pow_of_two(htt->max_num_pending_tx);
351 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL);
355 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt)
357 struct ath10k *ar = htt->ar;
360 ret = ath10k_htt_tx_alloc_cont_txbuf(htt);
362 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret);
366 ret = ath10k_htt_tx_alloc_cont_frag_desc(htt);
368 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret);
372 ret = ath10k_htt_tx_alloc_txq(htt);
374 ath10k_err(ar, "failed to alloc txq: %d\n", ret);
378 ret = ath10k_htt_tx_alloc_txdone_fifo(htt);
380 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret);
387 ath10k_htt_tx_free_txq(htt);
390 ath10k_htt_tx_free_cont_frag_desc(htt);
393 ath10k_htt_tx_free_cont_txbuf(htt);
398 int ath10k_htt_tx_start(struct ath10k_htt *htt)
400 struct ath10k *ar = htt->ar;
403 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
404 htt->max_num_pending_tx);
406 spin_lock_init(&htt->tx_lock);
407 idr_init(&htt->pending_tx);
409 if (htt->tx_mem_allocated)
412 ret = ath10k_htt_tx_alloc_buf(htt);
414 goto free_idr_pending_tx;
416 htt->tx_mem_allocated = true;
421 idr_destroy(&htt->pending_tx);
426 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx)
428 struct ath10k *ar = ctx;
429 struct ath10k_htt *htt = &ar->htt;
430 struct htt_tx_done tx_done = {0};
432 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id);
434 tx_done.msdu_id = msdu_id;
435 tx_done.status = HTT_TX_COMPL_STATE_DISCARD;
437 ath10k_txrx_tx_unref(htt, &tx_done);
442 void ath10k_htt_tx_destroy(struct ath10k_htt *htt)
444 if (!htt->tx_mem_allocated)
447 ath10k_htt_tx_free_cont_txbuf(htt);
448 ath10k_htt_tx_free_txq(htt);
449 ath10k_htt_tx_free_cont_frag_desc(htt);
450 ath10k_htt_tx_free_txdone_fifo(htt);
451 htt->tx_mem_allocated = false;
454 void ath10k_htt_tx_stop(struct ath10k_htt *htt)
456 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
457 idr_destroy(&htt->pending_tx);
460 void ath10k_htt_tx_free(struct ath10k_htt *htt)
462 ath10k_htt_tx_stop(htt);
463 ath10k_htt_tx_destroy(htt);
466 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
468 dev_kfree_skb_any(skb);
471 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb)
473 dev_kfree_skb_any(skb);
475 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete);
477 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
479 struct ath10k *ar = htt->ar;
485 len += sizeof(cmd->hdr);
486 len += sizeof(cmd->ver_req);
488 skb = ath10k_htc_alloc_skb(ar, len);
493 cmd = (struct htt_cmd *)skb->data;
494 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
496 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
498 dev_kfree_skb_any(skb);
505 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
507 struct ath10k *ar = htt->ar;
508 struct htt_stats_req *req;
513 len += sizeof(cmd->hdr);
514 len += sizeof(cmd->stats_req);
516 skb = ath10k_htc_alloc_skb(ar, len);
521 cmd = (struct htt_cmd *)skb->data;
522 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
524 req = &cmd->stats_req;
526 memset(req, 0, sizeof(*req));
528 /* currently we support only max 8 bit masks so no need to worry
529 * about endian support
531 req->upload_types[0] = mask;
532 req->reset_types[0] = mask;
533 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
534 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
535 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
537 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
539 ath10k_warn(ar, "failed to send htt type stats request: %d",
541 dev_kfree_skb_any(skb);
548 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)
550 struct ath10k *ar = htt->ar;
553 struct htt_frag_desc_bank_cfg *cfg;
557 if (!ar->hw_params.continuous_frag_desc)
560 if (!htt->frag_desc.paddr) {
561 ath10k_warn(ar, "invalid frag desc memory\n");
565 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg);
566 skb = ath10k_htc_alloc_skb(ar, size);
571 cmd = (struct htt_cmd *)skb->data;
572 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG;
575 info |= SM(htt->tx_q_state.type,
576 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE);
578 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
579 ar->running_fw->fw_file.fw_features))
580 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID;
582 cfg = &cmd->frag_desc_bank_cfg;
585 cfg->desc_size = sizeof(struct htt_msdu_ext_desc);
586 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr);
587 cfg->bank_id[0].bank_min_id = 0;
588 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx -
591 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr);
592 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers);
593 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids);
594 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE;
595 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER;
597 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n");
599 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
601 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n",
603 dev_kfree_skb_any(skb);
610 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
612 struct ath10k *ar = htt->ar;
615 struct htt_rx_ring_setup_ring *ring;
616 const int num_rx_ring = 1;
623 * the HW expects the buffer to be an integral number of 4-byte
626 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
627 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
629 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
630 + (sizeof(*ring) * num_rx_ring);
631 skb = ath10k_htc_alloc_skb(ar, len);
637 cmd = (struct htt_cmd *)skb->data;
638 ring = &cmd->rx_setup.rings[0];
640 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
641 cmd->rx_setup.hdr.num_rings = 1;
643 /* FIXME: do we need all of this? */
645 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
646 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
647 flags |= HTT_RX_RING_FLAGS_PPDU_START;
648 flags |= HTT_RX_RING_FLAGS_PPDU_END;
649 flags |= HTT_RX_RING_FLAGS_MPDU_START;
650 flags |= HTT_RX_RING_FLAGS_MPDU_END;
651 flags |= HTT_RX_RING_FLAGS_MSDU_START;
652 flags |= HTT_RX_RING_FLAGS_MSDU_END;
653 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
654 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
655 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
656 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
657 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
658 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
659 flags |= HTT_RX_RING_FLAGS_NULL_RX;
660 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
662 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
664 ring->fw_idx_shadow_reg_paddr =
665 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
666 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
667 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
668 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
669 ring->flags = __cpu_to_le16(flags);
670 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
672 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
674 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
675 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
676 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
677 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
678 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
679 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
680 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
681 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
682 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
683 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
687 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
689 dev_kfree_skb_any(skb);
696 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
697 u8 max_subfrms_ampdu,
698 u8 max_subfrms_amsdu)
700 struct ath10k *ar = htt->ar;
701 struct htt_aggr_conf *aggr_conf;
707 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
709 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
712 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
715 len = sizeof(cmd->hdr);
716 len += sizeof(cmd->aggr_conf);
718 skb = ath10k_htc_alloc_skb(ar, len);
723 cmd = (struct htt_cmd *)skb->data;
724 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
726 aggr_conf = &cmd->aggr_conf;
727 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
728 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
730 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
731 aggr_conf->max_num_amsdu_subframes,
732 aggr_conf->max_num_ampdu_subframes);
734 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
736 dev_kfree_skb_any(skb);
743 int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
745 __le16 fetch_seq_num,
746 struct htt_tx_fetch_record *records,
751 const u16 resp_id = 0;
755 /* Response IDs are echo-ed back only for host driver convienence
756 * purposes. They aren't used for anything in the driver yet so use 0.
759 len += sizeof(cmd->hdr);
760 len += sizeof(cmd->tx_fetch_resp);
761 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records;
763 skb = ath10k_htc_alloc_skb(ar, len);
768 cmd = (struct htt_cmd *)skb->data;
769 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP;
770 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id);
771 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num;
772 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records);
773 cmd->tx_fetch_resp.token = token;
775 memcpy(cmd->tx_fetch_resp.records, records,
776 sizeof(records[0]) * num_records);
778 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb);
780 ath10k_warn(ar, "failed to submit htc command: %d\n", ret);
787 dev_kfree_skb_any(skb);
792 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb)
794 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
795 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
796 struct ath10k_vif *arvif;
798 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) {
799 return ar->scan.vdev_id;
800 } else if (cb->vif) {
801 arvif = (void *)cb->vif->drv_priv;
802 return arvif->vdev_id;
803 } else if (ar->monitor_started) {
804 return ar->monitor_vdev_id;
810 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth)
812 struct ieee80211_hdr *hdr = (void *)skb->data;
813 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
815 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control))
816 return HTT_DATA_TX_EXT_TID_MGMT;
817 else if (cb->flags & ATH10K_SKB_F_QOS)
818 return skb->priority % IEEE80211_QOS_CTL_TID_MASK;
820 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST;
823 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
825 struct ath10k *ar = htt->ar;
826 struct device *dev = ar->dev;
827 struct sk_buff *txdesc = NULL;
829 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
830 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
834 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
836 len += sizeof(cmd->hdr);
837 len += sizeof(cmd->mgmt_tx);
839 spin_lock_bh(&htt->tx_lock);
840 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
841 spin_unlock_bh(&htt->tx_lock);
847 if ((ieee80211_is_action(hdr->frame_control) ||
848 ieee80211_is_deauth(hdr->frame_control) ||
849 ieee80211_is_disassoc(hdr->frame_control)) &&
850 ieee80211_has_protected(hdr->frame_control)) {
851 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
854 txdesc = ath10k_htc_alloc_skb(ar, len);
857 goto err_free_msdu_id;
860 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
862 res = dma_mapping_error(dev, skb_cb->paddr);
865 goto err_free_txdesc;
868 skb_put(txdesc, len);
869 cmd = (struct htt_cmd *)txdesc->data;
872 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
873 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
874 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
875 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
876 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
877 memcpy(cmd->mgmt_tx.hdr, msdu->data,
878 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
880 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
887 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
889 dev_kfree_skb_any(txdesc);
891 spin_lock_bh(&htt->tx_lock);
892 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
893 spin_unlock_bh(&htt->tx_lock);
898 int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
899 struct sk_buff *msdu)
901 struct ath10k *ar = htt->ar;
902 struct device *dev = ar->dev;
903 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
904 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
905 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
906 struct ath10k_hif_sg_item sg_items[2];
907 struct ath10k_htt_txbuf *txbuf;
908 struct htt_data_tx_desc_frag *frags;
909 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET);
910 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu);
911 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth);
915 u16 msdu_id, flags1 = 0;
919 struct htt_msdu_ext_desc *ext_desc = NULL;
921 spin_lock_bh(&htt->tx_lock);
922 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
923 spin_unlock_bh(&htt->tx_lock);
929 prefetch_len = min(htt->prefetch_len, msdu->len);
930 prefetch_len = roundup(prefetch_len, 4);
932 txbuf = &htt->txbuf.vaddr[msdu_id];
933 txbuf_paddr = htt->txbuf.paddr +
934 (sizeof(struct ath10k_htt_txbuf) * msdu_id);
936 if ((ieee80211_is_action(hdr->frame_control) ||
937 ieee80211_is_deauth(hdr->frame_control) ||
938 ieee80211_is_disassoc(hdr->frame_control)) &&
939 ieee80211_has_protected(hdr->frame_control)) {
940 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
941 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) &&
942 txmode == ATH10K_HW_TXRX_RAW &&
943 ieee80211_has_protected(hdr->frame_control)) {
944 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
947 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
949 res = dma_mapping_error(dev, skb_cb->paddr);
952 goto err_free_msdu_id;
955 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))
956 freq = ar->scan.roc_freq;
959 case ATH10K_HW_TXRX_RAW:
960 case ATH10K_HW_TXRX_NATIVE_WIFI:
961 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
963 case ATH10K_HW_TXRX_ETHERNET:
964 if (ar->hw_params.continuous_frag_desc) {
965 memset(&htt->frag_desc.vaddr[msdu_id], 0,
966 sizeof(struct htt_msdu_ext_desc));
967 frags = (struct htt_data_tx_desc_frag *)
968 &htt->frag_desc.vaddr[msdu_id].frags;
969 ext_desc = &htt->frag_desc.vaddr[msdu_id];
970 frags[0].tword_addr.paddr_lo =
971 __cpu_to_le32(skb_cb->paddr);
972 frags[0].tword_addr.paddr_hi = 0;
973 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len);
975 frags_paddr = htt->frag_desc.paddr +
976 (sizeof(struct htt_msdu_ext_desc) * msdu_id);
978 frags = txbuf->frags;
979 frags[0].dword_addr.paddr =
980 __cpu_to_le32(skb_cb->paddr);
981 frags[0].dword_addr.len = __cpu_to_le32(msdu->len);
982 frags[1].dword_addr.paddr = 0;
983 frags[1].dword_addr.len = 0;
985 frags_paddr = txbuf_paddr;
987 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
989 case ATH10K_HW_TXRX_MGMT:
990 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
991 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
992 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
994 frags_paddr = skb_cb->paddr;
998 /* Normally all commands go through HTC which manages tx credits for
999 * each endpoint and notifies when tx is completed.
1001 * HTT endpoint is creditless so there's no need to care about HTC
1002 * flags. In that case it is trivial to fill the HTC header here.
1004 * MSDU transmission is considered completed upon HTT event. This
1005 * implies no relevant resources can be freed until after the event is
1006 * received. That's why HTC tx completion handler itself is ignored by
1007 * setting NULL to transfer_context for all sg items.
1009 * There is simply no point in pushing HTT TX_FRM through HTC tx path
1010 * as it's a waste of resources. By bypassing HTC it is possible to
1011 * avoid extra memory allocations, compress data structures and thus
1012 * improve performance.
1015 txbuf->htc_hdr.eid = htt->eid;
1016 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) +
1017 sizeof(txbuf->cmd_tx) +
1019 txbuf->htc_hdr.flags = 0;
1021 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT)
1022 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
1024 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
1025 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
1026 if (msdu->ip_summed == CHECKSUM_PARTIAL &&
1027 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
1028 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
1029 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
1030 if (ar->hw_params.continuous_frag_desc)
1031 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE;
1034 /* Prevent firmware from sending up tx inspection requests. There's
1035 * nothing ath10k can do with frames requested for inspection so force
1036 * it to simply rely a regular tx completion with discard status.
1038 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
1040 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
1041 txbuf->cmd_tx.flags0 = flags0;
1042 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
1043 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
1044 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
1045 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
1046 if (ath10k_mac_tx_frm_has_freq(ar)) {
1047 txbuf->cmd_tx.offchan_tx.peerid =
1048 __cpu_to_le16(HTT_INVALID_PEERID);
1049 txbuf->cmd_tx.offchan_tx.freq =
1050 __cpu_to_le16(freq);
1052 txbuf->cmd_tx.peerid =
1053 __cpu_to_le32(HTT_INVALID_PEERID);
1056 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
1057 ath10k_dbg(ar, ATH10K_DBG_HTT,
1058 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
1059 flags0, flags1, msdu->len, msdu_id, frags_paddr,
1060 (u32)skb_cb->paddr, vdev_id, tid, freq);
1061 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
1062 msdu->data, msdu->len);
1063 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
1064 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
1066 sg_items[0].transfer_id = 0;
1067 sg_items[0].transfer_context = NULL;
1068 sg_items[0].vaddr = &txbuf->htc_hdr;
1069 sg_items[0].paddr = txbuf_paddr +
1070 sizeof(txbuf->frags);
1071 sg_items[0].len = sizeof(txbuf->htc_hdr) +
1072 sizeof(txbuf->cmd_hdr) +
1073 sizeof(txbuf->cmd_tx);
1075 sg_items[1].transfer_id = 0;
1076 sg_items[1].transfer_context = NULL;
1077 sg_items[1].vaddr = msdu->data;
1078 sg_items[1].paddr = skb_cb->paddr;
1079 sg_items[1].len = prefetch_len;
1081 res = ath10k_hif_tx_sg(htt->ar,
1082 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
1083 sg_items, ARRAY_SIZE(sg_items));
1085 goto err_unmap_msdu;
1090 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
1092 ath10k_htt_tx_free_msdu_id(htt, msdu_id);