1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/net/wan/slic_ds26522.c
5 * Copyright (C) 2016 Freescale Semiconductor, Inc.
7 * Author:Zhao Qiang<qiang.zhao@nxp.com>
10 #include <linux/bitrev.h>
11 #include <linux/module.h>
12 #include <linux/device.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/kthread.h>
16 #include <linux/spi/spi.h>
17 #include <linux/wait.h>
18 #include <linux/param.h>
19 #include <linux/delay.h>
21 #include <linux/of_address.h>
23 #include "slic_ds26522.h"
25 #define SLIC_TRANS_LEN 1
26 #define SLIC_TWO_LEN 2
27 #define SLIC_THREE_LEN 3
29 static struct spi_device *g_spi;
31 MODULE_LICENSE("GPL");
32 MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>");
34 /* the read/write format of address is
35 * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x
37 static void slic_write(struct spi_device *spi, u16 addr,
42 addr = bitrev16(addr) >> 1;
44 temp[0] = (u8)((addr >> 8) & 0x7f);
45 temp[1] = (u8)(addr & 0xfe);
48 /* write spi addr and value */
49 spi_write(spi, &temp[0], SLIC_THREE_LEN);
52 static u8 slic_read(struct spi_device *spi, u16 addr)
57 addr = bitrev16(addr) >> 1;
58 temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80);
59 temp[1] = (u8)(addr & 0xfe);
61 spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data,
68 static bool get_slic_product_code(struct spi_device *spi)
72 device_id = slic_read(spi, DS26522_IDR_ADDR);
73 if ((device_id & 0xf8) == 0x68)
79 static void ds26522_e1_spec_config(struct spi_device *spi)
81 /* Receive E1 Mode, Framer Disabled */
82 slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
84 /* Transmit E1 Mode, Framer Disable */
85 slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
87 /* Receive E1 Mode Framer Enable */
88 slic_write(spi, DS26522_RMMR_ADDR,
89 slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN);
91 /* Transmit E1 Mode Framer Enable */
92 slic_write(spi, DS26522_TMMR_ADDR,
93 slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN);
95 /* RCR1, receive E1 B8zs & ESF */
96 slic_write(spi, DS26522_RCR1_ADDR,
97 DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS);
99 /* RSYSCLK=2.048MHz, RSYNC-Output */
100 slic_write(spi, DS26522_RIOCR_ADDR,
101 DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT);
103 /* TCR1 Transmit E1 b8zs */
104 slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
106 /* TSYSCLK=2.048MHz, TSYNC-Output */
107 slic_write(spi, DS26522_TIOCR_ADDR,
108 DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT);
111 slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
113 /* Set E1TNAF register */
114 slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
116 /* Receive E1 Mode Framer Enable & init Done */
117 slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
118 DS26522_RMMR_INIT_DONE);
120 /* Transmit E1 Mode Framer Enable & init Done */
121 slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
122 DS26522_TMMR_INIT_DONE);
124 /* Configure LIU E1 mode */
125 slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
127 /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */
128 slic_write(spi, DS26522_LTITSR_ADDR,
129 DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM);
131 /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */
132 slic_write(spi, DS26522_LRISMR_ADDR,
133 DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX);
135 /* Enable Transmit output */
136 slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
139 static int slic_ds26522_init_configure(struct spi_device *spi)
144 slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
145 DS26522_GTCCR_BFREQSEL_2048KHZ |
146 DS26522_GTCCR_FREQSEL_2048KHZ);
147 slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
148 slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
151 slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
153 /* Global LIU Software Reset Register */
154 slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
156 /* Global Framer and BERT Software Reset Register */
157 slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
159 usleep_range(100, 120);
161 slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
162 slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
164 /* Perform RX/TX SRESET,Reset receiver */
165 slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
167 /* Reset tranceiver */
168 slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
170 usleep_range(100, 120);
172 /* Zero all Framer Registers */
173 for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END;
175 slic_write(spi, addr, 0);
177 for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END;
179 slic_write(spi, addr, 0);
181 for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END;
183 slic_write(spi, addr, 0);
185 for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END;
187 slic_write(spi, addr, 0);
189 /* setup ds26522 for E1 specification */
190 ds26522_e1_spec_config(spi);
192 slic_write(spi, DS26522_GTCR1_ADDR, 0x00);
197 static int slic_ds26522_remove(struct spi_device *spi)
199 pr_info("DS26522 module uninstalled\n");
203 static int slic_ds26522_probe(struct spi_device *spi)
208 spi->bits_per_word = 8;
210 if (!get_slic_product_code(spi))
213 ret = slic_ds26522_init_configure(spi);
215 pr_info("DS26522 cs%d configured\n", spi->chip_select);
220 static const struct spi_device_id slic_ds26522_id[] = {
221 { .name = "ds26522" },
224 MODULE_DEVICE_TABLE(spi, slic_ds26522_id);
226 static const struct of_device_id slic_ds26522_match[] = {
228 .compatible = "maxim,ds26522",
232 MODULE_DEVICE_TABLE(of, slic_ds26522_match);
234 static struct spi_driver slic_ds26522_driver = {
237 .bus = &spi_bus_type,
238 .of_match_table = slic_ds26522_match,
240 .probe = slic_ds26522_probe,
241 .remove = slic_ds26522_remove,
242 .id_table = slic_ds26522_id,
245 module_spi_driver(slic_ds26522_driver);