drivers/net/vmxnet3/vmxnet3_drv.c

   1 /*
   2  * Linux driver for VMware's vmxnet3 ethernet NIC.
   3  *
   4  * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; version 2 of the License and no later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13  * NON INFRINGEMENT. See the GNU General Public License for more
  14  * details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * The full GNU General Public License is included in this distribution in
  21  * the file called "COPYING".
  22  *
  23  * Maintained by: pv-drivers@vmware.com
  24  *
  25  */
  26
  27 #include <linux/module.h>
  28 #include <net/ip6_checksum.h>
  29
  30 #include "vmxnet3_int.h"
  31
  32 char vmxnet3_driver_name[] = "vmxnet3";
  33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
  34
  35 /*
  36  * PCI Device ID Table
  37  * Last entry must be all 0s
  38  */
  39 static const struct pci_device_id vmxnet3_pciid_table[] = {
  40         {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
  41         {0}
  42 };
  43
  44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
  45
  46 static int enable_mq = 1;
  47
  48 static void
  49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
  50
  51 /*
  52  *    Enable/Disable the given intr
  53  */
  54 static void
  55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  56 {
  57         VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
  58 }
  59
  60
  61 static void
  62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  63 {
  64         VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
  65 }
  66
  67
  68 /*
  69  *    Enable/Disable all intrs used by the device
  70  */
  71 static void
  72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
  73 {
  74         int i;
  75
  76         for (i = 0; i < adapter->intr.num_intrs; i++)
  77                 vmxnet3_enable_intr(adapter, i);
  78         adapter->shared->devRead.intrConf.intrCtrl &=
  79                                         cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
  80 }
  81
  82
  83 static void
  84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
  85 {
  86         int i;
  87
  88         adapter->shared->devRead.intrConf.intrCtrl |=
  89                                         cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
  90         for (i = 0; i < adapter->intr.num_intrs; i++)
  91                 vmxnet3_disable_intr(adapter, i);
  92 }
  93
  94
  95 static void
  96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
  97 {
  98         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
  99 }
 100
 101
 102 static bool
 103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 104 {
 105         return tq->stopped;
 106 }
 107
 108
 109 static void
 110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 111 {
 112         tq->stopped = false;
 113         netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
 114 }
 115
 116
 117 static void
 118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 119 {
 120         tq->stopped = false;
 121         netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
 122 }
 123
 124
 125 static void
 126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 127 {
 128         tq->stopped = true;
 129         tq->num_stop++;
 130         netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
 131 }
 132
 133
 134 /*
 135  * Check the link state. This may start or stop the tx queue.
 136  */
 137 static void
 138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
 139 {
 140         u32 ret;
 141         int i;
 142         unsigned long flags;
 143
 144         spin_lock_irqsave(&adapter->cmd_lock, flags);
 145         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
 146         ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
 147         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
 148
 149         adapter->link_speed = ret >> 16;
 150         if (ret & 1) { /* Link is up. */
 151                 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
 152                             adapter->link_speed);
 153                 netif_carrier_on(adapter->netdev);
 154
 155                 if (affectTxQueue) {
 156                         for (i = 0; i < adapter->num_tx_queues; i++)
 157                                 vmxnet3_tq_start(&adapter->tx_queue[i],
 158                                                  adapter);
 159                 }
 160         } else {
 161                 netdev_info(adapter->netdev, "NIC Link is Down\n");
 162                 netif_carrier_off(adapter->netdev);
 163
 164                 if (affectTxQueue) {
 165                         for (i = 0; i < adapter->num_tx_queues; i++)
 166                                 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
 167                 }
 168         }
 169 }
 170
 171 static void
 172 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
 173 {
 174         int i;
 175         unsigned long flags;
 176         u32 events = le32_to_cpu(adapter->shared->ecr);
 177         if (!events)
 178                 return;
 179
 180         vmxnet3_ack_events(adapter, events);
 181
 182         /* Check if link state has changed */
 183         if (events & VMXNET3_ECR_LINK)
 184                 vmxnet3_check_link(adapter, true);
 185
 186         /* Check if there is an error on xmit/recv queues */
 187         if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
 188                 spin_lock_irqsave(&adapter->cmd_lock, flags);
 189                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
 190                                        VMXNET3_CMD_GET_QUEUE_STATUS);
 191                 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
 192
 193                 for (i = 0; i < adapter->num_tx_queues; i++)
 194                         if (adapter->tqd_start[i].status.stopped)
 195                                 dev_err(&adapter->netdev->dev,
 196                                         "%s: tq[%d] error 0x%x\n",
 197                                         adapter->netdev->name, i, le32_to_cpu(
 198                                         adapter->tqd_start[i].status.error));
 199                 for (i = 0; i < adapter->num_rx_queues; i++)
 200                         if (adapter->rqd_start[i].status.stopped)
 201                                 dev_err(&adapter->netdev->dev,
 202                                         "%s: rq[%d] error 0x%x\n",
 203                                         adapter->netdev->name, i,
 204                                         adapter->rqd_start[i].status.error);
 205
 206                 schedule_work(&adapter->work);
 207         }
 208 }
 209
 210 #ifdef __BIG_ENDIAN_BITFIELD
 211 /*
 212  * The device expects the bitfields in shared structures to be written in
 213  * little endian. When CPU is big endian, the following routines are used to
 214  * correctly read and write into ABI.
 215  * The general technique used here is : double word bitfields are defined in
 216  * opposite order for big endian architecture. Then before reading them in
 217  * driver the complete double word is translated using le32_to_cpu. Similarly
 218  * After the driver writes into bitfields, cpu_to_le32 is used to translate the
 219  * double words into required format.
 220  * In order to avoid touching bits in shared structure more than once, temporary
 221  * descriptors are used. These are passed as srcDesc to following functions.
 222  */
 223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
 224                                 struct Vmxnet3_RxDesc *dstDesc)
 225 {
 226         u32 *src = (u32 *)srcDesc + 2;
 227         u32 *dst = (u32 *)dstDesc + 2;
 228         dstDesc->addr = le64_to_cpu(srcDesc->addr);
 229         *dst = le32_to_cpu(*src);
 230         dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
 231 }
 232
 233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
 234                                struct Vmxnet3_TxDesc *dstDesc)
 235 {
 236         int i;
 237         u32 *src = (u32 *)(srcDesc + 1);
 238         u32 *dst = (u32 *)(dstDesc + 1);
 239
 240         /* Working backwards so that the gen bit is set at the end. */
 241         for (i = 2; i > 0; i--) {
 242                 src--;
 243                 dst--;
 244                 *dst = cpu_to_le32(*src);
 245         }
 246 }
 247
 248
 249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
 250                                 struct Vmxnet3_RxCompDesc *dstDesc)
 251 {
 252         int i = 0;
 253         u32 *src = (u32 *)srcDesc;
 254         u32 *dst = (u32 *)dstDesc;
 255         for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
 256                 *dst = le32_to_cpu(*src);
 257                 src++;
 258                 dst++;
 259         }
 260 }
 261
 262
 263 /* Used to read bitfield values from double words. */
 264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
 265 {
 266         u32 temp = le32_to_cpu(*bitfield);
 267         u32 mask = ((1 << size) - 1) << pos;
 268         temp &= mask;
 269         temp >>= pos;
 270         return temp;
 271 }
 272
 273
 274
 275 #endif  /* __BIG_ENDIAN_BITFIELD */
 276
 277 #ifdef __BIG_ENDIAN_BITFIELD
 278
 279 #   define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
 280                         txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
 281                         VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
 282 #   define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
 283                         txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
 284                         VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
 285 #   define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
 286                         VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
 287                         VMXNET3_TCD_GEN_SIZE)
 288 #   define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
 289                         VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
 290 #   define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
 291                         (dstrcd) = (tmp); \
 292                         vmxnet3_RxCompToCPU((rcd), (tmp)); \
 293                 } while (0)
 294 #   define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
 295                         (dstrxd) = (tmp); \
 296                         vmxnet3_RxDescToCPU((rxd), (tmp)); \
 297                 } while (0)
 298
 299 #else
 300
 301 #   define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
 302 #   define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
 303 #   define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
 304 #   define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
 305 #   define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
 306 #   define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
 307
 308 #endif /* __BIG_ENDIAN_BITFIELD  */
 309
 310
 311 static void
 312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
 313                      struct pci_dev *pdev)
 314 {
 315         if (tbi->map_type == VMXNET3_MAP_SINGLE)
 316                 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
 317                                  PCI_DMA_TODEVICE);
 318         else if (tbi->map_type == VMXNET3_MAP_PAGE)
 319                 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
 320                                PCI_DMA_TODEVICE);
 321         else
 322                 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
 323
 324         tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
 325 }
 326
 327
 328 static int
 329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
 330                   struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
 331 {
 332         struct sk_buff *skb;
 333         int entries = 0;
 334
 335         /* no out of order completion */
 336         BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
 337         BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
 338
 339         skb = tq->buf_info[eop_idx].skb;
 340         BUG_ON(skb == NULL);
 341         tq->buf_info[eop_idx].skb = NULL;
 342
 343         VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
 344
 345         while (tq->tx_ring.next2comp != eop_idx) {
 346                 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
 347                                      pdev);
 348
 349                 /* update next2comp w/o tx_lock. Since we are marking more,
 350                  * instead of less, tx ring entries avail, the worst case is
 351                  * that the tx routine incorrectly re-queues a pkt due to
 352                  * insufficient tx ring entries.
 353                  */
 354                 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
 355                 entries++;
 356         }
 357
 358         dev_kfree_skb_any(skb);
 359         return entries;
 360 }
 361
 362
 363 static int
 364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
 365                         struct vmxnet3_adapter *adapter)
 366 {
 367         int completed = 0;
 368         union Vmxnet3_GenericDesc *gdesc;
 369
 370         gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
 371         while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
 372                 /* Prevent any &gdesc->tcd field from being (speculatively)
 373                  * read before (&gdesc->tcd)->gen is read.
 374                  */
 375                 dma_rmb();
 376
 377                 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
 378                                                &gdesc->tcd), tq, adapter->pdev,
 379                                                adapter);
 380
 381                 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
 382                 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
 383         }
 384
 385         if (completed) {
 386                 spin_lock(&tq->tx_lock);
 387                 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
 388                              vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
 389                              VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
 390                              netif_carrier_ok(adapter->netdev))) {
 391                         vmxnet3_tq_wake(tq, adapter);
 392                 }
 393                 spin_unlock(&tq->tx_lock);
 394         }
 395         return completed;
 396 }
 397
 398
 399 static void
 400 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
 401                    struct vmxnet3_adapter *adapter)
 402 {
 403         int i;
 404
 405         while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
 406                 struct vmxnet3_tx_buf_info *tbi;
 407
 408                 tbi = tq->buf_info + tq->tx_ring.next2comp;
 409
 410                 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
 411                 if (tbi->skb) {
 412                         dev_kfree_skb_any(tbi->skb);
 413                         tbi->skb = NULL;
 414                 }
 415                 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
 416         }
 417
 418         /* sanity check, verify all buffers are indeed unmapped and freed */
 419         for (i = 0; i < tq->tx_ring.size; i++) {
 420                 BUG_ON(tq->buf_info[i].skb != NULL ||
 421                        tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
 422         }
 423
 424         tq->tx_ring.gen = VMXNET3_INIT_GEN;
 425         tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
 426
 427         tq->comp_ring.gen = VMXNET3_INIT_GEN;
 428         tq->comp_ring.next2proc = 0;
 429 }
 430
 431
 432 static void
 433 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
 434                    struct vmxnet3_adapter *adapter)
 435 {
 436         if (tq->tx_ring.base) {
 437                 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
 438                                   sizeof(struct Vmxnet3_TxDesc),
 439                                   tq->tx_ring.base, tq->tx_ring.basePA);
 440                 tq->tx_ring.base = NULL;
 441         }
 442         if (tq->data_ring.base) {
 443                 dma_free_coherent(&adapter->pdev->dev,
 444                                   tq->data_ring.size * tq->txdata_desc_size,
 445                                   tq->data_ring.base, tq->data_ring.basePA);
 446                 tq->data_ring.base = NULL;
 447         }
 448         if (tq->comp_ring.base) {
 449                 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
 450                                   sizeof(struct Vmxnet3_TxCompDesc),
 451                                   tq->comp_ring.base, tq->comp_ring.basePA);
 452                 tq->comp_ring.base = NULL;
 453         }
 454         if (tq->buf_info) {
 455                 dma_free_coherent(&adapter->pdev->dev,
 456                                   tq->tx_ring.size * sizeof(tq->buf_info[0]),
 457                                   tq->buf_info, tq->buf_info_pa);
 458                 tq->buf_info = NULL;
 459         }
 460 }
 461
 462
 463 /* Destroy all tx queues */
 464 void
 465 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
 466 {
 467         int i;
 468
 469         for (i = 0; i < adapter->num_tx_queues; i++)
 470                 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
 471 }
 472
 473
 474 static void
 475 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
 476                 struct vmxnet3_adapter *adapter)
 477 {
 478         int i;
 479
 480         /* reset the tx ring contents to 0 and reset the tx ring states */
 481         memset(tq->tx_ring.base, 0, tq->tx_ring.size *
 482                sizeof(struct Vmxnet3_TxDesc));
 483         tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
 484         tq->tx_ring.gen = VMXNET3_INIT_GEN;
 485
 486         memset(tq->data_ring.base, 0,
 487                tq->data_ring.size * tq->txdata_desc_size);
 488
 489         /* reset the tx comp ring contents to 0 and reset comp ring states */
 490         memset(tq->comp_ring.base, 0, tq->comp_ring.size *
 491                sizeof(struct Vmxnet3_TxCompDesc));
 492         tq->comp_ring.next2proc = 0;
 493         tq->comp_ring.gen = VMXNET3_INIT_GEN;
 494
 495         /* reset the bookkeeping data */
 496         memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
 497         for (i = 0; i < tq->tx_ring.size; i++)
 498                 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
 499
 500         /* stats are not reset */
 501 }
 502
 503
 504 static int
 505 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
 506                   struct vmxnet3_adapter *adapter)
 507 {
 508         size_t sz;
 509
 510         BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
 511                tq->comp_ring.base || tq->buf_info);
 512
 513         tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
 514                         tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
 515                         &tq->tx_ring.basePA, GFP_KERNEL);
 516         if (!tq->tx_ring.base) {
 517                 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
 518                 goto err;
 519         }
 520
 521         tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
 522                         tq->data_ring.size * tq->txdata_desc_size,
 523                         &tq->data_ring.basePA, GFP_KERNEL);
 524         if (!tq->data_ring.base) {
 525                 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
 526                 goto err;
 527         }
 528
 529         tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
 530                         tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
 531                         &tq->comp_ring.basePA, GFP_KERNEL);
 532         if (!tq->comp_ring.base) {
 533                 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
 534                 goto err;
 535         }
 536
 537         sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
 538         tq->buf_info = dma_alloc_coherent(&adapter->pdev->dev, sz,
 539                                           &tq->buf_info_pa, GFP_KERNEL);
 540         if (!tq->buf_info)
 541                 goto err;
 542
 543         return 0;
 544
 545 err:
 546         vmxnet3_tq_destroy(tq, adapter);
 547         return -ENOMEM;
 548 }
 549
 550 static void
 551 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
 552 {
 553         int i;
 554
 555         for (i = 0; i < adapter->num_tx_queues; i++)
 556                 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
 557 }
 558
 559 /*
 560  *    starting from ring->next2fill, allocate rx buffers for the given ring
 561  *    of the rx queue and update the rx desc. stop after @num_to_alloc buffers
 562  *    are allocated or allocation fails
 563  */
 564
 565 static int
 566 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
 567                         int num_to_alloc, struct vmxnet3_adapter *adapter)
 568 {
 569         int num_allocated = 0;
 570         struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
 571         struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
 572         u32 val;
 573
 574         while (num_allocated <= num_to_alloc) {
 575                 struct vmxnet3_rx_buf_info *rbi;
 576                 union Vmxnet3_GenericDesc *gd;
 577
 578                 rbi = rbi_base + ring->next2fill;
 579                 gd = ring->base + ring->next2fill;
 580
 581                 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
 582                         if (rbi->skb == NULL) {
 583                                 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
 584                                                                        rbi->len,
 585                                                                        GFP_KERNEL);
 586                                 if (unlikely(rbi->skb == NULL)) {
 587                                         rq->stats.rx_buf_alloc_failure++;
 588                                         break;
 589                                 }
 590
 591                                 rbi->dma_addr = dma_map_single(
 592                                                 &adapter->pdev->dev,
 593                                                 rbi->skb->data, rbi->len,
 594                                                 PCI_DMA_FROMDEVICE);
 595                                 if (dma_mapping_error(&adapter->pdev->dev,
 596                                                       rbi->dma_addr)) {
 597                                         dev_kfree_skb_any(rbi->skb);
 598                                         rbi->skb = NULL;
 599                                         rq->stats.rx_buf_alloc_failure++;
 600                                         break;
 601                                 }
 602                         } else {
 603                                 /* rx buffer skipped by the device */
 604                         }
 605                         val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
 606                 } else {
 607                         BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
 608                                rbi->len  != PAGE_SIZE);
 609
 610                         if (rbi->page == NULL) {
 611                                 rbi->page = alloc_page(GFP_ATOMIC);
 612                                 if (unlikely(rbi->page == NULL)) {
 613                                         rq->stats.rx_buf_alloc_failure++;
 614                                         break;
 615                                 }
 616                                 rbi->dma_addr = dma_map_page(
 617                                                 &adapter->pdev->dev,
 618                                                 rbi->page, 0, PAGE_SIZE,
 619                                                 PCI_DMA_FROMDEVICE);
 620                                 if (dma_mapping_error(&adapter->pdev->dev,
 621                                                       rbi->dma_addr)) {
 622                                         put_page(rbi->page);
 623                                         rbi->page = NULL;
 624                                         rq->stats.rx_buf_alloc_failure++;
 625                                         break;
 626                                 }
 627                         } else {
 628                                 /* rx buffers skipped by the device */
 629                         }
 630                         val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
 631                 }
 632
 633                 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
 634                 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
 635                                            | val | rbi->len);
 636
 637                 /* Fill the last buffer but dont mark it ready, or else the
 638                  * device will think that the queue is full */
 639                 if (num_allocated == num_to_alloc)
 640                         break;
 641
 642                 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
 643                 num_allocated++;
 644                 vmxnet3_cmd_ring_adv_next2fill(ring);
 645         }
 646
 647         netdev_dbg(adapter->netdev,
 648                 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
 649                 num_allocated, ring->next2fill, ring->next2comp);
 650
 651         /* so that the device can distinguish a full ring and an empty ring */
 652         BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
 653
 654         return num_allocated;
 655 }
 656
 657
 658 static void
 659 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
 660                     struct vmxnet3_rx_buf_info *rbi)
 661 {
 662         skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
 663
 664         BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
 665
 666         __skb_frag_set_page(frag, rbi->page);
 667         skb_frag_off_set(frag, 0);
 668         skb_frag_size_set(frag, rcd->len);
 669         skb->data_len += rcd->len;
 670         skb->truesize += PAGE_SIZE;
 671         skb_shinfo(skb)->nr_frags++;
 672 }
 673
 674
 675 static int
 676 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
 677                 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
 678                 struct vmxnet3_adapter *adapter)
 679 {
 680         u32 dw2, len;
 681         unsigned long buf_offset;
 682         int i;
 683         union Vmxnet3_GenericDesc *gdesc;
 684         struct vmxnet3_tx_buf_info *tbi = NULL;
 685
 686         BUG_ON(ctx->copy_size > skb_headlen(skb));
 687
 688         /* use the previous gen bit for the SOP desc */
 689         dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
 690
 691         ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
 692         gdesc = ctx->sop_txd; /* both loops below can be skipped */
 693
 694         /* no need to map the buffer if headers are copied */
 695         if (ctx->copy_size) {
 696                 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
 697                                         tq->tx_ring.next2fill *
 698                                         tq->txdata_desc_size);
 699                 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
 700                 ctx->sop_txd->dword[3] = 0;
 701
 702                 tbi = tq->buf_info + tq->tx_ring.next2fill;
 703                 tbi->map_type = VMXNET3_MAP_NONE;
 704
 705                 netdev_dbg(adapter->netdev,
 706                         "txd[%u]: 0x%Lx 0x%x 0x%x\n",
 707                         tq->tx_ring.next2fill,
 708                         le64_to_cpu(ctx->sop_txd->txd.addr),
 709                         ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
 710                 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
 711
 712                 /* use the right gen for non-SOP desc */
 713                 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
 714         }
 715
 716         /* linear part can use multiple tx desc if it's big */
 717         len = skb_headlen(skb) - ctx->copy_size;
 718         buf_offset = ctx->copy_size;
 719         while (len) {
 720                 u32 buf_size;
 721
 722                 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
 723                         buf_size = len;
 724                         dw2 |= len;
 725                 } else {
 726                         buf_size = VMXNET3_MAX_TX_BUF_SIZE;
 727                         /* spec says that for TxDesc.len, 0 == 2^14 */
 728                 }
 729
 730                 tbi = tq->buf_info + tq->tx_ring.next2fill;
 731                 tbi->map_type = VMXNET3_MAP_SINGLE;
 732                 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
 733                                 skb->data + buf_offset, buf_size,
 734                                 PCI_DMA_TODEVICE);
 735                 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
 736                         return -EFAULT;
 737
 738                 tbi->len = buf_size;
 739
 740                 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
 741                 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
 742
 743                 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
 744                 gdesc->dword[2] = cpu_to_le32(dw2);
 745                 gdesc->dword[3] = 0;
 746
 747                 netdev_dbg(adapter->netdev,
 748                         "txd[%u]: 0x%Lx 0x%x 0x%x\n",
 749                         tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
 750                         le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
 751                 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
 752                 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
 753
 754                 len -= buf_size;
 755                 buf_offset += buf_size;
 756         }
 757
 758         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 759                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 760                 u32 buf_size;
 761
 762                 buf_offset = 0;
 763                 len = skb_frag_size(frag);
 764                 while (len) {
 765                         tbi = tq->buf_info + tq->tx_ring.next2fill;
 766                         if (len < VMXNET3_MAX_TX_BUF_SIZE) {
 767                                 buf_size = len;
 768                                 dw2 |= len;
 769                         } else {
 770                                 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
 771                                 /* spec says that for TxDesc.len, 0 == 2^14 */
 772                         }
 773                         tbi->map_type = VMXNET3_MAP_PAGE;
 774                         tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
 775                                                          buf_offset, buf_size,
 776                                                          DMA_TO_DEVICE);
 777                         if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
 778                                 return -EFAULT;
 779
 780                         tbi->len = buf_size;
 781
 782                         gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
 783                         BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
 784
 785                         gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
 786                         gdesc->dword[2] = cpu_to_le32(dw2);
 787                         gdesc->dword[3] = 0;
 788
 789                         netdev_dbg(adapter->netdev,
 790                                 "txd[%u]: 0x%llx %u %u\n",
 791                                 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
 792                                 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
 793                         vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
 794                         dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
 795
 796                         len -= buf_size;
 797                         buf_offset += buf_size;
 798                 }
 799         }
 800
 801         ctx->eop_txd = gdesc;
 802
 803         /* set the last buf_info for the pkt */
 804         tbi->skb = skb;
 805         tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
 806
 807         return 0;
 808 }
 809
 810
 811 /* Init all tx queues */
 812 static void
 813 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
 814 {
 815         int i;
 816
 817         for (i = 0; i < adapter->num_tx_queues; i++)
 818                 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
 819 }
 820
 821
 822 /*
 823  *    parse relevant protocol headers:
 824  *      For a tso pkt, relevant headers are L2/3/4 including options
 825  *      For a pkt requesting csum offloading, they are L2/3 and may include L4
 826  *      if it's a TCP/UDP pkt
 827  *
 828  * Returns:
 829  *    -1:  error happens during parsing
 830  *     0:  protocol headers parsed, but too big to be copied
 831  *     1:  protocol headers parsed and copied
 832  *
 833  * Other effects:
 834  *    1. related *ctx fields are updated.
 835  *    2. ctx->copy_size is # of bytes copied
 836  *    3. the portion to be copied is guaranteed to be in the linear part
 837  *
 838  */
 839 static int
 840 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
 841                   struct vmxnet3_tx_ctx *ctx,
 842                   struct vmxnet3_adapter *adapter)
 843 {
 844         u8 protocol = 0;
 845
 846         if (ctx->mss) { /* TSO */
 847                 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
 848                         ctx->l4_offset = skb_inner_transport_offset(skb);
 849                         ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
 850                         ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
 851                 } else {
 852                         ctx->l4_offset = skb_transport_offset(skb);
 853                         ctx->l4_hdr_size = tcp_hdrlen(skb);
 854                         ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
 855                 }
 856         } else {
 857                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
 858                         /* For encap packets, skb_checksum_start_offset refers
 859                          * to inner L4 offset. Thus, below works for encap as
 860                          * well as non-encap case
 861                          */
 862                         ctx->l4_offset = skb_checksum_start_offset(skb);
 863
 864                         if (VMXNET3_VERSION_GE_4(adapter) &&
 865                             skb->encapsulation) {
 866                                 struct iphdr *iph = inner_ip_hdr(skb);
 867
 868                                 if (iph->version == 4) {
 869                                         protocol = iph->protocol;
 870                                 } else {
 871                                         const struct ipv6hdr *ipv6h;
 872
 873                                         ipv6h = inner_ipv6_hdr(skb);
 874                                         protocol = ipv6h->nexthdr;
 875                                 }
 876                         } else {
 877                                 if (ctx->ipv4) {
 878                                         const struct iphdr *iph = ip_hdr(skb);
 879
 880                                         protocol = iph->protocol;
 881                                 } else if (ctx->ipv6) {
 882                                         const struct ipv6hdr *ipv6h;
 883
 884                                         ipv6h = ipv6_hdr(skb);
 885                                         protocol = ipv6h->nexthdr;
 886                                 }
 887                         }
 888
 889                         switch (protocol) {
 890                         case IPPROTO_TCP:
 891                                 ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) :
 892                                                    tcp_hdrlen(skb);
 893                                 break;
 894                         case IPPROTO_UDP:
 895                                 ctx->l4_hdr_size = sizeof(struct udphdr);
 896                                 break;
 897                         default:
 898                                 ctx->l4_hdr_size = 0;
 899                                 break;
 900                         }
 901
 902                         ctx->copy_size = min(ctx->l4_offset +
 903                                          ctx->l4_hdr_size, skb->len);
 904                 } else {
 905                         ctx->l4_offset = 0;
 906                         ctx->l4_hdr_size = 0;
 907                         /* copy as much as allowed */
 908                         ctx->copy_size = min_t(unsigned int,
 909                                                tq->txdata_desc_size,
 910                                                skb_headlen(skb));
 911                 }
 912
 913                 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
 914                         ctx->copy_size = skb->len;
 915
 916                 /* make sure headers are accessible directly */
 917                 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
 918                         goto err;
 919         }
 920
 921         if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
 922                 tq->stats.oversized_hdr++;
 923                 ctx->copy_size = 0;
 924                 return 0;
 925         }
 926
 927         return 1;
 928 err:
 929         return -1;
 930 }
 931
 932 /*
 933  *    copy relevant protocol headers to the transmit ring:
 934  *      For a tso pkt, relevant headers are L2/3/4 including options
 935  *      For a pkt requesting csum offloading, they are L2/3 and may include L4
 936  *      if it's a TCP/UDP pkt
 937  *
 938  *
 939  *    Note that this requires that vmxnet3_parse_hdr be called first to set the
 940  *      appropriate bits in ctx first
 941  */
 942 static void
 943 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
 944                  struct vmxnet3_tx_ctx *ctx,
 945                  struct vmxnet3_adapter *adapter)
 946 {
 947         struct Vmxnet3_TxDataDesc *tdd;
 948
 949         tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
 950                                             tq->tx_ring.next2fill *
 951                                             tq->txdata_desc_size);
 952
 953         memcpy(tdd->data, skb->data, ctx->copy_size);
 954         netdev_dbg(adapter->netdev,
 955                 "copy %u bytes to dataRing[%u]\n",
 956                 ctx->copy_size, tq->tx_ring.next2fill);
 957 }
 958
 959
 960 static void
 961 vmxnet3_prepare_inner_tso(struct sk_buff *skb,
 962                           struct vmxnet3_tx_ctx *ctx)
 963 {
 964         struct tcphdr *tcph = inner_tcp_hdr(skb);
 965         struct iphdr *iph = inner_ip_hdr(skb);
 966
 967         if (iph->version == 4) {
 968                 iph->check = 0;
 969                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
 970                                                  IPPROTO_TCP, 0);
 971         } else {
 972                 struct ipv6hdr *iph = inner_ipv6_hdr(skb);
 973
 974                 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
 975                                                IPPROTO_TCP, 0);
 976         }
 977 }
 978
 979 static void
 980 vmxnet3_prepare_tso(struct sk_buff *skb,
 981                     struct vmxnet3_tx_ctx *ctx)
 982 {
 983         struct tcphdr *tcph = tcp_hdr(skb);
 984
 985         if (ctx->ipv4) {
 986                 struct iphdr *iph = ip_hdr(skb);
 987
 988                 iph->check = 0;
 989                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
 990                                                  IPPROTO_TCP, 0);
 991         } else if (ctx->ipv6) {
 992                 tcp_v6_gso_csum_prep(skb);
 993         }
 994 }
 995
 996 static int txd_estimate(const struct sk_buff *skb)
 997 {
 998         int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
 999         int i;
1000
1001         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1002                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1003
1004                 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
1005         }
1006         return count;
1007 }
1008
1009 /*
1010  * Transmits a pkt thru a given tq
1011  * Returns:
1012  *    NETDEV_TX_OK:      descriptors are setup successfully
1013  *    NETDEV_TX_OK:      error occurred, the pkt is dropped
1014  *    NETDEV_TX_BUSY:    tx ring is full, queue is stopped
1015  *
1016  * Side-effects:
1017  *    1. tx ring may be changed
1018  *    2. tq stats may be updated accordingly
1019  *    3. shared->txNumDeferred may be updated
1020  */
1021
1022 static int
1023 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1024                 struct vmxnet3_adapter *adapter, struct net_device *netdev)
1025 {
1026         int ret;
1027         u32 count;
1028         int num_pkts;
1029         int tx_num_deferred;
1030         unsigned long flags;
1031         struct vmxnet3_tx_ctx ctx;
1032         union Vmxnet3_GenericDesc *gdesc;
1033 #ifdef __BIG_ENDIAN_BITFIELD
1034         /* Use temporary descriptor to avoid touching bits multiple times */
1035         union Vmxnet3_GenericDesc tempTxDesc;
1036 #endif
1037
1038         count = txd_estimate(skb);
1039
1040         ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
1041         ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
1042
1043         ctx.mss = skb_shinfo(skb)->gso_size;
1044         if (ctx.mss) {
1045                 if (skb_header_cloned(skb)) {
1046                         if (unlikely(pskb_expand_head(skb, 0, 0,
1047                                                       GFP_ATOMIC) != 0)) {
1048                                 tq->stats.drop_tso++;
1049                                 goto drop_pkt;
1050                         }
1051                         tq->stats.copy_skb_header++;
1052                 }
1053                 if (skb->encapsulation) {
1054                         vmxnet3_prepare_inner_tso(skb, &ctx);
1055                 } else {
1056                         vmxnet3_prepare_tso(skb, &ctx);
1057                 }
1058         } else {
1059                 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1060
1061                         /* non-tso pkts must not use more than
1062                          * VMXNET3_MAX_TXD_PER_PKT entries
1063                          */
1064                         if (skb_linearize(skb) != 0) {
1065                                 tq->stats.drop_too_many_frags++;
1066                                 goto drop_pkt;
1067                         }
1068                         tq->stats.linearized++;
1069
1070                         /* recalculate the # of descriptors to use */
1071                         count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1072                 }
1073         }
1074
1075         ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
1076         if (ret >= 0) {
1077                 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1078                 /* hdrs parsed, check against other limits */
1079                 if (ctx.mss) {
1080                         if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
1081                                      VMXNET3_MAX_TX_BUF_SIZE)) {
1082                                 tq->stats.drop_oversized_hdr++;
1083                                 goto drop_pkt;
1084                         }
1085                 } else {
1086                         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1087                                 if (unlikely(ctx.l4_offset +
1088                                              skb->csum_offset >
1089                                              VMXNET3_MAX_CSUM_OFFSET)) {
1090                                         tq->stats.drop_oversized_hdr++;
1091                                         goto drop_pkt;
1092                                 }
1093                         }
1094                 }
1095         } else {
1096                 tq->stats.drop_hdr_inspect_err++;
1097                 goto drop_pkt;
1098         }
1099
1100         spin_lock_irqsave(&tq->tx_lock, flags);
1101
1102         if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1103                 tq->stats.tx_ring_full++;
1104                 netdev_dbg(adapter->netdev,
1105                         "tx queue stopped on %s, next2comp %u"
1106                         " next2fill %u\n", adapter->netdev->name,
1107                         tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1108
1109                 vmxnet3_tq_stop(tq, adapter);
1110                 spin_unlock_irqrestore(&tq->tx_lock, flags);
1111                 return NETDEV_TX_BUSY;
1112         }
1113
1114
1115         vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1116
1117         /* fill tx descs related to addr & len */
1118         if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1119                 goto unlock_drop_pkt;
1120
1121         /* setup the EOP desc */
1122         ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1123
1124         /* setup the SOP desc */
1125 #ifdef __BIG_ENDIAN_BITFIELD
1126         gdesc = &tempTxDesc;
1127         gdesc->dword[2] = ctx.sop_txd->dword[2];
1128         gdesc->dword[3] = ctx.sop_txd->dword[3];
1129 #else
1130         gdesc = ctx.sop_txd;
1131 #endif
1132         tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
1133         if (ctx.mss) {
1134                 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
1135                         gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1136                         gdesc->txd.om = VMXNET3_OM_ENCAP;
1137                         gdesc->txd.msscof = ctx.mss;
1138
1139                         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1140                                 gdesc->txd.oco = 1;
1141                 } else {
1142                         gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1143                         gdesc->txd.om = VMXNET3_OM_TSO;
1144                         gdesc->txd.msscof = ctx.mss;
1145                 }
1146                 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1147         } else {
1148                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1149                         if (VMXNET3_VERSION_GE_4(adapter) &&
1150                             skb->encapsulation) {
1151                                 gdesc->txd.hlen = ctx.l4_offset +
1152                                                   ctx.l4_hdr_size;
1153                                 gdesc->txd.om = VMXNET3_OM_ENCAP;
1154                                 gdesc->txd.msscof = 0;          /* Reserved */
1155                         } else {
1156                                 gdesc->txd.hlen = ctx.l4_offset;
1157                                 gdesc->txd.om = VMXNET3_OM_CSUM;
1158                                 gdesc->txd.msscof = ctx.l4_offset +
1159                                                     skb->csum_offset;
1160                         }
1161                 } else {
1162                         gdesc->txd.om = 0;
1163                         gdesc->txd.msscof = 0;
1164                 }
1165                 num_pkts = 1;
1166         }
1167         le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
1168         tx_num_deferred += num_pkts;
1169
1170         if (skb_vlan_tag_present(skb)) {
1171                 gdesc->txd.ti = 1;
1172                 gdesc->txd.tci = skb_vlan_tag_get(skb);
1173         }
1174
1175         /* Ensure that the write to (&gdesc->txd)->gen will be observed after
1176          * all other writes to &gdesc->txd.
1177          */
1178         dma_wmb();
1179
1180         /* finally flips the GEN bit of the SOP desc. */
1181         gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1182                                                   VMXNET3_TXD_GEN);
1183 #ifdef __BIG_ENDIAN_BITFIELD
1184         /* Finished updating in bitfields of Tx Desc, so write them in original
1185          * place.
1186          */
1187         vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1188                            (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1189         gdesc = ctx.sop_txd;
1190 #endif
1191         netdev_dbg(adapter->netdev,
1192                 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1193                 (u32)(ctx.sop_txd -
1194                 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1195                 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1196
1197         spin_unlock_irqrestore(&tq->tx_lock, flags);
1198
1199         if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
1200                 tq->shared->txNumDeferred = 0;
1201                 VMXNET3_WRITE_BAR0_REG(adapter,
1202                                        VMXNET3_REG_TXPROD + tq->qid * 8,
1203                                        tq->tx_ring.next2fill);
1204         }
1205
1206         return NETDEV_TX_OK;
1207
1208 unlock_drop_pkt:
1209         spin_unlock_irqrestore(&tq->tx_lock, flags);
1210 drop_pkt:
1211         tq->stats.drop_total++;
1212         dev_kfree_skb_any(skb);
1213         return NETDEV_TX_OK;
1214 }
1215
1216
1217 static netdev_tx_t
1218 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1219 {
1220         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1221
1222         BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1223         return vmxnet3_tq_xmit(skb,
1224                                &adapter->tx_queue[skb->queue_mapping],
1225                                adapter, netdev);
1226 }
1227
1228
1229 static void
1230 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1231                 struct sk_buff *skb,
1232                 union Vmxnet3_GenericDesc *gdesc)
1233 {
1234         if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1235                 if (gdesc->rcd.v4 &&
1236                     (le32_to_cpu(gdesc->dword[3]) &
1237                      VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1238                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1239                         WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1240                                      !(le32_to_cpu(gdesc->dword[0]) &
1241                                      (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1242                         WARN_ON_ONCE(gdesc->rcd.frg &&
1243                                      !(le32_to_cpu(gdesc->dword[0]) &
1244                                      (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1245                 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1246                                              (1 << VMXNET3_RCD_TUC_SHIFT))) {
1247                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1248                         WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1249                                      !(le32_to_cpu(gdesc->dword[0]) &
1250                                      (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1251                         WARN_ON_ONCE(gdesc->rcd.frg &&
1252                                      !(le32_to_cpu(gdesc->dword[0]) &
1253                                      (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1254                 } else {
1255                         if (gdesc->rcd.csum) {
1256                                 skb->csum = htons(gdesc->rcd.csum);
1257                                 skb->ip_summed = CHECKSUM_PARTIAL;
1258                         } else {
1259                                 skb_checksum_none_assert(skb);
1260                         }
1261                 }
1262         } else {
1263                 skb_checksum_none_assert(skb);
1264         }
1265 }
1266
1267
1268 static void
1269 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1270                  struct vmxnet3_rx_ctx *ctx,  struct vmxnet3_adapter *adapter)
1271 {
1272         rq->stats.drop_err++;
1273         if (!rcd->fcs)
1274                 rq->stats.drop_fcs++;
1275
1276         rq->stats.drop_total++;
1277
1278         /*
1279          * We do not unmap and chain the rx buffer to the skb.
1280          * We basically pretend this buffer is not used and will be recycled
1281          * by vmxnet3_rq_alloc_rx_buf()
1282          */
1283
1284         /*
1285          * ctx->skb may be NULL if this is the first and the only one
1286          * desc for the pkt
1287          */
1288         if (ctx->skb)
1289                 dev_kfree_skb_irq(ctx->skb);
1290
1291         ctx->skb = NULL;
1292 }
1293
1294
1295 static u32
1296 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1297                     union Vmxnet3_GenericDesc *gdesc)
1298 {
1299         u32 hlen, maplen;
1300         union {
1301                 void *ptr;
1302                 struct ethhdr *eth;
1303                 struct vlan_ethhdr *veth;
1304                 struct iphdr *ipv4;
1305                 struct ipv6hdr *ipv6;
1306                 struct tcphdr *tcp;
1307         } hdr;
1308         BUG_ON(gdesc->rcd.tcp == 0);
1309
1310         maplen = skb_headlen(skb);
1311         if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1312                 return 0;
1313
1314         if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
1315             skb->protocol == cpu_to_be16(ETH_P_8021AD))
1316                 hlen = sizeof(struct vlan_ethhdr);
1317         else
1318                 hlen = sizeof(struct ethhdr);
1319
1320         hdr.eth = eth_hdr(skb);
1321         if (gdesc->rcd.v4) {
1322                 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
1323                        hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
1324                 hdr.ptr += hlen;
1325                 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1326                 hlen = hdr.ipv4->ihl << 2;
1327                 hdr.ptr += hdr.ipv4->ihl << 2;
1328         } else if (gdesc->rcd.v6) {
1329                 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
1330                        hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
1331                 hdr.ptr += hlen;
1332                 /* Use an estimated value, since we also need to handle
1333                  * TSO case.
1334                  */
1335                 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1336                         return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1337                 hlen = sizeof(struct ipv6hdr);
1338                 hdr.ptr += sizeof(struct ipv6hdr);
1339         } else {
1340                 /* Non-IP pkt, dont estimate header length */
1341                 return 0;
1342         }
1343
1344         if (hlen + sizeof(struct tcphdr) > maplen)
1345                 return 0;
1346
1347         return (hlen + (hdr.tcp->doff << 2));
1348 }
1349
1350 static int
1351 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1352                        struct vmxnet3_adapter *adapter, int quota)
1353 {
1354         static const u32 rxprod_reg[2] = {
1355                 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1356         };
1357         u32 num_pkts = 0;
1358         bool skip_page_frags = false;
1359         struct Vmxnet3_RxCompDesc *rcd;
1360         struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1361         u16 segCnt = 0, mss = 0;
1362 #ifdef __BIG_ENDIAN_BITFIELD
1363         struct Vmxnet3_RxDesc rxCmdDesc;
1364         struct Vmxnet3_RxCompDesc rxComp;
1365 #endif
1366         vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1367                           &rxComp);
1368         while (rcd->gen == rq->comp_ring.gen) {
1369                 struct vmxnet3_rx_buf_info *rbi;
1370                 struct sk_buff *skb, *new_skb = NULL;
1371                 struct page *new_page = NULL;
1372                 dma_addr_t new_dma_addr;
1373                 int num_to_alloc;
1374                 struct Vmxnet3_RxDesc *rxd;
1375                 u32 idx, ring_idx;
1376                 struct vmxnet3_cmd_ring *ring = NULL;
1377                 if (num_pkts >= quota) {
1378                         /* we may stop even before we see the EOP desc of
1379                          * the current pkt
1380                          */
1381                         break;
1382                 }
1383
1384                 /* Prevent any rcd field from being (speculatively) read before
1385                  * rcd->gen is read.
1386                  */
1387                 dma_rmb();
1388
1389                 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1390                        rcd->rqID != rq->dataRingQid);
1391                 idx = rcd->rxdIdx;
1392                 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
1393                 ring = rq->rx_ring + ring_idx;
1394                 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1395                                   &rxCmdDesc);
1396                 rbi = rq->buf_info[ring_idx] + idx;
1397
1398                 BUG_ON(rxd->addr != rbi->dma_addr ||
1399                        rxd->len != rbi->len);
1400
1401                 if (unlikely(rcd->eop && rcd->err)) {
1402                         vmxnet3_rx_error(rq, rcd, ctx, adapter);
1403                         goto rcd_done;
1404                 }
1405
1406                 if (rcd->sop) { /* first buf of the pkt */
1407                         bool rxDataRingUsed;
1408                         u16 len;
1409
1410                         BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1411                                (rcd->rqID != rq->qid &&
1412                                 rcd->rqID != rq->dataRingQid));
1413
1414                         BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1415                         BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1416
1417                         if (unlikely(rcd->len == 0)) {
1418                                 /* Pretend the rx buffer is skipped. */
1419                                 BUG_ON(!(rcd->sop && rcd->eop));
1420                                 netdev_dbg(adapter->netdev,
1421                                         "rxRing[%u][%u] 0 length\n",
1422                                         ring_idx, idx);
1423                                 goto rcd_done;
1424                         }
1425
1426                         skip_page_frags = false;
1427                         ctx->skb = rbi->skb;
1428
1429                         rxDataRingUsed =
1430                                 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1431                         len = rxDataRingUsed ? rcd->len : rbi->len;
1432                         new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1433                                                             len);
1434                         if (new_skb == NULL) {
1435                                 /* Skb allocation failed, do not handover this
1436                                  * skb to stack. Reuse it. Drop the existing pkt
1437                                  */
1438                                 rq->stats.rx_buf_alloc_failure++;
1439                                 ctx->skb = NULL;
1440                                 rq->stats.drop_total++;
1441                                 skip_page_frags = true;
1442                                 goto rcd_done;
1443                         }
1444
1445                         if (rxDataRingUsed) {
1446                                 size_t sz;
1447
1448                                 BUG_ON(rcd->len > rq->data_ring.desc_size);
1449
1450                                 ctx->skb = new_skb;
1451                                 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1452                                 memcpy(new_skb->data,
1453                                        &rq->data_ring.base[sz], rcd->len);
1454                         } else {
1455                                 ctx->skb = rbi->skb;
1456
1457                                 new_dma_addr =
1458                                         dma_map_single(&adapter->pdev->dev,
1459                                                        new_skb->data, rbi->len,
1460                                                        PCI_DMA_FROMDEVICE);
1461                                 if (dma_mapping_error(&adapter->pdev->dev,
1462                                                       new_dma_addr)) {
1463                                         dev_kfree_skb(new_skb);
1464                                         /* Skb allocation failed, do not
1465                                          * handover this skb to stack. Reuse
1466                                          * it. Drop the existing pkt.
1467                                          */
1468                                         rq->stats.rx_buf_alloc_failure++;
1469                                         ctx->skb = NULL;
1470                                         rq->stats.drop_total++;
1471                                         skip_page_frags = true;
1472                                         goto rcd_done;
1473                                 }
1474
1475                                 dma_unmap_single(&adapter->pdev->dev,
1476                                                  rbi->dma_addr,
1477                                                  rbi->len,
1478                                                  PCI_DMA_FROMDEVICE);
1479
1480                                 /* Immediate refill */
1481                                 rbi->skb = new_skb;
1482                                 rbi->dma_addr = new_dma_addr;
1483                                 rxd->addr = cpu_to_le64(rbi->dma_addr);
1484                                 rxd->len = rbi->len;
1485                         }
1486
1487 #ifdef VMXNET3_RSS
1488                         if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1489                             (adapter->netdev->features & NETIF_F_RXHASH))
1490                                 skb_set_hash(ctx->skb,
1491                                              le32_to_cpu(rcd->rssHash),
1492                                              PKT_HASH_TYPE_L3);
1493 #endif
1494                         skb_put(ctx->skb, rcd->len);
1495
1496                         if (VMXNET3_VERSION_GE_2(adapter) &&
1497                             rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1498                                 struct Vmxnet3_RxCompDescExt *rcdlro;
1499                                 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1500
1501                                 segCnt = rcdlro->segCnt;
1502                                 WARN_ON_ONCE(segCnt == 0);
1503                                 mss = rcdlro->mss;
1504                                 if (unlikely(segCnt <= 1))
1505                                         segCnt = 0;
1506                         } else {
1507                                 segCnt = 0;
1508                         }
1509                 } else {
1510                         BUG_ON(ctx->skb == NULL && !skip_page_frags);
1511
1512                         /* non SOP buffer must be type 1 in most cases */
1513                         BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1514                         BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1515
1516                         /* If an sop buffer was dropped, skip all
1517                          * following non-sop fragments. They will be reused.
1518                          */
1519                         if (skip_page_frags)
1520                                 goto rcd_done;
1521
1522                         if (rcd->len) {
1523                                 new_page = alloc_page(GFP_ATOMIC);
1524                                 /* Replacement page frag could not be allocated.
1525                                  * Reuse this page. Drop the pkt and free the
1526                                  * skb which contained this page as a frag. Skip
1527                                  * processing all the following non-sop frags.
1528                                  */
1529                                 if (unlikely(!new_page)) {
1530                                         rq->stats.rx_buf_alloc_failure++;
1531                                         dev_kfree_skb(ctx->skb);
1532                                         ctx->skb = NULL;
1533                                         skip_page_frags = true;
1534                                         goto rcd_done;
1535                                 }
1536                                 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1537                                                             new_page,
1538                                                             0, PAGE_SIZE,
1539                                                             PCI_DMA_FROMDEVICE);
1540                                 if (dma_mapping_error(&adapter->pdev->dev,
1541                                                       new_dma_addr)) {
1542                                         put_page(new_page);
1543                                         rq->stats.rx_buf_alloc_failure++;
1544                                         dev_kfree_skb(ctx->skb);
1545                                         ctx->skb = NULL;
1546                                         skip_page_frags = true;
1547                                         goto rcd_done;
1548                                 }
1549
1550                                 dma_unmap_page(&adapter->pdev->dev,
1551                                                rbi->dma_addr, rbi->len,
1552                                                PCI_DMA_FROMDEVICE);
1553
1554                                 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1555
1556                                 /* Immediate refill */
1557                                 rbi->page = new_page;
1558                                 rbi->dma_addr = new_dma_addr;
1559                                 rxd->addr = cpu_to_le64(rbi->dma_addr);
1560                                 rxd->len = rbi->len;
1561                         }
1562                 }
1563
1564
1565                 skb = ctx->skb;
1566                 if (rcd->eop) {
1567                         u32 mtu = adapter->netdev->mtu;
1568                         skb->len += skb->data_len;
1569
1570                         vmxnet3_rx_csum(adapter, skb,
1571                                         (union Vmxnet3_GenericDesc *)rcd);
1572                         skb->protocol = eth_type_trans(skb, adapter->netdev);
1573                         if (!rcd->tcp ||
1574                             !(adapter->netdev->features & NETIF_F_LRO))
1575                                 goto not_lro;
1576
1577                         if (segCnt != 0 && mss != 0) {
1578                                 skb_shinfo(skb)->gso_type = rcd->v4 ?
1579                                         SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1580                                 skb_shinfo(skb)->gso_size = mss;
1581                                 skb_shinfo(skb)->gso_segs = segCnt;
1582                         } else if (segCnt != 0 || skb->len > mtu) {
1583                                 u32 hlen;
1584
1585                                 hlen = vmxnet3_get_hdr_len(adapter, skb,
1586                                         (union Vmxnet3_GenericDesc *)rcd);
1587                                 if (hlen == 0)
1588                                         goto not_lro;
1589
1590                                 skb_shinfo(skb)->gso_type =
1591                                         rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1592                                 if (segCnt != 0) {
1593                                         skb_shinfo(skb)->gso_segs = segCnt;
1594                                         skb_shinfo(skb)->gso_size =
1595                                                 DIV_ROUND_UP(skb->len -
1596                                                         hlen, segCnt);
1597                                 } else {
1598                                         skb_shinfo(skb)->gso_size = mtu - hlen;
1599                                 }
1600                         }
1601 not_lro:
1602                         if (unlikely(rcd->ts))
1603                                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
1604
1605                         if (adapter->netdev->features & NETIF_F_LRO)
1606                                 netif_receive_skb(skb);
1607                         else
1608                                 napi_gro_receive(&rq->napi, skb);
1609
1610                         ctx->skb = NULL;
1611                         num_pkts++;
1612                 }
1613
1614 rcd_done:
1615                 /* device may have skipped some rx descs */
1616                 ring->next2comp = idx;
1617                 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1618                 ring = rq->rx_ring + ring_idx;
1619
1620                 /* Ensure that the writes to rxd->gen bits will be observed
1621                  * after all other writes to rxd objects.
1622                  */
1623                 dma_wmb();
1624
1625                 while (num_to_alloc) {
1626                         vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1627                                           &rxCmdDesc);
1628                         BUG_ON(!rxd->addr);
1629
1630                         /* Recv desc is ready to be used by the device */
1631                         rxd->gen = ring->gen;
1632                         vmxnet3_cmd_ring_adv_next2fill(ring);
1633                         num_to_alloc--;
1634                 }
1635
1636                 /* if needed, update the register */
1637                 if (unlikely(rq->shared->updateRxProd)) {
1638                         VMXNET3_WRITE_BAR0_REG(adapter,
1639                                                rxprod_reg[ring_idx] + rq->qid * 8,
1640                                                ring->next2fill);
1641                 }
1642
1643                 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1644                 vmxnet3_getRxComp(rcd,
1645                                   &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1646         }
1647
1648         return num_pkts;
1649 }
1650
1651
1652 static void
1653 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1654                    struct vmxnet3_adapter *adapter)
1655 {
1656         u32 i, ring_idx;
1657         struct Vmxnet3_RxDesc *rxd;
1658
1659         /* ring has already been cleaned up */
1660         if (!rq->rx_ring[0].base)
1661                 return;
1662
1663         for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1664                 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1665 #ifdef __BIG_ENDIAN_BITFIELD
1666                         struct Vmxnet3_RxDesc rxDesc;
1667 #endif
1668                         vmxnet3_getRxDesc(rxd,
1669                                 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1670
1671                         if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1672                                         rq->buf_info[ring_idx][i].skb) {
1673                                 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
1674                                                  rxd->len, PCI_DMA_FROMDEVICE);
1675                                 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1676                                 rq->buf_info[ring_idx][i].skb = NULL;
1677                         } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1678                                         rq->buf_info[ring_idx][i].page) {
1679                                 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
1680                                                rxd->len, PCI_DMA_FROMDEVICE);
1681                                 put_page(rq->buf_info[ring_idx][i].page);
1682                                 rq->buf_info[ring_idx][i].page = NULL;
1683                         }
1684                 }
1685
1686                 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1687                 rq->rx_ring[ring_idx].next2fill =
1688                                         rq->rx_ring[ring_idx].next2comp = 0;
1689         }
1690
1691         rq->comp_ring.gen = VMXNET3_INIT_GEN;
1692         rq->comp_ring.next2proc = 0;
1693 }
1694
1695
1696 static void
1697 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1698 {
1699         int i;
1700
1701         for (i = 0; i < adapter->num_rx_queues; i++)
1702                 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1703 }
1704
1705
1706 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1707                                struct vmxnet3_adapter *adapter)
1708 {
1709         int i;
1710         int j;
1711
1712         /* all rx buffers must have already been freed */
1713         for (i = 0; i < 2; i++) {
1714                 if (rq->buf_info[i]) {
1715                         for (j = 0; j < rq->rx_ring[i].size; j++)
1716                                 BUG_ON(rq->buf_info[i][j].page != NULL);
1717                 }
1718         }
1719
1720
1721         for (i = 0; i < 2; i++) {
1722                 if (rq->rx_ring[i].base) {
1723                         dma_free_coherent(&adapter->pdev->dev,
1724                                           rq->rx_ring[i].size
1725                                           * sizeof(struct Vmxnet3_RxDesc),
1726                                           rq->rx_ring[i].base,
1727                                           rq->rx_ring[i].basePA);
1728                         rq->rx_ring[i].base = NULL;
1729                 }
1730         }
1731
1732         if (rq->data_ring.base) {
1733                 dma_free_coherent(&adapter->pdev->dev,
1734                                   rq->rx_ring[0].size * rq->data_ring.desc_size,
1735                                   rq->data_ring.base, rq->data_ring.basePA);
1736                 rq->data_ring.base = NULL;
1737         }
1738
1739         if (rq->comp_ring.base) {
1740                 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1741                                   * sizeof(struct Vmxnet3_RxCompDesc),
1742                                   rq->comp_ring.base, rq->comp_ring.basePA);
1743                 rq->comp_ring.base = NULL;
1744         }
1745
1746         if (rq->buf_info[0]) {
1747                 size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
1748                         (rq->rx_ring[0].size + rq->rx_ring[1].size);
1749                 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
1750                                   rq->buf_info_pa);
1751                 rq->buf_info[0] = rq->buf_info[1] = NULL;
1752         }
1753 }
1754
1755 static void
1756 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1757 {
1758         int i;
1759
1760         for (i = 0; i < adapter->num_rx_queues; i++) {
1761                 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1762
1763                 if (rq->data_ring.base) {
1764                         dma_free_coherent(&adapter->pdev->dev,
1765                                           (rq->rx_ring[0].size *
1766                                           rq->data_ring.desc_size),
1767                                           rq->data_ring.base,
1768                                           rq->data_ring.basePA);
1769                         rq->data_ring.base = NULL;
1770                         rq->data_ring.desc_size = 0;
1771                 }
1772         }
1773 }
1774
1775 static int
1776 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1777                 struct vmxnet3_adapter  *adapter)
1778 {
1779         int i;
1780
1781         /* initialize buf_info */
1782         for (i = 0; i < rq->rx_ring[0].size; i++) {
1783
1784                 /* 1st buf for a pkt is skbuff */
1785                 if (i % adapter->rx_buf_per_pkt == 0) {
1786                         rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1787                         rq->buf_info[0][i].len = adapter->skb_buf_size;
1788                 } else { /* subsequent bufs for a pkt is frag */
1789                         rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1790                         rq->buf_info[0][i].len = PAGE_SIZE;
1791                 }
1792         }
1793         for (i = 0; i < rq->rx_ring[1].size; i++) {
1794                 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1795                 rq->buf_info[1][i].len = PAGE_SIZE;
1796         }
1797
1798         /* reset internal state and allocate buffers for both rings */
1799         for (i = 0; i < 2; i++) {
1800                 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1801
1802                 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1803                        sizeof(struct Vmxnet3_RxDesc));
1804                 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1805         }
1806         if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1807                                     adapter) == 0) {
1808                 /* at least has 1 rx buffer for the 1st ring */
1809                 return -ENOMEM;
1810         }
1811         vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1812
1813         /* reset the comp ring */
1814         rq->comp_ring.next2proc = 0;
1815         memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1816                sizeof(struct Vmxnet3_RxCompDesc));
1817         rq->comp_ring.gen = VMXNET3_INIT_GEN;
1818
1819         /* reset rxctx */
1820         rq->rx_ctx.skb = NULL;
1821
1822         /* stats are not reset */
1823         return 0;
1824 }
1825
1826
1827 static int
1828 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1829 {
1830         int i, err = 0;
1831
1832         for (i = 0; i < adapter->num_rx_queues; i++) {
1833                 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1834                 if (unlikely(err)) {
1835                         dev_err(&adapter->netdev->dev, "%s: failed to "
1836                                 "initialize rx queue%i\n",
1837                                 adapter->netdev->name, i);
1838                         break;
1839                 }
1840         }
1841         return err;
1842
1843 }
1844
1845
1846 static int
1847 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1848 {
1849         int i;
1850         size_t sz;
1851         struct vmxnet3_rx_buf_info *bi;
1852
1853         for (i = 0; i < 2; i++) {
1854
1855                 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1856                 rq->rx_ring[i].base = dma_alloc_coherent(
1857                                                 &adapter->pdev->dev, sz,
1858                                                 &rq->rx_ring[i].basePA,
1859                                                 GFP_KERNEL);
1860                 if (!rq->rx_ring[i].base) {
1861                         netdev_err(adapter->netdev,
1862                                    "failed to allocate rx ring %d\n", i);
1863                         goto err;
1864                 }
1865         }
1866
1867         if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1868                 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1869                 rq->data_ring.base =
1870                         dma_alloc_coherent(&adapter->pdev->dev, sz,
1871                                            &rq->data_ring.basePA,
1872                                            GFP_KERNEL);
1873                 if (!rq->data_ring.base) {
1874                         netdev_err(adapter->netdev,
1875                                    "rx data ring will be disabled\n");
1876                         adapter->rxdataring_enabled = false;
1877                 }
1878         } else {
1879                 rq->data_ring.base = NULL;
1880                 rq->data_ring.desc_size = 0;
1881         }
1882
1883         sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1884         rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1885                                                 &rq->comp_ring.basePA,
1886                                                 GFP_KERNEL);
1887         if (!rq->comp_ring.base) {
1888                 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
1889                 goto err;
1890         }
1891
1892         sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1893                                                    rq->rx_ring[1].size);
1894         bi = dma_alloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
1895                                 GFP_KERNEL);
1896         if (!bi)
1897                 goto err;
1898
1899         rq->buf_info[0] = bi;
1900         rq->buf_info[1] = bi + rq->rx_ring[0].size;
1901
1902         return 0;
1903
1904 err:
1905         vmxnet3_rq_destroy(rq, adapter);
1906         return -ENOMEM;
1907 }
1908
1909
1910 static int
1911 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1912 {
1913         int i, err = 0;
1914
1915         adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1916
1917         for (i = 0; i < adapter->num_rx_queues; i++) {
1918                 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1919                 if (unlikely(err)) {
1920                         dev_err(&adapter->netdev->dev,
1921                                 "%s: failed to create rx queue%i\n",
1922                                 adapter->netdev->name, i);
1923                         goto err_out;
1924                 }
1925         }
1926
1927         if (!adapter->rxdataring_enabled)
1928                 vmxnet3_rq_destroy_all_rxdataring(adapter);
1929
1930         return err;
1931 err_out:
1932         vmxnet3_rq_destroy_all(adapter);
1933         return err;
1934
1935 }
1936
1937 /* Multiple queue aware polling function for tx and rx */
1938
1939 static int
1940 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1941 {
1942         int rcd_done = 0, i;
1943         if (unlikely(adapter->shared->ecr))
1944                 vmxnet3_process_events(adapter);
1945         for (i = 0; i < adapter->num_tx_queues; i++)
1946                 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1947
1948         for (i = 0; i < adapter->num_rx_queues; i++)
1949                 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1950                                                    adapter, budget);
1951         return rcd_done;
1952 }
1953
1954
1955 static int
1956 vmxnet3_poll(struct napi_struct *napi, int budget)
1957 {
1958         struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1959                                           struct vmxnet3_rx_queue, napi);
1960         int rxd_done;
1961
1962         rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1963
1964         if (rxd_done < budget) {
1965                 napi_complete_done(napi, rxd_done);
1966                 vmxnet3_enable_all_intrs(rx_queue->adapter);
1967         }
1968         return rxd_done;
1969 }
1970
1971 /*
1972  * NAPI polling function for MSI-X mode with multiple Rx queues
1973  * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1974  */
1975
1976 static int
1977 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1978 {
1979         struct vmxnet3_rx_queue *rq = container_of(napi,
1980                                                 struct vmxnet3_rx_queue, napi);
1981         struct vmxnet3_adapter *adapter = rq->adapter;
1982         int rxd_done;
1983
1984         /* When sharing interrupt with corresponding tx queue, process
1985          * tx completions in that queue as well
1986          */
1987         if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1988                 struct vmxnet3_tx_queue *tq =
1989                                 &adapter->tx_queue[rq - adapter->rx_queue];
1990                 vmxnet3_tq_tx_complete(tq, adapter);
1991         }
1992
1993         rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
1994
1995         if (rxd_done < budget) {
1996                 napi_complete_done(napi, rxd_done);
1997                 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
1998         }
1999         return rxd_done;
2000 }
2001
2002
2003 #ifdef CONFIG_PCI_MSI
2004
2005 /*
2006  * Handle completion interrupts on tx queues
2007  * Returns whether or not the intr is handled
2008  */
2009
2010 static irqreturn_t
2011 vmxnet3_msix_tx(int irq, void *data)
2012 {
2013         struct vmxnet3_tx_queue *tq = data;
2014         struct vmxnet3_adapter *adapter = tq->adapter;
2015
2016         if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2017                 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
2018
2019         /* Handle the case where only one irq is allocate for all tx queues */
2020         if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2021                 int i;
2022                 for (i = 0; i < adapter->num_tx_queues; i++) {
2023                         struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
2024                         vmxnet3_tq_tx_complete(txq, adapter);
2025                 }
2026         } else {
2027                 vmxnet3_tq_tx_complete(tq, adapter);
2028         }
2029         vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
2030
2031         return IRQ_HANDLED;
2032 }
2033
2034
2035 /*
2036  * Handle completion interrupts on rx queues. Returns whether or not the
2037  * intr is handled
2038  */
2039
2040 static irqreturn_t
2041 vmxnet3_msix_rx(int irq, void *data)
2042 {
2043         struct vmxnet3_rx_queue *rq = data;
2044         struct vmxnet3_adapter *adapter = rq->adapter;
2045
2046         /* disable intr if needed */
2047         if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2048                 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
2049         napi_schedule(&rq->napi);
2050
2051         return IRQ_HANDLED;
2052 }
2053
2054 /*
2055  *----------------------------------------------------------------------------
2056  *
2057  * vmxnet3_msix_event --
2058  *
2059  *    vmxnet3 msix event intr handler
2060  *
2061  * Result:
2062  *    whether or not the intr is handled
2063  *
2064  *----------------------------------------------------------------------------
2065  */
2066
2067 static irqreturn_t
2068 vmxnet3_msix_event(int irq, void *data)
2069 {
2070         struct net_device *dev = data;
2071         struct vmxnet3_adapter *adapter = netdev_priv(dev);
2072
2073         /* disable intr if needed */
2074         if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2075                 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
2076
2077         if (adapter->shared->ecr)
2078                 vmxnet3_process_events(adapter);
2079
2080         vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
2081
2082         return IRQ_HANDLED;
2083 }
2084
2085 #endif /* CONFIG_PCI_MSI  */
2086
2087
2088 /* Interrupt handler for vmxnet3  */
2089 static irqreturn_t
2090 vmxnet3_intr(int irq, void *dev_id)
2091 {
2092         struct net_device *dev = dev_id;
2093         struct vmxnet3_adapter *adapter = netdev_priv(dev);
2094
2095         if (adapter->intr.type == VMXNET3_IT_INTX) {
2096                 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
2097                 if (unlikely(icr == 0))
2098                         /* not ours */
2099                         return IRQ_NONE;
2100         }
2101
2102
2103         /* disable intr if needed */
2104         if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2105                 vmxnet3_disable_all_intrs(adapter);
2106
2107         napi_schedule(&adapter->rx_queue[0].napi);
2108
2109         return IRQ_HANDLED;
2110 }
2111
2112 #ifdef CONFIG_NET_POLL_CONTROLLER
2113
2114 /* netpoll callback. */
2115 static void
2116 vmxnet3_netpoll(struct net_device *netdev)
2117 {
2118         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2119
2120         switch (adapter->intr.type) {
2121 #ifdef CONFIG_PCI_MSI
2122         case VMXNET3_IT_MSIX: {
2123                 int i;
2124                 for (i = 0; i < adapter->num_rx_queues; i++)
2125                         vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2126                 break;
2127         }
2128 #endif
2129         case VMXNET3_IT_MSI:
2130         default:
2131                 vmxnet3_intr(0, adapter->netdev);
2132                 break;
2133         }
2134
2135 }
2136 #endif  /* CONFIG_NET_POLL_CONTROLLER */
2137
2138 static int
2139 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2140 {
2141         struct vmxnet3_intr *intr = &adapter->intr;
2142         int err = 0, i;
2143         int vector = 0;
2144
2145 #ifdef CONFIG_PCI_MSI
2146         if (adapter->intr.type == VMXNET3_IT_MSIX) {
2147                 for (i = 0; i < adapter->num_tx_queues; i++) {
2148                         if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2149                                 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2150                                         adapter->netdev->name, vector);
2151                                 err = request_irq(
2152                                               intr->msix_entries[vector].vector,
2153                                               vmxnet3_msix_tx, 0,
2154                                               adapter->tx_queue[i].name,
2155                                               &adapter->tx_queue[i]);
2156                         } else {
2157                                 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2158                                         adapter->netdev->name, vector);
2159                         }
2160                         if (err) {
2161                                 dev_err(&adapter->netdev->dev,
2162                                         "Failed to request irq for MSIX, %s, "
2163                                         "error %d\n",
2164                                         adapter->tx_queue[i].name, err);
2165                                 return err;
2166                         }
2167
2168                         /* Handle the case where only 1 MSIx was allocated for
2169                          * all tx queues */
2170                         if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2171                                 for (; i < adapter->num_tx_queues; i++)
2172                                         adapter->tx_queue[i].comp_ring.intr_idx
2173                                                                 = vector;
2174                                 vector++;
2175                                 break;
2176                         } else {
2177                                 adapter->tx_queue[i].comp_ring.intr_idx
2178                                                                 = vector++;
2179                         }
2180                 }
2181                 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2182                         vector = 0;
2183
2184                 for (i = 0; i < adapter->num_rx_queues; i++) {
2185                         if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2186                                 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2187                                         adapter->netdev->name, vector);
2188                         else
2189                                 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2190                                         adapter->netdev->name, vector);
2191                         err = request_irq(intr->msix_entries[vector].vector,
2192                                           vmxnet3_msix_rx, 0,
2193                                           adapter->rx_queue[i].name,
2194                                           &(adapter->rx_queue[i]));
2195                         if (err) {
2196                                 netdev_err(adapter->netdev,
2197                                            "Failed to request irq for MSIX, "
2198                                            "%s, error %d\n",
2199                                            adapter->rx_queue[i].name, err);
2200                                 return err;
2201                         }
2202
2203                         adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2204                 }
2205
2206                 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2207                         adapter->netdev->name, vector);
2208                 err = request_irq(intr->msix_entries[vector].vector,
2209                                   vmxnet3_msix_event, 0,
2210                                   intr->event_msi_vector_name, adapter->netdev);
2211                 intr->event_intr_idx = vector;
2212
2213         } else if (intr->type == VMXNET3_IT_MSI) {
2214                 adapter->num_rx_queues = 1;
2215                 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2216                                   adapter->netdev->name, adapter->netdev);
2217         } else {
2218 #endif
2219                 adapter->num_rx_queues = 1;
2220                 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2221                                   IRQF_SHARED, adapter->netdev->name,
2222                                   adapter->netdev);
2223 #ifdef CONFIG_PCI_MSI
2224         }
2225 #endif
2226         intr->num_intrs = vector + 1;
2227         if (err) {
2228                 netdev_err(adapter->netdev,
2229                            "Failed to request irq (intr type:%d), error %d\n",
2230                            intr->type, err);
2231         } else {
2232                 /* Number of rx queues will not change after this */
2233                 for (i = 0; i < adapter->num_rx_queues; i++) {
2234                         struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2235                         rq->qid = i;
2236                         rq->qid2 = i + adapter->num_rx_queues;
2237                         rq->dataRingQid = i + 2 * adapter->num_rx_queues;
2238                 }
2239
2240                 /* init our intr settings */
2241                 for (i = 0; i < intr->num_intrs; i++)
2242                         intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2243                 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2244                         adapter->intr.event_intr_idx = 0;
2245                         for (i = 0; i < adapter->num_tx_queues; i++)
2246                                 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2247                         adapter->rx_queue[0].comp_ring.intr_idx = 0;
2248                 }
2249
2250                 netdev_info(adapter->netdev,
2251                             "intr type %u, mode %u, %u vectors allocated\n",
2252                             intr->type, intr->mask_mode, intr->num_intrs);
2253         }
2254
2255         return err;
2256 }
2257
2258
2259 static void
2260 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2261 {
2262         struct vmxnet3_intr *intr = &adapter->intr;
2263         BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
2264
2265         switch (intr->type) {
2266 #ifdef CONFIG_PCI_MSI
2267         case VMXNET3_IT_MSIX:
2268         {
2269                 int i, vector = 0;
2270
2271                 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2272                         for (i = 0; i < adapter->num_tx_queues; i++) {
2273                                 free_irq(intr->msix_entries[vector++].vector,
2274                                          &(adapter->tx_queue[i]));
2275                                 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2276                                         break;
2277                         }
2278                 }
2279
2280                 for (i = 0; i < adapter->num_rx_queues; i++) {
2281                         free_irq(intr->msix_entries[vector++].vector,
2282                                  &(adapter->rx_queue[i]));
2283                 }
2284
2285                 free_irq(intr->msix_entries[vector].vector,
2286                          adapter->netdev);
2287                 BUG_ON(vector >= intr->num_intrs);
2288                 break;
2289         }
2290 #endif
2291         case VMXNET3_IT_MSI:
2292                 free_irq(adapter->pdev->irq, adapter->netdev);
2293                 break;
2294         case VMXNET3_IT_INTX:
2295                 free_irq(adapter->pdev->irq, adapter->netdev);
2296                 break;
2297         default:
2298                 BUG();
2299         }
2300 }
2301
2302
2303 static void
2304 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2305 {
2306         u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2307         u16 vid;
2308
2309         /* allow untagged pkts */
2310         VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2311
2312         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2313                 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2314 }
2315
2316
2317 static int
2318 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
2319 {
2320         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2321
2322         if (!(netdev->flags & IFF_PROMISC)) {
2323                 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2324                 unsigned long flags;
2325
2326                 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2327                 spin_lock_irqsave(&adapter->cmd_lock, flags);
2328                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2329                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2330                 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2331         }
2332
2333         set_bit(vid, adapter->active_vlans);
2334
2335         return 0;
2336 }
2337
2338
2339 static int
2340 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2341 {
2342         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2343
2344         if (!(netdev->flags & IFF_PROMISC)) {
2345                 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2346                 unsigned long flags;
2347
2348                 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2349                 spin_lock_irqsave(&adapter->cmd_lock, flags);
2350                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2351                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2352                 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2353         }
2354
2355         clear_bit(vid, adapter->active_vlans);
2356
2357         return 0;
2358 }
2359
2360
2361 static u8 *
2362 vmxnet3_copy_mc(struct net_device *netdev)
2363 {
2364         u8 *buf = NULL;
2365         u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
2366
2367         /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2368         if (sz <= 0xffff) {
2369                 /* We may be called with BH disabled */
2370                 buf = kmalloc(sz, GFP_ATOMIC);
2371                 if (buf) {
2372                         struct netdev_hw_addr *ha;
2373                         int i = 0;
2374
2375                         netdev_for_each_mc_addr(ha, netdev)
2376                                 memcpy(buf + i++ * ETH_ALEN, ha->addr,
2377                                        ETH_ALEN);
2378                 }
2379         }
2380         return buf;
2381 }
2382
2383
2384 static void
2385 vmxnet3_set_mc(struct net_device *netdev)
2386 {
2387         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2388         unsigned long flags;
2389         struct Vmxnet3_RxFilterConf *rxConf =
2390                                         &adapter->shared->devRead.rxFilterConf;
2391         u8 *new_table = NULL;
2392         dma_addr_t new_table_pa = 0;
2393         bool new_table_pa_valid = false;
2394         u32 new_mode = VMXNET3_RXM_UCAST;
2395
2396         if (netdev->flags & IFF_PROMISC) {
2397                 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2398                 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2399
2400                 new_mode |= VMXNET3_RXM_PROMISC;
2401         } else {
2402                 vmxnet3_restore_vlan(adapter);
2403         }
2404
2405         if (netdev->flags & IFF_BROADCAST)
2406                 new_mode |= VMXNET3_RXM_BCAST;
2407
2408         if (netdev->flags & IFF_ALLMULTI)
2409                 new_mode |= VMXNET3_RXM_ALL_MULTI;
2410         else
2411                 if (!netdev_mc_empty(netdev)) {
2412                         new_table = vmxnet3_copy_mc(netdev);
2413                         if (new_table) {
2414                                 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2415
2416                                 rxConf->mfTableLen = cpu_to_le16(sz);
2417                                 new_table_pa = dma_map_single(
2418                                                         &adapter->pdev->dev,
2419                                                         new_table,
2420                                                         sz,
2421                                                         PCI_DMA_TODEVICE);
2422                                 if (!dma_mapping_error(&adapter->pdev->dev,
2423                                                        new_table_pa)) {
2424                                         new_mode |= VMXNET3_RXM_MCAST;
2425                                         new_table_pa_valid = true;
2426                                         rxConf->mfTablePA = cpu_to_le64(
2427                                                                 new_table_pa);
2428                                 }
2429                         }
2430                         if (!new_table_pa_valid) {
2431                                 netdev_info(netdev,
2432                                             "failed to copy mcast list, setting ALL_MULTI\n");
2433                                 new_mode |= VMXNET3_RXM_ALL_MULTI;
2434                         }
2435                 }
2436
2437         if (!(new_mode & VMXNET3_RXM_MCAST)) {
2438                 rxConf->mfTableLen = 0;
2439                 rxConf->mfTablePA = 0;
2440         }
2441
2442         spin_lock_irqsave(&adapter->cmd_lock, flags);
2443         if (new_mode != rxConf->rxMode) {
2444                 rxConf->rxMode = cpu_to_le32(new_mode);
2445                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2446                                        VMXNET3_CMD_UPDATE_RX_MODE);
2447                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2448                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2449         }
2450
2451         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2452                                VMXNET3_CMD_UPDATE_MAC_FILTERS);
2453         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2454
2455         if (new_table_pa_valid)
2456                 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2457                                  rxConf->mfTableLen, PCI_DMA_TODEVICE);
2458         kfree(new_table);
2459 }
2460
2461 void
2462 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2463 {
2464         int i;
2465
2466         for (i = 0; i < adapter->num_rx_queues; i++)
2467                 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2468 }
2469
2470
2471 /*
2472  *   Set up driver_shared based on settings in adapter.
2473  */
2474
2475 static void
2476 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2477 {
2478         struct Vmxnet3_DriverShared *shared = adapter->shared;
2479         struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2480         struct Vmxnet3_TxQueueConf *tqc;
2481         struct Vmxnet3_RxQueueConf *rqc;
2482         int i;
2483
2484         memset(shared, 0, sizeof(*shared));
2485
2486         /* driver settings */
2487         shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2488         devRead->misc.driverInfo.version = cpu_to_le32(
2489                                                 VMXNET3_DRIVER_VERSION_NUM);
2490         devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2491                                 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2492         devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2493         *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2494                                 *((u32 *)&devRead->misc.driverInfo.gos));
2495         devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2496         devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2497
2498         devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
2499         devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2500
2501         /* set up feature flags */
2502         if (adapter->netdev->features & NETIF_F_RXCSUM)
2503                 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2504
2505         if (adapter->netdev->features & NETIF_F_LRO) {
2506                 devRead->misc.uptFeatures |= UPT1_F_LRO;
2507                 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2508         }
2509         if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2510                 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2511
2512         if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
2513                                          NETIF_F_GSO_UDP_TUNNEL_CSUM))
2514                 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
2515
2516         devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2517         devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2518         devRead->misc.queueDescLen = cpu_to_le32(
2519                 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2520                 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2521
2522         /* tx queue settings */
2523         devRead->misc.numTxQueues =  adapter->num_tx_queues;
2524         for (i = 0; i < adapter->num_tx_queues; i++) {
2525                 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2526                 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2527                 tqc = &adapter->tqd_start[i].conf;
2528                 tqc->txRingBasePA   = cpu_to_le64(tq->tx_ring.basePA);
2529                 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2530                 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2531                 tqc->ddPA           = cpu_to_le64(tq->buf_info_pa);
2532                 tqc->txRingSize     = cpu_to_le32(tq->tx_ring.size);
2533                 tqc->dataRingSize   = cpu_to_le32(tq->data_ring.size);
2534                 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
2535                 tqc->compRingSize   = cpu_to_le32(tq->comp_ring.size);
2536                 tqc->ddLen          = cpu_to_le32(
2537                                         sizeof(struct vmxnet3_tx_buf_info) *
2538                                         tqc->txRingSize);
2539                 tqc->intrIdx        = tq->comp_ring.intr_idx;
2540         }
2541
2542         /* rx queue settings */
2543         devRead->misc.numRxQueues = adapter->num_rx_queues;
2544         for (i = 0; i < adapter->num_rx_queues; i++) {
2545                 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2546                 rqc = &adapter->rqd_start[i].conf;
2547                 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2548                 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2549                 rqc->compRingBasePA  = cpu_to_le64(rq->comp_ring.basePA);
2550                 rqc->ddPA            = cpu_to_le64(rq->buf_info_pa);
2551                 rqc->rxRingSize[0]   = cpu_to_le32(rq->rx_ring[0].size);
2552                 rqc->rxRingSize[1]   = cpu_to_le32(rq->rx_ring[1].size);
2553                 rqc->compRingSize    = cpu_to_le32(rq->comp_ring.size);
2554                 rqc->ddLen           = cpu_to_le32(
2555                                         sizeof(struct vmxnet3_rx_buf_info) *
2556                                         (rqc->rxRingSize[0] +
2557                                          rqc->rxRingSize[1]));
2558                 rqc->intrIdx         = rq->comp_ring.intr_idx;
2559                 if (VMXNET3_VERSION_GE_3(adapter)) {
2560                         rqc->rxDataRingBasePA =
2561                                 cpu_to_le64(rq->data_ring.basePA);
2562                         rqc->rxDataRingDescSize =
2563                                 cpu_to_le16(rq->data_ring.desc_size);
2564                 }
2565         }
2566
2567 #ifdef VMXNET3_RSS
2568         memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2569
2570         if (adapter->rss) {
2571                 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2572
2573                 devRead->misc.uptFeatures |= UPT1_F_RSS;
2574                 devRead->misc.numRxQueues = adapter->num_rx_queues;
2575                 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2576                                     UPT1_RSS_HASH_TYPE_IPV4 |
2577                                     UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2578                                     UPT1_RSS_HASH_TYPE_IPV6;
2579                 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2580                 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2581                 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2582                 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
2583
2584                 for (i = 0; i < rssConf->indTableSize; i++)
2585                         rssConf->indTable[i] = ethtool_rxfh_indir_default(
2586                                 i, adapter->num_rx_queues);
2587
2588                 devRead->rssConfDesc.confVer = 1;
2589                 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2590                 devRead->rssConfDesc.confPA =
2591                         cpu_to_le64(adapter->rss_conf_pa);
2592         }
2593
2594 #endif /* VMXNET3_RSS */
2595
2596         /* intr settings */
2597         devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2598                                      VMXNET3_IMM_AUTO;
2599         devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2600         for (i = 0; i < adapter->intr.num_intrs; i++)
2601                 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2602
2603         devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2604         devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2605
2606         /* rx filter settings */
2607         devRead->rxFilterConf.rxMode = 0;
2608         vmxnet3_restore_vlan(adapter);
2609         vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2610
2611         /* the rest are already zeroed */
2612 }
2613
2614 static void
2615 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2616 {
2617         struct Vmxnet3_DriverShared *shared = adapter->shared;
2618         union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2619         unsigned long flags;
2620
2621         if (!VMXNET3_VERSION_GE_3(adapter))
2622                 return;
2623
2624         spin_lock_irqsave(&adapter->cmd_lock, flags);
2625         cmdInfo->varConf.confVer = 1;
2626         cmdInfo->varConf.confLen =
2627                 cpu_to_le32(sizeof(*adapter->coal_conf));
2628         cmdInfo->varConf.confPA  = cpu_to_le64(adapter->coal_conf_pa);
2629
2630         if (adapter->default_coal_mode) {
2631                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2632                                        VMXNET3_CMD_GET_COALESCE);
2633         } else {
2634                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2635                                        VMXNET3_CMD_SET_COALESCE);
2636         }
2637
2638         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2639 }
2640
2641 static void
2642 vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
2643 {
2644         struct Vmxnet3_DriverShared *shared = adapter->shared;
2645         union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2646         unsigned long flags;
2647
2648         if (!VMXNET3_VERSION_GE_4(adapter))
2649                 return;
2650
2651         spin_lock_irqsave(&adapter->cmd_lock, flags);
2652
2653         if (adapter->default_rss_fields) {
2654                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2655                                        VMXNET3_CMD_GET_RSS_FIELDS);
2656                 adapter->rss_fields =
2657                         VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2658         } else {
2659                 cmdInfo->setRssFields = adapter->rss_fields;
2660                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2661                                        VMXNET3_CMD_SET_RSS_FIELDS);
2662                 /* Not all requested RSS may get applied, so get and
2663                  * cache what was actually applied.
2664                  */
2665                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2666                                        VMXNET3_CMD_GET_RSS_FIELDS);
2667                 adapter->rss_fields =
2668                         VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2669         }
2670
2671         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2672 }
2673
2674 int
2675 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2676 {
2677         int err, i;
2678         u32 ret;
2679         unsigned long flags;
2680
2681         netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2682                 " ring sizes %u %u %u\n", adapter->netdev->name,
2683                 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2684                 adapter->tx_queue[0].tx_ring.size,
2685                 adapter->rx_queue[0].rx_ring[0].size,
2686                 adapter->rx_queue[0].rx_ring[1].size);
2687
2688         vmxnet3_tq_init_all(adapter);
2689         err = vmxnet3_rq_init_all(adapter);
2690         if (err) {
2691                 netdev_err(adapter->netdev,
2692                            "Failed to init rx queue error %d\n", err);
2693                 goto rq_err;
2694         }
2695
2696         err = vmxnet3_request_irqs(adapter);
2697         if (err) {
2698                 netdev_err(adapter->netdev,
2699                            "Failed to setup irq for error %d\n", err);
2700                 goto irq_err;
2701         }
2702
2703         vmxnet3_setup_driver_shared(adapter);
2704
2705         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2706                                adapter->shared_pa));
2707         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2708                                adapter->shared_pa));
2709         spin_lock_irqsave(&adapter->cmd_lock, flags);
2710         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2711                                VMXNET3_CMD_ACTIVATE_DEV);
2712         ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2713         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2714
2715         if (ret != 0) {
2716                 netdev_err(adapter->netdev,
2717                            "Failed to activate dev: error %u\n", ret);
2718                 err = -EINVAL;
2719                 goto activate_err;
2720         }
2721
2722         vmxnet3_init_coalesce(adapter);
2723         vmxnet3_init_rssfields(adapter);
2724
2725         for (i = 0; i < adapter->num_rx_queues; i++) {
2726                 VMXNET3_WRITE_BAR0_REG(adapter,
2727                                 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2728                                 adapter->rx_queue[i].rx_ring[0].next2fill);
2729                 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2730                                 (i * VMXNET3_REG_ALIGN)),
2731                                 adapter->rx_queue[i].rx_ring[1].next2fill);
2732         }
2733
2734         /* Apply the rx filter settins last. */
2735         vmxnet3_set_mc(adapter->netdev);
2736
2737         /*
2738          * Check link state when first activating device. It will start the
2739          * tx queue if the link is up.
2740          */
2741         vmxnet3_check_link(adapter, true);
2742         for (i = 0; i < adapter->num_rx_queues; i++)
2743                 napi_enable(&adapter->rx_queue[i].napi);
2744         vmxnet3_enable_all_intrs(adapter);
2745         clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2746         return 0;
2747
2748 activate_err:
2749         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2750         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2751         vmxnet3_free_irqs(adapter);
2752 irq_err:
2753 rq_err:
2754         /* free up buffers we allocated */
2755         vmxnet3_rq_cleanup_all(adapter);
2756         return err;
2757 }
2758
2759
2760 void
2761 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2762 {
2763         unsigned long flags;
2764         spin_lock_irqsave(&adapter->cmd_lock, flags);
2765         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2766         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2767 }
2768
2769
2770 int
2771 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2772 {
2773         int i;
2774         unsigned long flags;
2775         if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2776                 return 0;
2777
2778
2779         spin_lock_irqsave(&adapter->cmd_lock, flags);
2780         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2781                                VMXNET3_CMD_QUIESCE_DEV);
2782         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2783         vmxnet3_disable_all_intrs(adapter);
2784
2785         for (i = 0; i < adapter->num_rx_queues; i++)
2786                 napi_disable(&adapter->rx_queue[i].napi);
2787         netif_tx_disable(adapter->netdev);
2788         adapter->link_speed = 0;
2789         netif_carrier_off(adapter->netdev);
2790
2791         vmxnet3_tq_cleanup_all(adapter);
2792         vmxnet3_rq_cleanup_all(adapter);
2793         vmxnet3_free_irqs(adapter);
2794         return 0;
2795 }
2796
2797
2798 static void
2799 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2800 {
2801         u32 tmp;
2802
2803         tmp = *(u32 *)mac;
2804         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2805
2806         tmp = (mac[5] << 8) | mac[4];
2807         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2808 }
2809
2810
2811 static int
2812 vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2813 {
2814         struct sockaddr *addr = p;
2815         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2816
2817         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2818         vmxnet3_write_mac_addr(adapter, addr->sa_data);
2819
2820         return 0;
2821 }
2822
2823
2824 /* ==================== initialization and cleanup routines ============ */
2825
2826 static int
2827 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
2828 {
2829         int err;
2830         unsigned long mmio_start, mmio_len;
2831         struct pci_dev *pdev = adapter->pdev;
2832
2833         err = pci_enable_device(pdev);
2834         if (err) {
2835                 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
2836                 return err;
2837         }
2838
2839         err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2840                                            vmxnet3_driver_name);
2841         if (err) {
2842                 dev_err(&pdev->dev,
2843                         "Failed to request region for adapter: error %d\n", err);
2844                 goto err_enable_device;
2845         }
2846
2847         pci_set_master(pdev);
2848
2849         mmio_start = pci_resource_start(pdev, 0);
2850         mmio_len = pci_resource_len(pdev, 0);
2851         adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2852         if (!adapter->hw_addr0) {
2853                 dev_err(&pdev->dev, "Failed to map bar0\n");
2854                 err = -EIO;
2855                 goto err_ioremap;
2856         }
2857
2858         mmio_start = pci_resource_start(pdev, 1);
2859         mmio_len = pci_resource_len(pdev, 1);
2860         adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2861         if (!adapter->hw_addr1) {
2862                 dev_err(&pdev->dev, "Failed to map bar1\n");
2863                 err = -EIO;
2864                 goto err_bar1;
2865         }
2866         return 0;
2867
2868 err_bar1:
2869         iounmap(adapter->hw_addr0);
2870 err_ioremap:
2871         pci_release_selected_regions(pdev, (1 << 2) - 1);
2872 err_enable_device:
2873         pci_disable_device(pdev);
2874         return err;
2875 }
2876
2877
2878 static void
2879 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2880 {
2881         BUG_ON(!adapter->pdev);
2882
2883         iounmap(adapter->hw_addr0);
2884         iounmap(adapter->hw_addr1);
2885         pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2886         pci_disable_device(adapter->pdev);
2887 }
2888
2889
2890 static void
2891 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2892 {
2893         size_t sz, i, ring0_size, ring1_size, comp_size;
2894         if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2895                                     VMXNET3_MAX_ETH_HDR_SIZE) {
2896                 adapter->skb_buf_size = adapter->netdev->mtu +
2897                                         VMXNET3_MAX_ETH_HDR_SIZE;
2898                 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2899                         adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2900
2901                 adapter->rx_buf_per_pkt = 1;
2902         } else {
2903                 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2904                 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2905                                             VMXNET3_MAX_ETH_HDR_SIZE;
2906                 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2907         }
2908
2909         /*
2910          * for simplicity, force the ring0 size to be a multiple of
2911          * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2912          */
2913         sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2914         ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2915         ring0_size = (ring0_size + sz - 1) / sz * sz;
2916         ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2917                            sz * sz);
2918         ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2919         ring1_size = (ring1_size + sz - 1) / sz * sz;
2920         ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2921                            sz * sz);
2922         comp_size = ring0_size + ring1_size;
2923
2924         for (i = 0; i < adapter->num_rx_queues; i++) {
2925                 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2926
2927                 rq->rx_ring[0].size = ring0_size;
2928                 rq->rx_ring[1].size = ring1_size;
2929                 rq->comp_ring.size = comp_size;
2930         }
2931 }
2932
2933
2934 int
2935 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2936                       u32 rx_ring_size, u32 rx_ring2_size,
2937                       u16 txdata_desc_size, u16 rxdata_desc_size)
2938 {
2939         int err = 0, i;
2940
2941         for (i = 0; i < adapter->num_tx_queues; i++) {
2942                 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2943                 tq->tx_ring.size   = tx_ring_size;
2944                 tq->data_ring.size = tx_ring_size;
2945                 tq->comp_ring.size = tx_ring_size;
2946                 tq->txdata_desc_size = txdata_desc_size;
2947                 tq->shared = &adapter->tqd_start[i].ctrl;
2948                 tq->stopped = true;
2949                 tq->adapter = adapter;
2950                 tq->qid = i;
2951                 err = vmxnet3_tq_create(tq, adapter);
2952                 /*
2953                  * Too late to change num_tx_queues. We cannot do away with
2954                  * lesser number of queues than what we asked for
2955                  */
2956                 if (err)
2957                         goto queue_err;
2958         }
2959
2960         adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2961         adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
2962         vmxnet3_adjust_rx_ring_size(adapter);
2963
2964         adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
2965         for (i = 0; i < adapter->num_rx_queues; i++) {
2966                 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2967                 /* qid and qid2 for rx queues will be assigned later when num
2968                  * of rx queues is finalized after allocating intrs */
2969                 rq->shared = &adapter->rqd_start[i].ctrl;
2970                 rq->adapter = adapter;
2971                 rq->data_ring.desc_size = rxdata_desc_size;
2972                 err = vmxnet3_rq_create(rq, adapter);
2973                 if (err) {
2974                         if (i == 0) {
2975                                 netdev_err(adapter->netdev,
2976                                            "Could not allocate any rx queues. "
2977                                            "Aborting.\n");
2978                                 goto queue_err;
2979                         } else {
2980                                 netdev_info(adapter->netdev,
2981                                             "Number of rx queues changed "
2982                                             "to : %d.\n", i);
2983                                 adapter->num_rx_queues = i;
2984                                 err = 0;
2985                                 break;
2986                         }
2987                 }
2988         }
2989
2990         if (!adapter->rxdataring_enabled)
2991                 vmxnet3_rq_destroy_all_rxdataring(adapter);
2992
2993         return err;
2994 queue_err:
2995         vmxnet3_tq_destroy_all(adapter);
2996         return err;
2997 }
2998
2999 static int
3000 vmxnet3_open(struct net_device *netdev)
3001 {
3002         struct vmxnet3_adapter *adapter;
3003         int err, i;
3004
3005         adapter = netdev_priv(netdev);
3006
3007         for (i = 0; i < adapter->num_tx_queues; i++)
3008                 spin_lock_init(&adapter->tx_queue[i].tx_lock);
3009
3010         if (VMXNET3_VERSION_GE_3(adapter)) {
3011                 unsigned long flags;
3012                 u16 txdata_desc_size;
3013
3014                 spin_lock_irqsave(&adapter->cmd_lock, flags);
3015                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3016                                        VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
3017                 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
3018                                                          VMXNET3_REG_CMD);
3019                 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3020
3021                 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
3022                     (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
3023                     (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
3024                         adapter->txdata_desc_size =
3025                                 sizeof(struct Vmxnet3_TxDataDesc);
3026                 } else {
3027                         adapter->txdata_desc_size = txdata_desc_size;
3028                 }
3029         } else {
3030                 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
3031         }
3032
3033         err = vmxnet3_create_queues(adapter,
3034                                     adapter->tx_ring_size,
3035                                     adapter->rx_ring_size,
3036                                     adapter->rx_ring2_size,
3037                                     adapter->txdata_desc_size,
3038                                     adapter->rxdata_desc_size);
3039         if (err)
3040                 goto queue_err;
3041
3042         err = vmxnet3_activate_dev(adapter);
3043         if (err)
3044                 goto activate_err;
3045
3046         return 0;
3047
3048 activate_err:
3049         vmxnet3_rq_destroy_all(adapter);
3050         vmxnet3_tq_destroy_all(adapter);
3051 queue_err:
3052         return err;
3053 }
3054
3055
3056 static int
3057 vmxnet3_close(struct net_device *netdev)
3058 {
3059         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3060
3061         /*
3062          * Reset_work may be in the middle of resetting the device, wait for its
3063          * completion.
3064          */
3065         while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3066                 usleep_range(1000, 2000);
3067
3068         vmxnet3_quiesce_dev(adapter);
3069
3070         vmxnet3_rq_destroy_all(adapter);
3071         vmxnet3_tq_destroy_all(adapter);
3072
3073         clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3074
3075
3076         return 0;
3077 }
3078
3079
3080 void
3081 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
3082 {
3083         int i;
3084
3085         /*
3086          * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
3087          * vmxnet3_close() will deadlock.
3088          */
3089         BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
3090
3091         /* we need to enable NAPI, otherwise dev_close will deadlock */
3092         for (i = 0; i < adapter->num_rx_queues; i++)
3093                 napi_enable(&adapter->rx_queue[i].napi);
3094         /*
3095          * Need to clear the quiesce bit to ensure that vmxnet3_close
3096          * can quiesce the device properly
3097          */
3098         clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3099         dev_close(adapter->netdev);
3100 }
3101
3102
3103 static int
3104 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
3105 {
3106         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3107         int err = 0;
3108
3109         netdev->mtu = new_mtu;
3110
3111         /*
3112          * Reset_work may be in the middle of resetting the device, wait for its
3113          * completion.
3114          */
3115         while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3116                 usleep_range(1000, 2000);
3117
3118         if (netif_running(netdev)) {
3119                 vmxnet3_quiesce_dev(adapter);
3120                 vmxnet3_reset_dev(adapter);
3121
3122                 /* we need to re-create the rx queue based on the new mtu */
3123                 vmxnet3_rq_destroy_all(adapter);
3124                 vmxnet3_adjust_rx_ring_size(adapter);
3125                 err = vmxnet3_rq_create_all(adapter);
3126                 if (err) {
3127                         netdev_err(netdev,
3128                                    "failed to re-create rx queues, "
3129                                    " error %d. Closing it.\n", err);
3130                         goto out;
3131                 }
3132
3133                 err = vmxnet3_activate_dev(adapter);
3134                 if (err) {
3135                         netdev_err(netdev,
3136                                    "failed to re-activate, error %d. "
3137                                    "Closing it\n", err);
3138                         goto out;
3139                 }
3140         }
3141
3142 out:
3143         clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3144         if (err)
3145                 vmxnet3_force_close(adapter);
3146
3147         return err;
3148 }
3149
3150
3151 static void
3152 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
3153 {
3154         struct net_device *netdev = adapter->netdev;
3155
3156         netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3157                 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3158                 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3159                 NETIF_F_LRO;
3160
3161         if (VMXNET3_VERSION_GE_4(adapter)) {
3162                 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3163                                 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3164
3165                 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
3166                         NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3167                         NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3168                         NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
3169                         NETIF_F_GSO_UDP_TUNNEL_CSUM;
3170         }
3171
3172         if (dma64)
3173                 netdev->hw_features |= NETIF_F_HIGHDMA;
3174         netdev->vlan_features = netdev->hw_features &
3175                                 ~(NETIF_F_HW_VLAN_CTAG_TX |
3176                                   NETIF_F_HW_VLAN_CTAG_RX);
3177         netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3178 }
3179
3180
3181 static void
3182 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3183 {
3184         u32 tmp;
3185
3186         tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3187         *(u32 *)mac = tmp;
3188
3189         tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3190         mac[4] = tmp & 0xff;
3191         mac[5] = (tmp >> 8) & 0xff;
3192 }
3193
3194 #ifdef CONFIG_PCI_MSI
3195
3196 /*
3197  * Enable MSIx vectors.
3198  * Returns :
3199  *      VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
3200  *       were enabled.
3201  *      number of vectors which were enabled otherwise (this number is greater
3202  *       than VMXNET3_LINUX_MIN_MSIX_VECT)
3203  */
3204
3205 static int
3206 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
3207 {
3208         int ret = pci_enable_msix_range(adapter->pdev,
3209                                         adapter->intr.msix_entries, nvec, nvec);
3210
3211         if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3212                 dev_err(&adapter->netdev->dev,
3213                         "Failed to enable %d MSI-X, trying %d\n",
3214                         nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3215
3216                 ret = pci_enable_msix_range(adapter->pdev,
3217                                             adapter->intr.msix_entries,
3218                                             VMXNET3_LINUX_MIN_MSIX_VECT,
3219                                             VMXNET3_LINUX_MIN_MSIX_VECT);
3220         }
3221
3222         if (ret < 0) {
3223                 dev_err(&adapter->netdev->dev,
3224                         "Failed to enable MSI-X, error: %d\n", ret);
3225         }
3226
3227         return ret;
3228 }
3229
3230
3231 #endif /* CONFIG_PCI_MSI */
3232
3233 static void
3234 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3235 {
3236         u32 cfg;
3237         unsigned long flags;
3238
3239         /* intr settings */
3240         spin_lock_irqsave(&adapter->cmd_lock, flags);
3241         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3242                                VMXNET3_CMD_GET_CONF_INTR);
3243         cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3244         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3245         adapter->intr.type = cfg & 0x3;
3246         adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3247
3248         if (adapter->intr.type == VMXNET3_IT_AUTO) {
3249                 adapter->intr.type = VMXNET3_IT_MSIX;
3250         }
3251
3252 #ifdef CONFIG_PCI_MSI
3253         if (adapter->intr.type == VMXNET3_IT_MSIX) {
3254                 int i, nvec;
3255
3256                 nvec  = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3257                         1 : adapter->num_tx_queues;
3258                 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3259                         0 : adapter->num_rx_queues;
3260                 nvec += 1;      /* for link event */
3261                 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3262                        nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3263
3264                 for (i = 0; i < nvec; i++)
3265                         adapter->intr.msix_entries[i].entry = i;
3266
3267                 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
3268                 if (nvec < 0)
3269                         goto msix_err;
3270
3271                 /* If we cannot allocate one MSIx vector per queue
3272                  * then limit the number of rx queues to 1
3273                  */
3274                 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
3275                         if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
3276                             || adapter->num_rx_queues != 1) {
3277                                 adapter->share_intr = VMXNET3_INTR_TXSHARE;
3278                                 netdev_err(adapter->netdev,
3279                                            "Number of rx queues : 1\n");
3280                                 adapter->num_rx_queues = 1;
3281                         }
3282                 }
3283
3284                 adapter->intr.num_intrs = nvec;
3285                 return;
3286
3287 msix_err:
3288                 /* If we cannot allocate MSIx vectors use only one rx queue */
3289                 dev_info(&adapter->pdev->dev,
3290                          "Failed to enable MSI-X, error %d. "
3291                          "Limiting #rx queues to 1, try MSI.\n", nvec);
3292
3293                 adapter->intr.type = VMXNET3_IT_MSI;
3294         }
3295
3296         if (adapter->intr.type == VMXNET3_IT_MSI) {
3297                 if (!pci_enable_msi(adapter->pdev)) {
3298                         adapter->num_rx_queues = 1;
3299                         adapter->intr.num_intrs = 1;
3300                         return;
3301                 }
3302         }
3303 #endif /* CONFIG_PCI_MSI */
3304
3305         adapter->num_rx_queues = 1;
3306         dev_info(&adapter->netdev->dev,
3307                  "Using INTx interrupt, #Rx queues: 1.\n");
3308         adapter->intr.type = VMXNET3_IT_INTX;
3309
3310         /* INT-X related setting */
3311         adapter->intr.num_intrs = 1;
3312 }
3313
3314
3315 static void
3316 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3317 {
3318         if (adapter->intr.type == VMXNET3_IT_MSIX)
3319                 pci_disable_msix(adapter->pdev);
3320         else if (adapter->intr.type == VMXNET3_IT_MSI)
3321                 pci_disable_msi(adapter->pdev);
3322         else
3323                 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3324 }
3325
3326
3327 static void
3328 vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
3329 {
3330         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3331         adapter->tx_timeout_count++;
3332
3333         netdev_err(adapter->netdev, "tx hang\n");
3334         schedule_work(&adapter->work);
3335 }
3336
3337
3338 static void
3339 vmxnet3_reset_work(struct work_struct *data)
3340 {
3341         struct vmxnet3_adapter *adapter;
3342
3343         adapter = container_of(data, struct vmxnet3_adapter, work);
3344
3345         /* if another thread is resetting the device, no need to proceed */
3346         if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3347                 return;
3348
3349         /* if the device is closed, we must leave it alone */
3350         rtnl_lock();
3351         if (netif_running(adapter->netdev)) {
3352                 netdev_notice(adapter->netdev, "resetting\n");
3353                 vmxnet3_quiesce_dev(adapter);
3354                 vmxnet3_reset_dev(adapter);
3355                 vmxnet3_activate_dev(adapter);
3356         } else {
3357                 netdev_info(adapter->netdev, "already closed\n");
3358         }
3359         rtnl_unlock();
3360
3361         netif_wake_queue(adapter->netdev);
3362         clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3363 }
3364
3365
3366 static int
3367 vmxnet3_probe_device(struct pci_dev *pdev,
3368                      const struct pci_device_id *id)
3369 {
3370         static const struct net_device_ops vmxnet3_netdev_ops = {
3371                 .ndo_open = vmxnet3_open,
3372                 .ndo_stop = vmxnet3_close,
3373                 .ndo_start_xmit = vmxnet3_xmit_frame,
3374                 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3375                 .ndo_change_mtu = vmxnet3_change_mtu,
3376                 .ndo_fix_features = vmxnet3_fix_features,
3377                 .ndo_set_features = vmxnet3_set_features,
3378                 .ndo_features_check = vmxnet3_features_check,
3379                 .ndo_get_stats64 = vmxnet3_get_stats64,
3380                 .ndo_tx_timeout = vmxnet3_tx_timeout,
3381                 .ndo_set_rx_mode = vmxnet3_set_mc,
3382                 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3383                 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3384 #ifdef CONFIG_NET_POLL_CONTROLLER
3385                 .ndo_poll_controller = vmxnet3_netpoll,
3386 #endif
3387         };
3388         int err;
3389         bool dma64;
3390         u32 ver;
3391         struct net_device *netdev;
3392         struct vmxnet3_adapter *adapter;
3393         u8 mac[ETH_ALEN];
3394         int size;
3395         int num_tx_queues;
3396         int num_rx_queues;
3397
3398         if (!pci_msi_enabled())
3399                 enable_mq = 0;
3400
3401 #ifdef VMXNET3_RSS
3402         if (enable_mq)
3403                 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3404                                     (int)num_online_cpus());
3405         else
3406 #endif
3407                 num_rx_queues = 1;
3408         num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3409
3410         if (enable_mq)
3411                 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3412                                     (int)num_online_cpus());
3413         else
3414                 num_tx_queues = 1;
3415
3416         num_tx_queues = rounddown_pow_of_two(num_tx_queues);
3417         netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3418                                    max(num_tx_queues, num_rx_queues));
3419         dev_info(&pdev->dev,
3420                  "# of Tx queues : %d, # of Rx queues : %d\n",
3421                  num_tx_queues, num_rx_queues);
3422
3423         if (!netdev)
3424                 return -ENOMEM;
3425
3426         pci_set_drvdata(pdev, netdev);
3427         adapter = netdev_priv(netdev);
3428         adapter->netdev = netdev;
3429         adapter->pdev = pdev;
3430
3431         adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3432         adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
3433         adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
3434
3435         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
3436                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
3437                         dev_err(&pdev->dev,
3438                                 "pci_set_consistent_dma_mask failed\n");
3439                         err = -EIO;
3440                         goto err_set_mask;
3441                 }
3442                 dma64 = true;
3443         } else {
3444                 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
3445                         dev_err(&pdev->dev,
3446                                 "pci_set_dma_mask failed\n");
3447                         err = -EIO;
3448                         goto err_set_mask;
3449                 }
3450                 dma64 = false;
3451         }
3452
3453         spin_lock_init(&adapter->cmd_lock);
3454         adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3455                                              sizeof(struct vmxnet3_adapter),
3456                                              PCI_DMA_TODEVICE);
3457         if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3458                 dev_err(&pdev->dev, "Failed to map dma\n");
3459                 err = -EFAULT;
3460                 goto err_set_mask;
3461         }
3462         adapter->shared = dma_alloc_coherent(
3463                                 &adapter->pdev->dev,
3464                                 sizeof(struct Vmxnet3_DriverShared),
3465                                 &adapter->shared_pa, GFP_KERNEL);
3466         if (!adapter->shared) {
3467                 dev_err(&pdev->dev, "Failed to allocate memory\n");
3468                 err = -ENOMEM;
3469                 goto err_alloc_shared;
3470         }
3471
3472         adapter->num_rx_queues = num_rx_queues;
3473         adapter->num_tx_queues = num_tx_queues;
3474         adapter->rx_buf_per_pkt = 1;
3475
3476         size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3477         size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
3478         adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3479                                                 &adapter->queue_desc_pa,
3480                                                 GFP_KERNEL);
3481
3482         if (!adapter->tqd_start) {
3483                 dev_err(&pdev->dev, "Failed to allocate memory\n");
3484                 err = -ENOMEM;
3485                 goto err_alloc_queue_desc;
3486         }
3487         adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
3488                                                             adapter->num_tx_queues);
3489
3490         adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3491                                               sizeof(struct Vmxnet3_PMConf),
3492                                               &adapter->pm_conf_pa,
3493                                               GFP_KERNEL);
3494         if (adapter->pm_conf == NULL) {
3495                 err = -ENOMEM;
3496                 goto err_alloc_pm;
3497         }
3498
3499 #ifdef VMXNET3_RSS
3500
3501         adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3502                                                sizeof(struct UPT1_RSSConf),
3503                                                &adapter->rss_conf_pa,
3504                                                GFP_KERNEL);
3505         if (adapter->rss_conf == NULL) {
3506                 err = -ENOMEM;
3507                 goto err_alloc_rss;
3508         }
3509 #endif /* VMXNET3_RSS */
3510
3511         err = vmxnet3_alloc_pci_resources(adapter);
3512         if (err < 0)
3513                 goto err_alloc_pci;
3514
3515         ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
3516         if (ver & (1 << VMXNET3_REV_4)) {
3517                 VMXNET3_WRITE_BAR1_REG(adapter,
3518                                        VMXNET3_REG_VRRS,
3519                                        1 << VMXNET3_REV_4);
3520                 adapter->version = VMXNET3_REV_4 + 1;
3521         } else if (ver & (1 << VMXNET3_REV_3)) {
3522                 VMXNET3_WRITE_BAR1_REG(adapter,
3523                                        VMXNET3_REG_VRRS,
3524                                        1 << VMXNET3_REV_3);
3525                 adapter->version = VMXNET3_REV_3 + 1;
3526         } else if (ver & (1 << VMXNET3_REV_2)) {
3527                 VMXNET3_WRITE_BAR1_REG(adapter,
3528                                        VMXNET3_REG_VRRS,
3529                                        1 << VMXNET3_REV_2);
3530                 adapter->version = VMXNET3_REV_2 + 1;
3531         } else if (ver & (1 << VMXNET3_REV_1)) {
3532                 VMXNET3_WRITE_BAR1_REG(adapter,
3533                                        VMXNET3_REG_VRRS,
3534                                        1 << VMXNET3_REV_1);
3535                 adapter->version = VMXNET3_REV_1 + 1;
3536         } else {
3537                 dev_err(&pdev->dev,
3538                         "Incompatible h/w version (0x%x) for adapter\n", ver);
3539                 err = -EBUSY;
3540                 goto err_ver;
3541         }
3542         dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
3543
3544         ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3545         if (ver & 1) {
3546                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3547         } else {
3548                 dev_err(&pdev->dev,
3549                         "Incompatible upt version (0x%x) for adapter\n", ver);
3550                 err = -EBUSY;
3551                 goto err_ver;
3552         }
3553
3554         if (VMXNET3_VERSION_GE_3(adapter)) {
3555                 adapter->coal_conf =
3556                         dma_alloc_coherent(&adapter->pdev->dev,
3557                                            sizeof(struct Vmxnet3_CoalesceScheme)
3558                                            ,
3559                                            &adapter->coal_conf_pa,
3560                                            GFP_KERNEL);
3561                 if (!adapter->coal_conf) {
3562                         err = -ENOMEM;
3563                         goto err_ver;
3564                 }
3565                 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
3566                 adapter->default_coal_mode = true;
3567         }
3568
3569         if (VMXNET3_VERSION_GE_4(adapter)) {
3570                 adapter->default_rss_fields = true;
3571                 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
3572         }
3573
3574         SET_NETDEV_DEV(netdev, &pdev->dev);
3575         vmxnet3_declare_features(adapter, dma64);
3576
3577         adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3578                 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3579
3580         if (adapter->num_tx_queues == adapter->num_rx_queues)
3581                 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3582         else
3583                 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3584
3585         vmxnet3_alloc_intr_resources(adapter);
3586
3587 #ifdef VMXNET3_RSS
3588         if (adapter->num_rx_queues > 1 &&
3589             adapter->intr.type == VMXNET3_IT_MSIX) {
3590                 adapter->rss = true;
3591                 netdev->hw_features |= NETIF_F_RXHASH;
3592                 netdev->features |= NETIF_F_RXHASH;
3593                 dev_dbg(&pdev->dev, "RSS is enabled.\n");
3594         } else {
3595                 adapter->rss = false;
3596         }
3597 #endif
3598
3599         vmxnet3_read_mac_addr(adapter, mac);
3600         memcpy(netdev->dev_addr,  mac, netdev->addr_len);
3601
3602         netdev->netdev_ops = &vmxnet3_netdev_ops;
3603         vmxnet3_set_ethtool_ops(netdev);
3604         netdev->watchdog_timeo = 5 * HZ;
3605
3606         /* MTU range: 60 - 9000 */
3607         netdev->min_mtu = VMXNET3_MIN_MTU;
3608         netdev->max_mtu = VMXNET3_MAX_MTU;
3609
3610         INIT_WORK(&adapter->work, vmxnet3_reset_work);
3611         set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3612
3613         if (adapter->intr.type == VMXNET3_IT_MSIX) {
3614                 int i;
3615                 for (i = 0; i < adapter->num_rx_queues; i++) {
3616                         netif_napi_add(adapter->netdev,
3617                                        &adapter->rx_queue[i].napi,
3618                                        vmxnet3_poll_rx_only, 64);
3619                 }
3620         } else {
3621                 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3622                                vmxnet3_poll, 64);
3623         }
3624
3625         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3626         netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3627
3628         netif_carrier_off(netdev);
3629         err = register_netdev(netdev);
3630
3631         if (err) {
3632                 dev_err(&pdev->dev, "Failed to register adapter\n");
3633                 goto err_register;
3634         }
3635
3636         vmxnet3_check_link(adapter, false);
3637         return 0;
3638
3639 err_register:
3640         if (VMXNET3_VERSION_GE_3(adapter)) {
3641                 dma_free_coherent(&adapter->pdev->dev,
3642                                   sizeof(struct Vmxnet3_CoalesceScheme),
3643                                   adapter->coal_conf, adapter->coal_conf_pa);
3644         }
3645         vmxnet3_free_intr_resources(adapter);
3646 err_ver:
3647         vmxnet3_free_pci_resources(adapter);
3648 err_alloc_pci:
3649 #ifdef VMXNET3_RSS
3650         dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3651                           adapter->rss_conf, adapter->rss_conf_pa);
3652 err_alloc_rss:
3653 #endif
3654         dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3655                           adapter->pm_conf, adapter->pm_conf_pa);
3656 err_alloc_pm:
3657         dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3658                           adapter->queue_desc_pa);
3659 err_alloc_queue_desc:
3660         dma_free_coherent(&adapter->pdev->dev,
3661                           sizeof(struct Vmxnet3_DriverShared),
3662                           adapter->shared, adapter->shared_pa);
3663 err_alloc_shared:
3664         dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3665                          sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3666 err_set_mask:
3667         free_netdev(netdev);
3668         return err;
3669 }
3670
3671
3672 static void
3673 vmxnet3_remove_device(struct pci_dev *pdev)
3674 {
3675         struct net_device *netdev = pci_get_drvdata(pdev);
3676         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3677         int size = 0;
3678         int num_rx_queues;
3679
3680 #ifdef VMXNET3_RSS
3681         if (enable_mq)
3682                 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3683                                     (int)num_online_cpus());
3684         else
3685 #endif
3686                 num_rx_queues = 1;
3687         num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3688
3689         cancel_work_sync(&adapter->work);
3690
3691         unregister_netdev(netdev);
3692
3693         vmxnet3_free_intr_resources(adapter);
3694         vmxnet3_free_pci_resources(adapter);
3695         if (VMXNET3_VERSION_GE_3(adapter)) {
3696                 dma_free_coherent(&adapter->pdev->dev,
3697                                   sizeof(struct Vmxnet3_CoalesceScheme),
3698                                   adapter->coal_conf, adapter->coal_conf_pa);
3699         }
3700 #ifdef VMXNET3_RSS
3701         dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3702                           adapter->rss_conf, adapter->rss_conf_pa);
3703 #endif
3704         dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3705                           adapter->pm_conf, adapter->pm_conf_pa);
3706
3707         size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3708         size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3709         dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3710                           adapter->queue_desc_pa);
3711         dma_free_coherent(&adapter->pdev->dev,
3712                           sizeof(struct Vmxnet3_DriverShared),
3713                           adapter->shared, adapter->shared_pa);
3714         dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3715                          sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3716         free_netdev(netdev);
3717 }
3718
3719 static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3720 {
3721         struct net_device *netdev = pci_get_drvdata(pdev);
3722         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3723         unsigned long flags;
3724
3725         /* Reset_work may be in the middle of resetting the device, wait for its
3726          * completion.
3727          */
3728         while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3729                 usleep_range(1000, 2000);
3730
3731         if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3732                              &adapter->state)) {
3733                 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3734                 return;
3735         }
3736         spin_lock_irqsave(&adapter->cmd_lock, flags);
3737         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3738                                VMXNET3_CMD_QUIESCE_DEV);
3739         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3740         vmxnet3_disable_all_intrs(adapter);
3741
3742         clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3743 }
3744
3745
3746 #ifdef CONFIG_PM
3747
3748 static int
3749 vmxnet3_suspend(struct device *device)
3750 {
3751         struct pci_dev *pdev = to_pci_dev(device);
3752         struct net_device *netdev = pci_get_drvdata(pdev);
3753         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3754         struct Vmxnet3_PMConf *pmConf;
3755         struct ethhdr *ehdr;
3756         struct arphdr *ahdr;
3757         u8 *arpreq;
3758         struct in_device *in_dev;
3759         struct in_ifaddr *ifa;
3760         unsigned long flags;
3761         int i = 0;
3762
3763         if (!netif_running(netdev))
3764                 return 0;
3765
3766         for (i = 0; i < adapter->num_rx_queues; i++)
3767                 napi_disable(&adapter->rx_queue[i].napi);
3768
3769         vmxnet3_disable_all_intrs(adapter);
3770         vmxnet3_free_irqs(adapter);
3771         vmxnet3_free_intr_resources(adapter);
3772
3773         netif_device_detach(netdev);
3774
3775         /* Create wake-up filters. */
3776         pmConf = adapter->pm_conf;
3777         memset(pmConf, 0, sizeof(*pmConf));
3778
3779         if (adapter->wol & WAKE_UCAST) {
3780                 pmConf->filters[i].patternSize = ETH_ALEN;
3781                 pmConf->filters[i].maskSize = 1;
3782                 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3783                 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3784
3785                 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3786                 i++;
3787         }
3788
3789         if (adapter->wol & WAKE_ARP) {
3790                 rcu_read_lock();
3791
3792                 in_dev = __in_dev_get_rcu(netdev);
3793                 if (!in_dev) {
3794                         rcu_read_unlock();
3795                         goto skip_arp;
3796                 }
3797
3798                 ifa = rcu_dereference(in_dev->ifa_list);
3799                 if (!ifa) {
3800                         rcu_read_unlock();
3801                         goto skip_arp;
3802                 }
3803
3804                 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3805                         sizeof(struct arphdr) +         /* ARP header */
3806                         2 * ETH_ALEN +          /* 2 Ethernet addresses*/
3807                         2 * sizeof(u32);        /*2 IPv4 addresses */
3808                 pmConf->filters[i].maskSize =
3809                         (pmConf->filters[i].patternSize - 1) / 8 + 1;
3810
3811                 /* ETH_P_ARP in Ethernet header. */
3812                 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3813                 ehdr->h_proto = htons(ETH_P_ARP);
3814
3815                 /* ARPOP_REQUEST in ARP header. */
3816                 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3817                 ahdr->ar_op = htons(ARPOP_REQUEST);
3818                 arpreq = (u8 *)(ahdr + 1);
3819
3820                 /* The Unicast IPv4 address in 'tip' field. */
3821                 arpreq += 2 * ETH_ALEN + sizeof(u32);
3822                 *(__be32 *)arpreq = ifa->ifa_address;
3823
3824                 rcu_read_unlock();
3825
3826                 /* The mask for the relevant bits. */
3827                 pmConf->filters[i].mask[0] = 0x00;
3828                 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3829                 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3830                 pmConf->filters[i].mask[3] = 0x00;
3831                 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3832                 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3833
3834                 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3835                 i++;
3836         }
3837
3838 skip_arp:
3839         if (adapter->wol & WAKE_MAGIC)
3840                 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3841
3842         pmConf->numFilters = i;
3843
3844         adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3845         adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3846                                                                   *pmConf));
3847         adapter->shared->devRead.pmConfDesc.confPA =
3848                 cpu_to_le64(adapter->pm_conf_pa);
3849
3850         spin_lock_irqsave(&adapter->cmd_lock, flags);
3851         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3852                                VMXNET3_CMD_UPDATE_PMCFG);
3853         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3854
3855         pci_save_state(pdev);
3856         pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3857                         adapter->wol);
3858         pci_disable_device(pdev);
3859         pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3860
3861         return 0;
3862 }
3863
3864
3865 static int
3866 vmxnet3_resume(struct device *device)
3867 {
3868         int err;
3869         unsigned long flags;
3870         struct pci_dev *pdev = to_pci_dev(device);
3871         struct net_device *netdev = pci_get_drvdata(pdev);
3872         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3873
3874         if (!netif_running(netdev))
3875                 return 0;
3876
3877         pci_set_power_state(pdev, PCI_D0);
3878         pci_restore_state(pdev);
3879         err = pci_enable_device_mem(pdev);
3880         if (err != 0)
3881                 return err;
3882
3883         pci_enable_wake(pdev, PCI_D0, 0);
3884
3885         vmxnet3_alloc_intr_resources(adapter);
3886
3887         /* During hibernate and suspend, device has to be reinitialized as the
3888          * device state need not be preserved.
3889          */
3890
3891         /* Need not check adapter state as other reset tasks cannot run during
3892          * device resume.
3893          */
3894         spin_lock_irqsave(&adapter->cmd_lock, flags);
3895         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3896                                VMXNET3_CMD_QUIESCE_DEV);
3897         spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3898         vmxnet3_tq_cleanup_all(adapter);
3899         vmxnet3_rq_cleanup_all(adapter);
3900
3901         vmxnet3_reset_dev(adapter);
3902         err = vmxnet3_activate_dev(adapter);
3903         if (err != 0) {
3904                 netdev_err(netdev,
3905                            "failed to re-activate on resume, error: %d", err);
3906                 vmxnet3_force_close(adapter);
3907                 return err;
3908         }
3909         netif_device_attach(netdev);
3910
3911         return 0;
3912 }
3913
3914 static const struct dev_pm_ops vmxnet3_pm_ops = {
3915         .suspend = vmxnet3_suspend,
3916         .resume = vmxnet3_resume,
3917         .freeze = vmxnet3_suspend,
3918         .restore = vmxnet3_resume,
3919 };
3920 #endif
3921
3922 static struct pci_driver vmxnet3_driver = {
3923         .name           = vmxnet3_driver_name,
3924         .id_table       = vmxnet3_pciid_table,
3925         .probe          = vmxnet3_probe_device,
3926         .remove         = vmxnet3_remove_device,
3927         .shutdown       = vmxnet3_shutdown_device,
3928 #ifdef CONFIG_PM
3929         .driver.pm      = &vmxnet3_pm_ops,
3930 #endif
3931 };
3932
3933
3934 static int __init
3935 vmxnet3_init_module(void)
3936 {
3937         pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
3938                 VMXNET3_DRIVER_VERSION_REPORT);
3939         return pci_register_driver(&vmxnet3_driver);
3940 }
3941
3942 module_init(vmxnet3_init_module);
3943
3944
3945 static void
3946 vmxnet3_exit_module(void)
3947 {
3948         pci_unregister_driver(&vmxnet3_driver);
3949 }
3950
3951 module_exit(vmxnet3_exit_module);
3952
3953 MODULE_AUTHOR("VMware, Inc.");
3954 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3955 MODULE_LICENSE("GPL v2");
3956 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);