GNU Linux-libre 4.14.302-gnu1
[releases.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION         "09"
33
34 /* Information for net */
35 #define NET_VERSION             "9"
36
37 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID            32
43
44 #define PLA_IDR                 0xc000
45 #define PLA_RCR                 0xc010
46 #define PLA_RMS                 0xc016
47 #define PLA_RXFIFO_CTRL0        0xc0a0
48 #define PLA_RXFIFO_CTRL1        0xc0a4
49 #define PLA_RXFIFO_CTRL2        0xc0a8
50 #define PLA_DMY_REG0            0xc0b0
51 #define PLA_FMC                 0xc0b4
52 #define PLA_CFG_WOL             0xc0b6
53 #define PLA_TEREDO_CFG          0xc0bc
54 #define PLA_TEREDO_WAKE_BASE    0xc0c4
55 #define PLA_MAR                 0xcd00
56 #define PLA_BACKUP              0xd000
57 #define PAL_BDC_CR              0xd1a0
58 #define PLA_TEREDO_TIMER        0xd2cc
59 #define PLA_REALWOW_TIMER       0xd2e8
60 #define PLA_EFUSE_DATA          0xdd00
61 #define PLA_EFUSE_CMD           0xdd02
62 #define PLA_LEDSEL              0xdd90
63 #define PLA_LED_FEATURE         0xdd92
64 #define PLA_PHYAR               0xde00
65 #define PLA_BOOT_CTRL           0xe004
66 #define PLA_GPHY_INTR_IMR       0xe022
67 #define PLA_EEE_CR              0xe040
68 #define PLA_EEEP_CR             0xe080
69 #define PLA_MAC_PWR_CTRL        0xe0c0
70 #define PLA_MAC_PWR_CTRL2       0xe0ca
71 #define PLA_MAC_PWR_CTRL3       0xe0cc
72 #define PLA_MAC_PWR_CTRL4       0xe0ce
73 #define PLA_WDT6_CTRL           0xe428
74 #define PLA_TCR0                0xe610
75 #define PLA_TCR1                0xe612
76 #define PLA_MTPS                0xe615
77 #define PLA_TXFIFO_CTRL         0xe618
78 #define PLA_RSTTALLY            0xe800
79 #define PLA_CR                  0xe813
80 #define PLA_CRWECR              0xe81c
81 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5             0xe822
84 #define PLA_PHY_PWR             0xe84c
85 #define PLA_OOB_CTRL            0xe84f
86 #define PLA_CPCR                0xe854
87 #define PLA_MISC_0              0xe858
88 #define PLA_MISC_1              0xe85a
89 #define PLA_OCP_GPHY_BASE       0xe86c
90 #define PLA_TALLYCNT            0xe890
91 #define PLA_SFF_STS_7           0xe8de
92 #define PLA_PHYSTATUS           0xe908
93 #define PLA_BP_BA               0xfc26
94 #define PLA_BP_0                0xfc28
95 #define PLA_BP_1                0xfc2a
96 #define PLA_BP_2                0xfc2c
97 #define PLA_BP_3                0xfc2e
98 #define PLA_BP_4                0xfc30
99 #define PLA_BP_5                0xfc32
100 #define PLA_BP_6                0xfc34
101 #define PLA_BP_7                0xfc36
102 #define PLA_BP_EN               0xfc38
103
104 #define USB_USB2PHY             0xb41e
105 #define USB_SSPHYLINK2          0xb428
106 #define USB_U2P3_CTRL           0xb460
107 #define USB_CSR_DUMMY1          0xb464
108 #define USB_CSR_DUMMY2          0xb466
109 #define USB_DEV_STAT            0xb808
110 #define USB_CONNECT_TIMER       0xcbf8
111 #define USB_MSC_TIMER           0xcbfc
112 #define USB_BURST_SIZE          0xcfc0
113 #define USB_LPM_CONFIG          0xcfd8
114 #define USB_USB_CTRL            0xd406
115 #define USB_PHY_CTRL            0xd408
116 #define USB_TX_AGG              0xd40a
117 #define USB_RX_BUF_TH           0xd40c
118 #define USB_USB_TIMER           0xd428
119 #define USB_RX_EARLY_TIMEOUT    0xd42c
120 #define USB_RX_EARLY_SIZE       0xd42e
121 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
123 #define USB_TX_DMA              0xd434
124 #define USB_UPT_RXDMA_OWN       0xd437
125 #define USB_TOLERANCE           0xd490
126 #define USB_LPM_CTRL            0xd41a
127 #define USB_BMU_RESET           0xd4b0
128 #define USB_U1U2_TIMER          0xd4da
129 #define USB_UPS_CTRL            0xd800
130 #define USB_POWER_CUT           0xd80a
131 #define USB_MISC_0              0xd81a
132 #define USB_AFE_CTRL2           0xd824
133 #define USB_UPS_CFG             0xd842
134 #define USB_UPS_FLAGS           0xd848
135 #define USB_WDT11_CTRL          0xe43c
136 #define USB_BP_BA               0xfc26
137 #define USB_BP_0                0xfc28
138 #define USB_BP_1                0xfc2a
139 #define USB_BP_2                0xfc2c
140 #define USB_BP_3                0xfc2e
141 #define USB_BP_4                0xfc30
142 #define USB_BP_5                0xfc32
143 #define USB_BP_6                0xfc34
144 #define USB_BP_7                0xfc36
145 #define USB_BP_EN               0xfc38
146 #define USB_BP_8                0xfc38
147 #define USB_BP_9                0xfc3a
148 #define USB_BP_10               0xfc3c
149 #define USB_BP_11               0xfc3e
150 #define USB_BP_12               0xfc40
151 #define USB_BP_13               0xfc42
152 #define USB_BP_14               0xfc44
153 #define USB_BP_15               0xfc46
154 #define USB_BP2_EN              0xfc48
155
156 /* OCP Registers */
157 #define OCP_ALDPS_CONFIG        0x2010
158 #define OCP_EEE_CONFIG1         0x2080
159 #define OCP_EEE_CONFIG2         0x2092
160 #define OCP_EEE_CONFIG3         0x2094
161 #define OCP_BASE_MII            0xa400
162 #define OCP_EEE_AR              0xa41a
163 #define OCP_EEE_DATA            0xa41c
164 #define OCP_PHY_STATUS          0xa420
165 #define OCP_NCTL_CFG            0xa42c
166 #define OCP_POWER_CFG           0xa430
167 #define OCP_EEE_CFG             0xa432
168 #define OCP_SRAM_ADDR           0xa436
169 #define OCP_SRAM_DATA           0xa438
170 #define OCP_DOWN_SPEED          0xa442
171 #define OCP_EEE_ABLE            0xa5c4
172 #define OCP_EEE_ADV             0xa5d0
173 #define OCP_EEE_LPABLE          0xa5d2
174 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT      0xb800
176 #define OCP_PHY_PATCH_CMD       0xb820
177 #define OCP_ADC_IOFFSET         0xbcfc
178 #define OCP_ADC_CFG             0xbc06
179 #define OCP_SYSCLK_CFG          0xc416
180
181 /* SRAM Register */
182 #define SRAM_GREEN_CFG          0x8011
183 #define SRAM_LPF_CFG            0x8012
184 #define SRAM_10M_AMP1           0x8080
185 #define SRAM_10M_AMP2           0x8082
186 #define SRAM_IMPEDANCE          0x8084
187
188 /* PLA_RCR */
189 #define RCR_AAP                 0x00000001
190 #define RCR_APM                 0x00000002
191 #define RCR_AM                  0x00000004
192 #define RCR_AB                  0x00000008
193 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
194
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL      0x00080002
197 #define RXFIFO_THR1_OOB         0x01800003
198
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL        0x00000060
201 #define RXFIFO_THR2_HIGH        0x00000038
202 #define RXFIFO_THR2_OOB         0x0000004a
203 #define RXFIFO_THR2_NORMAL      0x00a0
204
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL        0x00000078
207 #define RXFIFO_THR3_HIGH        0x00000048
208 #define RXFIFO_THR3_OOB         0x0000005a
209 #define RXFIFO_THR3_NORMAL      0x0110
210
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL       0x00400008
213 #define TXFIFO_THR_NORMAL2      0x01000008
214
215 /* PLA_DMY_REG0 */
216 #define ECM_ALDPS               0x0002
217
218 /* PLA_FMC */
219 #define FMC_FCR_MCU_EN          0x0001
220
221 /* PLA_EEEP_CR */
222 #define EEEP_CR_EEEP_TX         0x0002
223
224 /* PLA_WDT6_CTRL */
225 #define WDT6_SET_MODE           0x0010
226
227 /* PLA_TCR0 */
228 #define TCR0_TX_EMPTY           0x0800
229 #define TCR0_AUTO_FIFO          0x0080
230
231 /* PLA_TCR1 */
232 #define VERSION_MASK            0x7cf0
233
234 /* PLA_MTPS */
235 #define MTPS_JUMBO              (12 * 1024 / 64)
236 #define MTPS_DEFAULT            (6 * 1024 / 64)
237
238 /* PLA_RSTTALLY */
239 #define TALLY_RESET             0x0001
240
241 /* PLA_CR */
242 #define CR_RST                  0x10
243 #define CR_RE                   0x08
244 #define CR_TE                   0x04
245
246 /* PLA_CRWECR */
247 #define CRWECR_NORAML           0x00
248 #define CRWECR_CONFIG           0xc0
249
250 /* PLA_OOB_CTRL */
251 #define NOW_IS_OOB              0x80
252 #define TXFIFO_EMPTY            0x20
253 #define RXFIFO_EMPTY            0x10
254 #define LINK_LIST_READY         0x02
255 #define DIS_MCU_CLROOB          0x01
256 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
257
258 /* PLA_MISC_1 */
259 #define RXDY_GATED_EN           0x0008
260
261 /* PLA_SFF_STS_7 */
262 #define RE_INIT_LL              0x8000
263 #define MCU_BORW_EN             0x4000
264
265 /* PLA_CPCR */
266 #define CPCR_RX_VLAN            0x0040
267
268 /* PLA_CFG_WOL */
269 #define MAGIC_EN                0x0001
270
271 /* PLA_TEREDO_CFG */
272 #define TEREDO_SEL              0x8000
273 #define TEREDO_WAKE_MASK        0x7f00
274 #define TEREDO_RS_EVENT_MASK    0x00fe
275 #define OOB_TEREDO_EN           0x0001
276
277 /* PAL_BDC_CR */
278 #define ALDPS_PROXY_MODE        0x0001
279
280 /* PLA_EFUSE_CMD */
281 #define EFUSE_READ_CMD          BIT(15)
282 #define EFUSE_DATA_BIT16        BIT(7)
283
284 /* PLA_CONFIG34 */
285 #define LINK_ON_WAKE_EN         0x0010
286 #define LINK_OFF_WAKE_EN        0x0008
287
288 /* PLA_CONFIG5 */
289 #define BWF_EN                  0x0040
290 #define MWF_EN                  0x0020
291 #define UWF_EN                  0x0010
292 #define LAN_WAKE_EN             0x0002
293
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK           0x0700
296
297 /* PLA_PHY_PWR */
298 #define TX_10M_IDLE_EN          0x0080
299 #define PFM_PWM_SWITCH          0x0040
300
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN         0x00004000
303 #define MCU_CLK_RATIO           0x07010f07
304 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO       0x0f87
306
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO         0x8007
309 #define MAC_CLK_SPDWN_EN        BIT(15)
310
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN      0x0100
313 #define SUSPEND_SPDWN_EN        0x0004
314 #define U1U2_SPDWN_EN           0x0002
315 #define L1_SPDWN_EN             0x0001
316
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN        0x1000
319 #define RXDV_SPDWN_EN           0x0800
320 #define TX10MIDLE_EN            0x0100
321 #define TP100_SPDWN_EN          0x0020
322 #define TP500_SPDWN_EN          0x0010
323 #define TP1000_SPDWN_EN         0x0008
324 #define EEE_SPDWN_EN            0x0001
325
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK            0x0001
328 #define SPEED_DOWN_MSK          0x0002
329 #define SPDWN_RXDV_MSK          0x0004
330 #define SPDWN_LINKCHG_MSK       0x0008
331
332 /* PLA_PHYAR */
333 #define PHYAR_FLAG              0x80000000
334
335 /* PLA_EEE_CR */
336 #define EEE_RX_EN               0x0001
337 #define EEE_TX_EN               0x0002
338
339 /* PLA_BOOT_CTRL */
340 #define AUTOLOAD_DONE           0x0002
341
342 /* USB_USB2PHY */
343 #define USB2PHY_SUSPEND         0x0001
344 #define USB2PHY_L1              0x0002
345
346 /* USB_SSPHYLINK2 */
347 #define pwd_dn_scale_mask       0x3ffe
348 #define pwd_dn_scale(x)         ((x) << 1)
349
350 /* USB_CSR_DUMMY1 */
351 #define DYNAMIC_BURST           0x0001
352
353 /* USB_CSR_DUMMY2 */
354 #define EP4_FULL_FC             0x0001
355
356 /* USB_DEV_STAT */
357 #define STAT_SPEED_MASK         0x0006
358 #define STAT_SPEED_HIGH         0x0000
359 #define STAT_SPEED_FULL         0x0002
360
361 /* USB_LPM_CONFIG */
362 #define LPM_U1U2_EN             BIT(0)
363
364 /* USB_TX_AGG */
365 #define TX_AGG_MAX_THRESHOLD    0x03
366
367 /* USB_RX_BUF_TH */
368 #define RX_THR_SUPPER           0x0c350180
369 #define RX_THR_HIGH             0x7a120180
370 #define RX_THR_SLOW             0xffff0180
371 #define RX_THR_B                0x00010001
372
373 /* USB_TX_DMA */
374 #define TEST_MODE_DISABLE       0x00000001
375 #define TX_SIZE_ADJUST1         0x00000100
376
377 /* USB_BMU_RESET */
378 #define BMU_RESET_EP_IN         0x01
379 #define BMU_RESET_EP_OUT        0x02
380
381 /* USB_UPT_RXDMA_OWN */
382 #define OWN_UPDATE              BIT(0)
383 #define OWN_CLEAR               BIT(1)
384
385 /* USB_UPS_CTRL */
386 #define POWER_CUT               0x0100
387
388 /* USB_PM_CTRL_STATUS */
389 #define RESUME_INDICATE         0x0001
390
391 /* USB_USB_CTRL */
392 #define RX_AGG_DISABLE          0x0010
393 #define RX_ZERO_EN              0x0080
394
395 /* USB_U2P3_CTRL */
396 #define U2P3_ENABLE             0x0001
397
398 /* USB_POWER_CUT */
399 #define PWR_EN                  0x0001
400 #define PHASE2_EN               0x0008
401 #define UPS_EN                  BIT(4)
402 #define USP_PREWAKE             BIT(5)
403
404 /* USB_MISC_0 */
405 #define PCUT_STATUS             0x0001
406
407 /* USB_RX_EARLY_TIMEOUT */
408 #define COALESCE_SUPER           85000U
409 #define COALESCE_HIGH           250000U
410 #define COALESCE_SLOW           524280U
411
412 /* USB_WDT11_CTRL */
413 #define TIMER11_EN              0x0001
414
415 /* USB_LPM_CTRL */
416 /* bit 4 ~ 5: fifo empty boundary */
417 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
418 /* bit 2 ~ 3: LMP timer */
419 #define LPM_TIMER_MASK          0x0c
420 #define LPM_TIMER_500MS         0x04    /* 500 ms */
421 #define LPM_TIMER_500US         0x0c    /* 500 us */
422 #define ROK_EXIT_LPM            0x02
423
424 /* USB_AFE_CTRL2 */
425 #define SEN_VAL_MASK            0xf800
426 #define SEN_VAL_NORMAL          0xa000
427 #define SEL_RXIDLE              0x0100
428
429 /* USB_UPS_CFG */
430 #define SAW_CNT_1MS_MASK        0x0fff
431
432 /* USB_UPS_FLAGS */
433 #define UPS_FLAGS_R_TUNE                BIT(0)
434 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
435 #define UPS_FLAGS_250M_CKDIV            BIT(2)
436 #define UPS_FLAGS_EN_ALDPS              BIT(3)
437 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
438 #define UPS_FLAGS_SPEED_MASK            (0xf << 16)
439 #define ups_flags_speed(x)              ((x) << 16)
440 #define UPS_FLAGS_EN_EEE                BIT(20)
441 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
442 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
443 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
444 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
445 #define UPS_FLAGS_EN_GREEN              BIT(26)
446 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
447
448 enum spd_duplex {
449         NWAY_10M_HALF = 1,
450         NWAY_10M_FULL,
451         NWAY_100M_HALF,
452         NWAY_100M_FULL,
453         NWAY_1000M_FULL,
454         FORCE_10M_HALF,
455         FORCE_10M_FULL,
456         FORCE_100M_HALF,
457         FORCE_100M_FULL,
458 };
459
460 /* OCP_ALDPS_CONFIG */
461 #define ENPWRSAVE               0x8000
462 #define ENPDNPS                 0x0200
463 #define LINKENA                 0x0100
464 #define DIS_SDSAVE              0x0010
465
466 /* OCP_PHY_STATUS */
467 #define PHY_STAT_MASK           0x0007
468 #define PHY_STAT_EXT_INIT       2
469 #define PHY_STAT_LAN_ON         3
470 #define PHY_STAT_PWRDN          5
471
472 /* OCP_NCTL_CFG */
473 #define PGA_RETURN_EN           BIT(1)
474
475 /* OCP_POWER_CFG */
476 #define EEE_CLKDIV_EN           0x8000
477 #define EN_ALDPS                0x0004
478 #define EN_10M_PLLOFF           0x0001
479
480 /* OCP_EEE_CONFIG1 */
481 #define RG_TXLPI_MSK_HFDUP      0x8000
482 #define RG_MATCLR_EN            0x4000
483 #define EEE_10_CAP              0x2000
484 #define EEE_NWAY_EN             0x1000
485 #define TX_QUIET_EN             0x0200
486 #define RX_QUIET_EN             0x0100
487 #define sd_rise_time_mask       0x0070
488 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
489 #define RG_RXLPI_MSK_HFDUP      0x0008
490 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
491
492 /* OCP_EEE_CONFIG2 */
493 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN          0x0400
495 #define RG_LDVQUIET_EN          0x0200
496 #define RG_CKRSEL               0x0020
497 #define RG_EEEPRG_EN            0x0010
498
499 /* OCP_EEE_CONFIG3 */
500 #define fast_snr_mask           0xff80
501 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
502 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
503 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
504
505 /* OCP_EEE_AR */
506 /* bit[15:14] function */
507 #define FUN_ADDR                0x0000
508 #define FUN_DATA                0x4000
509 /* bit[4:0] device addr */
510
511 /* OCP_EEE_CFG */
512 #define CTAP_SHORT_EN           0x0040
513 #define EEE10_EN                0x0010
514
515 /* OCP_DOWN_SPEED */
516 #define EN_EEE_CMODE            BIT(14)
517 #define EN_EEE_1000             BIT(13)
518 #define EN_EEE_100              BIT(12)
519 #define EN_10M_CLKDIV           BIT(11)
520 #define EN_10M_BGOFF            0x0080
521
522 /* OCP_PHY_STATE */
523 #define TXDIS_STATE             0x01
524 #define ABD_STATE               0x02
525
526 /* OCP_PHY_PATCH_STAT */
527 #define PATCH_READY             BIT(6)
528
529 /* OCP_PHY_PATCH_CMD */
530 #define PATCH_REQUEST           BIT(4)
531
532 /* OCP_ADC_CFG */
533 #define CKADSEL_L               0x0100
534 #define ADC_EN                  0x0080
535 #define EN_EMI_L                0x0040
536
537 /* OCP_SYSCLK_CFG */
538 #define clk_div_expo(x)         (min(x, 5) << 8)
539
540 /* SRAM_GREEN_CFG */
541 #define GREEN_ETH_EN            BIT(15)
542 #define R_TUNE_EN               BIT(11)
543
544 /* SRAM_LPF_CFG */
545 #define LPF_AUTO_TUNE           0x8000
546
547 /* SRAM_10M_AMP1 */
548 #define GDAC_IB_UPALL           0x0008
549
550 /* SRAM_10M_AMP2 */
551 #define AMP_DN                  0x0200
552
553 /* SRAM_IMPEDANCE */
554 #define RX_DRIVING_MASK         0x6000
555
556 /* MAC PASSTHRU */
557 #define AD_MASK                 0xfee0
558 #define EFUSE                   0xcfdb
559 #define PASS_THRU_MASK          0x1
560
561 enum rtl_register_content {
562         _1000bps        = 0x10,
563         _100bps         = 0x08,
564         _10bps          = 0x04,
565         LINK_STATUS     = 0x02,
566         FULL_DUP        = 0x01,
567 };
568
569 #define RTL8152_MAX_TX          4
570 #define RTL8152_MAX_RX          10
571 #define INTBUFSIZE              2
572 #define TX_ALIGN                4
573 #define RX_ALIGN                8
574
575 #define INTR_LINK               0x0004
576
577 #define RTL8152_REQT_READ       0xc0
578 #define RTL8152_REQT_WRITE      0x40
579 #define RTL8152_REQ_GET_REGS    0x05
580 #define RTL8152_REQ_SET_REGS    0x05
581
582 #define BYTE_EN_DWORD           0xff
583 #define BYTE_EN_WORD            0x33
584 #define BYTE_EN_BYTE            0x11
585 #define BYTE_EN_SIX_BYTES       0x3f
586 #define BYTE_EN_START_MASK      0x0f
587 #define BYTE_EN_END_MASK        0xf0
588
589 #define RTL8153_MAX_PACKET      9216 /* 9K */
590 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
591                                  ETH_FCS_LEN)
592 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
593 #define RTL8153_RMS             RTL8153_MAX_PACKET
594 #define RTL8152_TX_TIMEOUT      (5 * HZ)
595 #define RTL8152_NAPI_WEIGHT     64
596 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
597                                  sizeof(struct rx_desc) + RX_ALIGN)
598
599 /* rtl8152 flags */
600 enum rtl8152_flags {
601         RTL8152_UNPLUG = 0,
602         RTL8152_SET_RX_MODE,
603         WORK_ENABLE,
604         RTL8152_LINK_CHG,
605         SELECTIVE_SUSPEND,
606         PHY_RESET,
607         SCHEDULE_NAPI,
608         GREEN_ETHERNET,
609 };
610
611 /* Define these values to match your device */
612 #define VENDOR_ID_REALTEK               0x0bda
613 #define VENDOR_ID_MICROSOFT             0x045e
614 #define VENDOR_ID_SAMSUNG               0x04e8
615 #define VENDOR_ID_LENOVO                0x17ef
616 #define VENDOR_ID_LINKSYS               0x13b1
617 #define VENDOR_ID_NVIDIA                0x0955
618 #define VENDOR_ID_TPLINK                0x2357
619
620 #define MCU_TYPE_PLA                    0x0100
621 #define MCU_TYPE_USB                    0x0000
622
623 struct tally_counter {
624         __le64  tx_packets;
625         __le64  rx_packets;
626         __le64  tx_errors;
627         __le32  rx_errors;
628         __le16  rx_missed;
629         __le16  align_errors;
630         __le32  tx_one_collision;
631         __le32  tx_multi_collision;
632         __le64  rx_unicast;
633         __le64  rx_broadcast;
634         __le32  rx_multicast;
635         __le16  tx_aborted;
636         __le16  tx_underrun;
637 };
638
639 struct rx_desc {
640         __le32 opts1;
641 #define RX_LEN_MASK                     0x7fff
642
643         __le32 opts2;
644 #define RD_UDP_CS                       BIT(23)
645 #define RD_TCP_CS                       BIT(22)
646 #define RD_IPV6_CS                      BIT(20)
647 #define RD_IPV4_CS                      BIT(19)
648
649         __le32 opts3;
650 #define IPF                             BIT(23) /* IP checksum fail */
651 #define UDPF                            BIT(22) /* UDP checksum fail */
652 #define TCPF                            BIT(21) /* TCP checksum fail */
653 #define RX_VLAN_TAG                     BIT(16)
654
655         __le32 opts4;
656         __le32 opts5;
657         __le32 opts6;
658 };
659
660 struct tx_desc {
661         __le32 opts1;
662 #define TX_FS                   BIT(31) /* First segment of a packet */
663 #define TX_LS                   BIT(30) /* Final segment of a packet */
664 #define GTSENDV4                BIT(28)
665 #define GTSENDV6                BIT(27)
666 #define GTTCPHO_SHIFT           18
667 #define GTTCPHO_MAX             0x7fU
668 #define TX_LEN_MAX              0x3ffffU
669
670         __le32 opts2;
671 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
672 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
673 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
674 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
675 #define MSS_SHIFT               17
676 #define MSS_MAX                 0x7ffU
677 #define TCPHO_SHIFT             17
678 #define TCPHO_MAX               0x7ffU
679 #define TX_VLAN_TAG             BIT(16)
680 };
681
682 struct r8152;
683
684 struct rx_agg {
685         struct list_head list;
686         struct urb *urb;
687         struct r8152 *context;
688         void *buffer;
689         void *head;
690 };
691
692 struct tx_agg {
693         struct list_head list;
694         struct urb *urb;
695         struct r8152 *context;
696         void *buffer;
697         void *head;
698         u32 skb_num;
699         u32 skb_len;
700 };
701
702 struct r8152 {
703         unsigned long flags;
704         struct usb_device *udev;
705         struct napi_struct napi;
706         struct usb_interface *intf;
707         struct net_device *netdev;
708         struct urb *intr_urb;
709         struct tx_agg tx_info[RTL8152_MAX_TX];
710         struct rx_agg rx_info[RTL8152_MAX_RX];
711         struct list_head rx_done, tx_free;
712         struct sk_buff_head tx_queue, rx_queue;
713         spinlock_t rx_lock, tx_lock;
714         struct delayed_work schedule, hw_phy_work;
715         struct mii_if_info mii;
716         struct mutex control;   /* use for hw setting */
717 #ifdef CONFIG_PM_SLEEP
718         struct notifier_block pm_notifier;
719 #endif
720
721         struct rtl_ops {
722                 void (*init)(struct r8152 *);
723                 int (*enable)(struct r8152 *);
724                 void (*disable)(struct r8152 *);
725                 void (*up)(struct r8152 *);
726                 void (*down)(struct r8152 *);
727                 void (*unload)(struct r8152 *);
728                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
729                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
730                 bool (*in_nway)(struct r8152 *);
731                 void (*hw_phy_cfg)(struct r8152 *);
732                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
733         } rtl_ops;
734
735         int intr_interval;
736         u32 saved_wolopts;
737         u32 msg_enable;
738         u32 tx_qlen;
739         u32 coalesce;
740         u16 ocp_base;
741         u16 speed;
742         u8 *intr_buff;
743         u8 version;
744         u8 duplex;
745         u8 autoneg;
746 };
747
748 enum rtl_version {
749         RTL_VER_UNKNOWN = 0,
750         RTL_VER_01,
751         RTL_VER_02,
752         RTL_VER_03,
753         RTL_VER_04,
754         RTL_VER_05,
755         RTL_VER_06,
756         RTL_VER_07,
757         RTL_VER_08,
758         RTL_VER_09,
759         RTL_VER_MAX
760 };
761
762 enum tx_csum_stat {
763         TX_CSUM_SUCCESS = 0,
764         TX_CSUM_TSO,
765         TX_CSUM_NONE
766 };
767
768 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
769  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
770  */
771 static const int multicast_filter_limit = 32;
772 static unsigned int agg_buf_sz = 16384;
773
774 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
775                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
776
777 static
778 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
779 {
780         int ret;
781         void *tmp;
782
783         tmp = kmalloc(size, GFP_KERNEL);
784         if (!tmp)
785                 return -ENOMEM;
786
787         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
788                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
789                               value, index, tmp, size, 500);
790         if (ret < 0)
791                 memset(data, 0xff, size);
792         else
793                 memcpy(data, tmp, size);
794
795         kfree(tmp);
796
797         return ret;
798 }
799
800 static
801 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
802 {
803         int ret;
804         void *tmp;
805
806         tmp = kmemdup(data, size, GFP_KERNEL);
807         if (!tmp)
808                 return -ENOMEM;
809
810         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
811                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
812                               value, index, tmp, size, 500);
813
814         kfree(tmp);
815
816         return ret;
817 }
818
819 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
820                             void *data, u16 type)
821 {
822         u16 limit = 64;
823         int ret = 0;
824
825         if (test_bit(RTL8152_UNPLUG, &tp->flags))
826                 return -ENODEV;
827
828         /* both size and indix must be 4 bytes align */
829         if ((size & 3) || !size || (index & 3) || !data)
830                 return -EPERM;
831
832         if ((u32)index + (u32)size > 0xffff)
833                 return -EPERM;
834
835         while (size) {
836                 if (size > limit) {
837                         ret = get_registers(tp, index, type, limit, data);
838                         if (ret < 0)
839                                 break;
840
841                         index += limit;
842                         data += limit;
843                         size -= limit;
844                 } else {
845                         ret = get_registers(tp, index, type, size, data);
846                         if (ret < 0)
847                                 break;
848
849                         index += size;
850                         data += size;
851                         size = 0;
852                         break;
853                 }
854         }
855
856         if (ret == -ENODEV)
857                 set_bit(RTL8152_UNPLUG, &tp->flags);
858
859         return ret;
860 }
861
862 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
863                              u16 size, void *data, u16 type)
864 {
865         int ret;
866         u16 byteen_start, byteen_end, byen;
867         u16 limit = 512;
868
869         if (test_bit(RTL8152_UNPLUG, &tp->flags))
870                 return -ENODEV;
871
872         /* both size and indix must be 4 bytes align */
873         if ((size & 3) || !size || (index & 3) || !data)
874                 return -EPERM;
875
876         if ((u32)index + (u32)size > 0xffff)
877                 return -EPERM;
878
879         byteen_start = byteen & BYTE_EN_START_MASK;
880         byteen_end = byteen & BYTE_EN_END_MASK;
881
882         byen = byteen_start | (byteen_start << 4);
883         ret = set_registers(tp, index, type | byen, 4, data);
884         if (ret < 0)
885                 goto error1;
886
887         index += 4;
888         data += 4;
889         size -= 4;
890
891         if (size) {
892                 size -= 4;
893
894                 while (size) {
895                         if (size > limit) {
896                                 ret = set_registers(tp, index,
897                                                     type | BYTE_EN_DWORD,
898                                                     limit, data);
899                                 if (ret < 0)
900                                         goto error1;
901
902                                 index += limit;
903                                 data += limit;
904                                 size -= limit;
905                         } else {
906                                 ret = set_registers(tp, index,
907                                                     type | BYTE_EN_DWORD,
908                                                     size, data);
909                                 if (ret < 0)
910                                         goto error1;
911
912                                 index += size;
913                                 data += size;
914                                 size = 0;
915                                 break;
916                         }
917                 }
918
919                 byen = byteen_end | (byteen_end >> 4);
920                 ret = set_registers(tp, index, type | byen, 4, data);
921                 if (ret < 0)
922                         goto error1;
923         }
924
925 error1:
926         if (ret == -ENODEV)
927                 set_bit(RTL8152_UNPLUG, &tp->flags);
928
929         return ret;
930 }
931
932 static inline
933 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
934 {
935         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
936 }
937
938 static inline
939 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
940 {
941         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
942 }
943
944 static inline
945 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
946 {
947         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
948 }
949
950 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
951 {
952         __le32 data;
953
954         generic_ocp_read(tp, index, sizeof(data), &data, type);
955
956         return __le32_to_cpu(data);
957 }
958
959 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
960 {
961         __le32 tmp = __cpu_to_le32(data);
962
963         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
964 }
965
966 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
967 {
968         u32 data;
969         __le32 tmp;
970         u16 byen = BYTE_EN_WORD;
971         u8 shift = index & 2;
972
973         index &= ~3;
974         byen <<= shift;
975
976         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
977
978         data = __le32_to_cpu(tmp);
979         data >>= (shift * 8);
980         data &= 0xffff;
981
982         return (u16)data;
983 }
984
985 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
986 {
987         u32 mask = 0xffff;
988         __le32 tmp;
989         u16 byen = BYTE_EN_WORD;
990         u8 shift = index & 2;
991
992         data &= mask;
993
994         if (index & 2) {
995                 byen <<= shift;
996                 mask <<= (shift * 8);
997                 data <<= (shift * 8);
998                 index &= ~3;
999         }
1000
1001         tmp = __cpu_to_le32(data);
1002
1003         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1004 }
1005
1006 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1007 {
1008         u32 data;
1009         __le32 tmp;
1010         u8 shift = index & 3;
1011
1012         index &= ~3;
1013
1014         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1015
1016         data = __le32_to_cpu(tmp);
1017         data >>= (shift * 8);
1018         data &= 0xff;
1019
1020         return (u8)data;
1021 }
1022
1023 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1024 {
1025         u32 mask = 0xff;
1026         __le32 tmp;
1027         u16 byen = BYTE_EN_BYTE;
1028         u8 shift = index & 3;
1029
1030         data &= mask;
1031
1032         if (index & 3) {
1033                 byen <<= shift;
1034                 mask <<= (shift * 8);
1035                 data <<= (shift * 8);
1036                 index &= ~3;
1037         }
1038
1039         tmp = __cpu_to_le32(data);
1040
1041         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1042 }
1043
1044 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1045 {
1046         u16 ocp_base, ocp_index;
1047
1048         ocp_base = addr & 0xf000;
1049         if (ocp_base != tp->ocp_base) {
1050                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1051                 tp->ocp_base = ocp_base;
1052         }
1053
1054         ocp_index = (addr & 0x0fff) | 0xb000;
1055         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1056 }
1057
1058 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1059 {
1060         u16 ocp_base, ocp_index;
1061
1062         ocp_base = addr & 0xf000;
1063         if (ocp_base != tp->ocp_base) {
1064                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1065                 tp->ocp_base = ocp_base;
1066         }
1067
1068         ocp_index = (addr & 0x0fff) | 0xb000;
1069         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1070 }
1071
1072 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1073 {
1074         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1075 }
1076
1077 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1078 {
1079         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1080 }
1081
1082 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1083 {
1084         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1085         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1086 }
1087
1088 static u16 sram_read(struct r8152 *tp, u16 addr)
1089 {
1090         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1091         return ocp_reg_read(tp, OCP_SRAM_DATA);
1092 }
1093
1094 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1095 {
1096         struct r8152 *tp = netdev_priv(netdev);
1097         int ret;
1098
1099         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1100                 return -ENODEV;
1101
1102         if (phy_id != R8152_PHY_ID)
1103                 return -EINVAL;
1104
1105         ret = r8152_mdio_read(tp, reg);
1106
1107         return ret;
1108 }
1109
1110 static
1111 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1112 {
1113         struct r8152 *tp = netdev_priv(netdev);
1114
1115         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1116                 return;
1117
1118         if (phy_id != R8152_PHY_ID)
1119                 return;
1120
1121         r8152_mdio_write(tp, reg, val);
1122 }
1123
1124 static int
1125 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1126
1127 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1128 {
1129         struct r8152 *tp = netdev_priv(netdev);
1130         struct sockaddr *addr = p;
1131         int ret = -EADDRNOTAVAIL;
1132
1133         if (!is_valid_ether_addr(addr->sa_data))
1134                 goto out1;
1135
1136         ret = usb_autopm_get_interface(tp->intf);
1137         if (ret < 0)
1138                 goto out1;
1139
1140         mutex_lock(&tp->control);
1141
1142         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1143
1144         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1145         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1146         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1147
1148         mutex_unlock(&tp->control);
1149
1150         usb_autopm_put_interface(tp->intf);
1151 out1:
1152         return ret;
1153 }
1154
1155 /* Devices containing RTL8153-AD can support a persistent
1156  * host system provided MAC address.
1157  * Examples of this are Dell TB15 and Dell WD15 docks
1158  */
1159 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1160 {
1161         acpi_status status;
1162         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1163         union acpi_object *obj;
1164         int ret = -EINVAL;
1165         u32 ocp_data;
1166         unsigned char buf[6];
1167
1168         /* test for -AD variant of RTL8153 */
1169         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1170         if ((ocp_data & AD_MASK) != 0x1000)
1171                 return -ENODEV;
1172
1173         /* test for MAC address pass-through bit */
1174         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1175         if ((ocp_data & PASS_THRU_MASK) != 1)
1176                 return -ENODEV;
1177
1178         /* returns _AUXMAC_#AABBCCDDEEFF# */
1179         status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1180         obj = (union acpi_object *)buffer.pointer;
1181         if (!ACPI_SUCCESS(status))
1182                 return -ENODEV;
1183         if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1184                 netif_warn(tp, probe, tp->netdev,
1185                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1186                            obj->type, obj->string.length);
1187                 goto amacout;
1188         }
1189         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1190             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1191                 netif_warn(tp, probe, tp->netdev,
1192                            "Invalid header when reading pass-thru MAC addr\n");
1193                 goto amacout;
1194         }
1195         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1196         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1197                 netif_warn(tp, probe, tp->netdev,
1198                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1199                            ret, buf);
1200                 ret = -EINVAL;
1201                 goto amacout;
1202         }
1203         memcpy(sa->sa_data, buf, 6);
1204         ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1205         netif_info(tp, probe, tp->netdev,
1206                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1207
1208 amacout:
1209         kfree(obj);
1210         return ret;
1211 }
1212
1213 static int set_ethernet_addr(struct r8152 *tp)
1214 {
1215         struct net_device *dev = tp->netdev;
1216         struct sockaddr sa;
1217         int ret;
1218
1219         if (tp->version == RTL_VER_01) {
1220                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1221         } else {
1222                 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1223                  * or system doesn't provide valid _SB.AMAC this will be
1224                  * be expected to non-zero
1225                  */
1226                 ret = vendor_mac_passthru_addr_read(tp, &sa);
1227                 if (ret < 0)
1228                         ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1229         }
1230
1231         if (ret < 0) {
1232                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1233         } else if (!is_valid_ether_addr(sa.sa_data)) {
1234                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1235                           sa.sa_data);
1236                 eth_hw_addr_random(dev);
1237                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1238                 ret = rtl8152_set_mac_address(dev, &sa);
1239                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1240                            sa.sa_data);
1241         } else {
1242                 if (tp->version == RTL_VER_01)
1243                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1244                 else
1245                         ret = rtl8152_set_mac_address(dev, &sa);
1246         }
1247
1248         return ret;
1249 }
1250
1251 static void read_bulk_callback(struct urb *urb)
1252 {
1253         struct net_device *netdev;
1254         int status = urb->status;
1255         struct rx_agg *agg;
1256         struct r8152 *tp;
1257
1258         agg = urb->context;
1259         if (!agg)
1260                 return;
1261
1262         tp = agg->context;
1263         if (!tp)
1264                 return;
1265
1266         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1267                 return;
1268
1269         if (!test_bit(WORK_ENABLE, &tp->flags))
1270                 return;
1271
1272         netdev = tp->netdev;
1273
1274         /* When link down, the driver would cancel all bulks. */
1275         /* This avoid the re-submitting bulk */
1276         if (!netif_carrier_ok(netdev))
1277                 return;
1278
1279         usb_mark_last_busy(tp->udev);
1280
1281         switch (status) {
1282         case 0:
1283                 if (urb->actual_length < ETH_ZLEN)
1284                         break;
1285
1286                 spin_lock(&tp->rx_lock);
1287                 list_add_tail(&agg->list, &tp->rx_done);
1288                 spin_unlock(&tp->rx_lock);
1289                 napi_schedule(&tp->napi);
1290                 return;
1291         case -ESHUTDOWN:
1292                 set_bit(RTL8152_UNPLUG, &tp->flags);
1293                 netif_device_detach(tp->netdev);
1294                 return;
1295         case -ENOENT:
1296                 return; /* the urb is in unlink state */
1297         case -ETIME:
1298                 if (net_ratelimit())
1299                         netdev_warn(netdev, "maybe reset is needed?\n");
1300                 break;
1301         default:
1302                 if (net_ratelimit())
1303                         netdev_warn(netdev, "Rx status %d\n", status);
1304                 break;
1305         }
1306
1307         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1308 }
1309
1310 static void write_bulk_callback(struct urb *urb)
1311 {
1312         struct net_device_stats *stats;
1313         struct net_device *netdev;
1314         struct tx_agg *agg;
1315         struct r8152 *tp;
1316         int status = urb->status;
1317
1318         agg = urb->context;
1319         if (!agg)
1320                 return;
1321
1322         tp = agg->context;
1323         if (!tp)
1324                 return;
1325
1326         netdev = tp->netdev;
1327         stats = &netdev->stats;
1328         if (status) {
1329                 if (net_ratelimit())
1330                         netdev_warn(netdev, "Tx status %d\n", status);
1331                 stats->tx_errors += agg->skb_num;
1332         } else {
1333                 stats->tx_packets += agg->skb_num;
1334                 stats->tx_bytes += agg->skb_len;
1335         }
1336
1337         spin_lock(&tp->tx_lock);
1338         list_add_tail(&agg->list, &tp->tx_free);
1339         spin_unlock(&tp->tx_lock);
1340
1341         usb_autopm_put_interface_async(tp->intf);
1342
1343         if (!netif_carrier_ok(netdev))
1344                 return;
1345
1346         if (!test_bit(WORK_ENABLE, &tp->flags))
1347                 return;
1348
1349         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1350                 return;
1351
1352         if (!skb_queue_empty(&tp->tx_queue))
1353                 napi_schedule(&tp->napi);
1354 }
1355
1356 static void intr_callback(struct urb *urb)
1357 {
1358         struct r8152 *tp;
1359         __le16 *d;
1360         int status = urb->status;
1361         int res;
1362
1363         tp = urb->context;
1364         if (!tp)
1365                 return;
1366
1367         if (!test_bit(WORK_ENABLE, &tp->flags))
1368                 return;
1369
1370         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1371                 return;
1372
1373         switch (status) {
1374         case 0:                 /* success */
1375                 break;
1376         case -ECONNRESET:       /* unlink */
1377         case -ESHUTDOWN:
1378                 netif_device_detach(tp->netdev);
1379         case -ENOENT:
1380         case -EPROTO:
1381                 netif_info(tp, intr, tp->netdev,
1382                            "Stop submitting intr, status %d\n", status);
1383                 return;
1384         case -EOVERFLOW:
1385                 if (net_ratelimit())
1386                         netif_info(tp, intr, tp->netdev,
1387                                    "intr status -EOVERFLOW\n");
1388                 goto resubmit;
1389         /* -EPIPE:  should clear the halt */
1390         default:
1391                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1392                 goto resubmit;
1393         }
1394
1395         d = urb->transfer_buffer;
1396         if (INTR_LINK & __le16_to_cpu(d[0])) {
1397                 if (!netif_carrier_ok(tp->netdev)) {
1398                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1399                         schedule_delayed_work(&tp->schedule, 0);
1400                 }
1401         } else {
1402                 if (netif_carrier_ok(tp->netdev)) {
1403                         netif_stop_queue(tp->netdev);
1404                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1405                         schedule_delayed_work(&tp->schedule, 0);
1406                 }
1407         }
1408
1409 resubmit:
1410         res = usb_submit_urb(urb, GFP_ATOMIC);
1411         if (res == -ENODEV) {
1412                 set_bit(RTL8152_UNPLUG, &tp->flags);
1413                 netif_device_detach(tp->netdev);
1414         } else if (res) {
1415                 netif_err(tp, intr, tp->netdev,
1416                           "can't resubmit intr, status %d\n", res);
1417         }
1418 }
1419
1420 static inline void *rx_agg_align(void *data)
1421 {
1422         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1423 }
1424
1425 static inline void *tx_agg_align(void *data)
1426 {
1427         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1428 }
1429
1430 static void free_all_mem(struct r8152 *tp)
1431 {
1432         int i;
1433
1434         for (i = 0; i < RTL8152_MAX_RX; i++) {
1435                 usb_free_urb(tp->rx_info[i].urb);
1436                 tp->rx_info[i].urb = NULL;
1437
1438                 kfree(tp->rx_info[i].buffer);
1439                 tp->rx_info[i].buffer = NULL;
1440                 tp->rx_info[i].head = NULL;
1441         }
1442
1443         for (i = 0; i < RTL8152_MAX_TX; i++) {
1444                 usb_free_urb(tp->tx_info[i].urb);
1445                 tp->tx_info[i].urb = NULL;
1446
1447                 kfree(tp->tx_info[i].buffer);
1448                 tp->tx_info[i].buffer = NULL;
1449                 tp->tx_info[i].head = NULL;
1450         }
1451
1452         usb_free_urb(tp->intr_urb);
1453         tp->intr_urb = NULL;
1454
1455         kfree(tp->intr_buff);
1456         tp->intr_buff = NULL;
1457 }
1458
1459 static int alloc_all_mem(struct r8152 *tp)
1460 {
1461         struct net_device *netdev = tp->netdev;
1462         struct usb_interface *intf = tp->intf;
1463         struct usb_host_interface *alt = intf->cur_altsetting;
1464         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1465         struct urb *urb;
1466         int node, i;
1467         u8 *buf;
1468
1469         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1470
1471         spin_lock_init(&tp->rx_lock);
1472         spin_lock_init(&tp->tx_lock);
1473         INIT_LIST_HEAD(&tp->tx_free);
1474         INIT_LIST_HEAD(&tp->rx_done);
1475         skb_queue_head_init(&tp->tx_queue);
1476         skb_queue_head_init(&tp->rx_queue);
1477
1478         for (i = 0; i < RTL8152_MAX_RX; i++) {
1479                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1480                 if (!buf)
1481                         goto err1;
1482
1483                 if (buf != rx_agg_align(buf)) {
1484                         kfree(buf);
1485                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1486                                            node);
1487                         if (!buf)
1488                                 goto err1;
1489                 }
1490
1491                 urb = usb_alloc_urb(0, GFP_KERNEL);
1492                 if (!urb) {
1493                         kfree(buf);
1494                         goto err1;
1495                 }
1496
1497                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1498                 tp->rx_info[i].context = tp;
1499                 tp->rx_info[i].urb = urb;
1500                 tp->rx_info[i].buffer = buf;
1501                 tp->rx_info[i].head = rx_agg_align(buf);
1502         }
1503
1504         for (i = 0; i < RTL8152_MAX_TX; i++) {
1505                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1506                 if (!buf)
1507                         goto err1;
1508
1509                 if (buf != tx_agg_align(buf)) {
1510                         kfree(buf);
1511                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1512                                            node);
1513                         if (!buf)
1514                                 goto err1;
1515                 }
1516
1517                 urb = usb_alloc_urb(0, GFP_KERNEL);
1518                 if (!urb) {
1519                         kfree(buf);
1520                         goto err1;
1521                 }
1522
1523                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1524                 tp->tx_info[i].context = tp;
1525                 tp->tx_info[i].urb = urb;
1526                 tp->tx_info[i].buffer = buf;
1527                 tp->tx_info[i].head = tx_agg_align(buf);
1528
1529                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1530         }
1531
1532         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1533         if (!tp->intr_urb)
1534                 goto err1;
1535
1536         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1537         if (!tp->intr_buff)
1538                 goto err1;
1539
1540         tp->intr_interval = (int)ep_intr->desc.bInterval;
1541         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1542                          tp->intr_buff, INTBUFSIZE, intr_callback,
1543                          tp, tp->intr_interval);
1544
1545         return 0;
1546
1547 err1:
1548         free_all_mem(tp);
1549         return -ENOMEM;
1550 }
1551
1552 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1553 {
1554         struct tx_agg *agg = NULL;
1555         unsigned long flags;
1556
1557         if (list_empty(&tp->tx_free))
1558                 return NULL;
1559
1560         spin_lock_irqsave(&tp->tx_lock, flags);
1561         if (!list_empty(&tp->tx_free)) {
1562                 struct list_head *cursor;
1563
1564                 cursor = tp->tx_free.next;
1565                 list_del_init(cursor);
1566                 agg = list_entry(cursor, struct tx_agg, list);
1567         }
1568         spin_unlock_irqrestore(&tp->tx_lock, flags);
1569
1570         return agg;
1571 }
1572
1573 /* r8152_csum_workaround()
1574  * The hw limites the value the transport offset. When the offset is out of the
1575  * range, calculate the checksum by sw.
1576  */
1577 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1578                                   struct sk_buff_head *list)
1579 {
1580         if (skb_shinfo(skb)->gso_size) {
1581                 netdev_features_t features = tp->netdev->features;
1582                 struct sk_buff_head seg_list;
1583                 struct sk_buff *segs, *nskb;
1584
1585                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1586                 segs = skb_gso_segment(skb, features);
1587                 if (IS_ERR(segs) || !segs)
1588                         goto drop;
1589
1590                 __skb_queue_head_init(&seg_list);
1591
1592                 do {
1593                         nskb = segs;
1594                         segs = segs->next;
1595                         nskb->next = NULL;
1596                         __skb_queue_tail(&seg_list, nskb);
1597                 } while (segs);
1598
1599                 skb_queue_splice(&seg_list, list);
1600                 dev_kfree_skb(skb);
1601         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1602                 if (skb_checksum_help(skb) < 0)
1603                         goto drop;
1604
1605                 __skb_queue_head(list, skb);
1606         } else {
1607                 struct net_device_stats *stats;
1608
1609 drop:
1610                 stats = &tp->netdev->stats;
1611                 stats->tx_dropped++;
1612                 dev_kfree_skb(skb);
1613         }
1614 }
1615
1616 /* msdn_giant_send_check()
1617  * According to the document of microsoft, the TCP Pseudo Header excludes the
1618  * packet length for IPv6 TCP large packets.
1619  */
1620 static int msdn_giant_send_check(struct sk_buff *skb)
1621 {
1622         const struct ipv6hdr *ipv6h;
1623         struct tcphdr *th;
1624         int ret;
1625
1626         ret = skb_cow_head(skb, 0);
1627         if (ret)
1628                 return ret;
1629
1630         ipv6h = ipv6_hdr(skb);
1631         th = tcp_hdr(skb);
1632
1633         th->check = 0;
1634         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1635
1636         return ret;
1637 }
1638
1639 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1640 {
1641         if (skb_vlan_tag_present(skb)) {
1642                 u32 opts2;
1643
1644                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1645                 desc->opts2 |= cpu_to_le32(opts2);
1646         }
1647 }
1648
1649 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1650 {
1651         u32 opts2 = le32_to_cpu(desc->opts2);
1652
1653         if (opts2 & RX_VLAN_TAG)
1654                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1655                                        swab16(opts2 & 0xffff));
1656 }
1657
1658 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1659                          struct sk_buff *skb, u32 len, u32 transport_offset)
1660 {
1661         u32 mss = skb_shinfo(skb)->gso_size;
1662         u32 opts1, opts2 = 0;
1663         int ret = TX_CSUM_SUCCESS;
1664
1665         WARN_ON_ONCE(len > TX_LEN_MAX);
1666
1667         opts1 = len | TX_FS | TX_LS;
1668
1669         if (mss) {
1670                 if (transport_offset > GTTCPHO_MAX) {
1671                         netif_warn(tp, tx_err, tp->netdev,
1672                                    "Invalid transport offset 0x%x for TSO\n",
1673                                    transport_offset);
1674                         ret = TX_CSUM_TSO;
1675                         goto unavailable;
1676                 }
1677
1678                 switch (vlan_get_protocol(skb)) {
1679                 case htons(ETH_P_IP):
1680                         opts1 |= GTSENDV4;
1681                         break;
1682
1683                 case htons(ETH_P_IPV6):
1684                         if (msdn_giant_send_check(skb)) {
1685                                 ret = TX_CSUM_TSO;
1686                                 goto unavailable;
1687                         }
1688                         opts1 |= GTSENDV6;
1689                         break;
1690
1691                 default:
1692                         WARN_ON_ONCE(1);
1693                         break;
1694                 }
1695
1696                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1697                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1698         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1699                 u8 ip_protocol;
1700
1701                 if (transport_offset > TCPHO_MAX) {
1702                         netif_warn(tp, tx_err, tp->netdev,
1703                                    "Invalid transport offset 0x%x\n",
1704                                    transport_offset);
1705                         ret = TX_CSUM_NONE;
1706                         goto unavailable;
1707                 }
1708
1709                 switch (vlan_get_protocol(skb)) {
1710                 case htons(ETH_P_IP):
1711                         opts2 |= IPV4_CS;
1712                         ip_protocol = ip_hdr(skb)->protocol;
1713                         break;
1714
1715                 case htons(ETH_P_IPV6):
1716                         opts2 |= IPV6_CS;
1717                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1718                         break;
1719
1720                 default:
1721                         ip_protocol = IPPROTO_RAW;
1722                         break;
1723                 }
1724
1725                 if (ip_protocol == IPPROTO_TCP)
1726                         opts2 |= TCP_CS;
1727                 else if (ip_protocol == IPPROTO_UDP)
1728                         opts2 |= UDP_CS;
1729                 else
1730                         WARN_ON_ONCE(1);
1731
1732                 opts2 |= transport_offset << TCPHO_SHIFT;
1733         }
1734
1735         desc->opts2 = cpu_to_le32(opts2);
1736         desc->opts1 = cpu_to_le32(opts1);
1737
1738 unavailable:
1739         return ret;
1740 }
1741
1742 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1743 {
1744         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1745         int remain, ret;
1746         u8 *tx_data;
1747
1748         __skb_queue_head_init(&skb_head);
1749         spin_lock(&tx_queue->lock);
1750         skb_queue_splice_init(tx_queue, &skb_head);
1751         spin_unlock(&tx_queue->lock);
1752
1753         tx_data = agg->head;
1754         agg->skb_num = 0;
1755         agg->skb_len = 0;
1756         remain = agg_buf_sz;
1757
1758         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1759                 struct tx_desc *tx_desc;
1760                 struct sk_buff *skb;
1761                 unsigned int len;
1762                 u32 offset;
1763
1764                 skb = __skb_dequeue(&skb_head);
1765                 if (!skb)
1766                         break;
1767
1768                 len = skb->len + sizeof(*tx_desc);
1769
1770                 if (len > remain) {
1771                         __skb_queue_head(&skb_head, skb);
1772                         break;
1773                 }
1774
1775                 tx_data = tx_agg_align(tx_data);
1776                 tx_desc = (struct tx_desc *)tx_data;
1777
1778                 offset = (u32)skb_transport_offset(skb);
1779
1780                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1781                         r8152_csum_workaround(tp, skb, &skb_head);
1782                         continue;
1783                 }
1784
1785                 rtl_tx_vlan_tag(tx_desc, skb);
1786
1787                 tx_data += sizeof(*tx_desc);
1788
1789                 len = skb->len;
1790                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1791                         struct net_device_stats *stats = &tp->netdev->stats;
1792
1793                         stats->tx_dropped++;
1794                         dev_kfree_skb_any(skb);
1795                         tx_data -= sizeof(*tx_desc);
1796                         continue;
1797                 }
1798
1799                 tx_data += len;
1800                 agg->skb_len += len;
1801                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1802
1803                 dev_kfree_skb_any(skb);
1804
1805                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1806         }
1807
1808         if (!skb_queue_empty(&skb_head)) {
1809                 spin_lock(&tx_queue->lock);
1810                 skb_queue_splice(&skb_head, tx_queue);
1811                 spin_unlock(&tx_queue->lock);
1812         }
1813
1814         netif_tx_lock(tp->netdev);
1815
1816         if (netif_queue_stopped(tp->netdev) &&
1817             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1818                 netif_wake_queue(tp->netdev);
1819
1820         netif_tx_unlock(tp->netdev);
1821
1822         ret = usb_autopm_get_interface_async(tp->intf);
1823         if (ret < 0)
1824                 goto out_tx_fill;
1825
1826         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1827                           agg->head, (int)(tx_data - (u8 *)agg->head),
1828                           (usb_complete_t)write_bulk_callback, agg);
1829
1830         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1831         if (ret < 0)
1832                 usb_autopm_put_interface_async(tp->intf);
1833
1834 out_tx_fill:
1835         return ret;
1836 }
1837
1838 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1839 {
1840         u8 checksum = CHECKSUM_NONE;
1841         u32 opts2, opts3;
1842
1843         if (!(tp->netdev->features & NETIF_F_RXCSUM))
1844                 goto return_result;
1845
1846         opts2 = le32_to_cpu(rx_desc->opts2);
1847         opts3 = le32_to_cpu(rx_desc->opts3);
1848
1849         if (opts2 & RD_IPV4_CS) {
1850                 if (opts3 & IPF)
1851                         checksum = CHECKSUM_NONE;
1852                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1853                         checksum = CHECKSUM_NONE;
1854                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1855                         checksum = CHECKSUM_NONE;
1856                 else
1857                         checksum = CHECKSUM_UNNECESSARY;
1858         } else if (opts2 & RD_IPV6_CS) {
1859                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1860                         checksum = CHECKSUM_UNNECESSARY;
1861                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1862                         checksum = CHECKSUM_UNNECESSARY;
1863         }
1864
1865 return_result:
1866         return checksum;
1867 }
1868
1869 static int rx_bottom(struct r8152 *tp, int budget)
1870 {
1871         unsigned long flags;
1872         struct list_head *cursor, *next, rx_queue;
1873         int ret = 0, work_done = 0;
1874         struct napi_struct *napi = &tp->napi;
1875
1876         if (!skb_queue_empty(&tp->rx_queue)) {
1877                 while (work_done < budget) {
1878                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1879                         struct net_device *netdev = tp->netdev;
1880                         struct net_device_stats *stats = &netdev->stats;
1881                         unsigned int pkt_len;
1882
1883                         if (!skb)
1884                                 break;
1885
1886                         pkt_len = skb->len;
1887                         napi_gro_receive(napi, skb);
1888                         work_done++;
1889                         stats->rx_packets++;
1890                         stats->rx_bytes += pkt_len;
1891                 }
1892         }
1893
1894         if (list_empty(&tp->rx_done))
1895                 goto out1;
1896
1897         INIT_LIST_HEAD(&rx_queue);
1898         spin_lock_irqsave(&tp->rx_lock, flags);
1899         list_splice_init(&tp->rx_done, &rx_queue);
1900         spin_unlock_irqrestore(&tp->rx_lock, flags);
1901
1902         list_for_each_safe(cursor, next, &rx_queue) {
1903                 struct rx_desc *rx_desc;
1904                 struct rx_agg *agg;
1905                 int len_used = 0;
1906                 struct urb *urb;
1907                 u8 *rx_data;
1908
1909                 list_del_init(cursor);
1910
1911                 agg = list_entry(cursor, struct rx_agg, list);
1912                 urb = agg->urb;
1913                 if (urb->actual_length < ETH_ZLEN)
1914                         goto submit;
1915
1916                 rx_desc = agg->head;
1917                 rx_data = agg->head;
1918                 len_used += sizeof(struct rx_desc);
1919
1920                 while (urb->actual_length > len_used) {
1921                         struct net_device *netdev = tp->netdev;
1922                         struct net_device_stats *stats = &netdev->stats;
1923                         unsigned int pkt_len;
1924                         struct sk_buff *skb;
1925
1926                         /* limite the skb numbers for rx_queue */
1927                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1928                                 break;
1929
1930                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1931                         if (pkt_len < ETH_ZLEN)
1932                                 break;
1933
1934                         len_used += pkt_len;
1935                         if (urb->actual_length < len_used)
1936                                 break;
1937
1938                         pkt_len -= ETH_FCS_LEN;
1939                         rx_data += sizeof(struct rx_desc);
1940
1941                         skb = napi_alloc_skb(napi, pkt_len);
1942                         if (!skb) {
1943                                 stats->rx_dropped++;
1944                                 goto find_next_rx;
1945                         }
1946
1947                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1948                         memcpy(skb->data, rx_data, pkt_len);
1949                         skb_put(skb, pkt_len);
1950                         skb->protocol = eth_type_trans(skb, netdev);
1951                         rtl_rx_vlan_tag(rx_desc, skb);
1952                         if (work_done < budget) {
1953                                 napi_gro_receive(napi, skb);
1954                                 work_done++;
1955                                 stats->rx_packets++;
1956                                 stats->rx_bytes += pkt_len;
1957                         } else {
1958                                 __skb_queue_tail(&tp->rx_queue, skb);
1959                         }
1960
1961 find_next_rx:
1962                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1963                         rx_desc = (struct rx_desc *)rx_data;
1964                         len_used = (int)(rx_data - (u8 *)agg->head);
1965                         len_used += sizeof(struct rx_desc);
1966                 }
1967
1968 submit:
1969                 if (!ret) {
1970                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1971                 } else {
1972                         urb->actual_length = 0;
1973                         list_add_tail(&agg->list, next);
1974                 }
1975         }
1976
1977         if (!list_empty(&rx_queue)) {
1978                 spin_lock_irqsave(&tp->rx_lock, flags);
1979                 list_splice_tail(&rx_queue, &tp->rx_done);
1980                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1981         }
1982
1983 out1:
1984         return work_done;
1985 }
1986
1987 static void tx_bottom(struct r8152 *tp)
1988 {
1989         int res;
1990
1991         do {
1992                 struct tx_agg *agg;
1993
1994                 if (skb_queue_empty(&tp->tx_queue))
1995                         break;
1996
1997                 agg = r8152_get_tx_agg(tp);
1998                 if (!agg)
1999                         break;
2000
2001                 res = r8152_tx_agg_fill(tp, agg);
2002                 if (res) {
2003                         struct net_device *netdev = tp->netdev;
2004
2005                         if (res == -ENODEV) {
2006                                 set_bit(RTL8152_UNPLUG, &tp->flags);
2007                                 netif_device_detach(netdev);
2008                         } else {
2009                                 struct net_device_stats *stats = &netdev->stats;
2010                                 unsigned long flags;
2011
2012                                 netif_warn(tp, tx_err, netdev,
2013                                            "failed tx_urb %d\n", res);
2014                                 stats->tx_dropped += agg->skb_num;
2015
2016                                 spin_lock_irqsave(&tp->tx_lock, flags);
2017                                 list_add_tail(&agg->list, &tp->tx_free);
2018                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
2019                         }
2020                 }
2021         } while (res == 0);
2022 }
2023
2024 static void bottom_half(struct r8152 *tp)
2025 {
2026         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2027                 return;
2028
2029         if (!test_bit(WORK_ENABLE, &tp->flags))
2030                 return;
2031
2032         /* When link down, the driver would cancel all bulks. */
2033         /* This avoid the re-submitting bulk */
2034         if (!netif_carrier_ok(tp->netdev))
2035                 return;
2036
2037         clear_bit(SCHEDULE_NAPI, &tp->flags);
2038
2039         tx_bottom(tp);
2040 }
2041
2042 static int r8152_poll(struct napi_struct *napi, int budget)
2043 {
2044         struct r8152 *tp = container_of(napi, struct r8152, napi);
2045         int work_done;
2046
2047         work_done = rx_bottom(tp, budget);
2048         bottom_half(tp);
2049
2050         if (work_done < budget) {
2051                 if (!napi_complete_done(napi, work_done))
2052                         goto out;
2053                 if (!list_empty(&tp->rx_done))
2054                         napi_schedule(napi);
2055                 else if (!skb_queue_empty(&tp->tx_queue) &&
2056                          !list_empty(&tp->tx_free))
2057                         napi_schedule(napi);
2058         }
2059
2060 out:
2061         return work_done;
2062 }
2063
2064 static
2065 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2066 {
2067         int ret;
2068
2069         /* The rx would be stopped, so skip submitting */
2070         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2071             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2072                 return 0;
2073
2074         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2075                           agg->head, agg_buf_sz,
2076                           (usb_complete_t)read_bulk_callback, agg);
2077
2078         ret = usb_submit_urb(agg->urb, mem_flags);
2079         if (ret == -ENODEV) {
2080                 set_bit(RTL8152_UNPLUG, &tp->flags);
2081                 netif_device_detach(tp->netdev);
2082         } else if (ret) {
2083                 struct urb *urb = agg->urb;
2084                 unsigned long flags;
2085
2086                 urb->actual_length = 0;
2087                 spin_lock_irqsave(&tp->rx_lock, flags);
2088                 list_add_tail(&agg->list, &tp->rx_done);
2089                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2090
2091                 netif_err(tp, rx_err, tp->netdev,
2092                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2093
2094                 napi_schedule(&tp->napi);
2095         }
2096
2097         return ret;
2098 }
2099
2100 static void rtl_drop_queued_tx(struct r8152 *tp)
2101 {
2102         struct net_device_stats *stats = &tp->netdev->stats;
2103         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2104         struct sk_buff *skb;
2105
2106         if (skb_queue_empty(tx_queue))
2107                 return;
2108
2109         __skb_queue_head_init(&skb_head);
2110         spin_lock_bh(&tx_queue->lock);
2111         skb_queue_splice_init(tx_queue, &skb_head);
2112         spin_unlock_bh(&tx_queue->lock);
2113
2114         while ((skb = __skb_dequeue(&skb_head))) {
2115                 dev_kfree_skb(skb);
2116                 stats->tx_dropped++;
2117         }
2118 }
2119
2120 static void rtl8152_tx_timeout(struct net_device *netdev)
2121 {
2122         struct r8152 *tp = netdev_priv(netdev);
2123
2124         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2125
2126         usb_queue_reset_device(tp->intf);
2127 }
2128
2129 static void rtl8152_set_rx_mode(struct net_device *netdev)
2130 {
2131         struct r8152 *tp = netdev_priv(netdev);
2132
2133         if (netif_carrier_ok(netdev)) {
2134                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2135                 schedule_delayed_work(&tp->schedule, 0);
2136         }
2137 }
2138
2139 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2140 {
2141         struct r8152 *tp = netdev_priv(netdev);
2142         u32 mc_filter[2];       /* Multicast hash filter */
2143         __le32 tmp[2];
2144         u32 ocp_data;
2145
2146         netif_stop_queue(netdev);
2147         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2148         ocp_data &= ~RCR_ACPT_ALL;
2149         ocp_data |= RCR_AB | RCR_APM;
2150
2151         if (netdev->flags & IFF_PROMISC) {
2152                 /* Unconditionally log net taps. */
2153                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2154                 ocp_data |= RCR_AM | RCR_AAP;
2155                 mc_filter[1] = 0xffffffff;
2156                 mc_filter[0] = 0xffffffff;
2157         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2158                    (netdev->flags & IFF_ALLMULTI)) {
2159                 /* Too many to filter perfectly -- accept all multicasts. */
2160                 ocp_data |= RCR_AM;
2161                 mc_filter[1] = 0xffffffff;
2162                 mc_filter[0] = 0xffffffff;
2163         } else {
2164                 struct netdev_hw_addr *ha;
2165
2166                 mc_filter[1] = 0;
2167                 mc_filter[0] = 0;
2168                 netdev_for_each_mc_addr(ha, netdev) {
2169                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2170
2171                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2172                         ocp_data |= RCR_AM;
2173                 }
2174         }
2175
2176         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2177         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2178
2179         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2180         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2181         netif_wake_queue(netdev);
2182 }
2183
2184 static netdev_features_t
2185 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2186                        netdev_features_t features)
2187 {
2188         u32 mss = skb_shinfo(skb)->gso_size;
2189         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2190         int offset = skb_transport_offset(skb);
2191
2192         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2193                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2194         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2195                 features &= ~NETIF_F_GSO_MASK;
2196
2197         return features;
2198 }
2199
2200 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2201                                       struct net_device *netdev)
2202 {
2203         struct r8152 *tp = netdev_priv(netdev);
2204
2205         skb_tx_timestamp(skb);
2206
2207         skb_queue_tail(&tp->tx_queue, skb);
2208
2209         if (!list_empty(&tp->tx_free)) {
2210                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2211                         set_bit(SCHEDULE_NAPI, &tp->flags);
2212                         schedule_delayed_work(&tp->schedule, 0);
2213                 } else {
2214                         usb_mark_last_busy(tp->udev);
2215                         napi_schedule(&tp->napi);
2216                 }
2217         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2218                 netif_stop_queue(netdev);
2219         }
2220
2221         return NETDEV_TX_OK;
2222 }
2223
2224 static void r8152b_reset_packet_filter(struct r8152 *tp)
2225 {
2226         u32     ocp_data;
2227
2228         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2229         ocp_data &= ~FMC_FCR_MCU_EN;
2230         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2231         ocp_data |= FMC_FCR_MCU_EN;
2232         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2233 }
2234
2235 static void rtl8152_nic_reset(struct r8152 *tp)
2236 {
2237         int     i;
2238
2239         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2240
2241         for (i = 0; i < 1000; i++) {
2242                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2243                         break;
2244                 usleep_range(100, 400);
2245         }
2246 }
2247
2248 static void set_tx_qlen(struct r8152 *tp)
2249 {
2250         struct net_device *netdev = tp->netdev;
2251
2252         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2253                                     sizeof(struct tx_desc));
2254 }
2255
2256 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2257 {
2258         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2259 }
2260
2261 static void rtl_set_eee_plus(struct r8152 *tp)
2262 {
2263         u32 ocp_data;
2264         u8 speed;
2265
2266         speed = rtl8152_get_speed(tp);
2267         if (speed & _10bps) {
2268                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2269                 ocp_data |= EEEP_CR_EEEP_TX;
2270                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2271         } else {
2272                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2273                 ocp_data &= ~EEEP_CR_EEEP_TX;
2274                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2275         }
2276 }
2277
2278 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2279 {
2280         u32 ocp_data;
2281
2282         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2283         if (enable)
2284                 ocp_data |= RXDY_GATED_EN;
2285         else
2286                 ocp_data &= ~RXDY_GATED_EN;
2287         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2288 }
2289
2290 static int rtl_start_rx(struct r8152 *tp)
2291 {
2292         int i, ret = 0;
2293
2294         INIT_LIST_HEAD(&tp->rx_done);
2295         for (i = 0; i < RTL8152_MAX_RX; i++) {
2296                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2297                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2298                 if (ret)
2299                         break;
2300         }
2301
2302         if (ret && ++i < RTL8152_MAX_RX) {
2303                 struct list_head rx_queue;
2304                 unsigned long flags;
2305
2306                 INIT_LIST_HEAD(&rx_queue);
2307
2308                 do {
2309                         struct rx_agg *agg = &tp->rx_info[i++];
2310                         struct urb *urb = agg->urb;
2311
2312                         urb->actual_length = 0;
2313                         list_add_tail(&agg->list, &rx_queue);
2314                 } while (i < RTL8152_MAX_RX);
2315
2316                 spin_lock_irqsave(&tp->rx_lock, flags);
2317                 list_splice_tail(&rx_queue, &tp->rx_done);
2318                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2319         }
2320
2321         return ret;
2322 }
2323
2324 static int rtl_stop_rx(struct r8152 *tp)
2325 {
2326         int i;
2327
2328         for (i = 0; i < RTL8152_MAX_RX; i++)
2329                 usb_kill_urb(tp->rx_info[i].urb);
2330
2331         while (!skb_queue_empty(&tp->rx_queue))
2332                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2333
2334         return 0;
2335 }
2336
2337 static int rtl_enable(struct r8152 *tp)
2338 {
2339         u32 ocp_data;
2340
2341         r8152b_reset_packet_filter(tp);
2342
2343         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2344         ocp_data |= CR_RE | CR_TE;
2345         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2346
2347         rxdy_gated_en(tp, false);
2348
2349         return 0;
2350 }
2351
2352 static int rtl8152_enable(struct r8152 *tp)
2353 {
2354         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2355                 return -ENODEV;
2356
2357         set_tx_qlen(tp);
2358         rtl_set_eee_plus(tp);
2359
2360         return rtl_enable(tp);
2361 }
2362
2363 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2364 {
2365         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2366                        OWN_UPDATE | OWN_CLEAR);
2367 }
2368
2369 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2370 {
2371         u32 ocp_data = tp->coalesce / 8;
2372
2373         switch (tp->version) {
2374         case RTL_VER_03:
2375         case RTL_VER_04:
2376         case RTL_VER_05:
2377         case RTL_VER_06:
2378                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2379                                ocp_data);
2380                 break;
2381
2382         case RTL_VER_08:
2383         case RTL_VER_09:
2384                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2385                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2386                  */
2387                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2388                                128 / 8);
2389                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2390                                ocp_data);
2391                 r8153b_rx_agg_chg_indicate(tp);
2392                 break;
2393
2394         default:
2395                 break;
2396         }
2397 }
2398
2399 static void r8153_set_rx_early_size(struct r8152 *tp)
2400 {
2401         u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2402
2403         switch (tp->version) {
2404         case RTL_VER_03:
2405         case RTL_VER_04:
2406         case RTL_VER_05:
2407         case RTL_VER_06:
2408                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2409                                ocp_data / 4);
2410                 break;
2411         case RTL_VER_08:
2412         case RTL_VER_09:
2413                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2414                                ocp_data / 8);
2415                 r8153b_rx_agg_chg_indicate(tp);
2416                 break;
2417         default:
2418                 WARN_ON_ONCE(1);
2419                 break;
2420         }
2421 }
2422
2423 static int rtl8153_enable(struct r8152 *tp)
2424 {
2425         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2426                 return -ENODEV;
2427
2428         set_tx_qlen(tp);
2429         rtl_set_eee_plus(tp);
2430         r8153_set_rx_early_timeout(tp);
2431         r8153_set_rx_early_size(tp);
2432
2433         return rtl_enable(tp);
2434 }
2435
2436 static void rtl_disable(struct r8152 *tp)
2437 {
2438         u32 ocp_data;
2439         int i;
2440
2441         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2442                 rtl_drop_queued_tx(tp);
2443                 return;
2444         }
2445
2446         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2447         ocp_data &= ~RCR_ACPT_ALL;
2448         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2449
2450         rtl_drop_queued_tx(tp);
2451
2452         for (i = 0; i < RTL8152_MAX_TX; i++)
2453                 usb_kill_urb(tp->tx_info[i].urb);
2454
2455         rxdy_gated_en(tp, true);
2456
2457         for (i = 0; i < 1000; i++) {
2458                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2459                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2460                         break;
2461                 usleep_range(1000, 2000);
2462         }
2463
2464         for (i = 0; i < 1000; i++) {
2465                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2466                         break;
2467                 usleep_range(1000, 2000);
2468         }
2469
2470         rtl_stop_rx(tp);
2471
2472         rtl8152_nic_reset(tp);
2473 }
2474
2475 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2476 {
2477         u32 ocp_data;
2478
2479         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2480         if (enable)
2481                 ocp_data |= POWER_CUT;
2482         else
2483                 ocp_data &= ~POWER_CUT;
2484         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2485
2486         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2487         ocp_data &= ~RESUME_INDICATE;
2488         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2489 }
2490
2491 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2492 {
2493         u32 ocp_data;
2494
2495         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2496         if (enable)
2497                 ocp_data |= CPCR_RX_VLAN;
2498         else
2499                 ocp_data &= ~CPCR_RX_VLAN;
2500         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2501 }
2502
2503 static int rtl8152_set_features(struct net_device *dev,
2504                                 netdev_features_t features)
2505 {
2506         netdev_features_t changed = features ^ dev->features;
2507         struct r8152 *tp = netdev_priv(dev);
2508         int ret;
2509
2510         ret = usb_autopm_get_interface(tp->intf);
2511         if (ret < 0)
2512                 goto out;
2513
2514         mutex_lock(&tp->control);
2515
2516         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2517                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2518                         rtl_rx_vlan_en(tp, true);
2519                 else
2520                         rtl_rx_vlan_en(tp, false);
2521         }
2522
2523         mutex_unlock(&tp->control);
2524
2525         usb_autopm_put_interface(tp->intf);
2526
2527 out:
2528         return ret;
2529 }
2530
2531 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2532
2533 static u32 __rtl_get_wol(struct r8152 *tp)
2534 {
2535         u32 ocp_data;
2536         u32 wolopts = 0;
2537
2538         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2539         if (ocp_data & LINK_ON_WAKE_EN)
2540                 wolopts |= WAKE_PHY;
2541
2542         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2543         if (ocp_data & UWF_EN)
2544                 wolopts |= WAKE_UCAST;
2545         if (ocp_data & BWF_EN)
2546                 wolopts |= WAKE_BCAST;
2547         if (ocp_data & MWF_EN)
2548                 wolopts |= WAKE_MCAST;
2549
2550         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2551         if (ocp_data & MAGIC_EN)
2552                 wolopts |= WAKE_MAGIC;
2553
2554         return wolopts;
2555 }
2556
2557 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2558 {
2559         u32 ocp_data;
2560
2561         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2562
2563         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2564         ocp_data &= ~LINK_ON_WAKE_EN;
2565         if (wolopts & WAKE_PHY)
2566                 ocp_data |= LINK_ON_WAKE_EN;
2567         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2568
2569         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2570         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2571         if (wolopts & WAKE_UCAST)
2572                 ocp_data |= UWF_EN;
2573         if (wolopts & WAKE_BCAST)
2574                 ocp_data |= BWF_EN;
2575         if (wolopts & WAKE_MCAST)
2576                 ocp_data |= MWF_EN;
2577         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2578
2579         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2580
2581         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2582         ocp_data &= ~MAGIC_EN;
2583         if (wolopts & WAKE_MAGIC)
2584                 ocp_data |= MAGIC_EN;
2585         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2586
2587         if (wolopts & WAKE_ANY)
2588                 device_set_wakeup_enable(&tp->udev->dev, true);
2589         else
2590                 device_set_wakeup_enable(&tp->udev->dev, false);
2591 }
2592
2593 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2594 {
2595         u8 u1u2[8];
2596
2597         if (enable)
2598                 memset(u1u2, 0xff, sizeof(u1u2));
2599         else
2600                 memset(u1u2, 0x00, sizeof(u1u2));
2601
2602         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2603 }
2604
2605 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2606 {
2607         u32 ocp_data;
2608
2609         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2610         if (enable)
2611                 ocp_data |= LPM_U1U2_EN;
2612         else
2613                 ocp_data &= ~LPM_U1U2_EN;
2614
2615         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2616 }
2617
2618 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2619 {
2620         u32 ocp_data;
2621
2622         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2623         if (enable)
2624                 ocp_data |= U2P3_ENABLE;
2625         else
2626                 ocp_data &= ~U2P3_ENABLE;
2627         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2628 }
2629
2630 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2631 {
2632         u32 ocp_data;
2633
2634         ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2635         ocp_data &= ~clear;
2636         ocp_data |= set;
2637         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2638 }
2639
2640 static void r8153b_green_en(struct r8152 *tp, bool enable)
2641 {
2642         u16 data;
2643
2644         if (enable) {
2645                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
2646                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2647                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2648         } else {
2649                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2650                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2651                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2652         }
2653
2654         data = sram_read(tp, SRAM_GREEN_CFG);
2655         data |= GREEN_ETH_EN;
2656         sram_write(tp, SRAM_GREEN_CFG, data);
2657
2658         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2659 }
2660
2661 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2662 {
2663         u16 data;
2664         int i;
2665
2666         for (i = 0; i < 500; i++) {
2667                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2668                 data &= PHY_STAT_MASK;
2669                 if (desired) {
2670                         if (data == desired)
2671                                 break;
2672                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2673                            data == PHY_STAT_EXT_INIT) {
2674                         break;
2675                 }
2676
2677                 msleep(20);
2678                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2679                         break;
2680         }
2681
2682         return data;
2683 }
2684
2685 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2686 {
2687         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2688
2689         if (enable) {
2690                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2691                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2692
2693                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2694                 ocp_data |= BIT(0);
2695                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2696         } else {
2697                 u16 data;
2698
2699                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2700                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2701
2702                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2703                 ocp_data &= ~BIT(0);
2704                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2705
2706                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2707                 ocp_data &= ~PCUT_STATUS;
2708                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2709
2710                 data = r8153_phy_status(tp, 0);
2711
2712                 switch (data) {
2713                 case PHY_STAT_PWRDN:
2714                 case PHY_STAT_EXT_INIT:
2715                         r8153b_green_en(tp,
2716                                         test_bit(GREEN_ETHERNET, &tp->flags));
2717
2718                         data = r8152_mdio_read(tp, MII_BMCR);
2719                         data &= ~BMCR_PDOWN;
2720                         data |= BMCR_RESET;
2721                         r8152_mdio_write(tp, MII_BMCR, data);
2722
2723                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2724
2725                 default:
2726                         if (data != PHY_STAT_LAN_ON)
2727                                 netif_warn(tp, link, tp->netdev,
2728                                            "PHY not ready");
2729                         break;
2730                 }
2731         }
2732 }
2733
2734 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2735 {
2736         u32 ocp_data;
2737
2738         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2739         if (enable)
2740                 ocp_data |= PWR_EN | PHASE2_EN;
2741         else
2742                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2743         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2744
2745         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2746         ocp_data &= ~PCUT_STATUS;
2747         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2748 }
2749
2750 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2751 {
2752         u32 ocp_data;
2753
2754         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2755         if (enable)
2756                 ocp_data |= PWR_EN | PHASE2_EN;
2757         else
2758                 ocp_data &= ~PWR_EN;
2759         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2760
2761         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2762         ocp_data &= ~PCUT_STATUS;
2763         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2764 }
2765
2766 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2767 {
2768         u32 ocp_data;
2769
2770         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2771         if (enable)
2772                 ocp_data |= BIT(0);
2773         else
2774                 ocp_data &= ~BIT(0);
2775         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2776
2777         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2778         ocp_data &= ~BIT(0);
2779         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2780 }
2781
2782 static bool rtl_can_wakeup(struct r8152 *tp)
2783 {
2784         struct usb_device *udev = tp->udev;
2785
2786         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2787 }
2788
2789 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2790 {
2791         if (enable) {
2792                 u32 ocp_data;
2793
2794                 __rtl_set_wol(tp, WAKE_ANY);
2795
2796                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2797
2798                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2799                 ocp_data |= LINK_OFF_WAKE_EN;
2800                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2801
2802                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2803         } else {
2804                 u32 ocp_data;
2805
2806                 __rtl_set_wol(tp, tp->saved_wolopts);
2807
2808                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2809
2810                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2811                 ocp_data &= ~LINK_OFF_WAKE_EN;
2812                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2813
2814                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2815         }
2816 }
2817
2818 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2819 {
2820         if (enable) {
2821                 r8153_u1u2en(tp, false);
2822                 r8153_u2p3en(tp, false);
2823                 rtl_runtime_suspend_enable(tp, true);
2824         } else {
2825                 rtl_runtime_suspend_enable(tp, false);
2826
2827                 switch (tp->version) {
2828                 case RTL_VER_03:
2829                 case RTL_VER_04:
2830                         break;
2831                 case RTL_VER_05:
2832                 case RTL_VER_06:
2833                 default:
2834                         r8153_u2p3en(tp, true);
2835                         break;
2836                 }
2837
2838                 r8153_u1u2en(tp, true);
2839         }
2840 }
2841
2842 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2843 {
2844         if (enable) {
2845                 r8153b_queue_wake(tp, true);
2846                 r8153b_u1u2en(tp, false);
2847                 r8153_u2p3en(tp, false);
2848                 rtl_runtime_suspend_enable(tp, true);
2849                 r8153b_ups_en(tp, true);
2850         } else {
2851                 r8153b_ups_en(tp, false);
2852                 r8153b_queue_wake(tp, false);
2853                 rtl_runtime_suspend_enable(tp, false);
2854                 r8153_u2p3en(tp, true);
2855                 r8153b_u1u2en(tp, true);
2856         }
2857 }
2858
2859 static void r8153_teredo_off(struct r8152 *tp)
2860 {
2861         u32 ocp_data;
2862
2863         switch (tp->version) {
2864         case RTL_VER_01:
2865         case RTL_VER_02:
2866         case RTL_VER_03:
2867         case RTL_VER_04:
2868         case RTL_VER_05:
2869         case RTL_VER_06:
2870         case RTL_VER_07:
2871                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2872                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2873                               OOB_TEREDO_EN);
2874                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2875                 break;
2876
2877         case RTL_VER_08:
2878         case RTL_VER_09:
2879                 /* The bit 0 ~ 7 are relative with teredo settings. They are
2880                  * W1C (write 1 to clear), so set all 1 to disable it.
2881                  */
2882                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2883                 break;
2884
2885         default:
2886                 break;
2887         }
2888
2889         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2890         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2891         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2892 }
2893
2894 static void rtl_reset_bmu(struct r8152 *tp)
2895 {
2896         u32 ocp_data;
2897
2898         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2899         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2900         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2901         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2902         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2903 }
2904
2905 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2906 {
2907         if (enable) {
2908                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2909                                                     LINKENA | DIS_SDSAVE);
2910         } else {
2911                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2912                                                     DIS_SDSAVE);
2913                 msleep(20);
2914         }
2915 }
2916
2917 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2918 {
2919         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2920         ocp_reg_write(tp, OCP_EEE_DATA, reg);
2921         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2922 }
2923
2924 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2925 {
2926         u16 data;
2927
2928         r8152_mmd_indirect(tp, dev, reg);
2929         data = ocp_reg_read(tp, OCP_EEE_DATA);
2930         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2931
2932         return data;
2933 }
2934
2935 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2936 {
2937         r8152_mmd_indirect(tp, dev, reg);
2938         ocp_reg_write(tp, OCP_EEE_DATA, data);
2939         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2940 }
2941
2942 static void r8152_eee_en(struct r8152 *tp, bool enable)
2943 {
2944         u16 config1, config2, config3;
2945         u32 ocp_data;
2946
2947         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2948         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2949         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2950         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2951
2952         if (enable) {
2953                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2954                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2955                 config1 |= sd_rise_time(1);
2956                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2957                 config3 |= fast_snr(42);
2958         } else {
2959                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2960                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2961                              RX_QUIET_EN);
2962                 config1 |= sd_rise_time(7);
2963                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2964                 config3 |= fast_snr(511);
2965         }
2966
2967         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2968         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2969         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2970         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2971 }
2972
2973 static void r8152b_enable_eee(struct r8152 *tp)
2974 {
2975         r8152_eee_en(tp, true);
2976         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2977 }
2978
2979 static void r8152b_enable_fc(struct r8152 *tp)
2980 {
2981         u16 anar;
2982
2983         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2984         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2985         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2986 }
2987
2988 static void rtl8152_disable(struct r8152 *tp)
2989 {
2990         r8152_aldps_en(tp, false);
2991         rtl_disable(tp);
2992         r8152_aldps_en(tp, true);
2993 }
2994
2995 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2996 {
2997         r8152b_enable_eee(tp);
2998         r8152_aldps_en(tp, true);
2999         r8152b_enable_fc(tp);
3000
3001         set_bit(PHY_RESET, &tp->flags);
3002 }
3003
3004 static void r8152b_exit_oob(struct r8152 *tp)
3005 {
3006         u32 ocp_data;
3007         int i;
3008
3009         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3010         ocp_data &= ~RCR_ACPT_ALL;
3011         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3012
3013         rxdy_gated_en(tp, true);
3014         r8153_teredo_off(tp);
3015         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3016         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3017
3018         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3019         ocp_data &= ~NOW_IS_OOB;
3020         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3021
3022         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3023         ocp_data &= ~MCU_BORW_EN;
3024         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3025
3026         for (i = 0; i < 1000; i++) {
3027                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3028                 if (ocp_data & LINK_LIST_READY)
3029                         break;
3030                 usleep_range(1000, 2000);
3031         }
3032
3033         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3034         ocp_data |= RE_INIT_LL;
3035         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3036
3037         for (i = 0; i < 1000; i++) {
3038                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3039                 if (ocp_data & LINK_LIST_READY)
3040                         break;
3041                 usleep_range(1000, 2000);
3042         }
3043
3044         rtl8152_nic_reset(tp);
3045
3046         /* rx share fifo credit full threshold */
3047         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3048
3049         if (tp->udev->speed == USB_SPEED_FULL ||
3050             tp->udev->speed == USB_SPEED_LOW) {
3051                 /* rx share fifo credit near full threshold */
3052                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3053                                 RXFIFO_THR2_FULL);
3054                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3055                                 RXFIFO_THR3_FULL);
3056         } else {
3057                 /* rx share fifo credit near full threshold */
3058                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3059                                 RXFIFO_THR2_HIGH);
3060                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3061                                 RXFIFO_THR3_HIGH);
3062         }
3063
3064         /* TX share fifo free credit full threshold */
3065         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3066
3067         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3068         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3069         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3070                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3071
3072         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3073
3074         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3075
3076         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3077         ocp_data |= TCR0_AUTO_FIFO;
3078         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3079 }
3080
3081 static void r8152b_enter_oob(struct r8152 *tp)
3082 {
3083         u32 ocp_data;
3084         int i;
3085
3086         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3087         ocp_data &= ~NOW_IS_OOB;
3088         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3089
3090         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3091         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3092         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3093
3094         rtl_disable(tp);
3095
3096         for (i = 0; i < 1000; i++) {
3097                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3098                 if (ocp_data & LINK_LIST_READY)
3099                         break;
3100                 usleep_range(1000, 2000);
3101         }
3102
3103         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3104         ocp_data |= RE_INIT_LL;
3105         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3106
3107         for (i = 0; i < 1000; i++) {
3108                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3109                 if (ocp_data & LINK_LIST_READY)
3110                         break;
3111                 usleep_range(1000, 2000);
3112         }
3113
3114         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3115
3116         rtl_rx_vlan_en(tp, true);
3117
3118         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3119         ocp_data |= ALDPS_PROXY_MODE;
3120         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3121
3122         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3123         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3124         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3125
3126         rxdy_gated_en(tp, false);
3127
3128         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3129         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3130         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3131 }
3132
3133 static int r8153_patch_request(struct r8152 *tp, bool request)
3134 {
3135         u16 data;
3136         int i;
3137
3138         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3139         if (request)
3140                 data |= PATCH_REQUEST;
3141         else
3142                 data &= ~PATCH_REQUEST;
3143         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3144
3145         for (i = 0; request && i < 5000; i++) {
3146                 usleep_range(1000, 2000);
3147                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3148                         break;
3149         }
3150
3151         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3152                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3153                 r8153_patch_request(tp, false);
3154                 return -ETIME;
3155         } else {
3156                 return 0;
3157         }
3158 }
3159
3160 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3161 {
3162         u16 data;
3163
3164         data = ocp_reg_read(tp, OCP_POWER_CFG);
3165         if (enable) {
3166                 data |= EN_ALDPS;
3167                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3168         } else {
3169                 int i;
3170
3171                 data &= ~EN_ALDPS;
3172                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3173                 for (i = 0; i < 20; i++) {
3174                         usleep_range(1000, 2000);
3175                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3176                                 break;
3177                 }
3178         }
3179 }
3180
3181 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3182 {
3183         r8153_aldps_en(tp, enable);
3184
3185         if (enable)
3186                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3187         else
3188                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3189 }
3190
3191 static void r8153_eee_en(struct r8152 *tp, bool enable)
3192 {
3193         u32 ocp_data;
3194         u16 config;
3195
3196         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3197         config = ocp_reg_read(tp, OCP_EEE_CFG);
3198
3199         if (enable) {
3200                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3201                 config |= EEE10_EN;
3202         } else {
3203                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3204                 config &= ~EEE10_EN;
3205         }
3206
3207         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3208         ocp_reg_write(tp, OCP_EEE_CFG, config);
3209 }
3210
3211 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3212 {
3213         r8153_eee_en(tp, enable);
3214
3215         if (enable)
3216                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3217         else
3218                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3219 }
3220
3221 static void r8153b_enable_fc(struct r8152 *tp)
3222 {
3223         r8152b_enable_fc(tp);
3224         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3225 }
3226
3227 static void r8153_hw_phy_cfg(struct r8152 *tp)
3228 {
3229         u32 ocp_data;
3230         u16 data;
3231
3232         /* disable ALDPS before updating the PHY parameters */
3233         r8153_aldps_en(tp, false);
3234
3235         /* disable EEE before updating the PHY parameters */
3236         r8153_eee_en(tp, false);
3237         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3238
3239         if (tp->version == RTL_VER_03) {
3240                 data = ocp_reg_read(tp, OCP_EEE_CFG);
3241                 data &= ~CTAP_SHORT_EN;
3242                 ocp_reg_write(tp, OCP_EEE_CFG, data);
3243         }
3244
3245         data = ocp_reg_read(tp, OCP_POWER_CFG);
3246         data |= EEE_CLKDIV_EN;
3247         ocp_reg_write(tp, OCP_POWER_CFG, data);
3248
3249         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3250         data |= EN_10M_BGOFF;
3251         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3252         data = ocp_reg_read(tp, OCP_POWER_CFG);
3253         data |= EN_10M_PLLOFF;
3254         ocp_reg_write(tp, OCP_POWER_CFG, data);
3255         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3256
3257         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3258         ocp_data |= PFM_PWM_SWITCH;
3259         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3260
3261         /* Enable LPF corner auto tune */
3262         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3263
3264         /* Adjust 10M Amplitude */
3265         sram_write(tp, SRAM_10M_AMP1, 0x00af);
3266         sram_write(tp, SRAM_10M_AMP2, 0x0208);
3267
3268         r8153_eee_en(tp, true);
3269         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3270
3271         r8153_aldps_en(tp, true);
3272         r8152b_enable_fc(tp);
3273
3274         switch (tp->version) {
3275         case RTL_VER_03:
3276         case RTL_VER_04:
3277                 break;
3278         case RTL_VER_05:
3279         case RTL_VER_06:
3280         default:
3281                 r8153_u2p3en(tp, true);
3282                 break;
3283         }
3284
3285         set_bit(PHY_RESET, &tp->flags);
3286 }
3287
3288 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3289 {
3290         u32 ocp_data;
3291
3292         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3293         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3294         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
3295         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3296
3297         return ocp_data;
3298 }
3299
3300 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3301 {
3302         u32 ocp_data, ups_flags = 0;
3303         u16 data;
3304
3305         /* disable ALDPS before updating the PHY parameters */
3306         r8153b_aldps_en(tp, false);
3307
3308         /* disable EEE before updating the PHY parameters */
3309         r8153b_eee_en(tp, false);
3310         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3311
3312         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3313
3314         data = sram_read(tp, SRAM_GREEN_CFG);
3315         data |= R_TUNE_EN;
3316         sram_write(tp, SRAM_GREEN_CFG, data);
3317         data = ocp_reg_read(tp, OCP_NCTL_CFG);
3318         data |= PGA_RETURN_EN;
3319         ocp_reg_write(tp, OCP_NCTL_CFG, data);
3320
3321         /* ADC Bias Calibration:
3322          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3323          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3324          * ADC ioffset.
3325          */
3326         ocp_data = r8152_efuse_read(tp, 0x7d);
3327         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3328         if (data != 0xffff)
3329                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3330
3331         /* ups mode tx-link-pulse timing adjustment:
3332          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3333          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3334          */
3335         ocp_data = ocp_reg_read(tp, 0xc426);
3336         ocp_data &= 0x3fff;
3337         if (ocp_data) {
3338                 u32 swr_cnt_1ms_ini;
3339
3340                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3341                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3342                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3343                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3344         }
3345
3346         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3347         ocp_data |= PFM_PWM_SWITCH;
3348         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3349
3350         /* Advnace EEE */
3351         if (!r8153_patch_request(tp, true)) {
3352                 data = ocp_reg_read(tp, OCP_POWER_CFG);
3353                 data |= EEE_CLKDIV_EN;
3354                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3355
3356                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3357                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3358                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3359
3360                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3361                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3362
3363                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3364                              UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3365                              UPS_FLAGS_EEE_PLLOFF_GIGA;
3366
3367                 r8153_patch_request(tp, false);
3368         }
3369
3370         r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3371
3372         r8153b_eee_en(tp, true);
3373         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3374
3375         r8153b_aldps_en(tp, true);
3376         r8153b_enable_fc(tp);
3377         r8153_u2p3en(tp, true);
3378
3379         set_bit(PHY_RESET, &tp->flags);
3380 }
3381
3382 static void r8153_first_init(struct r8152 *tp)
3383 {
3384         u32 ocp_data;
3385         int i;
3386
3387         rxdy_gated_en(tp, true);
3388         r8153_teredo_off(tp);
3389
3390         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3391         ocp_data &= ~RCR_ACPT_ALL;
3392         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3393
3394         rtl8152_nic_reset(tp);
3395         rtl_reset_bmu(tp);
3396
3397         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3398         ocp_data &= ~NOW_IS_OOB;
3399         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3400
3401         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3402         ocp_data &= ~MCU_BORW_EN;
3403         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3404
3405         for (i = 0; i < 1000; i++) {
3406                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3407                 if (ocp_data & LINK_LIST_READY)
3408                         break;
3409                 usleep_range(1000, 2000);
3410         }
3411
3412         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3413         ocp_data |= RE_INIT_LL;
3414         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3415
3416         for (i = 0; i < 1000; i++) {
3417                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3418                 if (ocp_data & LINK_LIST_READY)
3419                         break;
3420                 usleep_range(1000, 2000);
3421         }
3422
3423         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3424
3425         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3426         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3427         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3428
3429         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3430         ocp_data |= TCR0_AUTO_FIFO;
3431         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3432
3433         rtl8152_nic_reset(tp);
3434
3435         /* rx share fifo credit full threshold */
3436         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3437         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3438         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3439         /* TX share fifo free credit full threshold */
3440         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3441 }
3442
3443 static void r8153_enter_oob(struct r8152 *tp)
3444 {
3445         u32 ocp_data;
3446         int i;
3447
3448         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3449         ocp_data &= ~NOW_IS_OOB;
3450         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3451
3452         rtl_disable(tp);
3453         rtl_reset_bmu(tp);
3454
3455         for (i = 0; i < 1000; i++) {
3456                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3457                 if (ocp_data & LINK_LIST_READY)
3458                         break;
3459                 usleep_range(1000, 2000);
3460         }
3461
3462         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3463         ocp_data |= RE_INIT_LL;
3464         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3465
3466         for (i = 0; i < 1000; i++) {
3467                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3468                 if (ocp_data & LINK_LIST_READY)
3469                         break;
3470                 usleep_range(1000, 2000);
3471         }
3472
3473         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3474         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3475
3476         switch (tp->version) {
3477         case RTL_VER_03:
3478         case RTL_VER_04:
3479         case RTL_VER_05:
3480         case RTL_VER_06:
3481                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3482                 ocp_data &= ~TEREDO_WAKE_MASK;
3483                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3484                 break;
3485
3486         case RTL_VER_08:
3487         case RTL_VER_09:
3488                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3489                  * type. Set it to zero. bits[7:0] are the W1C bits about
3490                  * the events. Set them to all 1 to clear them.
3491                  */
3492                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3493                 break;
3494
3495         default:
3496                 break;
3497         }
3498
3499         rtl_rx_vlan_en(tp, true);
3500
3501         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3502         ocp_data |= ALDPS_PROXY_MODE;
3503         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3504
3505         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3506         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3507         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3508
3509         rxdy_gated_en(tp, false);
3510
3511         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3512         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3513         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3514 }
3515
3516 static void rtl8153_disable(struct r8152 *tp)
3517 {
3518         r8153_aldps_en(tp, false);
3519         rtl_disable(tp);
3520         rtl_reset_bmu(tp);
3521         r8153_aldps_en(tp, true);
3522 }
3523
3524 static void rtl8153b_disable(struct r8152 *tp)
3525 {
3526         r8153b_aldps_en(tp, false);
3527         rtl_disable(tp);
3528         rtl_reset_bmu(tp);
3529         r8153b_aldps_en(tp, true);
3530 }
3531
3532 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3533 {
3534         u16 bmcr, anar, gbcr;
3535         enum spd_duplex speed_duplex;
3536         int ret = 0;
3537
3538         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3539         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3540                   ADVERTISE_100HALF | ADVERTISE_100FULL);
3541         if (tp->mii.supports_gmii) {
3542                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3543                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3544         } else {
3545                 gbcr = 0;
3546         }
3547
3548         if (autoneg == AUTONEG_DISABLE) {
3549                 if (speed == SPEED_10) {
3550                         bmcr = 0;
3551                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3552                         speed_duplex = FORCE_10M_HALF;
3553                 } else if (speed == SPEED_100) {
3554                         bmcr = BMCR_SPEED100;
3555                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3556                         speed_duplex = FORCE_100M_HALF;
3557                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3558                         bmcr = BMCR_SPEED1000;
3559                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3560                         speed_duplex = NWAY_1000M_FULL;
3561                 } else {
3562                         ret = -EINVAL;
3563                         goto out;
3564                 }
3565
3566                 if (duplex == DUPLEX_FULL) {
3567                         bmcr |= BMCR_FULLDPLX;
3568                         if (speed != SPEED_1000)
3569                                 speed_duplex++;
3570                 }
3571         } else {
3572                 if (speed == SPEED_10) {
3573                         if (duplex == DUPLEX_FULL) {
3574                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3575                                 speed_duplex = NWAY_10M_FULL;
3576                         } else {
3577                                 anar |= ADVERTISE_10HALF;
3578                                 speed_duplex = NWAY_10M_HALF;
3579                         }
3580                 } else if (speed == SPEED_100) {
3581                         if (duplex == DUPLEX_FULL) {
3582                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3583                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3584                                 speed_duplex = NWAY_100M_FULL;
3585                         } else {
3586                                 anar |= ADVERTISE_10HALF;
3587                                 anar |= ADVERTISE_100HALF;
3588                                 speed_duplex = NWAY_100M_HALF;
3589                         }
3590                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3591                         if (duplex == DUPLEX_FULL) {
3592                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3593                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3594                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3595                         } else {
3596                                 anar |= ADVERTISE_10HALF;
3597                                 anar |= ADVERTISE_100HALF;
3598                                 gbcr |= ADVERTISE_1000HALF;
3599                         }
3600                         speed_duplex = NWAY_1000M_FULL;
3601                 } else {
3602                         ret = -EINVAL;
3603                         goto out;
3604                 }
3605
3606                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3607         }
3608
3609         if (test_and_clear_bit(PHY_RESET, &tp->flags))
3610                 bmcr |= BMCR_RESET;
3611
3612         if (tp->mii.supports_gmii)
3613                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3614
3615         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3616         r8152_mdio_write(tp, MII_BMCR, bmcr);
3617
3618         switch (tp->version) {
3619         case RTL_VER_08:
3620         case RTL_VER_09:
3621                 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3622                                       UPS_FLAGS_SPEED_MASK);
3623                 break;
3624
3625         default:
3626                 break;
3627         }
3628
3629         if (bmcr & BMCR_RESET) {
3630                 int i;
3631
3632                 for (i = 0; i < 50; i++) {
3633                         msleep(20);
3634                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3635                                 break;
3636                 }
3637         }
3638
3639 out:
3640         return ret;
3641 }
3642
3643 static void rtl8152_up(struct r8152 *tp)
3644 {
3645         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3646                 return;
3647
3648         r8152_aldps_en(tp, false);
3649         r8152b_exit_oob(tp);
3650         r8152_aldps_en(tp, true);
3651 }
3652
3653 static void rtl8152_down(struct r8152 *tp)
3654 {
3655         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3656                 rtl_drop_queued_tx(tp);
3657                 return;
3658         }
3659
3660         r8152_power_cut_en(tp, false);
3661         r8152_aldps_en(tp, false);
3662         r8152b_enter_oob(tp);
3663         r8152_aldps_en(tp, true);
3664 }
3665
3666 static void rtl8153_up(struct r8152 *tp)
3667 {
3668         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3669                 return;
3670
3671         r8153_u1u2en(tp, false);
3672         r8153_u2p3en(tp, false);
3673         r8153_aldps_en(tp, false);
3674         r8153_first_init(tp);
3675         r8153_aldps_en(tp, true);
3676
3677         switch (tp->version) {
3678         case RTL_VER_03:
3679         case RTL_VER_04:
3680                 break;
3681         case RTL_VER_05:
3682         case RTL_VER_06:
3683         default:
3684                 r8153_u2p3en(tp, true);
3685                 break;
3686         }
3687
3688         r8153_u1u2en(tp, true);
3689 }
3690
3691 static void rtl8153_down(struct r8152 *tp)
3692 {
3693         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3694                 rtl_drop_queued_tx(tp);
3695                 return;
3696         }
3697
3698         r8153_u1u2en(tp, false);
3699         r8153_u2p3en(tp, false);
3700         r8153_power_cut_en(tp, false);
3701         r8153_aldps_en(tp, false);
3702         r8153_enter_oob(tp);
3703         r8153_aldps_en(tp, true);
3704 }
3705
3706 static void rtl8153b_up(struct r8152 *tp)
3707 {
3708         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3709                 return;
3710
3711         r8153b_u1u2en(tp, false);
3712         r8153_u2p3en(tp, false);
3713         r8153b_aldps_en(tp, false);
3714
3715         r8153_first_init(tp);
3716         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3717
3718         r8153b_aldps_en(tp, true);
3719         r8153_u2p3en(tp, true);
3720         r8153b_u1u2en(tp, true);
3721 }
3722
3723 static void rtl8153b_down(struct r8152 *tp)
3724 {
3725         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3726                 rtl_drop_queued_tx(tp);
3727                 return;
3728         }
3729
3730         r8153b_u1u2en(tp, false);
3731         r8153_u2p3en(tp, false);
3732         r8153b_power_cut_en(tp, false);
3733         r8153b_aldps_en(tp, false);
3734         r8153_enter_oob(tp);
3735         r8153b_aldps_en(tp, true);
3736 }
3737
3738 static bool rtl8152_in_nway(struct r8152 *tp)
3739 {
3740         u16 nway_state;
3741
3742         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3743         tp->ocp_base = 0x2000;
3744         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
3745         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3746
3747         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3748         if (nway_state & 0xc000)
3749                 return false;
3750         else
3751                 return true;
3752 }
3753
3754 static bool rtl8153_in_nway(struct r8152 *tp)
3755 {
3756         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3757
3758         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3759                 return false;
3760         else
3761                 return true;
3762 }
3763
3764 static void set_carrier(struct r8152 *tp)
3765 {
3766         struct net_device *netdev = tp->netdev;
3767         struct napi_struct *napi = &tp->napi;
3768         u8 speed;
3769
3770         speed = rtl8152_get_speed(tp);
3771
3772         if (speed & LINK_STATUS) {
3773                 if (!netif_carrier_ok(netdev)) {
3774                         tp->rtl_ops.enable(tp);
3775                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3776                         netif_stop_queue(netdev);
3777                         napi_disable(napi);
3778                         netif_carrier_on(netdev);
3779                         rtl_start_rx(tp);
3780                         napi_enable(&tp->napi);
3781                         netif_wake_queue(netdev);
3782                         netif_info(tp, link, netdev, "carrier on\n");
3783                 } else if (netif_queue_stopped(netdev) &&
3784                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3785                         netif_wake_queue(netdev);
3786                 }
3787         } else {
3788                 if (netif_carrier_ok(netdev)) {
3789                         netif_carrier_off(netdev);
3790                         napi_disable(napi);
3791                         tp->rtl_ops.disable(tp);
3792                         napi_enable(napi);
3793                         netif_info(tp, link, netdev, "carrier off\n");
3794                 }
3795         }
3796 }
3797
3798 static void rtl_work_func_t(struct work_struct *work)
3799 {
3800         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3801
3802         /* If the device is unplugged or !netif_running(), the workqueue
3803          * doesn't need to wake the device, and could return directly.
3804          */
3805         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3806                 return;
3807
3808         if (usb_autopm_get_interface(tp->intf) < 0)
3809                 return;
3810
3811         if (!test_bit(WORK_ENABLE, &tp->flags))
3812                 goto out1;
3813
3814         if (!mutex_trylock(&tp->control)) {
3815                 schedule_delayed_work(&tp->schedule, 0);
3816                 goto out1;
3817         }
3818
3819         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3820                 set_carrier(tp);
3821
3822         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3823                 _rtl8152_set_rx_mode(tp->netdev);
3824
3825         /* don't schedule napi before linking */
3826         if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3827             netif_carrier_ok(tp->netdev))
3828                 napi_schedule(&tp->napi);
3829
3830         mutex_unlock(&tp->control);
3831
3832 out1:
3833         usb_autopm_put_interface(tp->intf);
3834 }
3835
3836 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3837 {
3838         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3839
3840         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3841                 return;
3842
3843         if (usb_autopm_get_interface(tp->intf) < 0)
3844                 return;
3845
3846         mutex_lock(&tp->control);
3847
3848         tp->rtl_ops.hw_phy_cfg(tp);
3849
3850         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3851
3852         mutex_unlock(&tp->control);
3853
3854         usb_autopm_put_interface(tp->intf);
3855 }
3856
3857 #ifdef CONFIG_PM_SLEEP
3858 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3859                         void *data)
3860 {
3861         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3862
3863         switch (action) {
3864         case PM_HIBERNATION_PREPARE:
3865         case PM_SUSPEND_PREPARE:
3866                 usb_autopm_get_interface(tp->intf);
3867                 break;
3868
3869         case PM_POST_HIBERNATION:
3870         case PM_POST_SUSPEND:
3871                 usb_autopm_put_interface(tp->intf);
3872                 break;
3873
3874         case PM_POST_RESTORE:
3875         case PM_RESTORE_PREPARE:
3876         default:
3877                 break;
3878         }
3879
3880         return NOTIFY_DONE;
3881 }
3882 #endif
3883
3884 static int rtl8152_open(struct net_device *netdev)
3885 {
3886         struct r8152 *tp = netdev_priv(netdev);
3887         int res = 0;
3888
3889         res = alloc_all_mem(tp);
3890         if (res)
3891                 goto out;
3892
3893         res = usb_autopm_get_interface(tp->intf);
3894         if (res < 0)
3895                 goto out_free;
3896
3897         mutex_lock(&tp->control);
3898
3899         tp->rtl_ops.up(tp);
3900
3901         netif_carrier_off(netdev);
3902         netif_start_queue(netdev);
3903         set_bit(WORK_ENABLE, &tp->flags);
3904
3905         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3906         if (res) {
3907                 if (res == -ENODEV)
3908                         netif_device_detach(tp->netdev);
3909                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3910                            res);
3911                 goto out_unlock;
3912         }
3913         napi_enable(&tp->napi);
3914
3915         mutex_unlock(&tp->control);
3916
3917         usb_autopm_put_interface(tp->intf);
3918 #ifdef CONFIG_PM_SLEEP
3919         tp->pm_notifier.notifier_call = rtl_notifier;
3920         register_pm_notifier(&tp->pm_notifier);
3921 #endif
3922         return 0;
3923
3924 out_unlock:
3925         mutex_unlock(&tp->control);
3926         usb_autopm_put_interface(tp->intf);
3927 out_free:
3928         free_all_mem(tp);
3929 out:
3930         return res;
3931 }
3932
3933 static int rtl8152_close(struct net_device *netdev)
3934 {
3935         struct r8152 *tp = netdev_priv(netdev);
3936         int res = 0;
3937
3938 #ifdef CONFIG_PM_SLEEP
3939         unregister_pm_notifier(&tp->pm_notifier);
3940 #endif
3941         if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3942                 napi_disable(&tp->napi);
3943         clear_bit(WORK_ENABLE, &tp->flags);
3944         usb_kill_urb(tp->intr_urb);
3945         cancel_delayed_work_sync(&tp->schedule);
3946         netif_stop_queue(netdev);
3947
3948         res = usb_autopm_get_interface(tp->intf);
3949         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3950                 rtl_drop_queued_tx(tp);
3951                 rtl_stop_rx(tp);
3952         } else {
3953                 mutex_lock(&tp->control);
3954
3955                 tp->rtl_ops.down(tp);
3956
3957                 mutex_unlock(&tp->control);
3958         }
3959
3960         if (!res)
3961                 usb_autopm_put_interface(tp->intf);
3962
3963         free_all_mem(tp);
3964
3965         return res;
3966 }
3967
3968 static void rtl_tally_reset(struct r8152 *tp)
3969 {
3970         u32 ocp_data;
3971
3972         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3973         ocp_data |= TALLY_RESET;
3974         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3975 }
3976
3977 static void r8152b_init(struct r8152 *tp)
3978 {
3979         u32 ocp_data;
3980         u16 data;
3981
3982         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3983                 return;
3984
3985         data = r8152_mdio_read(tp, MII_BMCR);
3986         if (data & BMCR_PDOWN) {
3987                 data &= ~BMCR_PDOWN;
3988                 r8152_mdio_write(tp, MII_BMCR, data);
3989         }
3990
3991         r8152_aldps_en(tp, false);
3992
3993         if (tp->version == RTL_VER_01) {
3994                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3995                 ocp_data &= ~LED_MODE_MASK;
3996                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3997         }
3998
3999         r8152_power_cut_en(tp, false);
4000
4001         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4002         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4003         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4004         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4005         ocp_data &= ~MCU_CLK_RATIO_MASK;
4006         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4007         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4008         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4009                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4010         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4011
4012         rtl_tally_reset(tp);
4013
4014         /* enable rx aggregation */
4015         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4016         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4017         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4018 }
4019
4020 static void r8153_init(struct r8152 *tp)
4021 {
4022         u32 ocp_data;
4023         u16 data;
4024         int i;
4025
4026         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4027                 return;
4028
4029         r8153_u1u2en(tp, false);
4030
4031         for (i = 0; i < 500; i++) {
4032                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4033                     AUTOLOAD_DONE)
4034                         break;
4035
4036                 msleep(20);
4037                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4038                         break;
4039         }
4040
4041         data = r8153_phy_status(tp, 0);
4042
4043         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4044             tp->version == RTL_VER_05)
4045                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4046
4047         data = r8152_mdio_read(tp, MII_BMCR);
4048         if (data & BMCR_PDOWN) {
4049                 data &= ~BMCR_PDOWN;
4050                 r8152_mdio_write(tp, MII_BMCR, data);
4051         }
4052
4053         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4054
4055         r8153_u2p3en(tp, false);
4056
4057         if (tp->version == RTL_VER_04) {
4058                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4059                 ocp_data &= ~pwd_dn_scale_mask;
4060                 ocp_data |= pwd_dn_scale(96);
4061                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4062
4063                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4064                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4065                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4066         } else if (tp->version == RTL_VER_05) {
4067                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4068                 ocp_data &= ~ECM_ALDPS;
4069                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4070
4071                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4072                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4073                         ocp_data &= ~DYNAMIC_BURST;
4074                 else
4075                         ocp_data |= DYNAMIC_BURST;
4076                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4077         } else if (tp->version == RTL_VER_06) {
4078                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4079                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4080                         ocp_data &= ~DYNAMIC_BURST;
4081                 else
4082                         ocp_data |= DYNAMIC_BURST;
4083                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4084         }
4085
4086         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4087         ocp_data |= EP4_FULL_FC;
4088         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4089
4090         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4091         ocp_data &= ~TIMER11_EN;
4092         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4093
4094         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4095         ocp_data &= ~LED_MODE_MASK;
4096         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4097
4098         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4099         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4100                 ocp_data |= LPM_TIMER_500MS;
4101         else
4102                 ocp_data |= LPM_TIMER_500US;
4103         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4104
4105         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4106         ocp_data &= ~SEN_VAL_MASK;
4107         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4108         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4109
4110         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4111
4112         /* MAC clock speed down */
4113         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
4114         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
4115         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
4116         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
4117
4118         r8153_power_cut_en(tp, false);
4119         r8153_u1u2en(tp, true);
4120         usb_enable_lpm(tp->udev);
4121
4122         /* rx aggregation */
4123         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4124         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4125         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4126
4127         rtl_tally_reset(tp);
4128
4129         switch (tp->udev->speed) {
4130         case USB_SPEED_SUPER:
4131         case USB_SPEED_SUPER_PLUS:
4132                 tp->coalesce = COALESCE_SUPER;
4133                 break;
4134         case USB_SPEED_HIGH:
4135                 tp->coalesce = COALESCE_HIGH;
4136                 break;
4137         default:
4138                 tp->coalesce = COALESCE_SLOW;
4139                 break;
4140         }
4141 }
4142
4143 static void r8153b_init(struct r8152 *tp)
4144 {
4145         u32 ocp_data;
4146         u16 data;
4147         int i;
4148
4149         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4150                 return;
4151
4152         r8153b_u1u2en(tp, false);
4153
4154         for (i = 0; i < 500; i++) {
4155                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4156                     AUTOLOAD_DONE)
4157                         break;
4158
4159                 msleep(20);
4160                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4161                         break;
4162         }
4163
4164         data = r8153_phy_status(tp, 0);
4165
4166         data = r8152_mdio_read(tp, MII_BMCR);
4167         if (data & BMCR_PDOWN) {
4168                 data &= ~BMCR_PDOWN;
4169                 r8152_mdio_write(tp, MII_BMCR, data);
4170         }
4171
4172         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4173
4174         r8153_u2p3en(tp, false);
4175
4176         /* MSC timer = 0xfff * 8ms = 32760 ms */
4177         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4178
4179         /* U1/U2/L1 idle timer. 500 us */
4180         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4181
4182         r8153b_power_cut_en(tp, false);
4183         r8153b_ups_en(tp, false);
4184         r8153b_queue_wake(tp, false);
4185         rtl_runtime_suspend_enable(tp, false);
4186         r8153b_u1u2en(tp, true);
4187         usb_enable_lpm(tp->udev);
4188
4189         /* MAC clock speed down */
4190         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4191         ocp_data |= MAC_CLK_SPDWN_EN;
4192         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4193
4194         set_bit(GREEN_ETHERNET, &tp->flags);
4195
4196         /* rx aggregation */
4197         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4198         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4199         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4200
4201         rtl_tally_reset(tp);
4202
4203         tp->coalesce = 15000;   /* 15 us */
4204 }
4205
4206 static int rtl8152_pre_reset(struct usb_interface *intf)
4207 {
4208         struct r8152 *tp = usb_get_intfdata(intf);
4209         struct net_device *netdev;
4210
4211         if (!tp)
4212                 return 0;
4213
4214         netdev = tp->netdev;
4215         if (!netif_running(netdev))
4216                 return 0;
4217
4218         netif_stop_queue(netdev);
4219         napi_disable(&tp->napi);
4220         clear_bit(WORK_ENABLE, &tp->flags);
4221         usb_kill_urb(tp->intr_urb);
4222         cancel_delayed_work_sync(&tp->schedule);
4223         if (netif_carrier_ok(netdev)) {
4224                 mutex_lock(&tp->control);
4225                 tp->rtl_ops.disable(tp);
4226                 mutex_unlock(&tp->control);
4227         }
4228
4229         return 0;
4230 }
4231
4232 static int rtl8152_post_reset(struct usb_interface *intf)
4233 {
4234         struct r8152 *tp = usb_get_intfdata(intf);
4235         struct net_device *netdev;
4236
4237         if (!tp)
4238                 return 0;
4239
4240         netdev = tp->netdev;
4241         if (!netif_running(netdev))
4242                 return 0;
4243
4244         set_bit(WORK_ENABLE, &tp->flags);
4245         if (netif_carrier_ok(netdev)) {
4246                 mutex_lock(&tp->control);
4247                 tp->rtl_ops.enable(tp);
4248                 rtl_start_rx(tp);
4249                 rtl8152_set_rx_mode(netdev);
4250                 mutex_unlock(&tp->control);
4251         }
4252
4253         napi_enable(&tp->napi);
4254         netif_wake_queue(netdev);
4255         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4256
4257         if (!list_empty(&tp->rx_done))
4258                 napi_schedule(&tp->napi);
4259
4260         return 0;
4261 }
4262
4263 static bool delay_autosuspend(struct r8152 *tp)
4264 {
4265         bool sw_linking = !!netif_carrier_ok(tp->netdev);
4266         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4267
4268         /* This means a linking change occurs and the driver doesn't detect it,
4269          * yet. If the driver has disabled tx/rx and hw is linking on, the
4270          * device wouldn't wake up by receiving any packet.
4271          */
4272         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4273                 return true;
4274
4275         /* If the linking down is occurred by nway, the device may miss the
4276          * linking change event. And it wouldn't wake when linking on.
4277          */
4278         if (!sw_linking && tp->rtl_ops.in_nway(tp))
4279                 return true;
4280         else if (!skb_queue_empty(&tp->tx_queue))
4281                 return true;
4282         else
4283                 return false;
4284 }
4285
4286 static int rtl8152_runtime_resume(struct r8152 *tp)
4287 {
4288         struct net_device *netdev = tp->netdev;
4289
4290         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4291                 struct napi_struct *napi = &tp->napi;
4292
4293                 tp->rtl_ops.autosuspend_en(tp, false);
4294                 napi_disable(napi);
4295                 set_bit(WORK_ENABLE, &tp->flags);
4296
4297                 if (netif_carrier_ok(netdev)) {
4298                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
4299                                 rtl_start_rx(tp);
4300                         } else {
4301                                 netif_carrier_off(netdev);
4302                                 tp->rtl_ops.disable(tp);
4303                                 netif_info(tp, link, netdev, "linking down\n");
4304                         }
4305                 }
4306
4307                 napi_enable(napi);
4308                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4309                 smp_mb__after_atomic();
4310
4311                 if (!list_empty(&tp->rx_done))
4312                         napi_schedule(&tp->napi);
4313
4314                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4315         } else {
4316                 if (netdev->flags & IFF_UP)
4317                         tp->rtl_ops.autosuspend_en(tp, false);
4318
4319                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4320         }
4321
4322         return 0;
4323 }
4324
4325 static int rtl8152_system_resume(struct r8152 *tp)
4326 {
4327         struct net_device *netdev = tp->netdev;
4328
4329         netif_device_attach(netdev);
4330
4331         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4332                 tp->rtl_ops.up(tp);
4333                 netif_carrier_off(netdev);
4334                 set_bit(WORK_ENABLE, &tp->flags);
4335                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4336         }
4337
4338         return 0;
4339 }
4340
4341 static int rtl8152_runtime_suspend(struct r8152 *tp)
4342 {
4343         struct net_device *netdev = tp->netdev;
4344         int ret = 0;
4345
4346         set_bit(SELECTIVE_SUSPEND, &tp->flags);
4347         smp_mb__after_atomic();
4348
4349         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4350                 u32 rcr = 0;
4351
4352                 if (netif_carrier_ok(netdev)) {
4353                         u32 ocp_data;
4354
4355                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4356                         ocp_data = rcr & ~RCR_ACPT_ALL;
4357                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4358                         rxdy_gated_en(tp, true);
4359                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4360                                                  PLA_OOB_CTRL);
4361                         if (!(ocp_data & RXFIFO_EMPTY)) {
4362                                 rxdy_gated_en(tp, false);
4363                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4364                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4365                                 smp_mb__after_atomic();
4366                                 ret = -EBUSY;
4367                                 goto out1;
4368                         }
4369                 }
4370
4371                 clear_bit(WORK_ENABLE, &tp->flags);
4372                 usb_kill_urb(tp->intr_urb);
4373
4374                 tp->rtl_ops.autosuspend_en(tp, true);
4375
4376                 if (netif_carrier_ok(netdev)) {
4377                         struct napi_struct *napi = &tp->napi;
4378
4379                         napi_disable(napi);
4380                         rtl_stop_rx(tp);
4381                         rxdy_gated_en(tp, false);
4382                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4383                         napi_enable(napi);
4384                 }
4385
4386                 if (delay_autosuspend(tp)) {
4387                         rtl8152_runtime_resume(tp);
4388                         ret = -EBUSY;
4389                 }
4390         }
4391
4392 out1:
4393         return ret;
4394 }
4395
4396 static int rtl8152_system_suspend(struct r8152 *tp)
4397 {
4398         struct net_device *netdev = tp->netdev;
4399         int ret = 0;
4400
4401         netif_device_detach(netdev);
4402
4403         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4404                 struct napi_struct *napi = &tp->napi;
4405
4406                 clear_bit(WORK_ENABLE, &tp->flags);
4407                 usb_kill_urb(tp->intr_urb);
4408                 napi_disable(napi);
4409                 cancel_delayed_work_sync(&tp->schedule);
4410                 tp->rtl_ops.down(tp);
4411                 napi_enable(napi);
4412         }
4413
4414         return ret;
4415 }
4416
4417 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4418 {
4419         struct r8152 *tp = usb_get_intfdata(intf);
4420         int ret;
4421
4422         mutex_lock(&tp->control);
4423
4424         if (PMSG_IS_AUTO(message))
4425                 ret = rtl8152_runtime_suspend(tp);
4426         else
4427                 ret = rtl8152_system_suspend(tp);
4428
4429         mutex_unlock(&tp->control);
4430
4431         return ret;
4432 }
4433
4434 static int rtl8152_resume(struct usb_interface *intf)
4435 {
4436         struct r8152 *tp = usb_get_intfdata(intf);
4437         int ret;
4438
4439         mutex_lock(&tp->control);
4440
4441         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4442                 ret = rtl8152_runtime_resume(tp);
4443         else
4444                 ret = rtl8152_system_resume(tp);
4445
4446         mutex_unlock(&tp->control);
4447
4448         return ret;
4449 }
4450
4451 static int rtl8152_reset_resume(struct usb_interface *intf)
4452 {
4453         struct r8152 *tp = usb_get_intfdata(intf);
4454
4455         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4456         tp->rtl_ops.init(tp);
4457         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4458         set_ethernet_addr(tp);
4459         return rtl8152_resume(intf);
4460 }
4461
4462 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4463 {
4464         struct r8152 *tp = netdev_priv(dev);
4465
4466         if (usb_autopm_get_interface(tp->intf) < 0)
4467                 return;
4468
4469         if (!rtl_can_wakeup(tp)) {
4470                 wol->supported = 0;
4471                 wol->wolopts = 0;
4472         } else {
4473                 mutex_lock(&tp->control);
4474                 wol->supported = WAKE_ANY;
4475                 wol->wolopts = __rtl_get_wol(tp);
4476                 mutex_unlock(&tp->control);
4477         }
4478
4479         usb_autopm_put_interface(tp->intf);
4480 }
4481
4482 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4483 {
4484         struct r8152 *tp = netdev_priv(dev);
4485         int ret;
4486
4487         if (!rtl_can_wakeup(tp))
4488                 return -EOPNOTSUPP;
4489
4490         if (wol->wolopts & ~WAKE_ANY)
4491                 return -EINVAL;
4492
4493         ret = usb_autopm_get_interface(tp->intf);
4494         if (ret < 0)
4495                 goto out_set_wol;
4496
4497         mutex_lock(&tp->control);
4498
4499         __rtl_set_wol(tp, wol->wolopts);
4500         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4501
4502         mutex_unlock(&tp->control);
4503
4504         usb_autopm_put_interface(tp->intf);
4505
4506 out_set_wol:
4507         return ret;
4508 }
4509
4510 static u32 rtl8152_get_msglevel(struct net_device *dev)
4511 {
4512         struct r8152 *tp = netdev_priv(dev);
4513
4514         return tp->msg_enable;
4515 }
4516
4517 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4518 {
4519         struct r8152 *tp = netdev_priv(dev);
4520
4521         tp->msg_enable = value;
4522 }
4523
4524 static void rtl8152_get_drvinfo(struct net_device *netdev,
4525                                 struct ethtool_drvinfo *info)
4526 {
4527         struct r8152 *tp = netdev_priv(netdev);
4528
4529         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4530         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4531         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4532 }
4533
4534 static
4535 int rtl8152_get_link_ksettings(struct net_device *netdev,
4536                                struct ethtool_link_ksettings *cmd)
4537 {
4538         struct r8152 *tp = netdev_priv(netdev);
4539         int ret;
4540
4541         if (!tp->mii.mdio_read)
4542                 return -EOPNOTSUPP;
4543
4544         ret = usb_autopm_get_interface(tp->intf);
4545         if (ret < 0)
4546                 goto out;
4547
4548         mutex_lock(&tp->control);
4549
4550         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4551
4552         mutex_unlock(&tp->control);
4553
4554         usb_autopm_put_interface(tp->intf);
4555
4556 out:
4557         return ret;
4558 }
4559
4560 static int rtl8152_set_link_ksettings(struct net_device *dev,
4561                                       const struct ethtool_link_ksettings *cmd)
4562 {
4563         struct r8152 *tp = netdev_priv(dev);
4564         int ret;
4565
4566         ret = usb_autopm_get_interface(tp->intf);
4567         if (ret < 0)
4568                 goto out;
4569
4570         mutex_lock(&tp->control);
4571
4572         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4573                                 cmd->base.duplex);
4574         if (!ret) {
4575                 tp->autoneg = cmd->base.autoneg;
4576                 tp->speed = cmd->base.speed;
4577                 tp->duplex = cmd->base.duplex;
4578         }
4579
4580         mutex_unlock(&tp->control);
4581
4582         usb_autopm_put_interface(tp->intf);
4583
4584 out:
4585         return ret;
4586 }
4587
4588 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4589         "tx_packets",
4590         "rx_packets",
4591         "tx_errors",
4592         "rx_errors",
4593         "rx_missed",
4594         "align_errors",
4595         "tx_single_collisions",
4596         "tx_multi_collisions",
4597         "rx_unicast",
4598         "rx_broadcast",
4599         "rx_multicast",
4600         "tx_aborted",
4601         "tx_underrun",
4602 };
4603
4604 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4605 {
4606         switch (sset) {
4607         case ETH_SS_STATS:
4608                 return ARRAY_SIZE(rtl8152_gstrings);
4609         default:
4610                 return -EOPNOTSUPP;
4611         }
4612 }
4613
4614 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4615                                       struct ethtool_stats *stats, u64 *data)
4616 {
4617         struct r8152 *tp = netdev_priv(dev);
4618         struct tally_counter tally;
4619
4620         if (usb_autopm_get_interface(tp->intf) < 0)
4621                 return;
4622
4623         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4624
4625         usb_autopm_put_interface(tp->intf);
4626
4627         data[0] = le64_to_cpu(tally.tx_packets);
4628         data[1] = le64_to_cpu(tally.rx_packets);
4629         data[2] = le64_to_cpu(tally.tx_errors);
4630         data[3] = le32_to_cpu(tally.rx_errors);
4631         data[4] = le16_to_cpu(tally.rx_missed);
4632         data[5] = le16_to_cpu(tally.align_errors);
4633         data[6] = le32_to_cpu(tally.tx_one_collision);
4634         data[7] = le32_to_cpu(tally.tx_multi_collision);
4635         data[8] = le64_to_cpu(tally.rx_unicast);
4636         data[9] = le64_to_cpu(tally.rx_broadcast);
4637         data[10] = le32_to_cpu(tally.rx_multicast);
4638         data[11] = le16_to_cpu(tally.tx_aborted);
4639         data[12] = le16_to_cpu(tally.tx_underrun);
4640 }
4641
4642 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4643 {
4644         switch (stringset) {
4645         case ETH_SS_STATS:
4646                 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
4647                 break;
4648         }
4649 }
4650
4651 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4652 {
4653         u32 ocp_data, lp, adv, supported = 0;
4654         u16 val;
4655
4656         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4657         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4658
4659         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4660         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4661
4662         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4663         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4664
4665         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4666         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4667
4668         eee->eee_enabled = !!ocp_data;
4669         eee->eee_active = !!(supported & adv & lp);
4670         eee->supported = supported;
4671         eee->advertised = adv;
4672         eee->lp_advertised = lp;
4673
4674         return 0;
4675 }
4676
4677 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4678 {
4679         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4680
4681         r8152_eee_en(tp, eee->eee_enabled);
4682
4683         if (!eee->eee_enabled)
4684                 val = 0;
4685
4686         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4687
4688         return 0;
4689 }
4690
4691 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4692 {
4693         u32 ocp_data, lp, adv, supported = 0;
4694         u16 val;
4695
4696         val = ocp_reg_read(tp, OCP_EEE_ABLE);
4697         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4698
4699         val = ocp_reg_read(tp, OCP_EEE_ADV);
4700         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4701
4702         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4703         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4704
4705         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4706         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4707
4708         eee->eee_enabled = !!ocp_data;
4709         eee->eee_active = !!(supported & adv & lp);
4710         eee->supported = supported;
4711         eee->advertised = adv;
4712         eee->lp_advertised = lp;
4713
4714         return 0;
4715 }
4716
4717 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4718 {
4719         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4720
4721         r8153_eee_en(tp, eee->eee_enabled);
4722
4723         if (!eee->eee_enabled)
4724                 val = 0;
4725
4726         ocp_reg_write(tp, OCP_EEE_ADV, val);
4727
4728         return 0;
4729 }
4730
4731 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4732 {
4733         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4734
4735         r8153b_eee_en(tp, eee->eee_enabled);
4736
4737         if (!eee->eee_enabled)
4738                 val = 0;
4739
4740         ocp_reg_write(tp, OCP_EEE_ADV, val);
4741
4742         return 0;
4743 }
4744
4745 static int
4746 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4747 {
4748         struct r8152 *tp = netdev_priv(net);
4749         int ret;
4750
4751         ret = usb_autopm_get_interface(tp->intf);
4752         if (ret < 0)
4753                 goto out;
4754
4755         mutex_lock(&tp->control);
4756
4757         ret = tp->rtl_ops.eee_get(tp, edata);
4758
4759         mutex_unlock(&tp->control);
4760
4761         usb_autopm_put_interface(tp->intf);
4762
4763 out:
4764         return ret;
4765 }
4766
4767 static int
4768 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4769 {
4770         struct r8152 *tp = netdev_priv(net);
4771         int ret;
4772
4773         ret = usb_autopm_get_interface(tp->intf);
4774         if (ret < 0)
4775                 goto out;
4776
4777         mutex_lock(&tp->control);
4778
4779         ret = tp->rtl_ops.eee_set(tp, edata);
4780         if (!ret)
4781                 ret = mii_nway_restart(&tp->mii);
4782
4783         mutex_unlock(&tp->control);
4784
4785         usb_autopm_put_interface(tp->intf);
4786
4787 out:
4788         return ret;
4789 }
4790
4791 static int rtl8152_nway_reset(struct net_device *dev)
4792 {
4793         struct r8152 *tp = netdev_priv(dev);
4794         int ret;
4795
4796         ret = usb_autopm_get_interface(tp->intf);
4797         if (ret < 0)
4798                 goto out;
4799
4800         mutex_lock(&tp->control);
4801
4802         ret = mii_nway_restart(&tp->mii);
4803
4804         mutex_unlock(&tp->control);
4805
4806         usb_autopm_put_interface(tp->intf);
4807
4808 out:
4809         return ret;
4810 }
4811
4812 static int rtl8152_get_coalesce(struct net_device *netdev,
4813                                 struct ethtool_coalesce *coalesce)
4814 {
4815         struct r8152 *tp = netdev_priv(netdev);
4816
4817         switch (tp->version) {
4818         case RTL_VER_01:
4819         case RTL_VER_02:
4820         case RTL_VER_07:
4821                 return -EOPNOTSUPP;
4822         default:
4823                 break;
4824         }
4825
4826         coalesce->rx_coalesce_usecs = tp->coalesce;
4827
4828         return 0;
4829 }
4830
4831 static int rtl8152_set_coalesce(struct net_device *netdev,
4832                                 struct ethtool_coalesce *coalesce)
4833 {
4834         struct r8152 *tp = netdev_priv(netdev);
4835         int ret;
4836
4837         switch (tp->version) {
4838         case RTL_VER_01:
4839         case RTL_VER_02:
4840         case RTL_VER_07:
4841                 return -EOPNOTSUPP;
4842         default:
4843                 break;
4844         }
4845
4846         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4847                 return -EINVAL;
4848
4849         ret = usb_autopm_get_interface(tp->intf);
4850         if (ret < 0)
4851                 return ret;
4852
4853         mutex_lock(&tp->control);
4854
4855         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4856                 tp->coalesce = coalesce->rx_coalesce_usecs;
4857
4858                 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4859                         r8153_set_rx_early_timeout(tp);
4860         }
4861
4862         mutex_unlock(&tp->control);
4863
4864         usb_autopm_put_interface(tp->intf);
4865
4866         return ret;
4867 }
4868
4869 static const struct ethtool_ops ops = {
4870         .get_drvinfo = rtl8152_get_drvinfo,
4871         .get_link = ethtool_op_get_link,
4872         .nway_reset = rtl8152_nway_reset,
4873         .get_msglevel = rtl8152_get_msglevel,
4874         .set_msglevel = rtl8152_set_msglevel,
4875         .get_wol = rtl8152_get_wol,
4876         .set_wol = rtl8152_set_wol,
4877         .get_strings = rtl8152_get_strings,
4878         .get_sset_count = rtl8152_get_sset_count,
4879         .get_ethtool_stats = rtl8152_get_ethtool_stats,
4880         .get_coalesce = rtl8152_get_coalesce,
4881         .set_coalesce = rtl8152_set_coalesce,
4882         .get_eee = rtl_ethtool_get_eee,
4883         .set_eee = rtl_ethtool_set_eee,
4884         .get_link_ksettings = rtl8152_get_link_ksettings,
4885         .set_link_ksettings = rtl8152_set_link_ksettings,
4886 };
4887
4888 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4889 {
4890         struct r8152 *tp = netdev_priv(netdev);
4891         struct mii_ioctl_data *data = if_mii(rq);
4892         int res;
4893
4894         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4895                 return -ENODEV;
4896
4897         res = usb_autopm_get_interface(tp->intf);
4898         if (res < 0)
4899                 goto out;
4900
4901         switch (cmd) {
4902         case SIOCGMIIPHY:
4903                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4904                 break;
4905
4906         case SIOCGMIIREG:
4907                 mutex_lock(&tp->control);
4908                 data->val_out = r8152_mdio_read(tp, data->reg_num);
4909                 mutex_unlock(&tp->control);
4910                 break;
4911
4912         case SIOCSMIIREG:
4913                 if (!capable(CAP_NET_ADMIN)) {
4914                         res = -EPERM;
4915                         break;
4916                 }
4917                 mutex_lock(&tp->control);
4918                 r8152_mdio_write(tp, data->reg_num, data->val_in);
4919                 mutex_unlock(&tp->control);
4920                 break;
4921
4922         default:
4923                 res = -EOPNOTSUPP;
4924         }
4925
4926         usb_autopm_put_interface(tp->intf);
4927
4928 out:
4929         return res;
4930 }
4931
4932 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4933 {
4934         struct r8152 *tp = netdev_priv(dev);
4935         int ret;
4936
4937         switch (tp->version) {
4938         case RTL_VER_01:
4939         case RTL_VER_02:
4940         case RTL_VER_07:
4941                 dev->mtu = new_mtu;
4942                 return 0;
4943         default:
4944                 break;
4945         }
4946
4947         ret = usb_autopm_get_interface(tp->intf);
4948         if (ret < 0)
4949                 return ret;
4950
4951         mutex_lock(&tp->control);
4952
4953         dev->mtu = new_mtu;
4954
4955         if (netif_running(dev)) {
4956                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4957
4958                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4959
4960                 if (netif_carrier_ok(dev))
4961                         r8153_set_rx_early_size(tp);
4962         }
4963
4964         mutex_unlock(&tp->control);
4965
4966         usb_autopm_put_interface(tp->intf);
4967
4968         return ret;
4969 }
4970
4971 static const struct net_device_ops rtl8152_netdev_ops = {
4972         .ndo_open               = rtl8152_open,
4973         .ndo_stop               = rtl8152_close,
4974         .ndo_do_ioctl           = rtl8152_ioctl,
4975         .ndo_start_xmit         = rtl8152_start_xmit,
4976         .ndo_tx_timeout         = rtl8152_tx_timeout,
4977         .ndo_set_features       = rtl8152_set_features,
4978         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
4979         .ndo_set_mac_address    = rtl8152_set_mac_address,
4980         .ndo_change_mtu         = rtl8152_change_mtu,
4981         .ndo_validate_addr      = eth_validate_addr,
4982         .ndo_features_check     = rtl8152_features_check,
4983 };
4984
4985 static void rtl8152_unload(struct r8152 *tp)
4986 {
4987         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4988                 return;
4989
4990         if (tp->version != RTL_VER_01)
4991                 r8152_power_cut_en(tp, true);
4992 }
4993
4994 static void rtl8153_unload(struct r8152 *tp)
4995 {
4996         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4997                 return;
4998
4999         r8153_power_cut_en(tp, false);
5000 }
5001
5002 static void rtl8153b_unload(struct r8152 *tp)
5003 {
5004         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5005                 return;
5006
5007         r8153b_power_cut_en(tp, false);
5008 }
5009
5010 static int rtl_ops_init(struct r8152 *tp)
5011 {
5012         struct rtl_ops *ops = &tp->rtl_ops;
5013         int ret = 0;
5014
5015         switch (tp->version) {
5016         case RTL_VER_01:
5017         case RTL_VER_02:
5018         case RTL_VER_07:
5019                 ops->init               = r8152b_init;
5020                 ops->enable             = rtl8152_enable;
5021                 ops->disable            = rtl8152_disable;
5022                 ops->up                 = rtl8152_up;
5023                 ops->down               = rtl8152_down;
5024                 ops->unload             = rtl8152_unload;
5025                 ops->eee_get            = r8152_get_eee;
5026                 ops->eee_set            = r8152_set_eee;
5027                 ops->in_nway            = rtl8152_in_nway;
5028                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
5029                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
5030                 break;
5031
5032         case RTL_VER_03:
5033         case RTL_VER_04:
5034         case RTL_VER_05:
5035         case RTL_VER_06:
5036                 ops->init               = r8153_init;
5037                 ops->enable             = rtl8153_enable;
5038                 ops->disable            = rtl8153_disable;
5039                 ops->up                 = rtl8153_up;
5040                 ops->down               = rtl8153_down;
5041                 ops->unload             = rtl8153_unload;
5042                 ops->eee_get            = r8153_get_eee;
5043                 ops->eee_set            = r8153_set_eee;
5044                 ops->in_nway            = rtl8153_in_nway;
5045                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
5046                 ops->autosuspend_en     = rtl8153_runtime_enable;
5047                 break;
5048
5049         case RTL_VER_08:
5050         case RTL_VER_09:
5051                 ops->init               = r8153b_init;
5052                 ops->enable             = rtl8153_enable;
5053                 ops->disable            = rtl8153b_disable;
5054                 ops->up                 = rtl8153b_up;
5055                 ops->down               = rtl8153b_down;
5056                 ops->unload             = rtl8153b_unload;
5057                 ops->eee_get            = r8153_get_eee;
5058                 ops->eee_set            = r8153b_set_eee;
5059                 ops->in_nway            = rtl8153_in_nway;
5060                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
5061                 ops->autosuspend_en     = rtl8153b_runtime_enable;
5062                 break;
5063
5064         default:
5065                 ret = -ENODEV;
5066                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5067                 break;
5068         }
5069
5070         return ret;
5071 }
5072
5073 static u8 rtl_get_version(struct usb_interface *intf)
5074 {
5075         struct usb_device *udev = interface_to_usbdev(intf);
5076         u32 ocp_data = 0;
5077         __le32 *tmp;
5078         u8 version;
5079         int ret;
5080
5081         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5082         if (!tmp)
5083                 return 0;
5084
5085         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5086                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5087                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5088         if (ret > 0)
5089                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5090
5091         kfree(tmp);
5092
5093         switch (ocp_data) {
5094         case 0x4c00:
5095                 version = RTL_VER_01;
5096                 break;
5097         case 0x4c10:
5098                 version = RTL_VER_02;
5099                 break;
5100         case 0x5c00:
5101                 version = RTL_VER_03;
5102                 break;
5103         case 0x5c10:
5104                 version = RTL_VER_04;
5105                 break;
5106         case 0x5c20:
5107                 version = RTL_VER_05;
5108                 break;
5109         case 0x5c30:
5110                 version = RTL_VER_06;
5111                 break;
5112         case 0x4800:
5113                 version = RTL_VER_07;
5114                 break;
5115         case 0x6000:
5116                 version = RTL_VER_08;
5117                 break;
5118         case 0x6010:
5119                 version = RTL_VER_09;
5120                 break;
5121         default:
5122                 version = RTL_VER_UNKNOWN;
5123                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5124                 break;
5125         }
5126
5127         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5128
5129         return version;
5130 }
5131
5132 static int rtl8152_probe(struct usb_interface *intf,
5133                          const struct usb_device_id *id)
5134 {
5135         struct usb_device *udev = interface_to_usbdev(intf);
5136         u8 version = rtl_get_version(intf);
5137         struct r8152 *tp;
5138         struct net_device *netdev;
5139         int ret;
5140
5141         if (version == RTL_VER_UNKNOWN)
5142                 return -ENODEV;
5143
5144         if (udev->actconfig->desc.bConfigurationValue != 1) {
5145                 usb_driver_set_configuration(udev, 1);
5146                 return -ENODEV;
5147         }
5148
5149         if (intf->cur_altsetting->desc.bNumEndpoints < 3)
5150                 return -ENODEV;
5151
5152         usb_reset_device(udev);
5153         netdev = alloc_etherdev(sizeof(struct r8152));
5154         if (!netdev) {
5155                 dev_err(&intf->dev, "Out of memory\n");
5156                 return -ENOMEM;
5157         }
5158
5159         SET_NETDEV_DEV(netdev, &intf->dev);
5160         tp = netdev_priv(netdev);
5161         tp->msg_enable = 0x7FFF;
5162
5163         tp->udev = udev;
5164         tp->netdev = netdev;
5165         tp->intf = intf;
5166         tp->version = version;
5167
5168         switch (version) {
5169         case RTL_VER_01:
5170         case RTL_VER_02:
5171         case RTL_VER_07:
5172                 tp->mii.supports_gmii = 0;
5173                 break;
5174         default:
5175                 tp->mii.supports_gmii = 1;
5176                 break;
5177         }
5178
5179         ret = rtl_ops_init(tp);
5180         if (ret)
5181                 goto out;
5182
5183         mutex_init(&tp->control);
5184         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5185         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5186
5187         netdev->netdev_ops = &rtl8152_netdev_ops;
5188         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5189
5190         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5191                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5192                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5193                             NETIF_F_HW_VLAN_CTAG_TX;
5194         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5195                               NETIF_F_TSO | NETIF_F_FRAGLIST |
5196                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5197                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5198         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5199                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5200                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5201
5202         if (tp->version == RTL_VER_01) {
5203                 netdev->features &= ~NETIF_F_RXCSUM;
5204                 netdev->hw_features &= ~NETIF_F_RXCSUM;
5205         }
5206
5207         netdev->ethtool_ops = &ops;
5208         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5209
5210         /* MTU range: 68 - 1500 or 9194 */
5211         netdev->min_mtu = ETH_MIN_MTU;
5212         switch (tp->version) {
5213         case RTL_VER_01:
5214         case RTL_VER_02:
5215                 netdev->max_mtu = ETH_DATA_LEN;
5216                 break;
5217         default:
5218                 netdev->max_mtu = RTL8153_MAX_MTU;
5219                 break;
5220         }
5221
5222         tp->mii.dev = netdev;
5223         tp->mii.mdio_read = read_mii_word;
5224         tp->mii.mdio_write = write_mii_word;
5225         tp->mii.phy_id_mask = 0x3f;
5226         tp->mii.reg_num_mask = 0x1f;
5227         tp->mii.phy_id = R8152_PHY_ID;
5228
5229         tp->autoneg = AUTONEG_ENABLE;
5230         tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5231         tp->duplex = DUPLEX_FULL;
5232
5233         intf->needs_remote_wakeup = 1;
5234
5235         if (!rtl_can_wakeup(tp))
5236                 __rtl_set_wol(tp, 0);
5237         else
5238                 tp->saved_wolopts = __rtl_get_wol(tp);
5239
5240         tp->rtl_ops.init(tp);
5241         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5242         set_ethernet_addr(tp);
5243
5244         usb_set_intfdata(intf, tp);
5245         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5246
5247         ret = register_netdev(netdev);
5248         if (ret != 0) {
5249                 netif_err(tp, probe, netdev, "couldn't register the device\n");
5250                 goto out1;
5251         }
5252
5253         if (tp->saved_wolopts)
5254                 device_set_wakeup_enable(&udev->dev, true);
5255         else
5256                 device_set_wakeup_enable(&udev->dev, false);
5257
5258         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5259
5260         return 0;
5261
5262 out1:
5263         netif_napi_del(&tp->napi);
5264         usb_set_intfdata(intf, NULL);
5265 out:
5266         free_netdev(netdev);
5267         return ret;
5268 }
5269
5270 static void rtl8152_disconnect(struct usb_interface *intf)
5271 {
5272         struct r8152 *tp = usb_get_intfdata(intf);
5273
5274         usb_set_intfdata(intf, NULL);
5275         if (tp) {
5276                 struct usb_device *udev = tp->udev;
5277
5278                 if (udev->state == USB_STATE_NOTATTACHED)
5279                         set_bit(RTL8152_UNPLUG, &tp->flags);
5280
5281                 netif_napi_del(&tp->napi);
5282                 unregister_netdev(tp->netdev);
5283                 cancel_delayed_work_sync(&tp->hw_phy_work);
5284                 tp->rtl_ops.unload(tp);
5285                 free_netdev(tp->netdev);
5286         }
5287 }
5288
5289 #define REALTEK_USB_DEVICE(vend, prod)  \
5290         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5291                        USB_DEVICE_ID_MATCH_INT_CLASS, \
5292         .idVendor = (vend), \
5293         .idProduct = (prod), \
5294         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5295 }, \
5296 { \
5297         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5298                        USB_DEVICE_ID_MATCH_DEVICE, \
5299         .idVendor = (vend), \
5300         .idProduct = (prod), \
5301         .bInterfaceClass = USB_CLASS_COMM, \
5302         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5303         .bInterfaceProtocol = USB_CDC_PROTO_NONE
5304
5305 /* table of devices that work with this driver */
5306 static const struct usb_device_id rtl8152_table[] = {
5307         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5308         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5309         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5310         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5311         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5312         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
5313         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5314         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
5315         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3054)},
5316         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
5317         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
5318         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
5319         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
5320         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
5321         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x721e)},
5322         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
5323         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5324         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
5325         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
5326         {}
5327 };
5328
5329 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5330
5331 static struct usb_driver rtl8152_driver = {
5332         .name =         MODULENAME,
5333         .id_table =     rtl8152_table,
5334         .probe =        rtl8152_probe,
5335         .disconnect =   rtl8152_disconnect,
5336         .suspend =      rtl8152_suspend,
5337         .resume =       rtl8152_resume,
5338         .reset_resume = rtl8152_reset_resume,
5339         .pre_reset =    rtl8152_pre_reset,
5340         .post_reset =   rtl8152_post_reset,
5341         .supports_autosuspend = 1,
5342         .disable_hub_initiated_lpm = 1,
5343 };
5344
5345 module_usb_driver(rtl8152_driver);
5346
5347 MODULE_AUTHOR(DRIVER_AUTHOR);
5348 MODULE_DESCRIPTION(DRIVER_DESC);
5349 MODULE_LICENSE("GPL");
5350 MODULE_VERSION(DRIVER_VERSION);