GNU Linux-libre 5.10.217-gnu1
[releases.git] / drivers / net / usb / r8152.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29
30 /* Information for net-next */
31 #define NETNEXT_VERSION         "11"
32
33 /* Information for net */
34 #define NET_VERSION             "11"
35
36 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
40
41 #define R8152_PHY_ID            32
42
43 #define PLA_IDR                 0xc000
44 #define PLA_RCR                 0xc010
45 #define PLA_RMS                 0xc016
46 #define PLA_RXFIFO_CTRL0        0xc0a0
47 #define PLA_RXFIFO_CTRL1        0xc0a4
48 #define PLA_RXFIFO_CTRL2        0xc0a8
49 #define PLA_DMY_REG0            0xc0b0
50 #define PLA_FMC                 0xc0b4
51 #define PLA_CFG_WOL             0xc0b6
52 #define PLA_TEREDO_CFG          0xc0bc
53 #define PLA_TEREDO_WAKE_BASE    0xc0c4
54 #define PLA_MAR                 0xcd00
55 #define PLA_BACKUP              0xd000
56 #define PLA_BDC_CR              0xd1a0
57 #define PLA_TEREDO_TIMER        0xd2cc
58 #define PLA_REALWOW_TIMER       0xd2e8
59 #define PLA_UPHY_TIMER          0xd388
60 #define PLA_SUSPEND_FLAG        0xd38a
61 #define PLA_INDICATE_FALG       0xd38c
62 #define PLA_MACDBG_PRE          0xd38c  /* RTL_VER_04 only */
63 #define PLA_MACDBG_POST         0xd38e  /* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS        0xd398
65 #define PLA_EFUSE_DATA          0xdd00
66 #define PLA_EFUSE_CMD           0xdd02
67 #define PLA_LEDSEL              0xdd90
68 #define PLA_LED_FEATURE         0xdd92
69 #define PLA_PHYAR               0xde00
70 #define PLA_BOOT_CTRL           0xe004
71 #define PLA_LWAKE_CTRL_REG      0xe007
72 #define PLA_GPHY_INTR_IMR       0xe022
73 #define PLA_EEE_CR              0xe040
74 #define PLA_EEEP_CR             0xe080
75 #define PLA_MAC_PWR_CTRL        0xe0c0
76 #define PLA_MAC_PWR_CTRL2       0xe0ca
77 #define PLA_MAC_PWR_CTRL3       0xe0cc
78 #define PLA_MAC_PWR_CTRL4       0xe0ce
79 #define PLA_WDT6_CTRL           0xe428
80 #define PLA_TCR0                0xe610
81 #define PLA_TCR1                0xe612
82 #define PLA_MTPS                0xe615
83 #define PLA_TXFIFO_CTRL         0xe618
84 #define PLA_RSTTALLY            0xe800
85 #define PLA_CR                  0xe813
86 #define PLA_CRWECR              0xe81c
87 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
88 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
89 #define PLA_CONFIG5             0xe822
90 #define PLA_PHY_PWR             0xe84c
91 #define PLA_OOB_CTRL            0xe84f
92 #define PLA_CPCR                0xe854
93 #define PLA_MISC_0              0xe858
94 #define PLA_MISC_1              0xe85a
95 #define PLA_OCP_GPHY_BASE       0xe86c
96 #define PLA_TALLYCNT            0xe890
97 #define PLA_SFF_STS_7           0xe8de
98 #define PLA_PHYSTATUS           0xe908
99 #define PLA_CONFIG6             0xe90a /* CONFIG6 */
100 #define PLA_BP_BA               0xfc26
101 #define PLA_BP_0                0xfc28
102 #define PLA_BP_1                0xfc2a
103 #define PLA_BP_2                0xfc2c
104 #define PLA_BP_3                0xfc2e
105 #define PLA_BP_4                0xfc30
106 #define PLA_BP_5                0xfc32
107 #define PLA_BP_6                0xfc34
108 #define PLA_BP_7                0xfc36
109 #define PLA_BP_EN               0xfc38
110
111 #define USB_USB2PHY             0xb41e
112 #define USB_SSPHYLINK1          0xb426
113 #define USB_SSPHYLINK2          0xb428
114 #define USB_U2P3_CTRL           0xb460
115 #define USB_CSR_DUMMY1          0xb464
116 #define USB_CSR_DUMMY2          0xb466
117 #define USB_DEV_STAT            0xb808
118 #define USB_CONNECT_TIMER       0xcbf8
119 #define USB_MSC_TIMER           0xcbfc
120 #define USB_BURST_SIZE          0xcfc0
121 #define USB_FW_FIX_EN0          0xcfca
122 #define USB_FW_FIX_EN1          0xcfcc
123 #define USB_LPM_CONFIG          0xcfd8
124 #define USB_CSTMR               0xcfef  /* RTL8153A */
125 #define USB_FW_CTRL             0xd334  /* RTL8153B */
126 #define USB_FC_TIMER            0xd340
127 #define USB_USB_CTRL            0xd406
128 #define USB_PHY_CTRL            0xd408
129 #define USB_TX_AGG              0xd40a
130 #define USB_RX_BUF_TH           0xd40c
131 #define USB_USB_TIMER           0xd428
132 #define USB_RX_EARLY_TIMEOUT    0xd42c
133 #define USB_RX_EARLY_SIZE       0xd42e
134 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
135 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
136 #define USB_TX_DMA              0xd434
137 #define USB_UPT_RXDMA_OWN       0xd437
138 #define USB_TOLERANCE           0xd490
139 #define USB_LPM_CTRL            0xd41a
140 #define USB_BMU_RESET           0xd4b0
141 #define USB_U1U2_TIMER          0xd4da
142 #define USB_FW_TASK             0xd4e8  /* RTL8153B */
143 #define USB_UPS_CTRL            0xd800
144 #define USB_POWER_CUT           0xd80a
145 #define USB_MISC_0              0xd81a
146 #define USB_MISC_1              0xd81f
147 #define USB_AFE_CTRL2           0xd824
148 #define USB_UPS_CFG             0xd842
149 #define USB_UPS_FLAGS           0xd848
150 #define USB_WDT1_CTRL           0xe404
151 #define USB_WDT11_CTRL          0xe43c
152 #define USB_BP_BA               PLA_BP_BA
153 #define USB_BP_0                PLA_BP_0
154 #define USB_BP_1                PLA_BP_1
155 #define USB_BP_2                PLA_BP_2
156 #define USB_BP_3                PLA_BP_3
157 #define USB_BP_4                PLA_BP_4
158 #define USB_BP_5                PLA_BP_5
159 #define USB_BP_6                PLA_BP_6
160 #define USB_BP_7                PLA_BP_7
161 #define USB_BP_EN               PLA_BP_EN       /* RTL8153A */
162 #define USB_BP_8                0xfc38          /* RTL8153B */
163 #define USB_BP_9                0xfc3a
164 #define USB_BP_10               0xfc3c
165 #define USB_BP_11               0xfc3e
166 #define USB_BP_12               0xfc40
167 #define USB_BP_13               0xfc42
168 #define USB_BP_14               0xfc44
169 #define USB_BP_15               0xfc46
170 #define USB_BP2_EN              0xfc48
171
172 /* OCP Registers */
173 #define OCP_ALDPS_CONFIG        0x2010
174 #define OCP_EEE_CONFIG1         0x2080
175 #define OCP_EEE_CONFIG2         0x2092
176 #define OCP_EEE_CONFIG3         0x2094
177 #define OCP_BASE_MII            0xa400
178 #define OCP_EEE_AR              0xa41a
179 #define OCP_EEE_DATA            0xa41c
180 #define OCP_PHY_STATUS          0xa420
181 #define OCP_NCTL_CFG            0xa42c
182 #define OCP_POWER_CFG           0xa430
183 #define OCP_EEE_CFG             0xa432
184 #define OCP_SRAM_ADDR           0xa436
185 #define OCP_SRAM_DATA           0xa438
186 #define OCP_DOWN_SPEED          0xa442
187 #define OCP_EEE_ABLE            0xa5c4
188 #define OCP_EEE_ADV             0xa5d0
189 #define OCP_EEE_LPABLE          0xa5d2
190 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
191 #define OCP_PHY_PATCH_STAT      0xb800
192 #define OCP_PHY_PATCH_CMD       0xb820
193 #define OCP_PHY_LOCK            0xb82e
194 #define OCP_ADC_IOFFSET         0xbcfc
195 #define OCP_ADC_CFG             0xbc06
196 #define OCP_SYSCLK_CFG          0xc416
197
198 /* SRAM Register */
199 #define SRAM_GREEN_CFG          0x8011
200 #define SRAM_LPF_CFG            0x8012
201 #define SRAM_10M_AMP1           0x8080
202 #define SRAM_10M_AMP2           0x8082
203 #define SRAM_IMPEDANCE          0x8084
204 #define SRAM_PHY_LOCK           0xb82e
205
206 /* PLA_RCR */
207 #define RCR_AAP                 0x00000001
208 #define RCR_APM                 0x00000002
209 #define RCR_AM                  0x00000004
210 #define RCR_AB                  0x00000008
211 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
212
213 /* PLA_RXFIFO_CTRL0 */
214 #define RXFIFO_THR1_NORMAL      0x00080002
215 #define RXFIFO_THR1_OOB         0x01800003
216
217 /* PLA_RXFIFO_CTRL1 */
218 #define RXFIFO_THR2_FULL        0x00000060
219 #define RXFIFO_THR2_HIGH        0x00000038
220 #define RXFIFO_THR2_OOB         0x0000004a
221 #define RXFIFO_THR2_NORMAL      0x00a0
222
223 /* PLA_RXFIFO_CTRL2 */
224 #define RXFIFO_THR3_FULL        0x00000078
225 #define RXFIFO_THR3_HIGH        0x00000048
226 #define RXFIFO_THR3_OOB         0x0000005a
227 #define RXFIFO_THR3_NORMAL      0x0110
228
229 /* PLA_TXFIFO_CTRL */
230 #define TXFIFO_THR_NORMAL       0x00400008
231 #define TXFIFO_THR_NORMAL2      0x01000008
232
233 /* PLA_DMY_REG0 */
234 #define ECM_ALDPS               0x0002
235
236 /* PLA_FMC */
237 #define FMC_FCR_MCU_EN          0x0001
238
239 /* PLA_EEEP_CR */
240 #define EEEP_CR_EEEP_TX         0x0002
241
242 /* PLA_WDT6_CTRL */
243 #define WDT6_SET_MODE           0x0010
244
245 /* PLA_TCR0 */
246 #define TCR0_TX_EMPTY           0x0800
247 #define TCR0_AUTO_FIFO          0x0080
248
249 /* PLA_TCR1 */
250 #define VERSION_MASK            0x7cf0
251
252 /* PLA_MTPS */
253 #define MTPS_JUMBO              (12 * 1024 / 64)
254 #define MTPS_DEFAULT            (6 * 1024 / 64)
255
256 /* PLA_RSTTALLY */
257 #define TALLY_RESET             0x0001
258
259 /* PLA_CR */
260 #define CR_RST                  0x10
261 #define CR_RE                   0x08
262 #define CR_TE                   0x04
263
264 /* PLA_CRWECR */
265 #define CRWECR_NORAML           0x00
266 #define CRWECR_CONFIG           0xc0
267
268 /* PLA_OOB_CTRL */
269 #define NOW_IS_OOB              0x80
270 #define TXFIFO_EMPTY            0x20
271 #define RXFIFO_EMPTY            0x10
272 #define LINK_LIST_READY         0x02
273 #define DIS_MCU_CLROOB          0x01
274 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
275
276 /* PLA_MISC_1 */
277 #define RXDY_GATED_EN           0x0008
278
279 /* PLA_SFF_STS_7 */
280 #define RE_INIT_LL              0x8000
281 #define MCU_BORW_EN             0x4000
282
283 /* PLA_CPCR */
284 #define CPCR_RX_VLAN            0x0040
285
286 /* PLA_CFG_WOL */
287 #define MAGIC_EN                0x0001
288
289 /* PLA_TEREDO_CFG */
290 #define TEREDO_SEL              0x8000
291 #define TEREDO_WAKE_MASK        0x7f00
292 #define TEREDO_RS_EVENT_MASK    0x00fe
293 #define OOB_TEREDO_EN           0x0001
294
295 /* PLA_BDC_CR */
296 #define ALDPS_PROXY_MODE        0x0001
297
298 /* PLA_EFUSE_CMD */
299 #define EFUSE_READ_CMD          BIT(15)
300 #define EFUSE_DATA_BIT16        BIT(7)
301
302 /* PLA_CONFIG34 */
303 #define LINK_ON_WAKE_EN         0x0010
304 #define LINK_OFF_WAKE_EN        0x0008
305
306 /* PLA_CONFIG6 */
307 #define LANWAKE_CLR_EN          BIT(0)
308
309 /* PLA_CONFIG5 */
310 #define BWF_EN                  0x0040
311 #define MWF_EN                  0x0020
312 #define UWF_EN                  0x0010
313 #define LAN_WAKE_EN             0x0002
314
315 /* PLA_LED_FEATURE */
316 #define LED_MODE_MASK           0x0700
317
318 /* PLA_PHY_PWR */
319 #define TX_10M_IDLE_EN          0x0080
320 #define PFM_PWM_SWITCH          0x0040
321 #define TEST_IO_OFF             BIT(4)
322
323 /* PLA_MAC_PWR_CTRL */
324 #define D3_CLK_GATED_EN         0x00004000
325 #define MCU_CLK_RATIO           0x07010f07
326 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
327 #define ALDPS_SPDWN_RATIO       0x0f87
328
329 /* PLA_MAC_PWR_CTRL2 */
330 #define EEE_SPDWN_RATIO         0x8007
331 #define MAC_CLK_SPDWN_EN        BIT(15)
332
333 /* PLA_MAC_PWR_CTRL3 */
334 #define PLA_MCU_SPDWN_EN        BIT(14)
335 #define PKT_AVAIL_SPDWN_EN      0x0100
336 #define SUSPEND_SPDWN_EN        0x0004
337 #define U1U2_SPDWN_EN           0x0002
338 #define L1_SPDWN_EN             0x0001
339
340 /* PLA_MAC_PWR_CTRL4 */
341 #define PWRSAVE_SPDWN_EN        0x1000
342 #define RXDV_SPDWN_EN           0x0800
343 #define TX10MIDLE_EN            0x0100
344 #define TP100_SPDWN_EN          0x0020
345 #define TP500_SPDWN_EN          0x0010
346 #define TP1000_SPDWN_EN         0x0008
347 #define EEE_SPDWN_EN            0x0001
348
349 /* PLA_GPHY_INTR_IMR */
350 #define GPHY_STS_MSK            0x0001
351 #define SPEED_DOWN_MSK          0x0002
352 #define SPDWN_RXDV_MSK          0x0004
353 #define SPDWN_LINKCHG_MSK       0x0008
354
355 /* PLA_PHYAR */
356 #define PHYAR_FLAG              0x80000000
357
358 /* PLA_EEE_CR */
359 #define EEE_RX_EN               0x0001
360 #define EEE_TX_EN               0x0002
361
362 /* PLA_BOOT_CTRL */
363 #define AUTOLOAD_DONE           0x0002
364
365 /* PLA_LWAKE_CTRL_REG */
366 #define LANWAKE_PIN             BIT(7)
367
368 /* PLA_SUSPEND_FLAG */
369 #define LINK_CHG_EVENT          BIT(0)
370
371 /* PLA_INDICATE_FALG */
372 #define UPCOMING_RUNTIME_D3     BIT(0)
373
374 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
375 #define DEBUG_OE                BIT(0)
376 #define DEBUG_LTSSM             0x0082
377
378 /* PLA_EXTRA_STATUS */
379 #define CUR_LINK_OK             BIT(15)
380 #define U3P3_CHECK_EN           BIT(7)  /* RTL_VER_05 only */
381 #define LINK_CHANGE_FLAG        BIT(8)
382 #define POLL_LINK_CHG           BIT(0)
383
384 /* USB_USB2PHY */
385 #define USB2PHY_SUSPEND         0x0001
386 #define USB2PHY_L1              0x0002
387
388 /* USB_SSPHYLINK1 */
389 #define DELAY_PHY_PWR_CHG       BIT(1)
390
391 /* USB_SSPHYLINK2 */
392 #define pwd_dn_scale_mask       0x3ffe
393 #define pwd_dn_scale(x)         ((x) << 1)
394
395 /* USB_CSR_DUMMY1 */
396 #define DYNAMIC_BURST           0x0001
397
398 /* USB_CSR_DUMMY2 */
399 #define EP4_FULL_FC             0x0001
400
401 /* USB_DEV_STAT */
402 #define STAT_SPEED_MASK         0x0006
403 #define STAT_SPEED_HIGH         0x0000
404 #define STAT_SPEED_FULL         0x0002
405
406 /* USB_FW_FIX_EN0 */
407 #define FW_FIX_SUSPEND          BIT(14)
408
409 /* USB_FW_FIX_EN1 */
410 #define FW_IP_RESET_EN          BIT(9)
411
412 /* USB_LPM_CONFIG */
413 #define LPM_U1U2_EN             BIT(0)
414
415 /* USB_TX_AGG */
416 #define TX_AGG_MAX_THRESHOLD    0x03
417
418 /* USB_RX_BUF_TH */
419 #define RX_THR_SUPPER           0x0c350180
420 #define RX_THR_HIGH             0x7a120180
421 #define RX_THR_SLOW             0xffff0180
422 #define RX_THR_B                0x00010001
423
424 /* USB_TX_DMA */
425 #define TEST_MODE_DISABLE       0x00000001
426 #define TX_SIZE_ADJUST1         0x00000100
427
428 /* USB_BMU_RESET */
429 #define BMU_RESET_EP_IN         0x01
430 #define BMU_RESET_EP_OUT        0x02
431
432 /* USB_UPT_RXDMA_OWN */
433 #define OWN_UPDATE              BIT(0)
434 #define OWN_CLEAR               BIT(1)
435
436 /* USB_FW_TASK */
437 #define FC_PATCH_TASK           BIT(1)
438
439 /* USB_UPS_CTRL */
440 #define POWER_CUT               0x0100
441
442 /* USB_PM_CTRL_STATUS */
443 #define RESUME_INDICATE         0x0001
444
445 /* USB_CSTMR */
446 #define FORCE_SUPER             BIT(0)
447
448 /* USB_FW_CTRL */
449 #define FLOW_CTRL_PATCH_OPT     BIT(1)
450
451 /* USB_FC_TIMER */
452 #define CTRL_TIMER_EN           BIT(15)
453
454 /* USB_USB_CTRL */
455 #define RX_AGG_DISABLE          0x0010
456 #define RX_ZERO_EN              0x0080
457
458 /* USB_U2P3_CTRL */
459 #define U2P3_ENABLE             0x0001
460
461 /* USB_POWER_CUT */
462 #define PWR_EN                  0x0001
463 #define PHASE2_EN               0x0008
464 #define UPS_EN                  BIT(4)
465 #define USP_PREWAKE             BIT(5)
466
467 /* USB_MISC_0 */
468 #define PCUT_STATUS             0x0001
469
470 /* USB_RX_EARLY_TIMEOUT */
471 #define COALESCE_SUPER           85000U
472 #define COALESCE_HIGH           250000U
473 #define COALESCE_SLOW           524280U
474
475 /* USB_WDT1_CTRL */
476 #define WTD1_EN                 BIT(0)
477
478 /* USB_WDT11_CTRL */
479 #define TIMER11_EN              0x0001
480
481 /* USB_LPM_CTRL */
482 /* bit 4 ~ 5: fifo empty boundary */
483 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
484 /* bit 2 ~ 3: LMP timer */
485 #define LPM_TIMER_MASK          0x0c
486 #define LPM_TIMER_500MS         0x04    /* 500 ms */
487 #define LPM_TIMER_500US         0x0c    /* 500 us */
488 #define ROK_EXIT_LPM            0x02
489
490 /* USB_AFE_CTRL2 */
491 #define SEN_VAL_MASK            0xf800
492 #define SEN_VAL_NORMAL          0xa000
493 #define SEL_RXIDLE              0x0100
494
495 /* USB_UPS_CFG */
496 #define SAW_CNT_1MS_MASK        0x0fff
497
498 /* USB_UPS_FLAGS */
499 #define UPS_FLAGS_R_TUNE                BIT(0)
500 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
501 #define UPS_FLAGS_250M_CKDIV            BIT(2)
502 #define UPS_FLAGS_EN_ALDPS              BIT(3)
503 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
504 #define ups_flags_speed(x)              ((x) << 16)
505 #define UPS_FLAGS_EN_EEE                BIT(20)
506 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
507 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
508 #define UPS_FLAGS_EEE_PLLOFF_100        BIT(23)
509 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
510 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
511 #define UPS_FLAGS_EN_GREEN              BIT(26)
512 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
513
514 enum spd_duplex {
515         NWAY_10M_HALF,
516         NWAY_10M_FULL,
517         NWAY_100M_HALF,
518         NWAY_100M_FULL,
519         NWAY_1000M_FULL,
520         FORCE_10M_HALF,
521         FORCE_10M_FULL,
522         FORCE_100M_HALF,
523         FORCE_100M_FULL,
524 };
525
526 /* OCP_ALDPS_CONFIG */
527 #define ENPWRSAVE               0x8000
528 #define ENPDNPS                 0x0200
529 #define LINKENA                 0x0100
530 #define DIS_SDSAVE              0x0010
531
532 /* OCP_PHY_STATUS */
533 #define PHY_STAT_MASK           0x0007
534 #define PHY_STAT_EXT_INIT       2
535 #define PHY_STAT_LAN_ON         3
536 #define PHY_STAT_PWRDN          5
537
538 /* OCP_NCTL_CFG */
539 #define PGA_RETURN_EN           BIT(1)
540
541 /* OCP_POWER_CFG */
542 #define EEE_CLKDIV_EN           0x8000
543 #define EN_ALDPS                0x0004
544 #define EN_10M_PLLOFF           0x0001
545
546 /* OCP_EEE_CONFIG1 */
547 #define RG_TXLPI_MSK_HFDUP      0x8000
548 #define RG_MATCLR_EN            0x4000
549 #define EEE_10_CAP              0x2000
550 #define EEE_NWAY_EN             0x1000
551 #define TX_QUIET_EN             0x0200
552 #define RX_QUIET_EN             0x0100
553 #define sd_rise_time_mask       0x0070
554 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
555 #define RG_RXLPI_MSK_HFDUP      0x0008
556 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
557
558 /* OCP_EEE_CONFIG2 */
559 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
560 #define RG_DACQUIET_EN          0x0400
561 #define RG_LDVQUIET_EN          0x0200
562 #define RG_CKRSEL               0x0020
563 #define RG_EEEPRG_EN            0x0010
564
565 /* OCP_EEE_CONFIG3 */
566 #define fast_snr_mask           0xff80
567 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
568 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
569 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
570
571 /* OCP_EEE_AR */
572 /* bit[15:14] function */
573 #define FUN_ADDR                0x0000
574 #define FUN_DATA                0x4000
575 /* bit[4:0] device addr */
576
577 /* OCP_EEE_CFG */
578 #define CTAP_SHORT_EN           0x0040
579 #define EEE10_EN                0x0010
580
581 /* OCP_DOWN_SPEED */
582 #define EN_EEE_CMODE            BIT(14)
583 #define EN_EEE_1000             BIT(13)
584 #define EN_EEE_100              BIT(12)
585 #define EN_10M_CLKDIV           BIT(11)
586 #define EN_10M_BGOFF            0x0080
587
588 /* OCP_PHY_STATE */
589 #define TXDIS_STATE             0x01
590 #define ABD_STATE               0x02
591
592 /* OCP_PHY_PATCH_STAT */
593 #define PATCH_READY             BIT(6)
594
595 /* OCP_PHY_PATCH_CMD */
596 #define PATCH_REQUEST           BIT(4)
597
598 /* OCP_PHY_LOCK */
599 #define PATCH_LOCK              BIT(0)
600
601 /* OCP_ADC_CFG */
602 #define CKADSEL_L               0x0100
603 #define ADC_EN                  0x0080
604 #define EN_EMI_L                0x0040
605
606 /* OCP_SYSCLK_CFG */
607 #define clk_div_expo(x)         (min(x, 5) << 8)
608
609 /* SRAM_GREEN_CFG */
610 #define GREEN_ETH_EN            BIT(15)
611 #define R_TUNE_EN               BIT(11)
612
613 /* SRAM_LPF_CFG */
614 #define LPF_AUTO_TUNE           0x8000
615
616 /* SRAM_10M_AMP1 */
617 #define GDAC_IB_UPALL           0x0008
618
619 /* SRAM_10M_AMP2 */
620 #define AMP_DN                  0x0200
621
622 /* SRAM_IMPEDANCE */
623 #define RX_DRIVING_MASK         0x6000
624
625 /* SRAM_PHY_LOCK */
626 #define PHY_PATCH_LOCK          0x0001
627
628 /* MAC PASSTHRU */
629 #define AD_MASK                 0xfee0
630 #define BND_MASK                0x0004
631 #define BD_MASK                 0x0001
632 #define EFUSE                   0xcfdb
633 #define PASS_THRU_MASK          0x1
634
635 #define BP4_SUPER_ONLY          0x1578  /* RTL_VER_04 only */
636
637 enum rtl_register_content {
638         _1000bps        = 0x10,
639         _100bps         = 0x08,
640         _10bps          = 0x04,
641         LINK_STATUS     = 0x02,
642         FULL_DUP        = 0x01,
643 };
644
645 #define RTL8152_MAX_TX          4
646 #define RTL8152_MAX_RX          10
647 #define INTBUFSIZE              2
648 #define TX_ALIGN                4
649 #define RX_ALIGN                8
650
651 #define RTL8152_RX_MAX_PENDING  4096
652 #define RTL8152_RXFG_HEADSZ     256
653
654 #define INTR_LINK               0x0004
655
656 #define RTL8152_REQT_READ       0xc0
657 #define RTL8152_REQT_WRITE      0x40
658 #define RTL8152_REQ_GET_REGS    0x05
659 #define RTL8152_REQ_SET_REGS    0x05
660
661 #define BYTE_EN_DWORD           0xff
662 #define BYTE_EN_WORD            0x33
663 #define BYTE_EN_BYTE            0x11
664 #define BYTE_EN_SIX_BYTES       0x3f
665 #define BYTE_EN_START_MASK      0x0f
666 #define BYTE_EN_END_MASK        0xf0
667
668 #define RTL8153_MAX_PACKET      9216 /* 9K */
669 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
670                                  ETH_FCS_LEN)
671 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
672 #define RTL8153_RMS             RTL8153_MAX_PACKET
673 #define RTL8152_TX_TIMEOUT      (5 * HZ)
674 #define RTL8152_NAPI_WEIGHT     64
675 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
676                                  sizeof(struct rx_desc) + RX_ALIGN)
677
678 /* rtl8152 flags */
679 enum rtl8152_flags {
680         RTL8152_UNPLUG = 0,
681         RTL8152_SET_RX_MODE,
682         WORK_ENABLE,
683         RTL8152_LINK_CHG,
684         SELECTIVE_SUSPEND,
685         PHY_RESET,
686         SCHEDULE_TASKLET,
687         GREEN_ETHERNET,
688         DELL_TB_RX_AGG_BUG,
689         LENOVO_MACPASSTHRU,
690 };
691
692 /* Define these values to match your device */
693 #define VENDOR_ID_REALTEK               0x0bda
694 #define VENDOR_ID_MICROSOFT             0x045e
695 #define VENDOR_ID_SAMSUNG               0x04e8
696 #define VENDOR_ID_LENOVO                0x17ef
697 #define VENDOR_ID_LINKSYS               0x13b1
698 #define VENDOR_ID_NVIDIA                0x0955
699 #define VENDOR_ID_TPLINK                0x2357
700
701 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2       0x3082
702 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2              0xa387
703
704 #define MCU_TYPE_PLA                    0x0100
705 #define MCU_TYPE_USB                    0x0000
706
707 struct tally_counter {
708         __le64  tx_packets;
709         __le64  rx_packets;
710         __le64  tx_errors;
711         __le32  rx_errors;
712         __le16  rx_missed;
713         __le16  align_errors;
714         __le32  tx_one_collision;
715         __le32  tx_multi_collision;
716         __le64  rx_unicast;
717         __le64  rx_broadcast;
718         __le32  rx_multicast;
719         __le16  tx_aborted;
720         __le16  tx_underrun;
721 };
722
723 struct rx_desc {
724         __le32 opts1;
725 #define RX_LEN_MASK                     0x7fff
726
727         __le32 opts2;
728 #define RD_UDP_CS                       BIT(23)
729 #define RD_TCP_CS                       BIT(22)
730 #define RD_IPV6_CS                      BIT(20)
731 #define RD_IPV4_CS                      BIT(19)
732
733         __le32 opts3;
734 #define IPF                             BIT(23) /* IP checksum fail */
735 #define UDPF                            BIT(22) /* UDP checksum fail */
736 #define TCPF                            BIT(21) /* TCP checksum fail */
737 #define RX_VLAN_TAG                     BIT(16)
738
739         __le32 opts4;
740         __le32 opts5;
741         __le32 opts6;
742 };
743
744 struct tx_desc {
745         __le32 opts1;
746 #define TX_FS                   BIT(31) /* First segment of a packet */
747 #define TX_LS                   BIT(30) /* Final segment of a packet */
748 #define GTSENDV4                BIT(28)
749 #define GTSENDV6                BIT(27)
750 #define GTTCPHO_SHIFT           18
751 #define GTTCPHO_MAX             0x7fU
752 #define TX_LEN_MAX              0x3ffffU
753
754         __le32 opts2;
755 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
756 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
757 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
758 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
759 #define MSS_SHIFT               17
760 #define MSS_MAX                 0x7ffU
761 #define TCPHO_SHIFT             17
762 #define TCPHO_MAX               0x7ffU
763 #define TX_VLAN_TAG             BIT(16)
764 };
765
766 struct r8152;
767
768 struct rx_agg {
769         struct list_head list, info_list;
770         struct urb *urb;
771         struct r8152 *context;
772         struct page *page;
773         void *buffer;
774 };
775
776 struct tx_agg {
777         struct list_head list;
778         struct urb *urb;
779         struct r8152 *context;
780         void *buffer;
781         void *head;
782         u32 skb_num;
783         u32 skb_len;
784 };
785
786 struct r8152 {
787         unsigned long flags;
788         struct usb_device *udev;
789         struct napi_struct napi;
790         struct usb_interface *intf;
791         struct net_device *netdev;
792         struct urb *intr_urb;
793         struct tx_agg tx_info[RTL8152_MAX_TX];
794         struct list_head rx_info, rx_used;
795         struct list_head rx_done, tx_free;
796         struct sk_buff_head tx_queue, rx_queue;
797         spinlock_t rx_lock, tx_lock;
798         struct delayed_work schedule, hw_phy_work;
799         struct mii_if_info mii;
800         struct mutex control;   /* use for hw setting */
801 #ifdef CONFIG_PM_SLEEP
802         struct notifier_block pm_notifier;
803 #endif
804         struct tasklet_struct tx_tl;
805
806         struct rtl_ops {
807                 void (*init)(struct r8152 *tp);
808                 int (*enable)(struct r8152 *tp);
809                 void (*disable)(struct r8152 *tp);
810                 void (*up)(struct r8152 *tp);
811                 void (*down)(struct r8152 *tp);
812                 void (*unload)(struct r8152 *tp);
813                 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
814                 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
815                 bool (*in_nway)(struct r8152 *tp);
816                 void (*hw_phy_cfg)(struct r8152 *tp);
817                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
818         } rtl_ops;
819
820         struct ups_info {
821                 u32 _10m_ckdiv:1;
822                 u32 _250m_ckdiv:1;
823                 u32 aldps:1;
824                 u32 lite_mode:2;
825                 u32 speed_duplex:4;
826                 u32 eee:1;
827                 u32 eee_lite:1;
828                 u32 eee_ckdiv:1;
829                 u32 eee_plloff_100:1;
830                 u32 eee_plloff_giga:1;
831                 u32 eee_cmod_lv:1;
832                 u32 green:1;
833                 u32 flow_control:1;
834                 u32 ctap_short_off:1;
835         } ups_info;
836
837 #define RTL_VER_SIZE            32
838
839         struct rtl_fw {
840                 const char *fw_name;
841                 const struct firmware *fw;
842
843                 char version[RTL_VER_SIZE];
844                 int (*pre_fw)(struct r8152 *tp);
845                 int (*post_fw)(struct r8152 *tp);
846
847                 bool retry;
848         } rtl_fw;
849
850         atomic_t rx_count;
851
852         bool eee_en;
853         int intr_interval;
854         u32 saved_wolopts;
855         u32 msg_enable;
856         u32 tx_qlen;
857         u32 coalesce;
858         u32 advertising;
859         u32 rx_buf_sz;
860         u32 rx_copybreak;
861         u32 rx_pending;
862
863         u16 ocp_base;
864         u16 speed;
865         u16 eee_adv;
866         u8 *intr_buff;
867         u8 version;
868         u8 duplex;
869         u8 autoneg;
870 };
871
872 /**
873  * struct fw_block - block type and total length
874  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
875  *      RTL_FW_USB and so on.
876  * @length: total length of the current block.
877  */
878 struct fw_block {
879         __le32 type;
880         __le32 length;
881 } __packed;
882
883 /**
884  * struct fw_header - header of the firmware file
885  * @checksum: checksum of sha256 which is calculated from the whole file
886  *      except the checksum field of the file. That is, calculate sha256
887  *      from the version field to the end of the file.
888  * @version: version of this firmware.
889  * @blocks: the first firmware block of the file
890  */
891 struct fw_header {
892         u8 checksum[32];
893         char version[RTL_VER_SIZE];
894         struct fw_block blocks[];
895 } __packed;
896
897 /**
898  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
899  *      The layout of the firmware block is:
900  *      <struct fw_mac> + <info> + <firmware data>.
901  * @fw_offset: offset of the firmware binary data. The start address of
902  *      the data would be the address of struct fw_mac + @fw_offset.
903  * @fw_reg: the register to load the firmware. Depends on chip.
904  * @bp_ba_addr: the register to write break point base address. Depends on
905  *      chip.
906  * @bp_ba_value: break point base address. Depends on chip.
907  * @bp_en_addr: the register to write break point enabled mask. Depends
908  *      on chip.
909  * @bp_en_value: break point enabled mask. Depends on the firmware.
910  * @bp_start: the start register of break points. Depends on chip.
911  * @bp_num: the break point number which needs to be set for this firmware.
912  *      Depends on the firmware.
913  * @bp: break points. Depends on firmware.
914  * @fw_ver_reg: the register to store the fw version.
915  * @fw_ver_data: the firmware version of the current type.
916  * @info: additional information for debugging, and is followed by the
917  *      binary data of firmware.
918  */
919 struct fw_mac {
920         struct fw_block blk_hdr;
921         __le16 fw_offset;
922         __le16 fw_reg;
923         __le16 bp_ba_addr;
924         __le16 bp_ba_value;
925         __le16 bp_en_addr;
926         __le16 bp_en_value;
927         __le16 bp_start;
928         __le16 bp_num;
929         __le16 bp[16]; /* any value determined by firmware */
930         __le32 reserved;
931         __le16 fw_ver_reg;
932         u8 fw_ver_data;
933         char info[];
934 } __packed;
935
936 /**
937  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
938  *      This is used to set patch key when loading the firmware of PHY.
939  * @key_reg: the register to write the patch key.
940  * @key_data: patch key.
941  */
942 struct fw_phy_patch_key {
943         struct fw_block blk_hdr;
944         __le16 key_reg;
945         __le16 key_data;
946         __le32 reserved;
947 } __packed;
948
949 /**
950  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
951  *      The layout of the firmware block is:
952  *      <struct fw_phy_nc> + <info> + <firmware data>.
953  * @fw_offset: offset of the firmware binary data. The start address of
954  *      the data would be the address of struct fw_phy_nc + @fw_offset.
955  * @fw_reg: the register to load the firmware. Depends on chip.
956  * @ba_reg: the register to write the base address. Depends on chip.
957  * @ba_data: base address. Depends on chip.
958  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
959  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
960  * @mode_reg: the regitster of switching the mode.
961  * @mod_pre: the mode needing to be set before loading the firmware.
962  * @mod_post: the mode to be set when finishing to load the firmware.
963  * @bp_start: the start register of break points. Depends on chip.
964  * @bp_num: the break point number which needs to be set for this firmware.
965  *      Depends on the firmware.
966  * @bp: break points. Depends on firmware.
967  * @info: additional information for debugging, and is followed by the
968  *      binary data of firmware.
969  */
970 struct fw_phy_nc {
971         struct fw_block blk_hdr;
972         __le16 fw_offset;
973         __le16 fw_reg;
974         __le16 ba_reg;
975         __le16 ba_data;
976         __le16 patch_en_addr;
977         __le16 patch_en_value;
978         __le16 mode_reg;
979         __le16 mode_pre;
980         __le16 mode_post;
981         __le16 reserved;
982         __le16 bp_start;
983         __le16 bp_num;
984         __le16 bp[4];
985         char info[];
986 } __packed;
987
988 enum rtl_fw_type {
989         RTL_FW_END = 0,
990         RTL_FW_PLA,
991         RTL_FW_USB,
992         RTL_FW_PHY_START,
993         RTL_FW_PHY_STOP,
994         RTL_FW_PHY_NC,
995 };
996
997 enum rtl_version {
998         RTL_VER_UNKNOWN = 0,
999         RTL_VER_01,
1000         RTL_VER_02,
1001         RTL_VER_03,
1002         RTL_VER_04,
1003         RTL_VER_05,
1004         RTL_VER_06,
1005         RTL_VER_07,
1006         RTL_VER_08,
1007         RTL_VER_09,
1008         RTL_VER_MAX
1009 };
1010
1011 enum tx_csum_stat {
1012         TX_CSUM_SUCCESS = 0,
1013         TX_CSUM_TSO,
1014         TX_CSUM_NONE
1015 };
1016
1017 #define RTL_ADVERTISED_10_HALF                  BIT(0)
1018 #define RTL_ADVERTISED_10_FULL                  BIT(1)
1019 #define RTL_ADVERTISED_100_HALF                 BIT(2)
1020 #define RTL_ADVERTISED_100_FULL                 BIT(3)
1021 #define RTL_ADVERTISED_1000_HALF                BIT(4)
1022 #define RTL_ADVERTISED_1000_FULL                BIT(5)
1023
1024 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1025  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1026  */
1027 static const int multicast_filter_limit = 32;
1028 static unsigned int agg_buf_sz = 16384;
1029
1030 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
1031                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
1032
1033 static
1034 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1035 {
1036         int ret;
1037         void *tmp;
1038
1039         tmp = kmalloc(size, GFP_KERNEL);
1040         if (!tmp)
1041                 return -ENOMEM;
1042
1043         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1044                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1045                               value, index, tmp, size, USB_CTRL_GET_TIMEOUT);
1046         if (ret < 0)
1047                 memset(data, 0xff, size);
1048         else
1049                 memcpy(data, tmp, size);
1050
1051         kfree(tmp);
1052
1053         return ret;
1054 }
1055
1056 static
1057 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1058 {
1059         int ret;
1060         void *tmp;
1061
1062         tmp = kmemdup(data, size, GFP_KERNEL);
1063         if (!tmp)
1064                 return -ENOMEM;
1065
1066         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1067                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1068                               value, index, tmp, size, USB_CTRL_SET_TIMEOUT);
1069
1070         kfree(tmp);
1071
1072         return ret;
1073 }
1074
1075 static void rtl_set_unplug(struct r8152 *tp)
1076 {
1077         if (tp->udev->state == USB_STATE_NOTATTACHED) {
1078                 set_bit(RTL8152_UNPLUG, &tp->flags);
1079                 smp_mb__after_atomic();
1080         }
1081 }
1082
1083 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1084                             void *data, u16 type)
1085 {
1086         u16 limit = 64;
1087         int ret = 0;
1088
1089         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1090                 return -ENODEV;
1091
1092         /* both size and indix must be 4 bytes align */
1093         if ((size & 3) || !size || (index & 3) || !data)
1094                 return -EPERM;
1095
1096         if ((u32)index + (u32)size > 0xffff)
1097                 return -EPERM;
1098
1099         while (size) {
1100                 if (size > limit) {
1101                         ret = get_registers(tp, index, type, limit, data);
1102                         if (ret < 0)
1103                                 break;
1104
1105                         index += limit;
1106                         data += limit;
1107                         size -= limit;
1108                 } else {
1109                         ret = get_registers(tp, index, type, size, data);
1110                         if (ret < 0)
1111                                 break;
1112
1113                         index += size;
1114                         data += size;
1115                         size = 0;
1116                         break;
1117                 }
1118         }
1119
1120         if (ret == -ENODEV)
1121                 rtl_set_unplug(tp);
1122
1123         return ret;
1124 }
1125
1126 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1127                              u16 size, void *data, u16 type)
1128 {
1129         int ret;
1130         u16 byteen_start, byteen_end, byen;
1131         u16 limit = 512;
1132
1133         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1134                 return -ENODEV;
1135
1136         /* both size and indix must be 4 bytes align */
1137         if ((size & 3) || !size || (index & 3) || !data)
1138                 return -EPERM;
1139
1140         if ((u32)index + (u32)size > 0xffff)
1141                 return -EPERM;
1142
1143         byteen_start = byteen & BYTE_EN_START_MASK;
1144         byteen_end = byteen & BYTE_EN_END_MASK;
1145
1146         byen = byteen_start | (byteen_start << 4);
1147         ret = set_registers(tp, index, type | byen, 4, data);
1148         if (ret < 0)
1149                 goto error1;
1150
1151         index += 4;
1152         data += 4;
1153         size -= 4;
1154
1155         if (size) {
1156                 size -= 4;
1157
1158                 while (size) {
1159                         if (size > limit) {
1160                                 ret = set_registers(tp, index,
1161                                                     type | BYTE_EN_DWORD,
1162                                                     limit, data);
1163                                 if (ret < 0)
1164                                         goto error1;
1165
1166                                 index += limit;
1167                                 data += limit;
1168                                 size -= limit;
1169                         } else {
1170                                 ret = set_registers(tp, index,
1171                                                     type | BYTE_EN_DWORD,
1172                                                     size, data);
1173                                 if (ret < 0)
1174                                         goto error1;
1175
1176                                 index += size;
1177                                 data += size;
1178                                 size = 0;
1179                                 break;
1180                         }
1181                 }
1182
1183                 byen = byteen_end | (byteen_end >> 4);
1184                 ret = set_registers(tp, index, type | byen, 4, data);
1185                 if (ret < 0)
1186                         goto error1;
1187         }
1188
1189 error1:
1190         if (ret == -ENODEV)
1191                 rtl_set_unplug(tp);
1192
1193         return ret;
1194 }
1195
1196 static inline
1197 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1198 {
1199         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1200 }
1201
1202 static inline
1203 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1204 {
1205         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1206 }
1207
1208 static inline
1209 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1210 {
1211         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1212 }
1213
1214 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1215 {
1216         __le32 data;
1217
1218         generic_ocp_read(tp, index, sizeof(data), &data, type);
1219
1220         return __le32_to_cpu(data);
1221 }
1222
1223 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1224 {
1225         __le32 tmp = __cpu_to_le32(data);
1226
1227         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1228 }
1229
1230 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1231 {
1232         u32 data;
1233         __le32 tmp;
1234         u16 byen = BYTE_EN_WORD;
1235         u8 shift = index & 2;
1236
1237         index &= ~3;
1238         byen <<= shift;
1239
1240         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1241
1242         data = __le32_to_cpu(tmp);
1243         data >>= (shift * 8);
1244         data &= 0xffff;
1245
1246         return (u16)data;
1247 }
1248
1249 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1250 {
1251         u32 mask = 0xffff;
1252         __le32 tmp;
1253         u16 byen = BYTE_EN_WORD;
1254         u8 shift = index & 2;
1255
1256         data &= mask;
1257
1258         if (index & 2) {
1259                 byen <<= shift;
1260                 mask <<= (shift * 8);
1261                 data <<= (shift * 8);
1262                 index &= ~3;
1263         }
1264
1265         tmp = __cpu_to_le32(data);
1266
1267         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1268 }
1269
1270 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1271 {
1272         u32 data;
1273         __le32 tmp;
1274         u8 shift = index & 3;
1275
1276         index &= ~3;
1277
1278         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1279
1280         data = __le32_to_cpu(tmp);
1281         data >>= (shift * 8);
1282         data &= 0xff;
1283
1284         return (u8)data;
1285 }
1286
1287 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1288 {
1289         u32 mask = 0xff;
1290         __le32 tmp;
1291         u16 byen = BYTE_EN_BYTE;
1292         u8 shift = index & 3;
1293
1294         data &= mask;
1295
1296         if (index & 3) {
1297                 byen <<= shift;
1298                 mask <<= (shift * 8);
1299                 data <<= (shift * 8);
1300                 index &= ~3;
1301         }
1302
1303         tmp = __cpu_to_le32(data);
1304
1305         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1306 }
1307
1308 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1309 {
1310         u16 ocp_base, ocp_index;
1311
1312         ocp_base = addr & 0xf000;
1313         if (ocp_base != tp->ocp_base) {
1314                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1315                 tp->ocp_base = ocp_base;
1316         }
1317
1318         ocp_index = (addr & 0x0fff) | 0xb000;
1319         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1320 }
1321
1322 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1323 {
1324         u16 ocp_base, ocp_index;
1325
1326         ocp_base = addr & 0xf000;
1327         if (ocp_base != tp->ocp_base) {
1328                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1329                 tp->ocp_base = ocp_base;
1330         }
1331
1332         ocp_index = (addr & 0x0fff) | 0xb000;
1333         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1334 }
1335
1336 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1337 {
1338         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1339 }
1340
1341 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1342 {
1343         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1344 }
1345
1346 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1347 {
1348         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1349         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1350 }
1351
1352 static u16 sram_read(struct r8152 *tp, u16 addr)
1353 {
1354         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1355         return ocp_reg_read(tp, OCP_SRAM_DATA);
1356 }
1357
1358 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1359 {
1360         struct r8152 *tp = netdev_priv(netdev);
1361         int ret;
1362
1363         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1364                 return -ENODEV;
1365
1366         if (phy_id != R8152_PHY_ID)
1367                 return -EINVAL;
1368
1369         ret = r8152_mdio_read(tp, reg);
1370
1371         return ret;
1372 }
1373
1374 static
1375 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1376 {
1377         struct r8152 *tp = netdev_priv(netdev);
1378
1379         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1380                 return;
1381
1382         if (phy_id != R8152_PHY_ID)
1383                 return;
1384
1385         r8152_mdio_write(tp, reg, val);
1386 }
1387
1388 static int
1389 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1390
1391 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1392 {
1393         struct r8152 *tp = netdev_priv(netdev);
1394         struct sockaddr *addr = p;
1395         int ret = -EADDRNOTAVAIL;
1396
1397         if (!is_valid_ether_addr(addr->sa_data))
1398                 goto out1;
1399
1400         ret = usb_autopm_get_interface(tp->intf);
1401         if (ret < 0)
1402                 goto out1;
1403
1404         mutex_lock(&tp->control);
1405
1406         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1407
1408         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1409         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1410         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1411
1412         mutex_unlock(&tp->control);
1413
1414         usb_autopm_put_interface(tp->intf);
1415 out1:
1416         return ret;
1417 }
1418
1419 /* Devices containing proper chips can support a persistent
1420  * host system provided MAC address.
1421  * Examples of this are Dell TB15 and Dell WD15 docks
1422  */
1423 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1424 {
1425         acpi_status status;
1426         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1427         union acpi_object *obj;
1428         int ret = -EINVAL;
1429         u32 ocp_data;
1430         unsigned char buf[6];
1431         char *mac_obj_name;
1432         acpi_object_type mac_obj_type;
1433         int mac_strlen;
1434
1435         if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1436                 mac_obj_name = "\\MACA";
1437                 mac_obj_type = ACPI_TYPE_STRING;
1438                 mac_strlen = 0x16;
1439         } else {
1440                 /* test for -AD variant of RTL8153 */
1441                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1442                 if ((ocp_data & AD_MASK) == 0x1000) {
1443                         /* test for MAC address pass-through bit */
1444                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1445                         if ((ocp_data & PASS_THRU_MASK) != 1) {
1446                                 netif_dbg(tp, probe, tp->netdev,
1447                                                 "No efuse for RTL8153-AD MAC pass through\n");
1448                                 return -ENODEV;
1449                         }
1450                 } else {
1451                         /* test for RTL8153-BND and RTL8153-BD */
1452                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1453                         if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1454                                 netif_dbg(tp, probe, tp->netdev,
1455                                                 "Invalid variant for MAC pass through\n");
1456                                 return -ENODEV;
1457                         }
1458                 }
1459
1460                 mac_obj_name = "\\_SB.AMAC";
1461                 mac_obj_type = ACPI_TYPE_BUFFER;
1462                 mac_strlen = 0x17;
1463         }
1464
1465         /* returns _AUXMAC_#AABBCCDDEEFF# */
1466         status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1467         obj = (union acpi_object *)buffer.pointer;
1468         if (!ACPI_SUCCESS(status))
1469                 return -ENODEV;
1470         if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1471                 netif_warn(tp, probe, tp->netdev,
1472                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1473                            obj->type, obj->string.length);
1474                 goto amacout;
1475         }
1476
1477         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1478             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1479                 netif_warn(tp, probe, tp->netdev,
1480                            "Invalid header when reading pass-thru MAC addr\n");
1481                 goto amacout;
1482         }
1483         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1484         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1485                 netif_warn(tp, probe, tp->netdev,
1486                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1487                            ret, buf);
1488                 ret = -EINVAL;
1489                 goto amacout;
1490         }
1491         memcpy(sa->sa_data, buf, 6);
1492         netif_info(tp, probe, tp->netdev,
1493                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1494
1495 amacout:
1496         kfree(obj);
1497         return ret;
1498 }
1499
1500 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1501 {
1502         struct net_device *dev = tp->netdev;
1503         int ret;
1504
1505         sa->sa_family = dev->type;
1506
1507         ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1508         if (ret < 0) {
1509                 if (tp->version == RTL_VER_01) {
1510                         ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1511                 } else {
1512                         /* if device doesn't support MAC pass through this will
1513                          * be expected to be non-zero
1514                          */
1515                         ret = vendor_mac_passthru_addr_read(tp, sa);
1516                         if (ret < 0)
1517                                 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1518                                                    sa->sa_data);
1519                 }
1520         }
1521
1522         if (ret < 0) {
1523                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1524         } else if (!is_valid_ether_addr(sa->sa_data)) {
1525                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1526                           sa->sa_data);
1527                 eth_hw_addr_random(dev);
1528                 ether_addr_copy(sa->sa_data, dev->dev_addr);
1529                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1530                            sa->sa_data);
1531                 return 0;
1532         }
1533
1534         return ret;
1535 }
1536
1537 static int set_ethernet_addr(struct r8152 *tp)
1538 {
1539         struct net_device *dev = tp->netdev;
1540         struct sockaddr sa;
1541         int ret;
1542
1543         ret = determine_ethernet_addr(tp, &sa);
1544         if (ret < 0)
1545                 return ret;
1546
1547         if (tp->version == RTL_VER_01)
1548                 ether_addr_copy(dev->dev_addr, sa.sa_data);
1549         else
1550                 ret = rtl8152_set_mac_address(dev, &sa);
1551
1552         return ret;
1553 }
1554
1555 static void read_bulk_callback(struct urb *urb)
1556 {
1557         struct net_device *netdev;
1558         int status = urb->status;
1559         struct rx_agg *agg;
1560         struct r8152 *tp;
1561         unsigned long flags;
1562
1563         agg = urb->context;
1564         if (!agg)
1565                 return;
1566
1567         tp = agg->context;
1568         if (!tp)
1569                 return;
1570
1571         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1572                 return;
1573
1574         if (!test_bit(WORK_ENABLE, &tp->flags))
1575                 return;
1576
1577         netdev = tp->netdev;
1578
1579         /* When link down, the driver would cancel all bulks. */
1580         /* This avoid the re-submitting bulk */
1581         if (!netif_carrier_ok(netdev))
1582                 return;
1583
1584         usb_mark_last_busy(tp->udev);
1585
1586         switch (status) {
1587         case 0:
1588                 if (urb->actual_length < ETH_ZLEN)
1589                         break;
1590
1591                 spin_lock_irqsave(&tp->rx_lock, flags);
1592                 list_add_tail(&agg->list, &tp->rx_done);
1593                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1594                 napi_schedule(&tp->napi);
1595                 return;
1596         case -ESHUTDOWN:
1597                 rtl_set_unplug(tp);
1598                 netif_device_detach(tp->netdev);
1599                 return;
1600         case -ENOENT:
1601                 return; /* the urb is in unlink state */
1602         case -ETIME:
1603                 if (net_ratelimit())
1604                         netdev_warn(netdev, "maybe reset is needed?\n");
1605                 break;
1606         default:
1607                 if (net_ratelimit())
1608                         netdev_warn(netdev, "Rx status %d\n", status);
1609                 break;
1610         }
1611
1612         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1613 }
1614
1615 static void write_bulk_callback(struct urb *urb)
1616 {
1617         struct net_device_stats *stats;
1618         struct net_device *netdev;
1619         struct tx_agg *agg;
1620         struct r8152 *tp;
1621         unsigned long flags;
1622         int status = urb->status;
1623
1624         agg = urb->context;
1625         if (!agg)
1626                 return;
1627
1628         tp = agg->context;
1629         if (!tp)
1630                 return;
1631
1632         netdev = tp->netdev;
1633         stats = &netdev->stats;
1634         if (status) {
1635                 if (net_ratelimit())
1636                         netdev_warn(netdev, "Tx status %d\n", status);
1637                 stats->tx_errors += agg->skb_num;
1638         } else {
1639                 stats->tx_packets += agg->skb_num;
1640                 stats->tx_bytes += agg->skb_len;
1641         }
1642
1643         spin_lock_irqsave(&tp->tx_lock, flags);
1644         list_add_tail(&agg->list, &tp->tx_free);
1645         spin_unlock_irqrestore(&tp->tx_lock, flags);
1646
1647         usb_autopm_put_interface_async(tp->intf);
1648
1649         if (!netif_carrier_ok(netdev))
1650                 return;
1651
1652         if (!test_bit(WORK_ENABLE, &tp->flags))
1653                 return;
1654
1655         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1656                 return;
1657
1658         if (!skb_queue_empty(&tp->tx_queue))
1659                 tasklet_schedule(&tp->tx_tl);
1660 }
1661
1662 static void intr_callback(struct urb *urb)
1663 {
1664         struct r8152 *tp;
1665         __le16 *d;
1666         int status = urb->status;
1667         int res;
1668
1669         tp = urb->context;
1670         if (!tp)
1671                 return;
1672
1673         if (!test_bit(WORK_ENABLE, &tp->flags))
1674                 return;
1675
1676         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1677                 return;
1678
1679         switch (status) {
1680         case 0:                 /* success */
1681                 break;
1682         case -ECONNRESET:       /* unlink */
1683         case -ESHUTDOWN:
1684                 netif_device_detach(tp->netdev);
1685                 fallthrough;
1686         case -ENOENT:
1687         case -EPROTO:
1688                 netif_info(tp, intr, tp->netdev,
1689                            "Stop submitting intr, status %d\n", status);
1690                 return;
1691         case -EOVERFLOW:
1692                 if (net_ratelimit())
1693                         netif_info(tp, intr, tp->netdev,
1694                                    "intr status -EOVERFLOW\n");
1695                 goto resubmit;
1696         /* -EPIPE:  should clear the halt */
1697         default:
1698                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1699                 goto resubmit;
1700         }
1701
1702         d = urb->transfer_buffer;
1703         if (INTR_LINK & __le16_to_cpu(d[0])) {
1704                 if (!netif_carrier_ok(tp->netdev)) {
1705                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1706                         schedule_delayed_work(&tp->schedule, 0);
1707                 }
1708         } else {
1709                 if (netif_carrier_ok(tp->netdev)) {
1710                         netif_stop_queue(tp->netdev);
1711                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1712                         schedule_delayed_work(&tp->schedule, 0);
1713                 }
1714         }
1715
1716 resubmit:
1717         res = usb_submit_urb(urb, GFP_ATOMIC);
1718         if (res == -ENODEV) {
1719                 rtl_set_unplug(tp);
1720                 netif_device_detach(tp->netdev);
1721         } else if (res) {
1722                 netif_err(tp, intr, tp->netdev,
1723                           "can't resubmit intr, status %d\n", res);
1724         }
1725 }
1726
1727 static inline void *rx_agg_align(void *data)
1728 {
1729         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1730 }
1731
1732 static inline void *tx_agg_align(void *data)
1733 {
1734         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1735 }
1736
1737 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1738 {
1739         list_del(&agg->info_list);
1740
1741         usb_free_urb(agg->urb);
1742         put_page(agg->page);
1743         kfree(agg);
1744
1745         atomic_dec(&tp->rx_count);
1746 }
1747
1748 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1749 {
1750         struct net_device *netdev = tp->netdev;
1751         int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1752         unsigned int order = get_order(tp->rx_buf_sz);
1753         struct rx_agg *rx_agg;
1754         unsigned long flags;
1755
1756         rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1757         if (!rx_agg)
1758                 return NULL;
1759
1760         rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1761         if (!rx_agg->page)
1762                 goto free_rx;
1763
1764         rx_agg->buffer = page_address(rx_agg->page);
1765
1766         rx_agg->urb = usb_alloc_urb(0, mflags);
1767         if (!rx_agg->urb)
1768                 goto free_buf;
1769
1770         rx_agg->context = tp;
1771
1772         INIT_LIST_HEAD(&rx_agg->list);
1773         INIT_LIST_HEAD(&rx_agg->info_list);
1774         spin_lock_irqsave(&tp->rx_lock, flags);
1775         list_add_tail(&rx_agg->info_list, &tp->rx_info);
1776         spin_unlock_irqrestore(&tp->rx_lock, flags);
1777
1778         atomic_inc(&tp->rx_count);
1779
1780         return rx_agg;
1781
1782 free_buf:
1783         __free_pages(rx_agg->page, order);
1784 free_rx:
1785         kfree(rx_agg);
1786         return NULL;
1787 }
1788
1789 static void free_all_mem(struct r8152 *tp)
1790 {
1791         struct rx_agg *agg, *agg_next;
1792         unsigned long flags;
1793         int i;
1794
1795         spin_lock_irqsave(&tp->rx_lock, flags);
1796
1797         list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1798                 free_rx_agg(tp, agg);
1799
1800         spin_unlock_irqrestore(&tp->rx_lock, flags);
1801
1802         WARN_ON(atomic_read(&tp->rx_count));
1803
1804         for (i = 0; i < RTL8152_MAX_TX; i++) {
1805                 usb_free_urb(tp->tx_info[i].urb);
1806                 tp->tx_info[i].urb = NULL;
1807
1808                 kfree(tp->tx_info[i].buffer);
1809                 tp->tx_info[i].buffer = NULL;
1810                 tp->tx_info[i].head = NULL;
1811         }
1812
1813         usb_free_urb(tp->intr_urb);
1814         tp->intr_urb = NULL;
1815
1816         kfree(tp->intr_buff);
1817         tp->intr_buff = NULL;
1818 }
1819
1820 static int alloc_all_mem(struct r8152 *tp)
1821 {
1822         struct net_device *netdev = tp->netdev;
1823         struct usb_interface *intf = tp->intf;
1824         struct usb_host_interface *alt = intf->cur_altsetting;
1825         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1826         int node, i;
1827
1828         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1829
1830         spin_lock_init(&tp->rx_lock);
1831         spin_lock_init(&tp->tx_lock);
1832         INIT_LIST_HEAD(&tp->rx_info);
1833         INIT_LIST_HEAD(&tp->tx_free);
1834         INIT_LIST_HEAD(&tp->rx_done);
1835         skb_queue_head_init(&tp->tx_queue);
1836         skb_queue_head_init(&tp->rx_queue);
1837         atomic_set(&tp->rx_count, 0);
1838
1839         for (i = 0; i < RTL8152_MAX_RX; i++) {
1840                 if (!alloc_rx_agg(tp, GFP_KERNEL))
1841                         goto err1;
1842         }
1843
1844         for (i = 0; i < RTL8152_MAX_TX; i++) {
1845                 struct urb *urb;
1846                 u8 *buf;
1847
1848                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1849                 if (!buf)
1850                         goto err1;
1851
1852                 if (buf != tx_agg_align(buf)) {
1853                         kfree(buf);
1854                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1855                                            node);
1856                         if (!buf)
1857                                 goto err1;
1858                 }
1859
1860                 urb = usb_alloc_urb(0, GFP_KERNEL);
1861                 if (!urb) {
1862                         kfree(buf);
1863                         goto err1;
1864                 }
1865
1866                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1867                 tp->tx_info[i].context = tp;
1868                 tp->tx_info[i].urb = urb;
1869                 tp->tx_info[i].buffer = buf;
1870                 tp->tx_info[i].head = tx_agg_align(buf);
1871
1872                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1873         }
1874
1875         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1876         if (!tp->intr_urb)
1877                 goto err1;
1878
1879         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1880         if (!tp->intr_buff)
1881                 goto err1;
1882
1883         tp->intr_interval = (int)ep_intr->desc.bInterval;
1884         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1885                          tp->intr_buff, INTBUFSIZE, intr_callback,
1886                          tp, tp->intr_interval);
1887
1888         return 0;
1889
1890 err1:
1891         free_all_mem(tp);
1892         return -ENOMEM;
1893 }
1894
1895 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1896 {
1897         struct tx_agg *agg = NULL;
1898         unsigned long flags;
1899
1900         if (list_empty(&tp->tx_free))
1901                 return NULL;
1902
1903         spin_lock_irqsave(&tp->tx_lock, flags);
1904         if (!list_empty(&tp->tx_free)) {
1905                 struct list_head *cursor;
1906
1907                 cursor = tp->tx_free.next;
1908                 list_del_init(cursor);
1909                 agg = list_entry(cursor, struct tx_agg, list);
1910         }
1911         spin_unlock_irqrestore(&tp->tx_lock, flags);
1912
1913         return agg;
1914 }
1915
1916 /* r8152_csum_workaround()
1917  * The hw limits the value of the transport offset. When the offset is out of
1918  * range, calculate the checksum by sw.
1919  */
1920 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1921                                   struct sk_buff_head *list)
1922 {
1923         if (skb_shinfo(skb)->gso_size) {
1924                 netdev_features_t features = tp->netdev->features;
1925                 struct sk_buff *segs, *seg, *next;
1926                 struct sk_buff_head seg_list;
1927
1928                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1929                 segs = skb_gso_segment(skb, features);
1930                 if (IS_ERR(segs) || !segs)
1931                         goto drop;
1932
1933                 __skb_queue_head_init(&seg_list);
1934
1935                 skb_list_walk_safe(segs, seg, next) {
1936                         skb_mark_not_on_list(seg);
1937                         __skb_queue_tail(&seg_list, seg);
1938                 }
1939
1940                 skb_queue_splice(&seg_list, list);
1941                 dev_kfree_skb(skb);
1942         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1943                 if (skb_checksum_help(skb) < 0)
1944                         goto drop;
1945
1946                 __skb_queue_head(list, skb);
1947         } else {
1948                 struct net_device_stats *stats;
1949
1950 drop:
1951                 stats = &tp->netdev->stats;
1952                 stats->tx_dropped++;
1953                 dev_kfree_skb(skb);
1954         }
1955 }
1956
1957 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1958 {
1959         if (skb_vlan_tag_present(skb)) {
1960                 u32 opts2;
1961
1962                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1963                 desc->opts2 |= cpu_to_le32(opts2);
1964         }
1965 }
1966
1967 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1968 {
1969         u32 opts2 = le32_to_cpu(desc->opts2);
1970
1971         if (opts2 & RX_VLAN_TAG)
1972                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1973                                        swab16(opts2 & 0xffff));
1974 }
1975
1976 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1977                          struct sk_buff *skb, u32 len, u32 transport_offset)
1978 {
1979         u32 mss = skb_shinfo(skb)->gso_size;
1980         u32 opts1, opts2 = 0;
1981         int ret = TX_CSUM_SUCCESS;
1982
1983         WARN_ON_ONCE(len > TX_LEN_MAX);
1984
1985         opts1 = len | TX_FS | TX_LS;
1986
1987         if (mss) {
1988                 if (transport_offset > GTTCPHO_MAX) {
1989                         netif_warn(tp, tx_err, tp->netdev,
1990                                    "Invalid transport offset 0x%x for TSO\n",
1991                                    transport_offset);
1992                         ret = TX_CSUM_TSO;
1993                         goto unavailable;
1994                 }
1995
1996                 switch (vlan_get_protocol(skb)) {
1997                 case htons(ETH_P_IP):
1998                         opts1 |= GTSENDV4;
1999                         break;
2000
2001                 case htons(ETH_P_IPV6):
2002                         if (skb_cow_head(skb, 0)) {
2003                                 ret = TX_CSUM_TSO;
2004                                 goto unavailable;
2005                         }
2006                         tcp_v6_gso_csum_prep(skb);
2007                         opts1 |= GTSENDV6;
2008                         break;
2009
2010                 default:
2011                         WARN_ON_ONCE(1);
2012                         break;
2013                 }
2014
2015                 opts1 |= transport_offset << GTTCPHO_SHIFT;
2016                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2017         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2018                 u8 ip_protocol;
2019
2020                 if (transport_offset > TCPHO_MAX) {
2021                         netif_warn(tp, tx_err, tp->netdev,
2022                                    "Invalid transport offset 0x%x\n",
2023                                    transport_offset);
2024                         ret = TX_CSUM_NONE;
2025                         goto unavailable;
2026                 }
2027
2028                 switch (vlan_get_protocol(skb)) {
2029                 case htons(ETH_P_IP):
2030                         opts2 |= IPV4_CS;
2031                         ip_protocol = ip_hdr(skb)->protocol;
2032                         break;
2033
2034                 case htons(ETH_P_IPV6):
2035                         opts2 |= IPV6_CS;
2036                         ip_protocol = ipv6_hdr(skb)->nexthdr;
2037                         break;
2038
2039                 default:
2040                         ip_protocol = IPPROTO_RAW;
2041                         break;
2042                 }
2043
2044                 if (ip_protocol == IPPROTO_TCP)
2045                         opts2 |= TCP_CS;
2046                 else if (ip_protocol == IPPROTO_UDP)
2047                         opts2 |= UDP_CS;
2048                 else
2049                         WARN_ON_ONCE(1);
2050
2051                 opts2 |= transport_offset << TCPHO_SHIFT;
2052         }
2053
2054         desc->opts2 = cpu_to_le32(opts2);
2055         desc->opts1 = cpu_to_le32(opts1);
2056
2057 unavailable:
2058         return ret;
2059 }
2060
2061 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2062 {
2063         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2064         int remain, ret;
2065         u8 *tx_data;
2066
2067         __skb_queue_head_init(&skb_head);
2068         spin_lock(&tx_queue->lock);
2069         skb_queue_splice_init(tx_queue, &skb_head);
2070         spin_unlock(&tx_queue->lock);
2071
2072         tx_data = agg->head;
2073         agg->skb_num = 0;
2074         agg->skb_len = 0;
2075         remain = agg_buf_sz;
2076
2077         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2078                 struct tx_desc *tx_desc;
2079                 struct sk_buff *skb;
2080                 unsigned int len;
2081                 u32 offset;
2082
2083                 skb = __skb_dequeue(&skb_head);
2084                 if (!skb)
2085                         break;
2086
2087                 len = skb->len + sizeof(*tx_desc);
2088
2089                 if (len > remain) {
2090                         __skb_queue_head(&skb_head, skb);
2091                         break;
2092                 }
2093
2094                 tx_data = tx_agg_align(tx_data);
2095                 tx_desc = (struct tx_desc *)tx_data;
2096
2097                 offset = (u32)skb_transport_offset(skb);
2098
2099                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2100                         r8152_csum_workaround(tp, skb, &skb_head);
2101                         continue;
2102                 }
2103
2104                 rtl_tx_vlan_tag(tx_desc, skb);
2105
2106                 tx_data += sizeof(*tx_desc);
2107
2108                 len = skb->len;
2109                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2110                         struct net_device_stats *stats = &tp->netdev->stats;
2111
2112                         stats->tx_dropped++;
2113                         dev_kfree_skb_any(skb);
2114                         tx_data -= sizeof(*tx_desc);
2115                         continue;
2116                 }
2117
2118                 tx_data += len;
2119                 agg->skb_len += len;
2120                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2121
2122                 dev_kfree_skb_any(skb);
2123
2124                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2125
2126                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2127                         break;
2128         }
2129
2130         if (!skb_queue_empty(&skb_head)) {
2131                 spin_lock(&tx_queue->lock);
2132                 skb_queue_splice(&skb_head, tx_queue);
2133                 spin_unlock(&tx_queue->lock);
2134         }
2135
2136         netif_tx_lock(tp->netdev);
2137
2138         if (netif_queue_stopped(tp->netdev) &&
2139             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2140                 netif_wake_queue(tp->netdev);
2141
2142         netif_tx_unlock(tp->netdev);
2143
2144         ret = usb_autopm_get_interface_async(tp->intf);
2145         if (ret < 0)
2146                 goto out_tx_fill;
2147
2148         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2149                           agg->head, (int)(tx_data - (u8 *)agg->head),
2150                           (usb_complete_t)write_bulk_callback, agg);
2151
2152         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2153         if (ret < 0)
2154                 usb_autopm_put_interface_async(tp->intf);
2155
2156 out_tx_fill:
2157         return ret;
2158 }
2159
2160 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2161 {
2162         u8 checksum = CHECKSUM_NONE;
2163         u32 opts2, opts3;
2164
2165         if (!(tp->netdev->features & NETIF_F_RXCSUM))
2166                 goto return_result;
2167
2168         opts2 = le32_to_cpu(rx_desc->opts2);
2169         opts3 = le32_to_cpu(rx_desc->opts3);
2170
2171         if (opts2 & RD_IPV4_CS) {
2172                 if (opts3 & IPF)
2173                         checksum = CHECKSUM_NONE;
2174                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2175                         checksum = CHECKSUM_UNNECESSARY;
2176                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2177                         checksum = CHECKSUM_UNNECESSARY;
2178         } else if (opts2 & RD_IPV6_CS) {
2179                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2180                         checksum = CHECKSUM_UNNECESSARY;
2181                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2182                         checksum = CHECKSUM_UNNECESSARY;
2183         }
2184
2185 return_result:
2186         return checksum;
2187 }
2188
2189 static inline bool rx_count_exceed(struct r8152 *tp)
2190 {
2191         return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2192 }
2193
2194 static inline int agg_offset(struct rx_agg *agg, void *addr)
2195 {
2196         return (int)(addr - agg->buffer);
2197 }
2198
2199 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2200 {
2201         struct rx_agg *agg, *agg_next, *agg_free = NULL;
2202         unsigned long flags;
2203
2204         spin_lock_irqsave(&tp->rx_lock, flags);
2205
2206         list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2207                 if (page_count(agg->page) == 1) {
2208                         if (!agg_free) {
2209                                 list_del_init(&agg->list);
2210                                 agg_free = agg;
2211                                 continue;
2212                         }
2213                         if (rx_count_exceed(tp)) {
2214                                 list_del_init(&agg->list);
2215                                 free_rx_agg(tp, agg);
2216                         }
2217                         break;
2218                 }
2219         }
2220
2221         spin_unlock_irqrestore(&tp->rx_lock, flags);
2222
2223         if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2224                 agg_free = alloc_rx_agg(tp, mflags);
2225
2226         return agg_free;
2227 }
2228
2229 static int rx_bottom(struct r8152 *tp, int budget)
2230 {
2231         unsigned long flags;
2232         struct list_head *cursor, *next, rx_queue;
2233         int ret = 0, work_done = 0;
2234         struct napi_struct *napi = &tp->napi;
2235
2236         if (!skb_queue_empty(&tp->rx_queue)) {
2237                 while (work_done < budget) {
2238                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2239                         struct net_device *netdev = tp->netdev;
2240                         struct net_device_stats *stats = &netdev->stats;
2241                         unsigned int pkt_len;
2242
2243                         if (!skb)
2244                                 break;
2245
2246                         pkt_len = skb->len;
2247                         napi_gro_receive(napi, skb);
2248                         work_done++;
2249                         stats->rx_packets++;
2250                         stats->rx_bytes += pkt_len;
2251                 }
2252         }
2253
2254         if (list_empty(&tp->rx_done))
2255                 goto out1;
2256
2257         INIT_LIST_HEAD(&rx_queue);
2258         spin_lock_irqsave(&tp->rx_lock, flags);
2259         list_splice_init(&tp->rx_done, &rx_queue);
2260         spin_unlock_irqrestore(&tp->rx_lock, flags);
2261
2262         list_for_each_safe(cursor, next, &rx_queue) {
2263                 struct rx_desc *rx_desc;
2264                 struct rx_agg *agg, *agg_free;
2265                 int len_used = 0;
2266                 struct urb *urb;
2267                 u8 *rx_data;
2268
2269                 list_del_init(cursor);
2270
2271                 agg = list_entry(cursor, struct rx_agg, list);
2272                 urb = agg->urb;
2273                 if (urb->actual_length < ETH_ZLEN)
2274                         goto submit;
2275
2276                 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2277
2278                 rx_desc = agg->buffer;
2279                 rx_data = agg->buffer;
2280                 len_used += sizeof(struct rx_desc);
2281
2282                 while (urb->actual_length > len_used) {
2283                         struct net_device *netdev = tp->netdev;
2284                         struct net_device_stats *stats = &netdev->stats;
2285                         unsigned int pkt_len, rx_frag_head_sz;
2286                         struct sk_buff *skb;
2287
2288                         /* limite the skb numbers for rx_queue */
2289                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2290                                 break;
2291
2292                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2293                         if (pkt_len < ETH_ZLEN)
2294                                 break;
2295
2296                         len_used += pkt_len;
2297                         if (urb->actual_length < len_used)
2298                                 break;
2299
2300                         pkt_len -= ETH_FCS_LEN;
2301                         rx_data += sizeof(struct rx_desc);
2302
2303                         if (!agg_free || tp->rx_copybreak > pkt_len)
2304                                 rx_frag_head_sz = pkt_len;
2305                         else
2306                                 rx_frag_head_sz = tp->rx_copybreak;
2307
2308                         skb = napi_alloc_skb(napi, rx_frag_head_sz);
2309                         if (!skb) {
2310                                 stats->rx_dropped++;
2311                                 goto find_next_rx;
2312                         }
2313
2314                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2315                         memcpy(skb->data, rx_data, rx_frag_head_sz);
2316                         skb_put(skb, rx_frag_head_sz);
2317                         pkt_len -= rx_frag_head_sz;
2318                         rx_data += rx_frag_head_sz;
2319                         if (pkt_len) {
2320                                 skb_add_rx_frag(skb, 0, agg->page,
2321                                                 agg_offset(agg, rx_data),
2322                                                 pkt_len,
2323                                                 SKB_DATA_ALIGN(pkt_len));
2324                                 get_page(agg->page);
2325                         }
2326
2327                         skb->protocol = eth_type_trans(skb, netdev);
2328                         rtl_rx_vlan_tag(rx_desc, skb);
2329                         if (work_done < budget) {
2330                                 work_done++;
2331                                 stats->rx_packets++;
2332                                 stats->rx_bytes += skb->len;
2333                                 napi_gro_receive(napi, skb);
2334                         } else {
2335                                 __skb_queue_tail(&tp->rx_queue, skb);
2336                         }
2337
2338 find_next_rx:
2339                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2340                         rx_desc = (struct rx_desc *)rx_data;
2341                         len_used = agg_offset(agg, rx_data);
2342                         len_used += sizeof(struct rx_desc);
2343                 }
2344
2345                 WARN_ON(!agg_free && page_count(agg->page) > 1);
2346
2347                 if (agg_free) {
2348                         spin_lock_irqsave(&tp->rx_lock, flags);
2349                         if (page_count(agg->page) == 1) {
2350                                 list_add(&agg_free->list, &tp->rx_used);
2351                         } else {
2352                                 list_add_tail(&agg->list, &tp->rx_used);
2353                                 agg = agg_free;
2354                                 urb = agg->urb;
2355                         }
2356                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2357                 }
2358
2359 submit:
2360                 if (!ret) {
2361                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2362                 } else {
2363                         urb->actual_length = 0;
2364                         list_add_tail(&agg->list, next);
2365                 }
2366         }
2367
2368         if (!list_empty(&rx_queue)) {
2369                 spin_lock_irqsave(&tp->rx_lock, flags);
2370                 list_splice_tail(&rx_queue, &tp->rx_done);
2371                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2372         }
2373
2374 out1:
2375         return work_done;
2376 }
2377
2378 static void tx_bottom(struct r8152 *tp)
2379 {
2380         int res;
2381
2382         do {
2383                 struct net_device *netdev = tp->netdev;
2384                 struct tx_agg *agg;
2385
2386                 if (skb_queue_empty(&tp->tx_queue))
2387                         break;
2388
2389                 agg = r8152_get_tx_agg(tp);
2390                 if (!agg)
2391                         break;
2392
2393                 res = r8152_tx_agg_fill(tp, agg);
2394                 if (!res)
2395                         continue;
2396
2397                 if (res == -ENODEV) {
2398                         rtl_set_unplug(tp);
2399                         netif_device_detach(netdev);
2400                 } else {
2401                         struct net_device_stats *stats = &netdev->stats;
2402                         unsigned long flags;
2403
2404                         netif_warn(tp, tx_err, netdev,
2405                                    "failed tx_urb %d\n", res);
2406                         stats->tx_dropped += agg->skb_num;
2407
2408                         spin_lock_irqsave(&tp->tx_lock, flags);
2409                         list_add_tail(&agg->list, &tp->tx_free);
2410                         spin_unlock_irqrestore(&tp->tx_lock, flags);
2411                 }
2412         } while (res == 0);
2413 }
2414
2415 static void bottom_half(unsigned long data)
2416 {
2417         struct r8152 *tp;
2418
2419         tp = (struct r8152 *)data;
2420
2421         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2422                 return;
2423
2424         if (!test_bit(WORK_ENABLE, &tp->flags))
2425                 return;
2426
2427         /* When link down, the driver would cancel all bulks. */
2428         /* This avoid the re-submitting bulk */
2429         if (!netif_carrier_ok(tp->netdev))
2430                 return;
2431
2432         clear_bit(SCHEDULE_TASKLET, &tp->flags);
2433
2434         tx_bottom(tp);
2435 }
2436
2437 static int r8152_poll(struct napi_struct *napi, int budget)
2438 {
2439         struct r8152 *tp = container_of(napi, struct r8152, napi);
2440         int work_done;
2441
2442         if (!budget)
2443                 return 0;
2444
2445         work_done = rx_bottom(tp, budget);
2446
2447         if (work_done < budget) {
2448                 if (!napi_complete_done(napi, work_done))
2449                         goto out;
2450                 if (!list_empty(&tp->rx_done))
2451                         napi_schedule(napi);
2452         }
2453
2454 out:
2455         return work_done;
2456 }
2457
2458 static
2459 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2460 {
2461         int ret;
2462
2463         /* The rx would be stopped, so skip submitting */
2464         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2465             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2466                 return 0;
2467
2468         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2469                           agg->buffer, tp->rx_buf_sz,
2470                           (usb_complete_t)read_bulk_callback, agg);
2471
2472         ret = usb_submit_urb(agg->urb, mem_flags);
2473         if (ret == -ENODEV) {
2474                 rtl_set_unplug(tp);
2475                 netif_device_detach(tp->netdev);
2476         } else if (ret) {
2477                 struct urb *urb = agg->urb;
2478                 unsigned long flags;
2479
2480                 urb->actual_length = 0;
2481                 spin_lock_irqsave(&tp->rx_lock, flags);
2482                 list_add_tail(&agg->list, &tp->rx_done);
2483                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2484
2485                 netif_err(tp, rx_err, tp->netdev,
2486                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2487
2488                 napi_schedule(&tp->napi);
2489         }
2490
2491         return ret;
2492 }
2493
2494 static void rtl_drop_queued_tx(struct r8152 *tp)
2495 {
2496         struct net_device_stats *stats = &tp->netdev->stats;
2497         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2498         struct sk_buff *skb;
2499
2500         if (skb_queue_empty(tx_queue))
2501                 return;
2502
2503         __skb_queue_head_init(&skb_head);
2504         spin_lock_bh(&tx_queue->lock);
2505         skb_queue_splice_init(tx_queue, &skb_head);
2506         spin_unlock_bh(&tx_queue->lock);
2507
2508         while ((skb = __skb_dequeue(&skb_head))) {
2509                 dev_kfree_skb(skb);
2510                 stats->tx_dropped++;
2511         }
2512 }
2513
2514 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2515 {
2516         struct r8152 *tp = netdev_priv(netdev);
2517
2518         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2519
2520         usb_queue_reset_device(tp->intf);
2521 }
2522
2523 static void rtl8152_set_rx_mode(struct net_device *netdev)
2524 {
2525         struct r8152 *tp = netdev_priv(netdev);
2526
2527         if (netif_carrier_ok(netdev)) {
2528                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2529                 schedule_delayed_work(&tp->schedule, 0);
2530         }
2531 }
2532
2533 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2534 {
2535         struct r8152 *tp = netdev_priv(netdev);
2536         u32 mc_filter[2];       /* Multicast hash filter */
2537         __le32 tmp[2];
2538         u32 ocp_data;
2539
2540         netif_stop_queue(netdev);
2541         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2542         ocp_data &= ~RCR_ACPT_ALL;
2543         ocp_data |= RCR_AB | RCR_APM;
2544
2545         if (netdev->flags & IFF_PROMISC) {
2546                 /* Unconditionally log net taps. */
2547                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2548                 ocp_data |= RCR_AM | RCR_AAP;
2549                 mc_filter[1] = 0xffffffff;
2550                 mc_filter[0] = 0xffffffff;
2551         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2552                    (netdev->flags & IFF_ALLMULTI)) {
2553                 /* Too many to filter perfectly -- accept all multicasts. */
2554                 ocp_data |= RCR_AM;
2555                 mc_filter[1] = 0xffffffff;
2556                 mc_filter[0] = 0xffffffff;
2557         } else {
2558                 struct netdev_hw_addr *ha;
2559
2560                 mc_filter[1] = 0;
2561                 mc_filter[0] = 0;
2562                 netdev_for_each_mc_addr(ha, netdev) {
2563                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2564
2565                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2566                         ocp_data |= RCR_AM;
2567                 }
2568         }
2569
2570         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2571         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2572
2573         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2574         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2575         netif_wake_queue(netdev);
2576 }
2577
2578 static netdev_features_t
2579 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2580                        netdev_features_t features)
2581 {
2582         u32 mss = skb_shinfo(skb)->gso_size;
2583         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2584         int offset = skb_transport_offset(skb);
2585
2586         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2587                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2588         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2589                 features &= ~NETIF_F_GSO_MASK;
2590
2591         return features;
2592 }
2593
2594 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2595                                       struct net_device *netdev)
2596 {
2597         struct r8152 *tp = netdev_priv(netdev);
2598
2599         skb_tx_timestamp(skb);
2600
2601         skb_queue_tail(&tp->tx_queue, skb);
2602
2603         if (!list_empty(&tp->tx_free)) {
2604                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2605                         set_bit(SCHEDULE_TASKLET, &tp->flags);
2606                         schedule_delayed_work(&tp->schedule, 0);
2607                 } else {
2608                         usb_mark_last_busy(tp->udev);
2609                         tasklet_schedule(&tp->tx_tl);
2610                 }
2611         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2612                 netif_stop_queue(netdev);
2613         }
2614
2615         return NETDEV_TX_OK;
2616 }
2617
2618 static void r8152b_reset_packet_filter(struct r8152 *tp)
2619 {
2620         u32     ocp_data;
2621
2622         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2623         ocp_data &= ~FMC_FCR_MCU_EN;
2624         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2625         ocp_data |= FMC_FCR_MCU_EN;
2626         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2627 }
2628
2629 static void rtl8152_nic_reset(struct r8152 *tp)
2630 {
2631         int     i;
2632
2633         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2634
2635         for (i = 0; i < 1000; i++) {
2636                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2637                         break;
2638                 usleep_range(100, 400);
2639         }
2640 }
2641
2642 static void set_tx_qlen(struct r8152 *tp)
2643 {
2644         struct net_device *netdev = tp->netdev;
2645
2646         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2647                                     sizeof(struct tx_desc));
2648 }
2649
2650 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2651 {
2652         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2653 }
2654
2655 static void rtl_set_eee_plus(struct r8152 *tp)
2656 {
2657         u32 ocp_data;
2658         u8 speed;
2659
2660         speed = rtl8152_get_speed(tp);
2661         if (speed & _10bps) {
2662                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2663                 ocp_data |= EEEP_CR_EEEP_TX;
2664                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2665         } else {
2666                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2667                 ocp_data &= ~EEEP_CR_EEEP_TX;
2668                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2669         }
2670 }
2671
2672 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2673 {
2674         u32 ocp_data;
2675
2676         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2677         if (enable)
2678                 ocp_data |= RXDY_GATED_EN;
2679         else
2680                 ocp_data &= ~RXDY_GATED_EN;
2681         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2682 }
2683
2684 static int rtl_start_rx(struct r8152 *tp)
2685 {
2686         struct rx_agg *agg, *agg_next;
2687         struct list_head tmp_list;
2688         unsigned long flags;
2689         int ret = 0, i = 0;
2690
2691         INIT_LIST_HEAD(&tmp_list);
2692
2693         spin_lock_irqsave(&tp->rx_lock, flags);
2694
2695         INIT_LIST_HEAD(&tp->rx_done);
2696         INIT_LIST_HEAD(&tp->rx_used);
2697
2698         list_splice_init(&tp->rx_info, &tmp_list);
2699
2700         spin_unlock_irqrestore(&tp->rx_lock, flags);
2701
2702         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2703                 INIT_LIST_HEAD(&agg->list);
2704
2705                 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2706                 if (++i > RTL8152_MAX_RX) {
2707                         spin_lock_irqsave(&tp->rx_lock, flags);
2708                         list_add_tail(&agg->list, &tp->rx_used);
2709                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2710                 } else if (unlikely(ret < 0)) {
2711                         spin_lock_irqsave(&tp->rx_lock, flags);
2712                         list_add_tail(&agg->list, &tp->rx_done);
2713                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2714                 } else {
2715                         ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2716                 }
2717         }
2718
2719         spin_lock_irqsave(&tp->rx_lock, flags);
2720         WARN_ON(!list_empty(&tp->rx_info));
2721         list_splice(&tmp_list, &tp->rx_info);
2722         spin_unlock_irqrestore(&tp->rx_lock, flags);
2723
2724         return ret;
2725 }
2726
2727 static int rtl_stop_rx(struct r8152 *tp)
2728 {
2729         struct rx_agg *agg, *agg_next;
2730         struct list_head tmp_list;
2731         unsigned long flags;
2732
2733         INIT_LIST_HEAD(&tmp_list);
2734
2735         /* The usb_kill_urb() couldn't be used in atomic.
2736          * Therefore, move the list of rx_info to a tmp one.
2737          * Then, list_for_each_entry_safe could be used without
2738          * spin lock.
2739          */
2740
2741         spin_lock_irqsave(&tp->rx_lock, flags);
2742         list_splice_init(&tp->rx_info, &tmp_list);
2743         spin_unlock_irqrestore(&tp->rx_lock, flags);
2744
2745         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2746                 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2747                  * equal to 1, so the other ones could be freed safely.
2748                  */
2749                 if (page_count(agg->page) > 1)
2750                         free_rx_agg(tp, agg);
2751                 else
2752                         usb_kill_urb(agg->urb);
2753         }
2754
2755         /* Move back the list of temp to the rx_info */
2756         spin_lock_irqsave(&tp->rx_lock, flags);
2757         WARN_ON(!list_empty(&tp->rx_info));
2758         list_splice(&tmp_list, &tp->rx_info);
2759         spin_unlock_irqrestore(&tp->rx_lock, flags);
2760
2761         while (!skb_queue_empty(&tp->rx_queue))
2762                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2763
2764         return 0;
2765 }
2766
2767 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2768 {
2769         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2770                        OWN_UPDATE | OWN_CLEAR);
2771 }
2772
2773 static int rtl_enable(struct r8152 *tp)
2774 {
2775         u32 ocp_data;
2776
2777         r8152b_reset_packet_filter(tp);
2778
2779         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2780         ocp_data |= CR_RE | CR_TE;
2781         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2782
2783         switch (tp->version) {
2784         case RTL_VER_08:
2785         case RTL_VER_09:
2786                 r8153b_rx_agg_chg_indicate(tp);
2787                 break;
2788         default:
2789                 break;
2790         }
2791
2792         rxdy_gated_en(tp, false);
2793
2794         return 0;
2795 }
2796
2797 static int rtl8152_enable(struct r8152 *tp)
2798 {
2799         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2800                 return -ENODEV;
2801
2802         set_tx_qlen(tp);
2803         rtl_set_eee_plus(tp);
2804
2805         return rtl_enable(tp);
2806 }
2807
2808 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2809 {
2810         u32 ocp_data = tp->coalesce / 8;
2811
2812         switch (tp->version) {
2813         case RTL_VER_03:
2814         case RTL_VER_04:
2815         case RTL_VER_05:
2816         case RTL_VER_06:
2817                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2818                                ocp_data);
2819                 break;
2820
2821         case RTL_VER_08:
2822         case RTL_VER_09:
2823                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2824                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2825                  */
2826                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2827                                128 / 8);
2828                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2829                                ocp_data);
2830                 break;
2831
2832         default:
2833                 break;
2834         }
2835 }
2836
2837 static void r8153_set_rx_early_size(struct r8152 *tp)
2838 {
2839         u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2840
2841         switch (tp->version) {
2842         case RTL_VER_03:
2843         case RTL_VER_04:
2844         case RTL_VER_05:
2845         case RTL_VER_06:
2846                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2847                                ocp_data / 4);
2848                 break;
2849         case RTL_VER_08:
2850         case RTL_VER_09:
2851                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2852                                ocp_data / 8);
2853                 break;
2854         default:
2855                 WARN_ON_ONCE(1);
2856                 break;
2857         }
2858 }
2859
2860 static int rtl8153_enable(struct r8152 *tp)
2861 {
2862         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2863                 return -ENODEV;
2864
2865         set_tx_qlen(tp);
2866         rtl_set_eee_plus(tp);
2867         r8153_set_rx_early_timeout(tp);
2868         r8153_set_rx_early_size(tp);
2869
2870         if (tp->version == RTL_VER_09) {
2871                 u32 ocp_data;
2872
2873                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2874                 ocp_data &= ~FC_PATCH_TASK;
2875                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2876                 usleep_range(1000, 2000);
2877                 ocp_data |= FC_PATCH_TASK;
2878                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2879         }
2880
2881         return rtl_enable(tp);
2882 }
2883
2884 static void rtl_disable(struct r8152 *tp)
2885 {
2886         u32 ocp_data;
2887         int i;
2888
2889         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2890                 rtl_drop_queued_tx(tp);
2891                 return;
2892         }
2893
2894         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2895         ocp_data &= ~RCR_ACPT_ALL;
2896         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2897
2898         rtl_drop_queued_tx(tp);
2899
2900         for (i = 0; i < RTL8152_MAX_TX; i++)
2901                 usb_kill_urb(tp->tx_info[i].urb);
2902
2903         rxdy_gated_en(tp, true);
2904
2905         for (i = 0; i < 1000; i++) {
2906                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2907                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2908                         break;
2909                 usleep_range(1000, 2000);
2910         }
2911
2912         for (i = 0; i < 1000; i++) {
2913                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2914                         break;
2915                 usleep_range(1000, 2000);
2916         }
2917
2918         rtl_stop_rx(tp);
2919
2920         rtl8152_nic_reset(tp);
2921 }
2922
2923 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2924 {
2925         u32 ocp_data;
2926
2927         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2928         if (enable)
2929                 ocp_data |= POWER_CUT;
2930         else
2931                 ocp_data &= ~POWER_CUT;
2932         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2933
2934         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2935         ocp_data &= ~RESUME_INDICATE;
2936         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2937 }
2938
2939 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2940 {
2941         u32 ocp_data;
2942
2943         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2944         if (enable)
2945                 ocp_data |= CPCR_RX_VLAN;
2946         else
2947                 ocp_data &= ~CPCR_RX_VLAN;
2948         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2949 }
2950
2951 static int rtl8152_set_features(struct net_device *dev,
2952                                 netdev_features_t features)
2953 {
2954         netdev_features_t changed = features ^ dev->features;
2955         struct r8152 *tp = netdev_priv(dev);
2956         int ret;
2957
2958         ret = usb_autopm_get_interface(tp->intf);
2959         if (ret < 0)
2960                 goto out;
2961
2962         mutex_lock(&tp->control);
2963
2964         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2965                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2966                         rtl_rx_vlan_en(tp, true);
2967                 else
2968                         rtl_rx_vlan_en(tp, false);
2969         }
2970
2971         mutex_unlock(&tp->control);
2972
2973         usb_autopm_put_interface(tp->intf);
2974
2975 out:
2976         return ret;
2977 }
2978
2979 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2980
2981 static u32 __rtl_get_wol(struct r8152 *tp)
2982 {
2983         u32 ocp_data;
2984         u32 wolopts = 0;
2985
2986         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2987         if (ocp_data & LINK_ON_WAKE_EN)
2988                 wolopts |= WAKE_PHY;
2989
2990         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2991         if (ocp_data & UWF_EN)
2992                 wolopts |= WAKE_UCAST;
2993         if (ocp_data & BWF_EN)
2994                 wolopts |= WAKE_BCAST;
2995         if (ocp_data & MWF_EN)
2996                 wolopts |= WAKE_MCAST;
2997
2998         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2999         if (ocp_data & MAGIC_EN)
3000                 wolopts |= WAKE_MAGIC;
3001
3002         return wolopts;
3003 }
3004
3005 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3006 {
3007         u32 ocp_data;
3008
3009         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3010
3011         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3012         ocp_data &= ~LINK_ON_WAKE_EN;
3013         if (wolopts & WAKE_PHY)
3014                 ocp_data |= LINK_ON_WAKE_EN;
3015         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3016
3017         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3018         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3019         if (wolopts & WAKE_UCAST)
3020                 ocp_data |= UWF_EN;
3021         if (wolopts & WAKE_BCAST)
3022                 ocp_data |= BWF_EN;
3023         if (wolopts & WAKE_MCAST)
3024                 ocp_data |= MWF_EN;
3025         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3026
3027         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3028
3029         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3030         ocp_data &= ~MAGIC_EN;
3031         if (wolopts & WAKE_MAGIC)
3032                 ocp_data |= MAGIC_EN;
3033         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3034
3035         if (wolopts & WAKE_ANY)
3036                 device_set_wakeup_enable(&tp->udev->dev, true);
3037         else
3038                 device_set_wakeup_enable(&tp->udev->dev, false);
3039 }
3040
3041 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3042 {
3043         u8 u1u2[8];
3044
3045         if (enable)
3046                 memset(u1u2, 0xff, sizeof(u1u2));
3047         else
3048                 memset(u1u2, 0x00, sizeof(u1u2));
3049
3050         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3051 }
3052
3053 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3054 {
3055         u32 ocp_data;
3056
3057         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3058         if (enable)
3059                 ocp_data |= LPM_U1U2_EN;
3060         else
3061                 ocp_data &= ~LPM_U1U2_EN;
3062
3063         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3064 }
3065
3066 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3067 {
3068         u32 ocp_data;
3069
3070         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3071         if (enable)
3072                 ocp_data |= U2P3_ENABLE;
3073         else
3074                 ocp_data &= ~U2P3_ENABLE;
3075         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3076 }
3077
3078 static void r8153b_ups_flags(struct r8152 *tp)
3079 {
3080         u32 ups_flags = 0;
3081
3082         if (tp->ups_info.green)
3083                 ups_flags |= UPS_FLAGS_EN_GREEN;
3084
3085         if (tp->ups_info.aldps)
3086                 ups_flags |= UPS_FLAGS_EN_ALDPS;
3087
3088         if (tp->ups_info.eee)
3089                 ups_flags |= UPS_FLAGS_EN_EEE;
3090
3091         if (tp->ups_info.flow_control)
3092                 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3093
3094         if (tp->ups_info.eee_ckdiv)
3095                 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3096
3097         if (tp->ups_info.eee_cmod_lv)
3098                 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3099
3100         if (tp->ups_info._10m_ckdiv)
3101                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3102
3103         if (tp->ups_info.eee_plloff_100)
3104                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3105
3106         if (tp->ups_info.eee_plloff_giga)
3107                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3108
3109         if (tp->ups_info._250m_ckdiv)
3110                 ups_flags |= UPS_FLAGS_250M_CKDIV;
3111
3112         if (tp->ups_info.ctap_short_off)
3113                 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3114
3115         switch (tp->ups_info.speed_duplex) {
3116         case NWAY_10M_HALF:
3117                 ups_flags |= ups_flags_speed(1);
3118                 break;
3119         case NWAY_10M_FULL:
3120                 ups_flags |= ups_flags_speed(2);
3121                 break;
3122         case NWAY_100M_HALF:
3123                 ups_flags |= ups_flags_speed(3);
3124                 break;
3125         case NWAY_100M_FULL:
3126                 ups_flags |= ups_flags_speed(4);
3127                 break;
3128         case NWAY_1000M_FULL:
3129                 ups_flags |= ups_flags_speed(5);
3130                 break;
3131         case FORCE_10M_HALF:
3132                 ups_flags |= ups_flags_speed(6);
3133                 break;
3134         case FORCE_10M_FULL:
3135                 ups_flags |= ups_flags_speed(7);
3136                 break;
3137         case FORCE_100M_HALF:
3138                 ups_flags |= ups_flags_speed(8);
3139                 break;
3140         case FORCE_100M_FULL:
3141                 ups_flags |= ups_flags_speed(9);
3142                 break;
3143         default:
3144                 break;
3145         }
3146
3147         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3148 }
3149
3150 static void r8153b_green_en(struct r8152 *tp, bool enable)
3151 {
3152         u16 data;
3153
3154         if (enable) {
3155                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
3156                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3157                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3158         } else {
3159                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3160                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3161                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3162         }
3163
3164         data = sram_read(tp, SRAM_GREEN_CFG);
3165         data |= GREEN_ETH_EN;
3166         sram_write(tp, SRAM_GREEN_CFG, data);
3167
3168         tp->ups_info.green = enable;
3169 }
3170
3171 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3172 {
3173         u16 data;
3174         int i;
3175
3176         for (i = 0; i < 500; i++) {
3177                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3178                 data &= PHY_STAT_MASK;
3179                 if (desired) {
3180                         if (data == desired)
3181                                 break;
3182                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3183                            data == PHY_STAT_EXT_INIT) {
3184                         break;
3185                 }
3186
3187                 msleep(20);
3188                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3189                         break;
3190         }
3191
3192         return data;
3193 }
3194
3195 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3196 {
3197         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3198
3199         if (enable) {
3200                 r8153b_ups_flags(tp);
3201
3202                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3203                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3204
3205                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3206                 ocp_data |= BIT(0);
3207                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3208         } else {
3209                 u16 data;
3210
3211                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3212                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3213
3214                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3215                 ocp_data &= ~BIT(0);
3216                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3217
3218                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3219                 ocp_data &= ~PCUT_STATUS;
3220                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3221
3222                 data = r8153_phy_status(tp, 0);
3223
3224                 switch (data) {
3225                 case PHY_STAT_PWRDN:
3226                 case PHY_STAT_EXT_INIT:
3227                         r8153b_green_en(tp,
3228                                         test_bit(GREEN_ETHERNET, &tp->flags));
3229
3230                         data = r8152_mdio_read(tp, MII_BMCR);
3231                         data &= ~BMCR_PDOWN;
3232                         data |= BMCR_RESET;
3233                         r8152_mdio_write(tp, MII_BMCR, data);
3234
3235                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3236                         fallthrough;
3237
3238                 default:
3239                         if (data != PHY_STAT_LAN_ON)
3240                                 netif_warn(tp, link, tp->netdev,
3241                                            "PHY not ready");
3242                         break;
3243                 }
3244         }
3245 }
3246
3247 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3248 {
3249         u32 ocp_data;
3250
3251         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3252         if (enable)
3253                 ocp_data |= PWR_EN | PHASE2_EN;
3254         else
3255                 ocp_data &= ~(PWR_EN | PHASE2_EN);
3256         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3257
3258         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3259         ocp_data &= ~PCUT_STATUS;
3260         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3261 }
3262
3263 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3264 {
3265         u32 ocp_data;
3266
3267         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3268         if (enable)
3269                 ocp_data |= PWR_EN | PHASE2_EN;
3270         else
3271                 ocp_data &= ~PWR_EN;
3272         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3273
3274         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3275         ocp_data &= ~PCUT_STATUS;
3276         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3277 }
3278
3279 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3280 {
3281         u32 ocp_data;
3282
3283         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3284         if (enable)
3285                 ocp_data |= UPCOMING_RUNTIME_D3;
3286         else
3287                 ocp_data &= ~UPCOMING_RUNTIME_D3;
3288         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3289
3290         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3291         ocp_data &= ~LINK_CHG_EVENT;
3292         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3293
3294         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3295         ocp_data &= ~LINK_CHANGE_FLAG;
3296         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3297 }
3298
3299 static bool rtl_can_wakeup(struct r8152 *tp)
3300 {
3301         struct usb_device *udev = tp->udev;
3302
3303         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3304 }
3305
3306 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3307 {
3308         if (enable) {
3309                 u32 ocp_data;
3310
3311                 __rtl_set_wol(tp, WAKE_ANY);
3312
3313                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3314
3315                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3316                 ocp_data |= LINK_OFF_WAKE_EN;
3317                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3318
3319                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3320         } else {
3321                 u32 ocp_data;
3322
3323                 __rtl_set_wol(tp, tp->saved_wolopts);
3324
3325                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3326
3327                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3328                 ocp_data &= ~LINK_OFF_WAKE_EN;
3329                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3330
3331                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3332         }
3333 }
3334
3335 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3336 {
3337         if (enable) {
3338                 r8153_u1u2en(tp, false);
3339                 r8153_u2p3en(tp, false);
3340                 rtl_runtime_suspend_enable(tp, true);
3341         } else {
3342                 rtl_runtime_suspend_enable(tp, false);
3343
3344                 switch (tp->version) {
3345                 case RTL_VER_03:
3346                 case RTL_VER_04:
3347                         break;
3348                 case RTL_VER_05:
3349                 case RTL_VER_06:
3350                 default:
3351                         r8153_u2p3en(tp, true);
3352                         break;
3353                 }
3354
3355                 r8153_u1u2en(tp, true);
3356         }
3357 }
3358
3359 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3360 {
3361         if (enable) {
3362                 r8153_queue_wake(tp, true);
3363                 r8153b_u1u2en(tp, false);
3364                 r8153_u2p3en(tp, false);
3365                 rtl_runtime_suspend_enable(tp, true);
3366                 r8153b_ups_en(tp, true);
3367         } else {
3368                 r8153b_ups_en(tp, false);
3369                 r8153_queue_wake(tp, false);
3370                 rtl_runtime_suspend_enable(tp, false);
3371                 if (tp->udev->speed != USB_SPEED_HIGH)
3372                         r8153b_u1u2en(tp, true);
3373         }
3374 }
3375
3376 static void r8153_teredo_off(struct r8152 *tp)
3377 {
3378         u32 ocp_data;
3379
3380         switch (tp->version) {
3381         case RTL_VER_01:
3382         case RTL_VER_02:
3383         case RTL_VER_03:
3384         case RTL_VER_04:
3385         case RTL_VER_05:
3386         case RTL_VER_06:
3387         case RTL_VER_07:
3388                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3389                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3390                               OOB_TEREDO_EN);
3391                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3392                 break;
3393
3394         case RTL_VER_08:
3395         case RTL_VER_09:
3396                 /* The bit 0 ~ 7 are relative with teredo settings. They are
3397                  * W1C (write 1 to clear), so set all 1 to disable it.
3398                  */
3399                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3400                 break;
3401
3402         default:
3403                 break;
3404         }
3405
3406         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3407         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3408         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3409 }
3410
3411 static void rtl_reset_bmu(struct r8152 *tp)
3412 {
3413         u32 ocp_data;
3414
3415         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3416         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3417         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3418         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3419         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3420 }
3421
3422 /* Clear the bp to stop the firmware before loading a new one */
3423 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3424 {
3425         switch (tp->version) {
3426         case RTL_VER_01:
3427         case RTL_VER_02:
3428         case RTL_VER_07:
3429                 break;
3430         case RTL_VER_03:
3431         case RTL_VER_04:
3432         case RTL_VER_05:
3433         case RTL_VER_06:
3434                 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3435                 break;
3436         case RTL_VER_08:
3437         case RTL_VER_09:
3438         default:
3439                 if (type == MCU_TYPE_USB) {
3440                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3441
3442                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3443                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3444                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3445                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3446                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3447                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3448                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3449                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3450                 } else {
3451                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3452                 }
3453                 break;
3454         }
3455
3456         ocp_write_word(tp, type, PLA_BP_0, 0);
3457         ocp_write_word(tp, type, PLA_BP_1, 0);
3458         ocp_write_word(tp, type, PLA_BP_2, 0);
3459         ocp_write_word(tp, type, PLA_BP_3, 0);
3460         ocp_write_word(tp, type, PLA_BP_4, 0);
3461         ocp_write_word(tp, type, PLA_BP_5, 0);
3462         ocp_write_word(tp, type, PLA_BP_6, 0);
3463         ocp_write_word(tp, type, PLA_BP_7, 0);
3464
3465         /* wait 3 ms to make sure the firmware is stopped */
3466         usleep_range(3000, 6000);
3467         ocp_write_word(tp, type, PLA_BP_BA, 0);
3468 }
3469
3470 static int r8153_patch_request(struct r8152 *tp, bool request)
3471 {
3472         u16 data;
3473         int i;
3474
3475         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3476         if (request)
3477                 data |= PATCH_REQUEST;
3478         else
3479                 data &= ~PATCH_REQUEST;
3480         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3481
3482         for (i = 0; request && i < 5000; i++) {
3483                 usleep_range(1000, 2000);
3484                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3485                         break;
3486         }
3487
3488         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3489                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3490                 r8153_patch_request(tp, false);
3491                 return -ETIME;
3492         } else {
3493                 return 0;
3494         }
3495 }
3496
3497 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3498 {
3499         if (r8153_patch_request(tp, true)) {
3500                 dev_err(&tp->intf->dev, "patch request fail\n");
3501                 return -ETIME;
3502         }
3503
3504         sram_write(tp, key_addr, patch_key);
3505         sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3506
3507         return 0;
3508 }
3509
3510 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3511 {
3512         u16 data;
3513
3514         sram_write(tp, 0x0000, 0x0000);
3515
3516         data = ocp_reg_read(tp, OCP_PHY_LOCK);
3517         data &= ~PATCH_LOCK;
3518         ocp_reg_write(tp, OCP_PHY_LOCK, data);
3519
3520         sram_write(tp, key_addr, 0x0000);
3521
3522         r8153_patch_request(tp, false);
3523
3524         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3525
3526         return 0;
3527 }
3528
3529 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3530 {
3531         u32 length;
3532         u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3533         bool rc = false;
3534
3535         switch (tp->version) {
3536         case RTL_VER_04:
3537         case RTL_VER_05:
3538         case RTL_VER_06:
3539                 fw_reg = 0xa014;
3540                 ba_reg = 0xa012;
3541                 patch_en_addr = 0xa01a;
3542                 mode_reg = 0xb820;
3543                 bp_start = 0xa000;
3544                 break;
3545         default:
3546                 goto out;
3547         }
3548
3549         fw_offset = __le16_to_cpu(phy->fw_offset);
3550         if (fw_offset < sizeof(*phy)) {
3551                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3552                 goto out;
3553         }
3554
3555         length = __le32_to_cpu(phy->blk_hdr.length);
3556         if (length < fw_offset) {
3557                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3558                 goto out;
3559         }
3560
3561         length -= __le16_to_cpu(phy->fw_offset);
3562         if (!length || (length & 1)) {
3563                 dev_err(&tp->intf->dev, "invalid block length\n");
3564                 goto out;
3565         }
3566
3567         if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3568                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3569                 goto out;
3570         }
3571
3572         if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3573                 dev_err(&tp->intf->dev, "invalid base address register\n");
3574                 goto out;
3575         }
3576
3577         if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3578                 dev_err(&tp->intf->dev,
3579                         "invalid patch mode enabled register\n");
3580                 goto out;
3581         }
3582
3583         if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3584                 dev_err(&tp->intf->dev,
3585                         "invalid register to switch the mode\n");
3586                 goto out;
3587         }
3588
3589         if (__le16_to_cpu(phy->bp_start) != bp_start) {
3590                 dev_err(&tp->intf->dev,
3591                         "invalid start register of break point\n");
3592                 goto out;
3593         }
3594
3595         if (__le16_to_cpu(phy->bp_num) > 4) {
3596                 dev_err(&tp->intf->dev, "invalid break point number\n");
3597                 goto out;
3598         }
3599
3600         rc = true;
3601 out:
3602         return rc;
3603 }
3604
3605 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3606 {
3607         u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3608         bool rc = false;
3609         u32 length, type;
3610         int i, max_bp;
3611
3612         type = __le32_to_cpu(mac->blk_hdr.type);
3613         if (type == RTL_FW_PLA) {
3614                 switch (tp->version) {
3615                 case RTL_VER_01:
3616                 case RTL_VER_02:
3617                 case RTL_VER_07:
3618                         fw_reg = 0xf800;
3619                         bp_ba_addr = PLA_BP_BA;
3620                         bp_en_addr = 0;
3621                         bp_start = PLA_BP_0;
3622                         max_bp = 8;
3623                         break;
3624                 case RTL_VER_03:
3625                 case RTL_VER_04:
3626                 case RTL_VER_05:
3627                 case RTL_VER_06:
3628                 case RTL_VER_08:
3629                 case RTL_VER_09:
3630                         fw_reg = 0xf800;
3631                         bp_ba_addr = PLA_BP_BA;
3632                         bp_en_addr = PLA_BP_EN;
3633                         bp_start = PLA_BP_0;
3634                         max_bp = 8;
3635                         break;
3636                 default:
3637                         goto out;
3638                 }
3639         } else if (type == RTL_FW_USB) {
3640                 switch (tp->version) {
3641                 case RTL_VER_03:
3642                 case RTL_VER_04:
3643                 case RTL_VER_05:
3644                 case RTL_VER_06:
3645                         fw_reg = 0xf800;
3646                         bp_ba_addr = USB_BP_BA;
3647                         bp_en_addr = USB_BP_EN;
3648                         bp_start = USB_BP_0;
3649                         max_bp = 8;
3650                         break;
3651                 case RTL_VER_08:
3652                 case RTL_VER_09:
3653                         fw_reg = 0xe600;
3654                         bp_ba_addr = USB_BP_BA;
3655                         bp_en_addr = USB_BP2_EN;
3656                         bp_start = USB_BP_0;
3657                         max_bp = 16;
3658                         break;
3659                 case RTL_VER_01:
3660                 case RTL_VER_02:
3661                 case RTL_VER_07:
3662                 default:
3663                         goto out;
3664                 }
3665         } else {
3666                 goto out;
3667         }
3668
3669         fw_offset = __le16_to_cpu(mac->fw_offset);
3670         if (fw_offset < sizeof(*mac)) {
3671                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3672                 goto out;
3673         }
3674
3675         length = __le32_to_cpu(mac->blk_hdr.length);
3676         if (length < fw_offset) {
3677                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3678                 goto out;
3679         }
3680
3681         length -= fw_offset;
3682         if (length < 4 || (length & 3)) {
3683                 dev_err(&tp->intf->dev, "invalid block length\n");
3684                 goto out;
3685         }
3686
3687         if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3688                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3689                 goto out;
3690         }
3691
3692         if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3693                 dev_err(&tp->intf->dev, "invalid base address register\n");
3694                 goto out;
3695         }
3696
3697         if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3698                 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3699                 goto out;
3700         }
3701
3702         if (__le16_to_cpu(mac->bp_start) != bp_start) {
3703                 dev_err(&tp->intf->dev,
3704                         "invalid start register of break point\n");
3705                 goto out;
3706         }
3707
3708         if (__le16_to_cpu(mac->bp_num) > max_bp) {
3709                 dev_err(&tp->intf->dev, "invalid break point number\n");
3710                 goto out;
3711         }
3712
3713         for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3714                 if (mac->bp[i]) {
3715                         dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3716                         goto out;
3717                 }
3718         }
3719
3720         rc = true;
3721 out:
3722         return rc;
3723 }
3724
3725 /* Verify the checksum for the firmware file. It is calculated from the version
3726  * field to the end of the file. Compare the result with the checksum field to
3727  * make sure the file is correct.
3728  */
3729 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3730                                        struct fw_header *fw_hdr, size_t size)
3731 {
3732         unsigned char checksum[sizeof(fw_hdr->checksum)];
3733         struct crypto_shash *alg;
3734         struct shash_desc *sdesc;
3735         size_t len;
3736         long rc;
3737
3738         alg = crypto_alloc_shash("sha256", 0, 0);
3739         if (IS_ERR(alg)) {
3740                 rc = PTR_ERR(alg);
3741                 goto out;
3742         }
3743
3744         if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3745                 rc = -EFAULT;
3746                 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3747                         crypto_shash_digestsize(alg));
3748                 goto free_shash;
3749         }
3750
3751         len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3752         sdesc = kmalloc(len, GFP_KERNEL);
3753         if (!sdesc) {
3754                 rc = -ENOMEM;
3755                 goto free_shash;
3756         }
3757         sdesc->tfm = alg;
3758
3759         len = size - sizeof(fw_hdr->checksum);
3760         rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3761         kfree(sdesc);
3762         if (rc)
3763                 goto free_shash;
3764
3765         if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3766                 dev_err(&tp->intf->dev, "checksum fail\n");
3767                 rc = -EFAULT;
3768         }
3769
3770 free_shash:
3771         crypto_free_shash(alg);
3772 out:
3773         return rc;
3774 }
3775
3776 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3777 {
3778         const struct firmware *fw = rtl_fw->fw;
3779         struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3780         struct fw_mac *pla = NULL, *usb = NULL;
3781         struct fw_phy_patch_key *start = NULL;
3782         struct fw_phy_nc *phy_nc = NULL;
3783         struct fw_block *stop = NULL;
3784         long ret = -EFAULT;
3785         int i;
3786
3787         if (fw->size < sizeof(*fw_hdr)) {
3788                 dev_err(&tp->intf->dev, "file too small\n");
3789                 goto fail;
3790         }
3791
3792         ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3793         if (ret)
3794                 goto fail;
3795
3796         ret = -EFAULT;
3797
3798         for (i = sizeof(*fw_hdr); i < fw->size;) {
3799                 struct fw_block *block = (struct fw_block *)&fw->data[i];
3800                 u32 type;
3801
3802                 if ((i + sizeof(*block)) > fw->size)
3803                         goto fail;
3804
3805                 type = __le32_to_cpu(block->type);
3806                 switch (type) {
3807                 case RTL_FW_END:
3808                         if (__le32_to_cpu(block->length) != sizeof(*block))
3809                                 goto fail;
3810                         goto fw_end;
3811                 case RTL_FW_PLA:
3812                         if (pla) {
3813                                 dev_err(&tp->intf->dev,
3814                                         "multiple PLA firmware encountered");
3815                                 goto fail;
3816                         }
3817
3818                         pla = (struct fw_mac *)block;
3819                         if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3820                                 dev_err(&tp->intf->dev,
3821                                         "check PLA firmware failed\n");
3822                                 goto fail;
3823                         }
3824                         break;
3825                 case RTL_FW_USB:
3826                         if (usb) {
3827                                 dev_err(&tp->intf->dev,
3828                                         "multiple USB firmware encountered");
3829                                 goto fail;
3830                         }
3831
3832                         usb = (struct fw_mac *)block;
3833                         if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3834                                 dev_err(&tp->intf->dev,
3835                                         "check USB firmware failed\n");
3836                                 goto fail;
3837                         }
3838                         break;
3839                 case RTL_FW_PHY_START:
3840                         if (start || phy_nc || stop) {
3841                                 dev_err(&tp->intf->dev,
3842                                         "check PHY_START fail\n");
3843                                 goto fail;
3844                         }
3845
3846                         if (__le32_to_cpu(block->length) != sizeof(*start)) {
3847                                 dev_err(&tp->intf->dev,
3848                                         "Invalid length for PHY_START\n");
3849                                 goto fail;
3850                         }
3851
3852                         start = (struct fw_phy_patch_key *)block;
3853                         break;
3854                 case RTL_FW_PHY_STOP:
3855                         if (stop || !start) {
3856                                 dev_err(&tp->intf->dev,
3857                                         "Check PHY_STOP fail\n");
3858                                 goto fail;
3859                         }
3860
3861                         if (__le32_to_cpu(block->length) != sizeof(*block)) {
3862                                 dev_err(&tp->intf->dev,
3863                                         "Invalid length for PHY_STOP\n");
3864                                 goto fail;
3865                         }
3866
3867                         stop = block;
3868                         break;
3869                 case RTL_FW_PHY_NC:
3870                         if (!start || stop) {
3871                                 dev_err(&tp->intf->dev,
3872                                         "check PHY_NC fail\n");
3873                                 goto fail;
3874                         }
3875
3876                         if (phy_nc) {
3877                                 dev_err(&tp->intf->dev,
3878                                         "multiple PHY NC encountered\n");
3879                                 goto fail;
3880                         }
3881
3882                         phy_nc = (struct fw_phy_nc *)block;
3883                         if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3884                                 dev_err(&tp->intf->dev,
3885                                         "check PHY NC firmware failed\n");
3886                                 goto fail;
3887                         }
3888
3889                         break;
3890                 default:
3891                         dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3892                                  type);
3893                         break;
3894                 }
3895
3896                 /* next block */
3897                 i += ALIGN(__le32_to_cpu(block->length), 8);
3898         }
3899
3900 fw_end:
3901         if ((phy_nc || start) && !stop) {
3902                 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3903                 goto fail;
3904         }
3905
3906         return 0;
3907 fail:
3908         return ret;
3909 }
3910
3911 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3912 {
3913         u16 mode_reg, bp_index;
3914         u32 length, i, num;
3915         __le16 *data;
3916
3917         mode_reg = __le16_to_cpu(phy->mode_reg);
3918         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3919         sram_write(tp, __le16_to_cpu(phy->ba_reg),
3920                    __le16_to_cpu(phy->ba_data));
3921
3922         length = __le32_to_cpu(phy->blk_hdr.length);
3923         length -= __le16_to_cpu(phy->fw_offset);
3924         num = length / 2;
3925         data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3926
3927         ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3928         for (i = 0; i < num; i++)
3929                 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3930
3931         sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3932                    __le16_to_cpu(phy->patch_en_value));
3933
3934         bp_index = __le16_to_cpu(phy->bp_start);
3935         num = __le16_to_cpu(phy->bp_num);
3936         for (i = 0; i < num; i++) {
3937                 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3938                 bp_index += 2;
3939         }
3940
3941         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3942
3943         dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3944 }
3945
3946 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3947 {
3948         u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3949         u32 length;
3950         u8 *data;
3951         int i;
3952
3953         switch (__le32_to_cpu(mac->blk_hdr.type)) {
3954         case RTL_FW_PLA:
3955                 type = MCU_TYPE_PLA;
3956                 break;
3957         case RTL_FW_USB:
3958                 type = MCU_TYPE_USB;
3959                 break;
3960         default:
3961                 return;
3962         }
3963
3964         rtl_clear_bp(tp, type);
3965
3966         /* Enable backup/restore of MACDBG. This is required after clearing PLA
3967          * break points and before applying the PLA firmware.
3968          */
3969         if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3970             !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3971                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3972                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3973         }
3974
3975         length = __le32_to_cpu(mac->blk_hdr.length);
3976         length -= __le16_to_cpu(mac->fw_offset);
3977
3978         data = (u8 *)mac;
3979         data += __le16_to_cpu(mac->fw_offset);
3980
3981         generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3982                           type);
3983
3984         ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3985                        __le16_to_cpu(mac->bp_ba_value));
3986
3987         bp_index = __le16_to_cpu(mac->bp_start);
3988         bp_num = __le16_to_cpu(mac->bp_num);
3989         for (i = 0; i < bp_num; i++) {
3990                 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3991                 bp_index += 2;
3992         }
3993
3994         bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3995         if (bp_en_addr)
3996                 ocp_write_word(tp, type, bp_en_addr,
3997                                __le16_to_cpu(mac->bp_en_value));
3998
3999         fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4000         if (fw_ver_reg)
4001                 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4002                                mac->fw_ver_data);
4003
4004         dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4005 }
4006
4007 static void rtl8152_apply_firmware(struct r8152 *tp)
4008 {
4009         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4010         const struct firmware *fw;
4011         struct fw_header *fw_hdr;
4012         struct fw_phy_patch_key *key;
4013         u16 key_addr = 0;
4014         int i;
4015
4016         if (IS_ERR_OR_NULL(rtl_fw->fw))
4017                 return;
4018
4019         fw = rtl_fw->fw;
4020         fw_hdr = (struct fw_header *)fw->data;
4021
4022         if (rtl_fw->pre_fw)
4023                 rtl_fw->pre_fw(tp);
4024
4025         for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4026                 struct fw_block *block = (struct fw_block *)&fw->data[i];
4027
4028                 switch (__le32_to_cpu(block->type)) {
4029                 case RTL_FW_END:
4030                         goto post_fw;
4031                 case RTL_FW_PLA:
4032                 case RTL_FW_USB:
4033                         rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4034                         break;
4035                 case RTL_FW_PHY_START:
4036                         key = (struct fw_phy_patch_key *)block;
4037                         key_addr = __le16_to_cpu(key->key_reg);
4038                         r8153_pre_ram_code(tp, key_addr,
4039                                            __le16_to_cpu(key->key_data));
4040                         break;
4041                 case RTL_FW_PHY_STOP:
4042                         WARN_ON(!key_addr);
4043                         r8153_post_ram_code(tp, key_addr);
4044                         break;
4045                 case RTL_FW_PHY_NC:
4046                         rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4047                         break;
4048                 default:
4049                         break;
4050                 }
4051
4052                 i += ALIGN(__le32_to_cpu(block->length), 8);
4053         }
4054
4055 post_fw:
4056         if (rtl_fw->post_fw)
4057                 rtl_fw->post_fw(tp);
4058
4059         strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4060         dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4061 }
4062
4063 static void rtl8152_release_firmware(struct r8152 *tp)
4064 {
4065         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4066
4067         if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4068                 release_firmware(rtl_fw->fw);
4069                 rtl_fw->fw = NULL;
4070         }
4071 }
4072
4073 static int rtl8152_request_firmware(struct r8152 *tp)
4074 {
4075         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4076         long rc;
4077
4078         if (rtl_fw->fw || !rtl_fw->fw_name) {
4079                 dev_info(&tp->intf->dev, "skip request firmware\n");
4080                 rc = 0;
4081                 goto result;
4082         }
4083
4084         rc = reject_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4085         if (rc < 0)
4086                 goto result;
4087
4088         rc = rtl8152_check_firmware(tp, rtl_fw);
4089         if (rc < 0)
4090                 release_firmware(rtl_fw->fw);
4091
4092 result:
4093         if (rc) {
4094                 rtl_fw->fw = ERR_PTR(rc);
4095
4096                 dev_warn(&tp->intf->dev,
4097                          "unable to load firmware patch %s (%ld)\n",
4098                          rtl_fw->fw_name, rc);
4099         }
4100
4101         return rc;
4102 }
4103
4104 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4105 {
4106         if (enable) {
4107                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4108                                                     LINKENA | DIS_SDSAVE);
4109         } else {
4110                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4111                                                     DIS_SDSAVE);
4112                 msleep(20);
4113         }
4114 }
4115
4116 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4117 {
4118         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4119         ocp_reg_write(tp, OCP_EEE_DATA, reg);
4120         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4121 }
4122
4123 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4124 {
4125         u16 data;
4126
4127         r8152_mmd_indirect(tp, dev, reg);
4128         data = ocp_reg_read(tp, OCP_EEE_DATA);
4129         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4130
4131         return data;
4132 }
4133
4134 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4135 {
4136         r8152_mmd_indirect(tp, dev, reg);
4137         ocp_reg_write(tp, OCP_EEE_DATA, data);
4138         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4139 }
4140
4141 static void r8152_eee_en(struct r8152 *tp, bool enable)
4142 {
4143         u16 config1, config2, config3;
4144         u32 ocp_data;
4145
4146         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4147         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4148         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4149         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4150
4151         if (enable) {
4152                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4153                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4154                 config1 |= sd_rise_time(1);
4155                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4156                 config3 |= fast_snr(42);
4157         } else {
4158                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4159                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4160                              RX_QUIET_EN);
4161                 config1 |= sd_rise_time(7);
4162                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4163                 config3 |= fast_snr(511);
4164         }
4165
4166         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4167         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4168         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4169         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4170 }
4171
4172 static void r8153_eee_en(struct r8152 *tp, bool enable)
4173 {
4174         u32 ocp_data;
4175         u16 config;
4176
4177         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4178         config = ocp_reg_read(tp, OCP_EEE_CFG);
4179
4180         if (enable) {
4181                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4182                 config |= EEE10_EN;
4183         } else {
4184                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4185                 config &= ~EEE10_EN;
4186         }
4187
4188         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4189         ocp_reg_write(tp, OCP_EEE_CFG, config);
4190
4191         tp->ups_info.eee = enable;
4192 }
4193
4194 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4195 {
4196         switch (tp->version) {
4197         case RTL_VER_01:
4198         case RTL_VER_02:
4199         case RTL_VER_07:
4200                 if (enable) {
4201                         r8152_eee_en(tp, true);
4202                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4203                                         tp->eee_adv);
4204                 } else {
4205                         r8152_eee_en(tp, false);
4206                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4207                 }
4208                 break;
4209         case RTL_VER_03:
4210         case RTL_VER_04:
4211         case RTL_VER_05:
4212         case RTL_VER_06:
4213         case RTL_VER_08:
4214         case RTL_VER_09:
4215                 if (enable) {
4216                         r8153_eee_en(tp, true);
4217                         ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4218                 } else {
4219                         r8153_eee_en(tp, false);
4220                         ocp_reg_write(tp, OCP_EEE_ADV, 0);
4221                 }
4222                 break;
4223         default:
4224                 break;
4225         }
4226 }
4227
4228 static void r8152b_enable_fc(struct r8152 *tp)
4229 {
4230         u16 anar;
4231
4232         anar = r8152_mdio_read(tp, MII_ADVERTISE);
4233         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4234         r8152_mdio_write(tp, MII_ADVERTISE, anar);
4235
4236         tp->ups_info.flow_control = true;
4237 }
4238
4239 static void rtl8152_disable(struct r8152 *tp)
4240 {
4241         r8152_aldps_en(tp, false);
4242         rtl_disable(tp);
4243         r8152_aldps_en(tp, true);
4244 }
4245
4246 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4247 {
4248         rtl8152_apply_firmware(tp);
4249         rtl_eee_enable(tp, tp->eee_en);
4250         r8152_aldps_en(tp, true);
4251         r8152b_enable_fc(tp);
4252
4253         set_bit(PHY_RESET, &tp->flags);
4254 }
4255
4256 static void wait_oob_link_list_ready(struct r8152 *tp)
4257 {
4258         u32 ocp_data;
4259         int i;
4260
4261         for (i = 0; i < 1000; i++) {
4262                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4263                 if (ocp_data & LINK_LIST_READY)
4264                         break;
4265                 usleep_range(1000, 2000);
4266         }
4267 }
4268
4269 static void r8152b_exit_oob(struct r8152 *tp)
4270 {
4271         u32 ocp_data;
4272
4273         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4274         ocp_data &= ~RCR_ACPT_ALL;
4275         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4276
4277         rxdy_gated_en(tp, true);
4278         r8153_teredo_off(tp);
4279         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4280         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4281
4282         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4283         ocp_data &= ~NOW_IS_OOB;
4284         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4285
4286         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4287         ocp_data &= ~MCU_BORW_EN;
4288         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4289
4290         wait_oob_link_list_ready(tp);
4291
4292         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4293         ocp_data |= RE_INIT_LL;
4294         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4295
4296         wait_oob_link_list_ready(tp);
4297
4298         rtl8152_nic_reset(tp);
4299
4300         /* rx share fifo credit full threshold */
4301         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4302
4303         if (tp->udev->speed == USB_SPEED_FULL ||
4304             tp->udev->speed == USB_SPEED_LOW) {
4305                 /* rx share fifo credit near full threshold */
4306                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4307                                 RXFIFO_THR2_FULL);
4308                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4309                                 RXFIFO_THR3_FULL);
4310         } else {
4311                 /* rx share fifo credit near full threshold */
4312                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4313                                 RXFIFO_THR2_HIGH);
4314                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4315                                 RXFIFO_THR3_HIGH);
4316         }
4317
4318         /* TX share fifo free credit full threshold */
4319         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4320
4321         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4322         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4323         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4324                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4325
4326         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4327
4328         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4329
4330         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4331         ocp_data |= TCR0_AUTO_FIFO;
4332         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4333 }
4334
4335 static void r8152b_enter_oob(struct r8152 *tp)
4336 {
4337         u32 ocp_data;
4338
4339         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4340         ocp_data &= ~NOW_IS_OOB;
4341         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4342
4343         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4344         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4345         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4346
4347         rtl_disable(tp);
4348
4349         wait_oob_link_list_ready(tp);
4350
4351         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4352         ocp_data |= RE_INIT_LL;
4353         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4354
4355         wait_oob_link_list_ready(tp);
4356
4357         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4358
4359         rtl_rx_vlan_en(tp, true);
4360
4361         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4362         ocp_data |= ALDPS_PROXY_MODE;
4363         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4364
4365         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4366         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4367         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4368
4369         rxdy_gated_en(tp, false);
4370
4371         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4372         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4373         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4374 }
4375
4376 static int r8153_pre_firmware_1(struct r8152 *tp)
4377 {
4378         int i;
4379
4380         /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4381         for (i = 0; i < 104; i++) {
4382                 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4383
4384                 if (!(ocp_data & WTD1_EN))
4385                         break;
4386                 usleep_range(1000, 2000);
4387         }
4388
4389         return 0;
4390 }
4391
4392 static int r8153_post_firmware_1(struct r8152 *tp)
4393 {
4394         /* set USB_BP_4 to support USB_SPEED_SUPER only */
4395         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4396                 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4397
4398         /* reset UPHY timer to 36 ms */
4399         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4400
4401         return 0;
4402 }
4403
4404 static int r8153_pre_firmware_2(struct r8152 *tp)
4405 {
4406         u32 ocp_data;
4407
4408         r8153_pre_firmware_1(tp);
4409
4410         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4411         ocp_data &= ~FW_FIX_SUSPEND;
4412         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4413
4414         return 0;
4415 }
4416
4417 static int r8153_post_firmware_2(struct r8152 *tp)
4418 {
4419         u32 ocp_data;
4420
4421         /* enable bp0 if support USB_SPEED_SUPER only */
4422         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4423                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4424                 ocp_data |= BIT(0);
4425                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4426         }
4427
4428         /* reset UPHY timer to 36 ms */
4429         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4430
4431         /* enable U3P3 check, set the counter to 4 */
4432         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4433
4434         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4435         ocp_data |= FW_FIX_SUSPEND;
4436         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4437
4438         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4439         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4440         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4441
4442         return 0;
4443 }
4444
4445 static int r8153_post_firmware_3(struct r8152 *tp)
4446 {
4447         u32 ocp_data;
4448
4449         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4450         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4451         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4452
4453         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4454         ocp_data |= FW_IP_RESET_EN;
4455         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4456
4457         return 0;
4458 }
4459
4460 static int r8153b_pre_firmware_1(struct r8152 *tp)
4461 {
4462         /* enable fc timer and set timer to 1 second. */
4463         ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4464                        CTRL_TIMER_EN | (1000 / 8));
4465
4466         return 0;
4467 }
4468
4469 static int r8153b_post_firmware_1(struct r8152 *tp)
4470 {
4471         u32 ocp_data;
4472
4473         /* enable bp0 for RTL8153-BND */
4474         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4475         if (ocp_data & BND_MASK) {
4476                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4477                 ocp_data |= BIT(0);
4478                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4479         }
4480
4481         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4482         ocp_data |= FLOW_CTRL_PATCH_OPT;
4483         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4484
4485         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4486         ocp_data |= FC_PATCH_TASK;
4487         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4488
4489         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4490         ocp_data |= FW_IP_RESET_EN;
4491         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4492
4493         return 0;
4494 }
4495
4496 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4497 {
4498         u16 data;
4499
4500         data = ocp_reg_read(tp, OCP_POWER_CFG);
4501         if (enable) {
4502                 data |= EN_ALDPS;
4503                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4504         } else {
4505                 int i;
4506
4507                 data &= ~EN_ALDPS;
4508                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4509                 for (i = 0; i < 20; i++) {
4510                         usleep_range(1000, 2000);
4511                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4512                                 break;
4513                 }
4514         }
4515
4516         tp->ups_info.aldps = enable;
4517 }
4518
4519 static void r8153_hw_phy_cfg(struct r8152 *tp)
4520 {
4521         u32 ocp_data;
4522         u16 data;
4523
4524         /* disable ALDPS before updating the PHY parameters */
4525         r8153_aldps_en(tp, false);
4526
4527         /* disable EEE before updating the PHY parameters */
4528         rtl_eee_enable(tp, false);
4529
4530         rtl8152_apply_firmware(tp);
4531
4532         if (tp->version == RTL_VER_03) {
4533                 data = ocp_reg_read(tp, OCP_EEE_CFG);
4534                 data &= ~CTAP_SHORT_EN;
4535                 ocp_reg_write(tp, OCP_EEE_CFG, data);
4536         }
4537
4538         data = ocp_reg_read(tp, OCP_POWER_CFG);
4539         data |= EEE_CLKDIV_EN;
4540         ocp_reg_write(tp, OCP_POWER_CFG, data);
4541
4542         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4543         data |= EN_10M_BGOFF;
4544         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4545         data = ocp_reg_read(tp, OCP_POWER_CFG);
4546         data |= EN_10M_PLLOFF;
4547         ocp_reg_write(tp, OCP_POWER_CFG, data);
4548         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4549
4550         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4551         ocp_data |= PFM_PWM_SWITCH;
4552         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4553
4554         /* Enable LPF corner auto tune */
4555         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4556
4557         /* Adjust 10M Amplitude */
4558         sram_write(tp, SRAM_10M_AMP1, 0x00af);
4559         sram_write(tp, SRAM_10M_AMP2, 0x0208);
4560
4561         if (tp->eee_en)
4562                 rtl_eee_enable(tp, true);
4563
4564         r8153_aldps_en(tp, true);
4565         r8152b_enable_fc(tp);
4566
4567         switch (tp->version) {
4568         case RTL_VER_03:
4569         case RTL_VER_04:
4570                 break;
4571         case RTL_VER_05:
4572         case RTL_VER_06:
4573         default:
4574                 r8153_u2p3en(tp, true);
4575                 break;
4576         }
4577
4578         set_bit(PHY_RESET, &tp->flags);
4579 }
4580
4581 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4582 {
4583         u32 ocp_data;
4584
4585         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4586         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4587         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
4588         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4589
4590         return ocp_data;
4591 }
4592
4593 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4594 {
4595         u32 ocp_data;
4596         u16 data;
4597
4598         /* disable ALDPS before updating the PHY parameters */
4599         r8153_aldps_en(tp, false);
4600
4601         /* disable EEE before updating the PHY parameters */
4602         rtl_eee_enable(tp, false);
4603
4604         rtl8152_apply_firmware(tp);
4605
4606         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4607
4608         data = sram_read(tp, SRAM_GREEN_CFG);
4609         data |= R_TUNE_EN;
4610         sram_write(tp, SRAM_GREEN_CFG, data);
4611         data = ocp_reg_read(tp, OCP_NCTL_CFG);
4612         data |= PGA_RETURN_EN;
4613         ocp_reg_write(tp, OCP_NCTL_CFG, data);
4614
4615         /* ADC Bias Calibration:
4616          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4617          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4618          * ADC ioffset.
4619          */
4620         ocp_data = r8152_efuse_read(tp, 0x7d);
4621         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4622         if (data != 0xffff)
4623                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4624
4625         /* ups mode tx-link-pulse timing adjustment:
4626          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4627          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4628          */
4629         ocp_data = ocp_reg_read(tp, 0xc426);
4630         ocp_data &= 0x3fff;
4631         if (ocp_data) {
4632                 u32 swr_cnt_1ms_ini;
4633
4634                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4635                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4636                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4637                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4638         }
4639
4640         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4641         ocp_data |= PFM_PWM_SWITCH;
4642         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4643
4644         /* Advnace EEE */
4645         if (!r8153_patch_request(tp, true)) {
4646                 data = ocp_reg_read(tp, OCP_POWER_CFG);
4647                 data |= EEE_CLKDIV_EN;
4648                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4649                 tp->ups_info.eee_ckdiv = true;
4650
4651                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4652                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4653                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4654                 tp->ups_info.eee_cmod_lv = true;
4655                 tp->ups_info._10m_ckdiv = true;
4656                 tp->ups_info.eee_plloff_giga = true;
4657
4658                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4659                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4660                 tp->ups_info._250m_ckdiv = true;
4661
4662                 r8153_patch_request(tp, false);
4663         }
4664
4665         if (tp->eee_en)
4666                 rtl_eee_enable(tp, true);
4667
4668         r8153_aldps_en(tp, true);
4669         r8152b_enable_fc(tp);
4670
4671         set_bit(PHY_RESET, &tp->flags);
4672 }
4673
4674 static void r8153_first_init(struct r8152 *tp)
4675 {
4676         u32 ocp_data;
4677
4678         rxdy_gated_en(tp, true);
4679         r8153_teredo_off(tp);
4680
4681         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4682         ocp_data &= ~RCR_ACPT_ALL;
4683         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4684
4685         rtl8152_nic_reset(tp);
4686         rtl_reset_bmu(tp);
4687
4688         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4689         ocp_data &= ~NOW_IS_OOB;
4690         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4691
4692         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4693         ocp_data &= ~MCU_BORW_EN;
4694         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4695
4696         wait_oob_link_list_ready(tp);
4697
4698         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4699         ocp_data |= RE_INIT_LL;
4700         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4701
4702         wait_oob_link_list_ready(tp);
4703
4704         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4705
4706         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4707         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4708         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4709
4710         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4711         ocp_data |= TCR0_AUTO_FIFO;
4712         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4713
4714         rtl8152_nic_reset(tp);
4715
4716         /* rx share fifo credit full threshold */
4717         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4718         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4719         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4720         /* TX share fifo free credit full threshold */
4721         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4722 }
4723
4724 static void r8153_enter_oob(struct r8152 *tp)
4725 {
4726         u32 ocp_data;
4727
4728         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4729         ocp_data &= ~NOW_IS_OOB;
4730         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4731
4732         rtl_disable(tp);
4733         rtl_reset_bmu(tp);
4734
4735         wait_oob_link_list_ready(tp);
4736
4737         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4738         ocp_data |= RE_INIT_LL;
4739         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4740
4741         wait_oob_link_list_ready(tp);
4742
4743         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4744         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4745
4746         switch (tp->version) {
4747         case RTL_VER_03:
4748         case RTL_VER_04:
4749         case RTL_VER_05:
4750         case RTL_VER_06:
4751                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4752                 ocp_data &= ~TEREDO_WAKE_MASK;
4753                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4754                 break;
4755
4756         case RTL_VER_08:
4757         case RTL_VER_09:
4758                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4759                  * type. Set it to zero. bits[7:0] are the W1C bits about
4760                  * the events. Set them to all 1 to clear them.
4761                  */
4762                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4763                 break;
4764
4765         default:
4766                 break;
4767         }
4768
4769         rtl_rx_vlan_en(tp, true);
4770
4771         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4772         ocp_data |= ALDPS_PROXY_MODE;
4773         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4774
4775         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4776         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4777         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4778
4779         rxdy_gated_en(tp, false);
4780
4781         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4782         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4783         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4784 }
4785
4786 static void rtl8153_disable(struct r8152 *tp)
4787 {
4788         r8153_aldps_en(tp, false);
4789         rtl_disable(tp);
4790         rtl_reset_bmu(tp);
4791         r8153_aldps_en(tp, true);
4792 }
4793
4794 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4795                              u32 advertising)
4796 {
4797         u16 bmcr;
4798         int ret = 0;
4799
4800         if (autoneg == AUTONEG_DISABLE) {
4801                 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4802                         return -EINVAL;
4803
4804                 switch (speed) {
4805                 case SPEED_10:
4806                         bmcr = BMCR_SPEED10;
4807                         if (duplex == DUPLEX_FULL) {
4808                                 bmcr |= BMCR_FULLDPLX;
4809                                 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4810                         } else {
4811                                 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4812                         }
4813                         break;
4814                 case SPEED_100:
4815                         bmcr = BMCR_SPEED100;
4816                         if (duplex == DUPLEX_FULL) {
4817                                 bmcr |= BMCR_FULLDPLX;
4818                                 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4819                         } else {
4820                                 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4821                         }
4822                         break;
4823                 case SPEED_1000:
4824                         if (tp->mii.supports_gmii) {
4825                                 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4826                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4827                                 break;
4828                         }
4829                         fallthrough;
4830                 default:
4831                         ret = -EINVAL;
4832                         goto out;
4833                 }
4834
4835                 if (duplex == DUPLEX_FULL)
4836                         tp->mii.full_duplex = 1;
4837                 else
4838                         tp->mii.full_duplex = 0;
4839
4840                 tp->mii.force_media = 1;
4841         } else {
4842                 u16 anar, tmp1;
4843                 u32 support;
4844
4845                 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4846                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4847
4848                 if (tp->mii.supports_gmii)
4849                         support |= RTL_ADVERTISED_1000_FULL;
4850
4851                 if (!(advertising & support))
4852                         return -EINVAL;
4853
4854                 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4855                 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4856                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
4857                 if (advertising & RTL_ADVERTISED_10_HALF) {
4858                         tmp1 |= ADVERTISE_10HALF;
4859                         tp->ups_info.speed_duplex = NWAY_10M_HALF;
4860                 }
4861                 if (advertising & RTL_ADVERTISED_10_FULL) {
4862                         tmp1 |= ADVERTISE_10FULL;
4863                         tp->ups_info.speed_duplex = NWAY_10M_FULL;
4864                 }
4865
4866                 if (advertising & RTL_ADVERTISED_100_HALF) {
4867                         tmp1 |= ADVERTISE_100HALF;
4868                         tp->ups_info.speed_duplex = NWAY_100M_HALF;
4869                 }
4870                 if (advertising & RTL_ADVERTISED_100_FULL) {
4871                         tmp1 |= ADVERTISE_100FULL;
4872                         tp->ups_info.speed_duplex = NWAY_100M_FULL;
4873                 }
4874
4875                 if (anar != tmp1) {
4876                         r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4877                         tp->mii.advertising = tmp1;
4878                 }
4879
4880                 if (tp->mii.supports_gmii) {
4881                         u16 gbcr;
4882
4883                         gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4884                         tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4885                                         ADVERTISE_1000HALF);
4886
4887                         if (advertising & RTL_ADVERTISED_1000_FULL) {
4888                                 tmp1 |= ADVERTISE_1000FULL;
4889                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4890                         }
4891
4892                         if (gbcr != tmp1)
4893                                 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4894                 }
4895
4896                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4897
4898                 tp->mii.force_media = 0;
4899         }
4900
4901         if (test_and_clear_bit(PHY_RESET, &tp->flags))
4902                 bmcr |= BMCR_RESET;
4903
4904         r8152_mdio_write(tp, MII_BMCR, bmcr);
4905
4906         if (bmcr & BMCR_RESET) {
4907                 int i;
4908
4909                 for (i = 0; i < 50; i++) {
4910                         msleep(20);
4911                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4912                                 break;
4913                 }
4914         }
4915
4916 out:
4917         return ret;
4918 }
4919
4920 static void rtl8152_up(struct r8152 *tp)
4921 {
4922         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4923                 return;
4924
4925         r8152_aldps_en(tp, false);
4926         r8152b_exit_oob(tp);
4927         r8152_aldps_en(tp, true);
4928 }
4929
4930 static void rtl8152_down(struct r8152 *tp)
4931 {
4932         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4933                 rtl_drop_queued_tx(tp);
4934                 return;
4935         }
4936
4937         r8152_power_cut_en(tp, false);
4938         r8152_aldps_en(tp, false);
4939         r8152b_enter_oob(tp);
4940         r8152_aldps_en(tp, true);
4941 }
4942
4943 static void rtl8153_up(struct r8152 *tp)
4944 {
4945         u32 ocp_data;
4946
4947         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4948                 return;
4949
4950         r8153_u1u2en(tp, false);
4951         r8153_u2p3en(tp, false);
4952         r8153_aldps_en(tp, false);
4953         r8153_first_init(tp);
4954
4955         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4956         ocp_data |= LANWAKE_CLR_EN;
4957         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4958
4959         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4960         ocp_data &= ~LANWAKE_PIN;
4961         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4962
4963         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4964         ocp_data &= ~DELAY_PHY_PWR_CHG;
4965         ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4966
4967         r8153_aldps_en(tp, true);
4968
4969         switch (tp->version) {
4970         case RTL_VER_03:
4971         case RTL_VER_04:
4972                 break;
4973         case RTL_VER_05:
4974         case RTL_VER_06:
4975         default:
4976                 r8153_u2p3en(tp, true);
4977                 break;
4978         }
4979
4980         r8153_u1u2en(tp, true);
4981 }
4982
4983 static void rtl8153_down(struct r8152 *tp)
4984 {
4985         u32 ocp_data;
4986
4987         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4988                 rtl_drop_queued_tx(tp);
4989                 return;
4990         }
4991
4992         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4993         ocp_data &= ~LANWAKE_CLR_EN;
4994         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4995
4996         r8153_u1u2en(tp, false);
4997         r8153_u2p3en(tp, false);
4998         r8153_power_cut_en(tp, false);
4999         r8153_aldps_en(tp, false);
5000         r8153_enter_oob(tp);
5001         r8153_aldps_en(tp, true);
5002 }
5003
5004 static void rtl8153b_up(struct r8152 *tp)
5005 {
5006         u32 ocp_data;
5007
5008         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5009                 return;
5010
5011         r8153b_u1u2en(tp, false);
5012         r8153_u2p3en(tp, false);
5013         r8153_aldps_en(tp, false);
5014
5015         r8153_first_init(tp);
5016         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5017
5018         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5019         ocp_data &= ~PLA_MCU_SPDWN_EN;
5020         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5021
5022         r8153_aldps_en(tp, true);
5023
5024         if (tp->udev->speed != USB_SPEED_HIGH)
5025                 r8153b_u1u2en(tp, true);
5026 }
5027
5028 static void rtl8153b_down(struct r8152 *tp)
5029 {
5030         u32 ocp_data;
5031
5032         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5033                 rtl_drop_queued_tx(tp);
5034                 return;
5035         }
5036
5037         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5038         ocp_data |= PLA_MCU_SPDWN_EN;
5039         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5040
5041         r8153b_u1u2en(tp, false);
5042         r8153_u2p3en(tp, false);
5043         r8153b_power_cut_en(tp, false);
5044         r8153_aldps_en(tp, false);
5045         r8153_enter_oob(tp);
5046         r8153_aldps_en(tp, true);
5047 }
5048
5049 static bool rtl8152_in_nway(struct r8152 *tp)
5050 {
5051         u16 nway_state;
5052
5053         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5054         tp->ocp_base = 0x2000;
5055         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
5056         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5057
5058         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5059         if (nway_state & 0xc000)
5060                 return false;
5061         else
5062                 return true;
5063 }
5064
5065 static bool rtl8153_in_nway(struct r8152 *tp)
5066 {
5067         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5068
5069         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5070                 return false;
5071         else
5072                 return true;
5073 }
5074
5075 static void set_carrier(struct r8152 *tp)
5076 {
5077         struct net_device *netdev = tp->netdev;
5078         struct napi_struct *napi = &tp->napi;
5079         u8 speed;
5080
5081         speed = rtl8152_get_speed(tp);
5082
5083         if (speed & LINK_STATUS) {
5084                 if (!netif_carrier_ok(netdev)) {
5085                         tp->rtl_ops.enable(tp);
5086                         netif_stop_queue(netdev);
5087                         napi_disable(napi);
5088                         netif_carrier_on(netdev);
5089                         rtl_start_rx(tp);
5090                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5091                         _rtl8152_set_rx_mode(netdev);
5092                         napi_enable(&tp->napi);
5093                         netif_wake_queue(netdev);
5094                         netif_info(tp, link, netdev, "carrier on\n");
5095                 } else if (netif_queue_stopped(netdev) &&
5096                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5097                         netif_wake_queue(netdev);
5098                 }
5099         } else {
5100                 if (netif_carrier_ok(netdev)) {
5101                         netif_carrier_off(netdev);
5102                         tasklet_disable(&tp->tx_tl);
5103                         napi_disable(napi);
5104                         tp->rtl_ops.disable(tp);
5105                         napi_enable(napi);
5106                         tasklet_enable(&tp->tx_tl);
5107                         netif_info(tp, link, netdev, "carrier off\n");
5108                 }
5109         }
5110 }
5111
5112 static void rtl_work_func_t(struct work_struct *work)
5113 {
5114         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5115
5116         /* If the device is unplugged or !netif_running(), the workqueue
5117          * doesn't need to wake the device, and could return directly.
5118          */
5119         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5120                 return;
5121
5122         if (usb_autopm_get_interface(tp->intf) < 0)
5123                 return;
5124
5125         if (!test_bit(WORK_ENABLE, &tp->flags))
5126                 goto out1;
5127
5128         if (!mutex_trylock(&tp->control)) {
5129                 schedule_delayed_work(&tp->schedule, 0);
5130                 goto out1;
5131         }
5132
5133         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5134                 set_carrier(tp);
5135
5136         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5137                 _rtl8152_set_rx_mode(tp->netdev);
5138
5139         /* don't schedule tasket before linking */
5140         if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5141             netif_carrier_ok(tp->netdev))
5142                 tasklet_schedule(&tp->tx_tl);
5143
5144         mutex_unlock(&tp->control);
5145
5146 out1:
5147         usb_autopm_put_interface(tp->intf);
5148 }
5149
5150 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5151 {
5152         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5153
5154         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5155                 return;
5156
5157         if (usb_autopm_get_interface(tp->intf) < 0)
5158                 return;
5159
5160         mutex_lock(&tp->control);
5161
5162         if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5163                 tp->rtl_fw.retry = false;
5164                 tp->rtl_fw.fw = NULL;
5165
5166                 /* Delay execution in case reject_firmware() is not ready yet.
5167                  */
5168                 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5169                 goto ignore_once;
5170         }
5171
5172         tp->rtl_ops.hw_phy_cfg(tp);
5173
5174         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5175                           tp->advertising);
5176
5177 ignore_once:
5178         mutex_unlock(&tp->control);
5179
5180         usb_autopm_put_interface(tp->intf);
5181 }
5182
5183 #ifdef CONFIG_PM_SLEEP
5184 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5185                         void *data)
5186 {
5187         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5188
5189         switch (action) {
5190         case PM_HIBERNATION_PREPARE:
5191         case PM_SUSPEND_PREPARE:
5192                 usb_autopm_get_interface(tp->intf);
5193                 break;
5194
5195         case PM_POST_HIBERNATION:
5196         case PM_POST_SUSPEND:
5197                 usb_autopm_put_interface(tp->intf);
5198                 break;
5199
5200         case PM_POST_RESTORE:
5201         case PM_RESTORE_PREPARE:
5202         default:
5203                 break;
5204         }
5205
5206         return NOTIFY_DONE;
5207 }
5208 #endif
5209
5210 static int rtl8152_open(struct net_device *netdev)
5211 {
5212         struct r8152 *tp = netdev_priv(netdev);
5213         int res = 0;
5214
5215         if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5216                 cancel_delayed_work_sync(&tp->hw_phy_work);
5217                 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5218         }
5219
5220         res = alloc_all_mem(tp);
5221         if (res)
5222                 goto out;
5223
5224         res = usb_autopm_get_interface(tp->intf);
5225         if (res < 0)
5226                 goto out_free;
5227
5228         mutex_lock(&tp->control);
5229
5230         tp->rtl_ops.up(tp);
5231
5232         netif_carrier_off(netdev);
5233         netif_start_queue(netdev);
5234         set_bit(WORK_ENABLE, &tp->flags);
5235
5236         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5237         if (res) {
5238                 if (res == -ENODEV)
5239                         netif_device_detach(tp->netdev);
5240                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5241                            res);
5242                 goto out_unlock;
5243         }
5244         napi_enable(&tp->napi);
5245         tasklet_enable(&tp->tx_tl);
5246
5247         mutex_unlock(&tp->control);
5248
5249         usb_autopm_put_interface(tp->intf);
5250 #ifdef CONFIG_PM_SLEEP
5251         tp->pm_notifier.notifier_call = rtl_notifier;
5252         register_pm_notifier(&tp->pm_notifier);
5253 #endif
5254         return 0;
5255
5256 out_unlock:
5257         mutex_unlock(&tp->control);
5258         usb_autopm_put_interface(tp->intf);
5259 out_free:
5260         free_all_mem(tp);
5261 out:
5262         return res;
5263 }
5264
5265 static int rtl8152_close(struct net_device *netdev)
5266 {
5267         struct r8152 *tp = netdev_priv(netdev);
5268         int res = 0;
5269
5270 #ifdef CONFIG_PM_SLEEP
5271         unregister_pm_notifier(&tp->pm_notifier);
5272 #endif
5273         tasklet_disable(&tp->tx_tl);
5274         clear_bit(WORK_ENABLE, &tp->flags);
5275         usb_kill_urb(tp->intr_urb);
5276         cancel_delayed_work_sync(&tp->schedule);
5277         napi_disable(&tp->napi);
5278         netif_stop_queue(netdev);
5279
5280         res = usb_autopm_get_interface(tp->intf);
5281         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5282                 rtl_drop_queued_tx(tp);
5283                 rtl_stop_rx(tp);
5284         } else {
5285                 mutex_lock(&tp->control);
5286
5287                 tp->rtl_ops.down(tp);
5288
5289                 mutex_unlock(&tp->control);
5290         }
5291
5292         if (!res)
5293                 usb_autopm_put_interface(tp->intf);
5294
5295         free_all_mem(tp);
5296
5297         return res;
5298 }
5299
5300 static void rtl_tally_reset(struct r8152 *tp)
5301 {
5302         u32 ocp_data;
5303
5304         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5305         ocp_data |= TALLY_RESET;
5306         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5307 }
5308
5309 static void r8152b_init(struct r8152 *tp)
5310 {
5311         u32 ocp_data;
5312         u16 data;
5313
5314         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5315                 return;
5316
5317         data = r8152_mdio_read(tp, MII_BMCR);
5318         if (data & BMCR_PDOWN) {
5319                 data &= ~BMCR_PDOWN;
5320                 r8152_mdio_write(tp, MII_BMCR, data);
5321         }
5322
5323         r8152_aldps_en(tp, false);
5324
5325         if (tp->version == RTL_VER_01) {
5326                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5327                 ocp_data &= ~LED_MODE_MASK;
5328                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5329         }
5330
5331         r8152_power_cut_en(tp, false);
5332
5333         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5334         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5335         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5336         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5337         ocp_data &= ~MCU_CLK_RATIO_MASK;
5338         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5339         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5340         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5341                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5342         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5343
5344         rtl_tally_reset(tp);
5345
5346         /* enable rx aggregation */
5347         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5348         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5349         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5350 }
5351
5352 static void r8153_init(struct r8152 *tp)
5353 {
5354         u32 ocp_data;
5355         u16 data;
5356         int i;
5357
5358         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5359                 return;
5360
5361         r8153_u1u2en(tp, false);
5362
5363         for (i = 0; i < 500; i++) {
5364                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5365                     AUTOLOAD_DONE)
5366                         break;
5367
5368                 msleep(20);
5369                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5370                         break;
5371         }
5372
5373         data = r8153_phy_status(tp, 0);
5374
5375         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5376             tp->version == RTL_VER_05)
5377                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5378
5379         data = r8152_mdio_read(tp, MII_BMCR);
5380         if (data & BMCR_PDOWN) {
5381                 data &= ~BMCR_PDOWN;
5382                 r8152_mdio_write(tp, MII_BMCR, data);
5383         }
5384
5385         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5386
5387         r8153_u2p3en(tp, false);
5388
5389         if (tp->version == RTL_VER_04) {
5390                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5391                 ocp_data &= ~pwd_dn_scale_mask;
5392                 ocp_data |= pwd_dn_scale(96);
5393                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5394
5395                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5396                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5397                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5398         } else if (tp->version == RTL_VER_05) {
5399                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5400                 ocp_data &= ~ECM_ALDPS;
5401                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5402
5403                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5404                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5405                         ocp_data &= ~DYNAMIC_BURST;
5406                 else
5407                         ocp_data |= DYNAMIC_BURST;
5408                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5409         } else if (tp->version == RTL_VER_06) {
5410                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5411                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5412                         ocp_data &= ~DYNAMIC_BURST;
5413                 else
5414                         ocp_data |= DYNAMIC_BURST;
5415                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5416
5417                 r8153_queue_wake(tp, false);
5418
5419                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5420                 if (rtl8152_get_speed(tp) & LINK_STATUS)
5421                         ocp_data |= CUR_LINK_OK;
5422                 else
5423                         ocp_data &= ~CUR_LINK_OK;
5424                 ocp_data |= POLL_LINK_CHG;
5425                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5426         }
5427
5428         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5429         ocp_data |= EP4_FULL_FC;
5430         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5431
5432         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5433         ocp_data &= ~TIMER11_EN;
5434         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5435
5436         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5437         ocp_data &= ~LED_MODE_MASK;
5438         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5439
5440         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5441         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5442                 ocp_data |= LPM_TIMER_500MS;
5443         else
5444                 ocp_data |= LPM_TIMER_500US;
5445         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5446
5447         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5448         ocp_data &= ~SEN_VAL_MASK;
5449         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5450         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5451
5452         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5453
5454         /* MAC clock speed down */
5455         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
5456         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
5457         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
5458         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
5459
5460         r8153_power_cut_en(tp, false);
5461         rtl_runtime_suspend_enable(tp, false);
5462         r8153_u1u2en(tp, true);
5463         usb_enable_lpm(tp->udev);
5464
5465         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5466         ocp_data |= LANWAKE_CLR_EN;
5467         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5468
5469         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5470         ocp_data &= ~LANWAKE_PIN;
5471         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5472
5473         /* rx aggregation */
5474         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5475         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5476         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5477                 ocp_data |= RX_AGG_DISABLE;
5478
5479         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5480
5481         rtl_tally_reset(tp);
5482
5483         switch (tp->udev->speed) {
5484         case USB_SPEED_SUPER:
5485         case USB_SPEED_SUPER_PLUS:
5486                 tp->coalesce = COALESCE_SUPER;
5487                 break;
5488         case USB_SPEED_HIGH:
5489                 tp->coalesce = COALESCE_HIGH;
5490                 break;
5491         default:
5492                 tp->coalesce = COALESCE_SLOW;
5493                 break;
5494         }
5495 }
5496
5497 static void r8153b_init(struct r8152 *tp)
5498 {
5499         u32 ocp_data;
5500         u16 data;
5501         int i;
5502
5503         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5504                 return;
5505
5506         r8153b_u1u2en(tp, false);
5507
5508         for (i = 0; i < 500; i++) {
5509                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5510                     AUTOLOAD_DONE)
5511                         break;
5512
5513                 msleep(20);
5514                 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5515                         break;
5516         }
5517
5518         data = r8153_phy_status(tp, 0);
5519
5520         data = r8152_mdio_read(tp, MII_BMCR);
5521         if (data & BMCR_PDOWN) {
5522                 data &= ~BMCR_PDOWN;
5523                 r8152_mdio_write(tp, MII_BMCR, data);
5524         }
5525
5526         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5527
5528         r8153_u2p3en(tp, false);
5529
5530         /* MSC timer = 0xfff * 8ms = 32760 ms */
5531         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5532
5533         /* U1/U2/L1 idle timer. 500 us */
5534         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5535
5536         r8153b_power_cut_en(tp, false);
5537         r8153b_ups_en(tp, false);
5538         r8153_queue_wake(tp, false);
5539         rtl_runtime_suspend_enable(tp, false);
5540
5541         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5542         if (rtl8152_get_speed(tp) & LINK_STATUS)
5543                 ocp_data |= CUR_LINK_OK;
5544         else
5545                 ocp_data &= ~CUR_LINK_OK;
5546         ocp_data |= POLL_LINK_CHG;
5547         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5548
5549         if (tp->udev->speed != USB_SPEED_HIGH)
5550                 r8153b_u1u2en(tp, true);
5551         usb_enable_lpm(tp->udev);
5552
5553         /* MAC clock speed down */
5554         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5555         ocp_data |= MAC_CLK_SPDWN_EN;
5556         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5557
5558         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5559         ocp_data &= ~PLA_MCU_SPDWN_EN;
5560         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5561
5562         if (tp->version == RTL_VER_09) {
5563                 /* Disable Test IO for 32QFN */
5564                 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5565                         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5566                         ocp_data |= TEST_IO_OFF;
5567                         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5568                 }
5569         }
5570
5571         set_bit(GREEN_ETHERNET, &tp->flags);
5572
5573         /* rx aggregation */
5574         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5575         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5576         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5577
5578         rtl_tally_reset(tp);
5579
5580         tp->coalesce = 15000;   /* 15 us */
5581 }
5582
5583 static int rtl8152_pre_reset(struct usb_interface *intf)
5584 {
5585         struct r8152 *tp = usb_get_intfdata(intf);
5586         struct net_device *netdev;
5587
5588         if (!tp)
5589                 return 0;
5590
5591         netdev = tp->netdev;
5592         if (!netif_running(netdev))
5593                 return 0;
5594
5595         netif_stop_queue(netdev);
5596         tasklet_disable(&tp->tx_tl);
5597         clear_bit(WORK_ENABLE, &tp->flags);
5598         usb_kill_urb(tp->intr_urb);
5599         cancel_delayed_work_sync(&tp->schedule);
5600         napi_disable(&tp->napi);
5601         if (netif_carrier_ok(netdev)) {
5602                 mutex_lock(&tp->control);
5603                 tp->rtl_ops.disable(tp);
5604                 mutex_unlock(&tp->control);
5605         }
5606
5607         return 0;
5608 }
5609
5610 static int rtl8152_post_reset(struct usb_interface *intf)
5611 {
5612         struct r8152 *tp = usb_get_intfdata(intf);
5613         struct net_device *netdev;
5614         struct sockaddr sa;
5615
5616         if (!tp)
5617                 return 0;
5618
5619         /* reset the MAC adddress in case of policy change */
5620         if (determine_ethernet_addr(tp, &sa) >= 0) {
5621                 rtnl_lock();
5622                 dev_set_mac_address (tp->netdev, &sa, NULL);
5623                 rtnl_unlock();
5624         }
5625
5626         netdev = tp->netdev;
5627         if (!netif_running(netdev))
5628                 return 0;
5629
5630         set_bit(WORK_ENABLE, &tp->flags);
5631         if (netif_carrier_ok(netdev)) {
5632                 mutex_lock(&tp->control);
5633                 tp->rtl_ops.enable(tp);
5634                 rtl_start_rx(tp);
5635                 _rtl8152_set_rx_mode(netdev);
5636                 mutex_unlock(&tp->control);
5637         }
5638
5639         napi_enable(&tp->napi);
5640         tasklet_enable(&tp->tx_tl);
5641         netif_wake_queue(netdev);
5642         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5643
5644         if (!list_empty(&tp->rx_done))
5645                 napi_schedule(&tp->napi);
5646
5647         return 0;
5648 }
5649
5650 static bool delay_autosuspend(struct r8152 *tp)
5651 {
5652         bool sw_linking = !!netif_carrier_ok(tp->netdev);
5653         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5654
5655         /* This means a linking change occurs and the driver doesn't detect it,
5656          * yet. If the driver has disabled tx/rx and hw is linking on, the
5657          * device wouldn't wake up by receiving any packet.
5658          */
5659         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5660                 return true;
5661
5662         /* If the linking down is occurred by nway, the device may miss the
5663          * linking change event. And it wouldn't wake when linking on.
5664          */
5665         if (!sw_linking && tp->rtl_ops.in_nway(tp))
5666                 return true;
5667         else if (!skb_queue_empty(&tp->tx_queue))
5668                 return true;
5669         else
5670                 return false;
5671 }
5672
5673 static int rtl8152_runtime_resume(struct r8152 *tp)
5674 {
5675         struct net_device *netdev = tp->netdev;
5676
5677         if (netif_running(netdev) && netdev->flags & IFF_UP) {
5678                 struct napi_struct *napi = &tp->napi;
5679
5680                 tp->rtl_ops.autosuspend_en(tp, false);
5681                 napi_disable(napi);
5682                 set_bit(WORK_ENABLE, &tp->flags);
5683
5684                 if (netif_carrier_ok(netdev)) {
5685                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
5686                                 rtl_start_rx(tp);
5687                         } else {
5688                                 netif_carrier_off(netdev);
5689                                 tp->rtl_ops.disable(tp);
5690                                 netif_info(tp, link, netdev, "linking down\n");
5691                         }
5692                 }
5693
5694                 napi_enable(napi);
5695                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5696                 smp_mb__after_atomic();
5697
5698                 if (!list_empty(&tp->rx_done))
5699                         napi_schedule(&tp->napi);
5700
5701                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5702         } else {
5703                 if (netdev->flags & IFF_UP)
5704                         tp->rtl_ops.autosuspend_en(tp, false);
5705
5706                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5707         }
5708
5709         return 0;
5710 }
5711
5712 static int rtl8152_system_resume(struct r8152 *tp)
5713 {
5714         struct net_device *netdev = tp->netdev;
5715
5716         netif_device_attach(netdev);
5717
5718         if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5719                 tp->rtl_ops.up(tp);
5720                 netif_carrier_off(netdev);
5721                 set_bit(WORK_ENABLE, &tp->flags);
5722                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5723         }
5724
5725         return 0;
5726 }
5727
5728 static int rtl8152_runtime_suspend(struct r8152 *tp)
5729 {
5730         struct net_device *netdev = tp->netdev;
5731         int ret = 0;
5732
5733         set_bit(SELECTIVE_SUSPEND, &tp->flags);
5734         smp_mb__after_atomic();
5735
5736         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5737                 u32 rcr = 0;
5738
5739                 if (netif_carrier_ok(netdev)) {
5740                         u32 ocp_data;
5741
5742                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5743                         ocp_data = rcr & ~RCR_ACPT_ALL;
5744                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5745                         rxdy_gated_en(tp, true);
5746                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5747                                                  PLA_OOB_CTRL);
5748                         if (!(ocp_data & RXFIFO_EMPTY)) {
5749                                 rxdy_gated_en(tp, false);
5750                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5751                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5752                                 smp_mb__after_atomic();
5753                                 ret = -EBUSY;
5754                                 goto out1;
5755                         }
5756                 }
5757
5758                 clear_bit(WORK_ENABLE, &tp->flags);
5759                 usb_kill_urb(tp->intr_urb);
5760
5761                 tp->rtl_ops.autosuspend_en(tp, true);
5762
5763                 if (netif_carrier_ok(netdev)) {
5764                         struct napi_struct *napi = &tp->napi;
5765
5766                         napi_disable(napi);
5767                         rtl_stop_rx(tp);
5768                         rxdy_gated_en(tp, false);
5769                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5770                         napi_enable(napi);
5771                 }
5772
5773                 if (delay_autosuspend(tp)) {
5774                         rtl8152_runtime_resume(tp);
5775                         ret = -EBUSY;
5776                 }
5777         }
5778
5779 out1:
5780         return ret;
5781 }
5782
5783 static int rtl8152_system_suspend(struct r8152 *tp)
5784 {
5785         struct net_device *netdev = tp->netdev;
5786
5787         netif_device_detach(netdev);
5788
5789         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5790                 struct napi_struct *napi = &tp->napi;
5791
5792                 clear_bit(WORK_ENABLE, &tp->flags);
5793                 usb_kill_urb(tp->intr_urb);
5794                 tasklet_disable(&tp->tx_tl);
5795                 napi_disable(napi);
5796                 cancel_delayed_work_sync(&tp->schedule);
5797                 tp->rtl_ops.down(tp);
5798                 napi_enable(napi);
5799                 tasklet_enable(&tp->tx_tl);
5800         }
5801
5802         return 0;
5803 }
5804
5805 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5806 {
5807         struct r8152 *tp = usb_get_intfdata(intf);
5808         int ret;
5809
5810         mutex_lock(&tp->control);
5811
5812         if (PMSG_IS_AUTO(message))
5813                 ret = rtl8152_runtime_suspend(tp);
5814         else
5815                 ret = rtl8152_system_suspend(tp);
5816
5817         mutex_unlock(&tp->control);
5818
5819         return ret;
5820 }
5821
5822 static int rtl8152_resume(struct usb_interface *intf)
5823 {
5824         struct r8152 *tp = usb_get_intfdata(intf);
5825         int ret;
5826
5827         mutex_lock(&tp->control);
5828
5829         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5830                 ret = rtl8152_runtime_resume(tp);
5831         else
5832                 ret = rtl8152_system_resume(tp);
5833
5834         mutex_unlock(&tp->control);
5835
5836         return ret;
5837 }
5838
5839 static int rtl8152_reset_resume(struct usb_interface *intf)
5840 {
5841         struct r8152 *tp = usb_get_intfdata(intf);
5842
5843         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5844         tp->rtl_ops.init(tp);
5845         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5846         set_ethernet_addr(tp);
5847         return rtl8152_resume(intf);
5848 }
5849
5850 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5851 {
5852         struct r8152 *tp = netdev_priv(dev);
5853
5854         if (usb_autopm_get_interface(tp->intf) < 0)
5855                 return;
5856
5857         if (!rtl_can_wakeup(tp)) {
5858                 wol->supported = 0;
5859                 wol->wolopts = 0;
5860         } else {
5861                 mutex_lock(&tp->control);
5862                 wol->supported = WAKE_ANY;
5863                 wol->wolopts = __rtl_get_wol(tp);
5864                 mutex_unlock(&tp->control);
5865         }
5866
5867         usb_autopm_put_interface(tp->intf);
5868 }
5869
5870 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5871 {
5872         struct r8152 *tp = netdev_priv(dev);
5873         int ret;
5874
5875         if (!rtl_can_wakeup(tp))
5876                 return -EOPNOTSUPP;
5877
5878         if (wol->wolopts & ~WAKE_ANY)
5879                 return -EINVAL;
5880
5881         ret = usb_autopm_get_interface(tp->intf);
5882         if (ret < 0)
5883                 goto out_set_wol;
5884
5885         mutex_lock(&tp->control);
5886
5887         __rtl_set_wol(tp, wol->wolopts);
5888         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5889
5890         mutex_unlock(&tp->control);
5891
5892         usb_autopm_put_interface(tp->intf);
5893
5894 out_set_wol:
5895         return ret;
5896 }
5897
5898 static u32 rtl8152_get_msglevel(struct net_device *dev)
5899 {
5900         struct r8152 *tp = netdev_priv(dev);
5901
5902         return tp->msg_enable;
5903 }
5904
5905 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5906 {
5907         struct r8152 *tp = netdev_priv(dev);
5908
5909         tp->msg_enable = value;
5910 }
5911
5912 static void rtl8152_get_drvinfo(struct net_device *netdev,
5913                                 struct ethtool_drvinfo *info)
5914 {
5915         struct r8152 *tp = netdev_priv(netdev);
5916
5917         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5918         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5919         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5920         if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5921                 strlcpy(info->fw_version, tp->rtl_fw.version,
5922                         sizeof(info->fw_version));
5923 }
5924
5925 static
5926 int rtl8152_get_link_ksettings(struct net_device *netdev,
5927                                struct ethtool_link_ksettings *cmd)
5928 {
5929         struct r8152 *tp = netdev_priv(netdev);
5930         int ret;
5931
5932         if (!tp->mii.mdio_read)
5933                 return -EOPNOTSUPP;
5934
5935         ret = usb_autopm_get_interface(tp->intf);
5936         if (ret < 0)
5937                 goto out;
5938
5939         mutex_lock(&tp->control);
5940
5941         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5942
5943         mutex_unlock(&tp->control);
5944
5945         usb_autopm_put_interface(tp->intf);
5946
5947 out:
5948         return ret;
5949 }
5950
5951 static int rtl8152_set_link_ksettings(struct net_device *dev,
5952                                       const struct ethtool_link_ksettings *cmd)
5953 {
5954         struct r8152 *tp = netdev_priv(dev);
5955         u32 advertising = 0;
5956         int ret;
5957
5958         ret = usb_autopm_get_interface(tp->intf);
5959         if (ret < 0)
5960                 goto out;
5961
5962         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5963                      cmd->link_modes.advertising))
5964                 advertising |= RTL_ADVERTISED_10_HALF;
5965
5966         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5967                      cmd->link_modes.advertising))
5968                 advertising |= RTL_ADVERTISED_10_FULL;
5969
5970         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5971                      cmd->link_modes.advertising))
5972                 advertising |= RTL_ADVERTISED_100_HALF;
5973
5974         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5975                      cmd->link_modes.advertising))
5976                 advertising |= RTL_ADVERTISED_100_FULL;
5977
5978         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5979                      cmd->link_modes.advertising))
5980                 advertising |= RTL_ADVERTISED_1000_HALF;
5981
5982         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5983                      cmd->link_modes.advertising))
5984                 advertising |= RTL_ADVERTISED_1000_FULL;
5985
5986         mutex_lock(&tp->control);
5987
5988         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5989                                 cmd->base.duplex, advertising);
5990         if (!ret) {
5991                 tp->autoneg = cmd->base.autoneg;
5992                 tp->speed = cmd->base.speed;
5993                 tp->duplex = cmd->base.duplex;
5994                 tp->advertising = advertising;
5995         }
5996
5997         mutex_unlock(&tp->control);
5998
5999         usb_autopm_put_interface(tp->intf);
6000
6001 out:
6002         return ret;
6003 }
6004
6005 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6006         "tx_packets",
6007         "rx_packets",
6008         "tx_errors",
6009         "rx_errors",
6010         "rx_missed",
6011         "align_errors",
6012         "tx_single_collisions",
6013         "tx_multi_collisions",
6014         "rx_unicast",
6015         "rx_broadcast",
6016         "rx_multicast",
6017         "tx_aborted",
6018         "tx_underrun",
6019 };
6020
6021 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6022 {
6023         switch (sset) {
6024         case ETH_SS_STATS:
6025                 return ARRAY_SIZE(rtl8152_gstrings);
6026         default:
6027                 return -EOPNOTSUPP;
6028         }
6029 }
6030
6031 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6032                                       struct ethtool_stats *stats, u64 *data)
6033 {
6034         struct r8152 *tp = netdev_priv(dev);
6035         struct tally_counter tally;
6036
6037         if (usb_autopm_get_interface(tp->intf) < 0)
6038                 return;
6039
6040         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6041
6042         usb_autopm_put_interface(tp->intf);
6043
6044         data[0] = le64_to_cpu(tally.tx_packets);
6045         data[1] = le64_to_cpu(tally.rx_packets);
6046         data[2] = le64_to_cpu(tally.tx_errors);
6047         data[3] = le32_to_cpu(tally.rx_errors);
6048         data[4] = le16_to_cpu(tally.rx_missed);
6049         data[5] = le16_to_cpu(tally.align_errors);
6050         data[6] = le32_to_cpu(tally.tx_one_collision);
6051         data[7] = le32_to_cpu(tally.tx_multi_collision);
6052         data[8] = le64_to_cpu(tally.rx_unicast);
6053         data[9] = le64_to_cpu(tally.rx_broadcast);
6054         data[10] = le32_to_cpu(tally.rx_multicast);
6055         data[11] = le16_to_cpu(tally.tx_aborted);
6056         data[12] = le16_to_cpu(tally.tx_underrun);
6057 }
6058
6059 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6060 {
6061         switch (stringset) {
6062         case ETH_SS_STATS:
6063                 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
6064                 break;
6065         }
6066 }
6067
6068 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6069 {
6070         u32 lp, adv, supported = 0;
6071         u16 val;
6072
6073         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6074         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6075
6076         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6077         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6078
6079         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6080         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6081
6082         eee->eee_enabled = tp->eee_en;
6083         eee->eee_active = !!(supported & adv & lp);
6084         eee->supported = supported;
6085         eee->advertised = tp->eee_adv;
6086         eee->lp_advertised = lp;
6087
6088         return 0;
6089 }
6090
6091 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6092 {
6093         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6094
6095         tp->eee_en = eee->eee_enabled;
6096         tp->eee_adv = val;
6097
6098         rtl_eee_enable(tp, tp->eee_en);
6099
6100         return 0;
6101 }
6102
6103 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6104 {
6105         u32 lp, adv, supported = 0;
6106         u16 val;
6107
6108         val = ocp_reg_read(tp, OCP_EEE_ABLE);
6109         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6110
6111         val = ocp_reg_read(tp, OCP_EEE_ADV);
6112         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6113
6114         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6115         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6116
6117         eee->eee_enabled = tp->eee_en;
6118         eee->eee_active = !!(supported & adv & lp);
6119         eee->supported = supported;
6120         eee->advertised = tp->eee_adv;
6121         eee->lp_advertised = lp;
6122
6123         return 0;
6124 }
6125
6126 static int
6127 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6128 {
6129         struct r8152 *tp = netdev_priv(net);
6130         int ret;
6131
6132         ret = usb_autopm_get_interface(tp->intf);
6133         if (ret < 0)
6134                 goto out;
6135
6136         mutex_lock(&tp->control);
6137
6138         ret = tp->rtl_ops.eee_get(tp, edata);
6139
6140         mutex_unlock(&tp->control);
6141
6142         usb_autopm_put_interface(tp->intf);
6143
6144 out:
6145         return ret;
6146 }
6147
6148 static int
6149 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6150 {
6151         struct r8152 *tp = netdev_priv(net);
6152         int ret;
6153
6154         ret = usb_autopm_get_interface(tp->intf);
6155         if (ret < 0)
6156                 goto out;
6157
6158         mutex_lock(&tp->control);
6159
6160         ret = tp->rtl_ops.eee_set(tp, edata);
6161         if (!ret)
6162                 ret = mii_nway_restart(&tp->mii);
6163
6164         mutex_unlock(&tp->control);
6165
6166         usb_autopm_put_interface(tp->intf);
6167
6168 out:
6169         return ret;
6170 }
6171
6172 static int rtl8152_nway_reset(struct net_device *dev)
6173 {
6174         struct r8152 *tp = netdev_priv(dev);
6175         int ret;
6176
6177         ret = usb_autopm_get_interface(tp->intf);
6178         if (ret < 0)
6179                 goto out;
6180
6181         mutex_lock(&tp->control);
6182
6183         ret = mii_nway_restart(&tp->mii);
6184
6185         mutex_unlock(&tp->control);
6186
6187         usb_autopm_put_interface(tp->intf);
6188
6189 out:
6190         return ret;
6191 }
6192
6193 static int rtl8152_get_coalesce(struct net_device *netdev,
6194                                 struct ethtool_coalesce *coalesce)
6195 {
6196         struct r8152 *tp = netdev_priv(netdev);
6197
6198         switch (tp->version) {
6199         case RTL_VER_01:
6200         case RTL_VER_02:
6201         case RTL_VER_07:
6202                 return -EOPNOTSUPP;
6203         default:
6204                 break;
6205         }
6206
6207         coalesce->rx_coalesce_usecs = tp->coalesce;
6208
6209         return 0;
6210 }
6211
6212 static int rtl8152_set_coalesce(struct net_device *netdev,
6213                                 struct ethtool_coalesce *coalesce)
6214 {
6215         struct r8152 *tp = netdev_priv(netdev);
6216         int ret;
6217
6218         switch (tp->version) {
6219         case RTL_VER_01:
6220         case RTL_VER_02:
6221         case RTL_VER_07:
6222                 return -EOPNOTSUPP;
6223         default:
6224                 break;
6225         }
6226
6227         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6228                 return -EINVAL;
6229
6230         ret = usb_autopm_get_interface(tp->intf);
6231         if (ret < 0)
6232                 return ret;
6233
6234         mutex_lock(&tp->control);
6235
6236         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6237                 tp->coalesce = coalesce->rx_coalesce_usecs;
6238
6239                 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6240                         netif_stop_queue(netdev);
6241                         napi_disable(&tp->napi);
6242                         tp->rtl_ops.disable(tp);
6243                         tp->rtl_ops.enable(tp);
6244                         rtl_start_rx(tp);
6245                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6246                         _rtl8152_set_rx_mode(netdev);
6247                         napi_enable(&tp->napi);
6248                         netif_wake_queue(netdev);
6249                 }
6250         }
6251
6252         mutex_unlock(&tp->control);
6253
6254         usb_autopm_put_interface(tp->intf);
6255
6256         return ret;
6257 }
6258
6259 static int rtl8152_get_tunable(struct net_device *netdev,
6260                                const struct ethtool_tunable *tunable, void *d)
6261 {
6262         struct r8152 *tp = netdev_priv(netdev);
6263
6264         switch (tunable->id) {
6265         case ETHTOOL_RX_COPYBREAK:
6266                 *(u32 *)d = tp->rx_copybreak;
6267                 break;
6268         default:
6269                 return -EOPNOTSUPP;
6270         }
6271
6272         return 0;
6273 }
6274
6275 static int rtl8152_set_tunable(struct net_device *netdev,
6276                                const struct ethtool_tunable *tunable,
6277                                const void *d)
6278 {
6279         struct r8152 *tp = netdev_priv(netdev);
6280         u32 val;
6281
6282         switch (tunable->id) {
6283         case ETHTOOL_RX_COPYBREAK:
6284                 val = *(u32 *)d;
6285                 if (val < ETH_ZLEN) {
6286                         netif_err(tp, rx_err, netdev,
6287                                   "Invalid rx copy break value\n");
6288                         return -EINVAL;
6289                 }
6290
6291                 if (tp->rx_copybreak != val) {
6292                         if (netdev->flags & IFF_UP) {
6293                                 mutex_lock(&tp->control);
6294                                 napi_disable(&tp->napi);
6295                                 tp->rx_copybreak = val;
6296                                 napi_enable(&tp->napi);
6297                                 mutex_unlock(&tp->control);
6298                         } else {
6299                                 tp->rx_copybreak = val;
6300                         }
6301                 }
6302                 break;
6303         default:
6304                 return -EOPNOTSUPP;
6305         }
6306
6307         return 0;
6308 }
6309
6310 static void rtl8152_get_ringparam(struct net_device *netdev,
6311                                   struct ethtool_ringparam *ring)
6312 {
6313         struct r8152 *tp = netdev_priv(netdev);
6314
6315         ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6316         ring->rx_pending = tp->rx_pending;
6317 }
6318
6319 static int rtl8152_set_ringparam(struct net_device *netdev,
6320                                  struct ethtool_ringparam *ring)
6321 {
6322         struct r8152 *tp = netdev_priv(netdev);
6323
6324         if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6325                 return -EINVAL;
6326
6327         if (tp->rx_pending != ring->rx_pending) {
6328                 if (netdev->flags & IFF_UP) {
6329                         mutex_lock(&tp->control);
6330                         napi_disable(&tp->napi);
6331                         tp->rx_pending = ring->rx_pending;
6332                         napi_enable(&tp->napi);
6333                         mutex_unlock(&tp->control);
6334                 } else {
6335                         tp->rx_pending = ring->rx_pending;
6336                 }
6337         }
6338
6339         return 0;
6340 }
6341
6342 static const struct ethtool_ops ops = {
6343         .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6344         .get_drvinfo = rtl8152_get_drvinfo,
6345         .get_link = ethtool_op_get_link,
6346         .nway_reset = rtl8152_nway_reset,
6347         .get_msglevel = rtl8152_get_msglevel,
6348         .set_msglevel = rtl8152_set_msglevel,
6349         .get_wol = rtl8152_get_wol,
6350         .set_wol = rtl8152_set_wol,
6351         .get_strings = rtl8152_get_strings,
6352         .get_sset_count = rtl8152_get_sset_count,
6353         .get_ethtool_stats = rtl8152_get_ethtool_stats,
6354         .get_coalesce = rtl8152_get_coalesce,
6355         .set_coalesce = rtl8152_set_coalesce,
6356         .get_eee = rtl_ethtool_get_eee,
6357         .set_eee = rtl_ethtool_set_eee,
6358         .get_link_ksettings = rtl8152_get_link_ksettings,
6359         .set_link_ksettings = rtl8152_set_link_ksettings,
6360         .get_tunable = rtl8152_get_tunable,
6361         .set_tunable = rtl8152_set_tunable,
6362         .get_ringparam = rtl8152_get_ringparam,
6363         .set_ringparam = rtl8152_set_ringparam,
6364 };
6365
6366 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6367 {
6368         struct r8152 *tp = netdev_priv(netdev);
6369         struct mii_ioctl_data *data = if_mii(rq);
6370         int res;
6371
6372         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6373                 return -ENODEV;
6374
6375         res = usb_autopm_get_interface(tp->intf);
6376         if (res < 0)
6377                 goto out;
6378
6379         switch (cmd) {
6380         case SIOCGMIIPHY:
6381                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6382                 break;
6383
6384         case SIOCGMIIREG:
6385                 mutex_lock(&tp->control);
6386                 data->val_out = r8152_mdio_read(tp, data->reg_num);
6387                 mutex_unlock(&tp->control);
6388                 break;
6389
6390         case SIOCSMIIREG:
6391                 if (!capable(CAP_NET_ADMIN)) {
6392                         res = -EPERM;
6393                         break;
6394                 }
6395                 mutex_lock(&tp->control);
6396                 r8152_mdio_write(tp, data->reg_num, data->val_in);
6397                 mutex_unlock(&tp->control);
6398                 break;
6399
6400         default:
6401                 res = -EOPNOTSUPP;
6402         }
6403
6404         usb_autopm_put_interface(tp->intf);
6405
6406 out:
6407         return res;
6408 }
6409
6410 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6411 {
6412         struct r8152 *tp = netdev_priv(dev);
6413         int ret;
6414
6415         switch (tp->version) {
6416         case RTL_VER_01:
6417         case RTL_VER_02:
6418         case RTL_VER_07:
6419                 dev->mtu = new_mtu;
6420                 return 0;
6421         default:
6422                 break;
6423         }
6424
6425         ret = usb_autopm_get_interface(tp->intf);
6426         if (ret < 0)
6427                 return ret;
6428
6429         mutex_lock(&tp->control);
6430
6431         dev->mtu = new_mtu;
6432
6433         if (netif_running(dev)) {
6434                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6435
6436                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6437
6438                 if (netif_carrier_ok(dev))
6439                         r8153_set_rx_early_size(tp);
6440         }
6441
6442         mutex_unlock(&tp->control);
6443
6444         usb_autopm_put_interface(tp->intf);
6445
6446         return ret;
6447 }
6448
6449 static const struct net_device_ops rtl8152_netdev_ops = {
6450         .ndo_open               = rtl8152_open,
6451         .ndo_stop               = rtl8152_close,
6452         .ndo_do_ioctl           = rtl8152_ioctl,
6453         .ndo_start_xmit         = rtl8152_start_xmit,
6454         .ndo_tx_timeout         = rtl8152_tx_timeout,
6455         .ndo_set_features       = rtl8152_set_features,
6456         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
6457         .ndo_set_mac_address    = rtl8152_set_mac_address,
6458         .ndo_change_mtu         = rtl8152_change_mtu,
6459         .ndo_validate_addr      = eth_validate_addr,
6460         .ndo_features_check     = rtl8152_features_check,
6461 };
6462
6463 static void rtl8152_unload(struct r8152 *tp)
6464 {
6465         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6466                 return;
6467
6468         if (tp->version != RTL_VER_01)
6469                 r8152_power_cut_en(tp, true);
6470 }
6471
6472 static void rtl8153_unload(struct r8152 *tp)
6473 {
6474         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6475                 return;
6476
6477         r8153_power_cut_en(tp, false);
6478 }
6479
6480 static void rtl8153b_unload(struct r8152 *tp)
6481 {
6482         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6483                 return;
6484
6485         r8153b_power_cut_en(tp, false);
6486 }
6487
6488 static int rtl_ops_init(struct r8152 *tp)
6489 {
6490         struct rtl_ops *ops = &tp->rtl_ops;
6491         int ret = 0;
6492
6493         switch (tp->version) {
6494         case RTL_VER_01:
6495         case RTL_VER_02:
6496         case RTL_VER_07:
6497                 ops->init               = r8152b_init;
6498                 ops->enable             = rtl8152_enable;
6499                 ops->disable            = rtl8152_disable;
6500                 ops->up                 = rtl8152_up;
6501                 ops->down               = rtl8152_down;
6502                 ops->unload             = rtl8152_unload;
6503                 ops->eee_get            = r8152_get_eee;
6504                 ops->eee_set            = r8152_set_eee;
6505                 ops->in_nway            = rtl8152_in_nway;
6506                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
6507                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
6508                 tp->rx_buf_sz           = 16 * 1024;
6509                 tp->eee_en              = true;
6510                 tp->eee_adv             = MDIO_EEE_100TX;
6511                 break;
6512
6513         case RTL_VER_03:
6514         case RTL_VER_04:
6515         case RTL_VER_05:
6516         case RTL_VER_06:
6517                 ops->init               = r8153_init;
6518                 ops->enable             = rtl8153_enable;
6519                 ops->disable            = rtl8153_disable;
6520                 ops->up                 = rtl8153_up;
6521                 ops->down               = rtl8153_down;
6522                 ops->unload             = rtl8153_unload;
6523                 ops->eee_get            = r8153_get_eee;
6524                 ops->eee_set            = r8152_set_eee;
6525                 ops->in_nway            = rtl8153_in_nway;
6526                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
6527                 ops->autosuspend_en     = rtl8153_runtime_enable;
6528                 if (tp->udev->speed < USB_SPEED_SUPER)
6529                         tp->rx_buf_sz   = 16 * 1024;
6530                 else
6531                         tp->rx_buf_sz   = 32 * 1024;
6532                 tp->eee_en              = true;
6533                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6534                 break;
6535
6536         case RTL_VER_08:
6537         case RTL_VER_09:
6538                 ops->init               = r8153b_init;
6539                 ops->enable             = rtl8153_enable;
6540                 ops->disable            = rtl8153_disable;
6541                 ops->up                 = rtl8153b_up;
6542                 ops->down               = rtl8153b_down;
6543                 ops->unload             = rtl8153b_unload;
6544                 ops->eee_get            = r8153_get_eee;
6545                 ops->eee_set            = r8152_set_eee;
6546                 ops->in_nway            = rtl8153_in_nway;
6547                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
6548                 ops->autosuspend_en     = rtl8153b_runtime_enable;
6549                 tp->rx_buf_sz           = 32 * 1024;
6550                 tp->eee_en              = true;
6551                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6552                 break;
6553
6554         default:
6555                 ret = -ENODEV;
6556                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6557                 break;
6558         }
6559
6560         return ret;
6561 }
6562
6563 #define FIRMWARE_8153A_2        "/*(DEBLOBBED)*/"
6564 #define FIRMWARE_8153A_3        "/*(DEBLOBBED)*/"
6565 #define FIRMWARE_8153A_4        "/*(DEBLOBBED)*/"
6566 #define FIRMWARE_8153B_2        "/*(DEBLOBBED)*/"
6567
6568 /*(DEBLOBBED)*/
6569
6570 static int rtl_fw_init(struct r8152 *tp)
6571 {
6572         struct rtl_fw *rtl_fw = &tp->rtl_fw;
6573
6574         switch (tp->version) {
6575         case RTL_VER_04:
6576                 rtl_fw->fw_name         = FIRMWARE_8153A_2;
6577                 rtl_fw->pre_fw          = r8153_pre_firmware_1;
6578                 rtl_fw->post_fw         = r8153_post_firmware_1;
6579                 break;
6580         case RTL_VER_05:
6581                 rtl_fw->fw_name         = FIRMWARE_8153A_3;
6582                 rtl_fw->pre_fw          = r8153_pre_firmware_2;
6583                 rtl_fw->post_fw         = r8153_post_firmware_2;
6584                 break;
6585         case RTL_VER_06:
6586                 rtl_fw->fw_name         = FIRMWARE_8153A_4;
6587                 rtl_fw->post_fw         = r8153_post_firmware_3;
6588                 break;
6589         case RTL_VER_09:
6590                 rtl_fw->fw_name         = FIRMWARE_8153B_2;
6591                 rtl_fw->pre_fw          = r8153b_pre_firmware_1;
6592                 rtl_fw->post_fw         = r8153b_post_firmware_1;
6593                 break;
6594         default:
6595                 break;
6596         }
6597
6598         return 0;
6599 }
6600
6601 static u8 rtl_get_version(struct usb_interface *intf)
6602 {
6603         struct usb_device *udev = interface_to_usbdev(intf);
6604         u32 ocp_data = 0;
6605         __le32 *tmp;
6606         u8 version;
6607         int ret;
6608
6609         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6610         if (!tmp)
6611                 return 0;
6612
6613         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6614                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6615                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),
6616                               USB_CTRL_GET_TIMEOUT);
6617         if (ret > 0)
6618                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6619
6620         kfree(tmp);
6621
6622         switch (ocp_data) {
6623         case 0x4c00:
6624                 version = RTL_VER_01;
6625                 break;
6626         case 0x4c10:
6627                 version = RTL_VER_02;
6628                 break;
6629         case 0x5c00:
6630                 version = RTL_VER_03;
6631                 break;
6632         case 0x5c10:
6633                 version = RTL_VER_04;
6634                 break;
6635         case 0x5c20:
6636                 version = RTL_VER_05;
6637                 break;
6638         case 0x5c30:
6639                 version = RTL_VER_06;
6640                 break;
6641         case 0x4800:
6642                 version = RTL_VER_07;
6643                 break;
6644         case 0x6000:
6645                 version = RTL_VER_08;
6646                 break;
6647         case 0x6010:
6648                 version = RTL_VER_09;
6649                 break;
6650         default:
6651                 version = RTL_VER_UNKNOWN;
6652                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6653                 break;
6654         }
6655
6656         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6657
6658         return version;
6659 }
6660
6661 static int rtl8152_probe(struct usb_interface *intf,
6662                          const struct usb_device_id *id)
6663 {
6664         struct usb_device *udev = interface_to_usbdev(intf);
6665         u8 version = rtl_get_version(intf);
6666         struct r8152 *tp;
6667         struct net_device *netdev;
6668         int ret;
6669
6670         if (version == RTL_VER_UNKNOWN)
6671                 return -ENODEV;
6672
6673         if (udev->actconfig->desc.bConfigurationValue != 1) {
6674                 usb_driver_set_configuration(udev, 1);
6675                 return -ENODEV;
6676         }
6677
6678         if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6679                 return -ENODEV;
6680
6681         usb_reset_device(udev);
6682         netdev = alloc_etherdev(sizeof(struct r8152));
6683         if (!netdev) {
6684                 dev_err(&intf->dev, "Out of memory\n");
6685                 return -ENOMEM;
6686         }
6687
6688         SET_NETDEV_DEV(netdev, &intf->dev);
6689         tp = netdev_priv(netdev);
6690         tp->msg_enable = 0x7FFF;
6691
6692         tp->udev = udev;
6693         tp->netdev = netdev;
6694         tp->intf = intf;
6695         tp->version = version;
6696
6697         switch (version) {
6698         case RTL_VER_01:
6699         case RTL_VER_02:
6700         case RTL_VER_07:
6701                 tp->mii.supports_gmii = 0;
6702                 break;
6703         default:
6704                 tp->mii.supports_gmii = 1;
6705                 break;
6706         }
6707
6708         ret = rtl_ops_init(tp);
6709         if (ret)
6710                 goto out;
6711
6712         rtl_fw_init(tp);
6713
6714         mutex_init(&tp->control);
6715         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6716         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6717         tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6718         tasklet_disable(&tp->tx_tl);
6719
6720         netdev->netdev_ops = &rtl8152_netdev_ops;
6721         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6722
6723         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6724                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6725                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6726                             NETIF_F_HW_VLAN_CTAG_TX;
6727         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6728                               NETIF_F_TSO | NETIF_F_FRAGLIST |
6729                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6730                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6731         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6732                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6733                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6734
6735         if (tp->version == RTL_VER_01) {
6736                 netdev->features &= ~NETIF_F_RXCSUM;
6737                 netdev->hw_features &= ~NETIF_F_RXCSUM;
6738         }
6739
6740         if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6741                 switch (le16_to_cpu(udev->descriptor.idProduct)) {
6742                 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6743                 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6744                         set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6745                 }
6746         }
6747
6748         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6749             (!strcmp(udev->serial, "000001000000") ||
6750              !strcmp(udev->serial, "000002000000"))) {
6751                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6752                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6753         }
6754
6755         netdev->ethtool_ops = &ops;
6756         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6757
6758         /* MTU range: 68 - 1500 or 9194 */
6759         netdev->min_mtu = ETH_MIN_MTU;
6760         switch (tp->version) {
6761         case RTL_VER_01:
6762         case RTL_VER_02:
6763                 netdev->max_mtu = ETH_DATA_LEN;
6764                 break;
6765         default:
6766                 netdev->max_mtu = RTL8153_MAX_MTU;
6767                 break;
6768         }
6769
6770         tp->mii.dev = netdev;
6771         tp->mii.mdio_read = read_mii_word;
6772         tp->mii.mdio_write = write_mii_word;
6773         tp->mii.phy_id_mask = 0x3f;
6774         tp->mii.reg_num_mask = 0x1f;
6775         tp->mii.phy_id = R8152_PHY_ID;
6776
6777         tp->autoneg = AUTONEG_ENABLE;
6778         tp->speed = SPEED_100;
6779         tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6780                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6781         if (tp->mii.supports_gmii) {
6782                 tp->speed = SPEED_1000;
6783                 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6784         }
6785         tp->duplex = DUPLEX_FULL;
6786
6787         tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6788         tp->rx_pending = 10 * RTL8152_MAX_RX;
6789
6790         intf->needs_remote_wakeup = 1;
6791
6792         if (!rtl_can_wakeup(tp))
6793                 __rtl_set_wol(tp, 0);
6794         else
6795                 tp->saved_wolopts = __rtl_get_wol(tp);
6796
6797         tp->rtl_ops.init(tp);
6798 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6799         /* Retry in case reject_firmware() is not ready yet. */
6800         tp->rtl_fw.retry = true;
6801 #endif
6802         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6803         set_ethernet_addr(tp);
6804
6805         usb_set_intfdata(intf, tp);
6806         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6807
6808         ret = register_netdev(netdev);
6809         if (ret != 0) {
6810                 netif_err(tp, probe, netdev, "couldn't register the device\n");
6811                 goto out1;
6812         }
6813
6814         if (tp->saved_wolopts)
6815                 device_set_wakeup_enable(&udev->dev, true);
6816         else
6817                 device_set_wakeup_enable(&udev->dev, false);
6818
6819         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6820
6821         return 0;
6822
6823 out1:
6824         tasklet_kill(&tp->tx_tl);
6825         cancel_delayed_work_sync(&tp->hw_phy_work);
6826         if (tp->rtl_ops.unload)
6827                 tp->rtl_ops.unload(tp);
6828         rtl8152_release_firmware(tp);
6829         usb_set_intfdata(intf, NULL);
6830 out:
6831         free_netdev(netdev);
6832         return ret;
6833 }
6834
6835 static void rtl8152_disconnect(struct usb_interface *intf)
6836 {
6837         struct r8152 *tp = usb_get_intfdata(intf);
6838
6839         usb_set_intfdata(intf, NULL);
6840         if (tp) {
6841                 rtl_set_unplug(tp);
6842
6843                 unregister_netdev(tp->netdev);
6844                 tasklet_kill(&tp->tx_tl);
6845                 cancel_delayed_work_sync(&tp->hw_phy_work);
6846                 tp->rtl_ops.unload(tp);
6847                 rtl8152_release_firmware(tp);
6848                 free_netdev(tp->netdev);
6849         }
6850 }
6851
6852 #define REALTEK_USB_DEVICE(vend, prod)  \
6853         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6854                        USB_DEVICE_ID_MATCH_INT_CLASS, \
6855         .idVendor = (vend), \
6856         .idProduct = (prod), \
6857         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6858 }, \
6859 { \
6860         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6861                        USB_DEVICE_ID_MATCH_DEVICE, \
6862         .idVendor = (vend), \
6863         .idProduct = (prod), \
6864         .bInterfaceClass = USB_CLASS_COMM, \
6865         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6866         .bInterfaceProtocol = USB_CDC_PROTO_NONE
6867
6868 /* table of devices that work with this driver */
6869 static const struct usb_device_id rtl8152_table[] = {
6870         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6871         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6872         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6873         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6874         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6875         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6876         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6877         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6878         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3054)},
6879         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6880         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6881         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082)},
6882         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6883         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6884         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6885         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x721e)},
6886         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
6887         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6888         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6889         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6890         {}
6891 };
6892
6893 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6894
6895 static struct usb_driver rtl8152_driver = {
6896         .name =         MODULENAME,
6897         .id_table =     rtl8152_table,
6898         .probe =        rtl8152_probe,
6899         .disconnect =   rtl8152_disconnect,
6900         .suspend =      rtl8152_suspend,
6901         .resume =       rtl8152_resume,
6902         .reset_resume = rtl8152_reset_resume,
6903         .pre_reset =    rtl8152_pre_reset,
6904         .post_reset =   rtl8152_post_reset,
6905         .supports_autosuspend = 1,
6906         .disable_hub_initiated_lpm = 1,
6907 };
6908
6909 module_usb_driver(rtl8152_driver);
6910
6911 MODULE_AUTHOR(DRIVER_AUTHOR);
6912 MODULE_DESCRIPTION(DRIVER_DESC);
6913 MODULE_LICENSE("GPL");
6914 MODULE_VERSION(DRIVER_VERSION);