1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
30 /* Information for net-next */
31 #define NETNEXT_VERSION "11"
33 /* Information for net */
34 #define NET_VERSION "11"
36 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
41 #define R8152_PHY_ID 32
43 #define PLA_IDR 0xc000
44 #define PLA_RCR 0xc010
45 #define PLA_RMS 0xc016
46 #define PLA_RXFIFO_CTRL0 0xc0a0
47 #define PLA_RXFIFO_CTRL1 0xc0a4
48 #define PLA_RXFIFO_CTRL2 0xc0a8
49 #define PLA_DMY_REG0 0xc0b0
50 #define PLA_FMC 0xc0b4
51 #define PLA_CFG_WOL 0xc0b6
52 #define PLA_TEREDO_CFG 0xc0bc
53 #define PLA_TEREDO_WAKE_BASE 0xc0c4
54 #define PLA_MAR 0xcd00
55 #define PLA_BACKUP 0xd000
56 #define PLA_BDC_CR 0xd1a0
57 #define PLA_TEREDO_TIMER 0xd2cc
58 #define PLA_REALWOW_TIMER 0xd2e8
59 #define PLA_UPHY_TIMER 0xd388
60 #define PLA_SUSPEND_FLAG 0xd38a
61 #define PLA_INDICATE_FALG 0xd38c
62 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
63 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS 0xd398
65 #define PLA_EFUSE_DATA 0xdd00
66 #define PLA_EFUSE_CMD 0xdd02
67 #define PLA_LEDSEL 0xdd90
68 #define PLA_LED_FEATURE 0xdd92
69 #define PLA_PHYAR 0xde00
70 #define PLA_BOOT_CTRL 0xe004
71 #define PLA_LWAKE_CTRL_REG 0xe007
72 #define PLA_GPHY_INTR_IMR 0xe022
73 #define PLA_EEE_CR 0xe040
74 #define PLA_EEEP_CR 0xe080
75 #define PLA_MAC_PWR_CTRL 0xe0c0
76 #define PLA_MAC_PWR_CTRL2 0xe0ca
77 #define PLA_MAC_PWR_CTRL3 0xe0cc
78 #define PLA_MAC_PWR_CTRL4 0xe0ce
79 #define PLA_WDT6_CTRL 0xe428
80 #define PLA_TCR0 0xe610
81 #define PLA_TCR1 0xe612
82 #define PLA_MTPS 0xe615
83 #define PLA_TXFIFO_CTRL 0xe618
84 #define PLA_RSTTALLY 0xe800
86 #define PLA_CRWECR 0xe81c
87 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
88 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
89 #define PLA_CONFIG5 0xe822
90 #define PLA_PHY_PWR 0xe84c
91 #define PLA_OOB_CTRL 0xe84f
92 #define PLA_CPCR 0xe854
93 #define PLA_MISC_0 0xe858
94 #define PLA_MISC_1 0xe85a
95 #define PLA_OCP_GPHY_BASE 0xe86c
96 #define PLA_TALLYCNT 0xe890
97 #define PLA_SFF_STS_7 0xe8de
98 #define PLA_PHYSTATUS 0xe908
99 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
100 #define PLA_BP_BA 0xfc26
101 #define PLA_BP_0 0xfc28
102 #define PLA_BP_1 0xfc2a
103 #define PLA_BP_2 0xfc2c
104 #define PLA_BP_3 0xfc2e
105 #define PLA_BP_4 0xfc30
106 #define PLA_BP_5 0xfc32
107 #define PLA_BP_6 0xfc34
108 #define PLA_BP_7 0xfc36
109 #define PLA_BP_EN 0xfc38
111 #define USB_USB2PHY 0xb41e
112 #define USB_SSPHYLINK1 0xb426
113 #define USB_SSPHYLINK2 0xb428
114 #define USB_U2P3_CTRL 0xb460
115 #define USB_CSR_DUMMY1 0xb464
116 #define USB_CSR_DUMMY2 0xb466
117 #define USB_DEV_STAT 0xb808
118 #define USB_CONNECT_TIMER 0xcbf8
119 #define USB_MSC_TIMER 0xcbfc
120 #define USB_BURST_SIZE 0xcfc0
121 #define USB_FW_FIX_EN0 0xcfca
122 #define USB_FW_FIX_EN1 0xcfcc
123 #define USB_LPM_CONFIG 0xcfd8
124 #define USB_CSTMR 0xcfef /* RTL8153A */
125 #define USB_FW_CTRL 0xd334 /* RTL8153B */
126 #define USB_FC_TIMER 0xd340
127 #define USB_USB_CTRL 0xd406
128 #define USB_PHY_CTRL 0xd408
129 #define USB_TX_AGG 0xd40a
130 #define USB_RX_BUF_TH 0xd40c
131 #define USB_USB_TIMER 0xd428
132 #define USB_RX_EARLY_TIMEOUT 0xd42c
133 #define USB_RX_EARLY_SIZE 0xd42e
134 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
135 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
136 #define USB_TX_DMA 0xd434
137 #define USB_UPT_RXDMA_OWN 0xd437
138 #define USB_TOLERANCE 0xd490
139 #define USB_LPM_CTRL 0xd41a
140 #define USB_BMU_RESET 0xd4b0
141 #define USB_U1U2_TIMER 0xd4da
142 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
143 #define USB_UPS_CTRL 0xd800
144 #define USB_POWER_CUT 0xd80a
145 #define USB_MISC_0 0xd81a
146 #define USB_MISC_1 0xd81f
147 #define USB_AFE_CTRL2 0xd824
148 #define USB_UPS_CFG 0xd842
149 #define USB_UPS_FLAGS 0xd848
150 #define USB_WDT1_CTRL 0xe404
151 #define USB_WDT11_CTRL 0xe43c
152 #define USB_BP_BA PLA_BP_BA
153 #define USB_BP_0 PLA_BP_0
154 #define USB_BP_1 PLA_BP_1
155 #define USB_BP_2 PLA_BP_2
156 #define USB_BP_3 PLA_BP_3
157 #define USB_BP_4 PLA_BP_4
158 #define USB_BP_5 PLA_BP_5
159 #define USB_BP_6 PLA_BP_6
160 #define USB_BP_7 PLA_BP_7
161 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
162 #define USB_BP_8 0xfc38 /* RTL8153B */
163 #define USB_BP_9 0xfc3a
164 #define USB_BP_10 0xfc3c
165 #define USB_BP_11 0xfc3e
166 #define USB_BP_12 0xfc40
167 #define USB_BP_13 0xfc42
168 #define USB_BP_14 0xfc44
169 #define USB_BP_15 0xfc46
170 #define USB_BP2_EN 0xfc48
173 #define OCP_ALDPS_CONFIG 0x2010
174 #define OCP_EEE_CONFIG1 0x2080
175 #define OCP_EEE_CONFIG2 0x2092
176 #define OCP_EEE_CONFIG3 0x2094
177 #define OCP_BASE_MII 0xa400
178 #define OCP_EEE_AR 0xa41a
179 #define OCP_EEE_DATA 0xa41c
180 #define OCP_PHY_STATUS 0xa420
181 #define OCP_NCTL_CFG 0xa42c
182 #define OCP_POWER_CFG 0xa430
183 #define OCP_EEE_CFG 0xa432
184 #define OCP_SRAM_ADDR 0xa436
185 #define OCP_SRAM_DATA 0xa438
186 #define OCP_DOWN_SPEED 0xa442
187 #define OCP_EEE_ABLE 0xa5c4
188 #define OCP_EEE_ADV 0xa5d0
189 #define OCP_EEE_LPABLE 0xa5d2
190 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
191 #define OCP_PHY_PATCH_STAT 0xb800
192 #define OCP_PHY_PATCH_CMD 0xb820
193 #define OCP_PHY_LOCK 0xb82e
194 #define OCP_ADC_IOFFSET 0xbcfc
195 #define OCP_ADC_CFG 0xbc06
196 #define OCP_SYSCLK_CFG 0xc416
199 #define SRAM_GREEN_CFG 0x8011
200 #define SRAM_LPF_CFG 0x8012
201 #define SRAM_10M_AMP1 0x8080
202 #define SRAM_10M_AMP2 0x8082
203 #define SRAM_IMPEDANCE 0x8084
204 #define SRAM_PHY_LOCK 0xb82e
207 #define RCR_AAP 0x00000001
208 #define RCR_APM 0x00000002
209 #define RCR_AM 0x00000004
210 #define RCR_AB 0x00000008
211 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
213 /* PLA_RXFIFO_CTRL0 */
214 #define RXFIFO_THR1_NORMAL 0x00080002
215 #define RXFIFO_THR1_OOB 0x01800003
217 /* PLA_RXFIFO_CTRL1 */
218 #define RXFIFO_THR2_FULL 0x00000060
219 #define RXFIFO_THR2_HIGH 0x00000038
220 #define RXFIFO_THR2_OOB 0x0000004a
221 #define RXFIFO_THR2_NORMAL 0x00a0
223 /* PLA_RXFIFO_CTRL2 */
224 #define RXFIFO_THR3_FULL 0x00000078
225 #define RXFIFO_THR3_HIGH 0x00000048
226 #define RXFIFO_THR3_OOB 0x0000005a
227 #define RXFIFO_THR3_NORMAL 0x0110
229 /* PLA_TXFIFO_CTRL */
230 #define TXFIFO_THR_NORMAL 0x00400008
231 #define TXFIFO_THR_NORMAL2 0x01000008
234 #define ECM_ALDPS 0x0002
237 #define FMC_FCR_MCU_EN 0x0001
240 #define EEEP_CR_EEEP_TX 0x0002
243 #define WDT6_SET_MODE 0x0010
246 #define TCR0_TX_EMPTY 0x0800
247 #define TCR0_AUTO_FIFO 0x0080
250 #define VERSION_MASK 0x7cf0
253 #define MTPS_JUMBO (12 * 1024 / 64)
254 #define MTPS_DEFAULT (6 * 1024 / 64)
257 #define TALLY_RESET 0x0001
265 #define CRWECR_NORAML 0x00
266 #define CRWECR_CONFIG 0xc0
269 #define NOW_IS_OOB 0x80
270 #define TXFIFO_EMPTY 0x20
271 #define RXFIFO_EMPTY 0x10
272 #define LINK_LIST_READY 0x02
273 #define DIS_MCU_CLROOB 0x01
274 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
277 #define RXDY_GATED_EN 0x0008
280 #define RE_INIT_LL 0x8000
281 #define MCU_BORW_EN 0x4000
284 #define CPCR_RX_VLAN 0x0040
287 #define MAGIC_EN 0x0001
290 #define TEREDO_SEL 0x8000
291 #define TEREDO_WAKE_MASK 0x7f00
292 #define TEREDO_RS_EVENT_MASK 0x00fe
293 #define OOB_TEREDO_EN 0x0001
296 #define ALDPS_PROXY_MODE 0x0001
299 #define EFUSE_READ_CMD BIT(15)
300 #define EFUSE_DATA_BIT16 BIT(7)
303 #define LINK_ON_WAKE_EN 0x0010
304 #define LINK_OFF_WAKE_EN 0x0008
307 #define LANWAKE_CLR_EN BIT(0)
310 #define BWF_EN 0x0040
311 #define MWF_EN 0x0020
312 #define UWF_EN 0x0010
313 #define LAN_WAKE_EN 0x0002
315 /* PLA_LED_FEATURE */
316 #define LED_MODE_MASK 0x0700
319 #define TX_10M_IDLE_EN 0x0080
320 #define PFM_PWM_SWITCH 0x0040
321 #define TEST_IO_OFF BIT(4)
323 /* PLA_MAC_PWR_CTRL */
324 #define D3_CLK_GATED_EN 0x00004000
325 #define MCU_CLK_RATIO 0x07010f07
326 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
327 #define ALDPS_SPDWN_RATIO 0x0f87
329 /* PLA_MAC_PWR_CTRL2 */
330 #define EEE_SPDWN_RATIO 0x8007
331 #define MAC_CLK_SPDWN_EN BIT(15)
333 /* PLA_MAC_PWR_CTRL3 */
334 #define PLA_MCU_SPDWN_EN BIT(14)
335 #define PKT_AVAIL_SPDWN_EN 0x0100
336 #define SUSPEND_SPDWN_EN 0x0004
337 #define U1U2_SPDWN_EN 0x0002
338 #define L1_SPDWN_EN 0x0001
340 /* PLA_MAC_PWR_CTRL4 */
341 #define PWRSAVE_SPDWN_EN 0x1000
342 #define RXDV_SPDWN_EN 0x0800
343 #define TX10MIDLE_EN 0x0100
344 #define TP100_SPDWN_EN 0x0020
345 #define TP500_SPDWN_EN 0x0010
346 #define TP1000_SPDWN_EN 0x0008
347 #define EEE_SPDWN_EN 0x0001
349 /* PLA_GPHY_INTR_IMR */
350 #define GPHY_STS_MSK 0x0001
351 #define SPEED_DOWN_MSK 0x0002
352 #define SPDWN_RXDV_MSK 0x0004
353 #define SPDWN_LINKCHG_MSK 0x0008
356 #define PHYAR_FLAG 0x80000000
359 #define EEE_RX_EN 0x0001
360 #define EEE_TX_EN 0x0002
363 #define AUTOLOAD_DONE 0x0002
365 /* PLA_LWAKE_CTRL_REG */
366 #define LANWAKE_PIN BIT(7)
368 /* PLA_SUSPEND_FLAG */
369 #define LINK_CHG_EVENT BIT(0)
371 /* PLA_INDICATE_FALG */
372 #define UPCOMING_RUNTIME_D3 BIT(0)
374 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
375 #define DEBUG_OE BIT(0)
376 #define DEBUG_LTSSM 0x0082
378 /* PLA_EXTRA_STATUS */
379 #define CUR_LINK_OK BIT(15)
380 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
381 #define LINK_CHANGE_FLAG BIT(8)
382 #define POLL_LINK_CHG BIT(0)
385 #define USB2PHY_SUSPEND 0x0001
386 #define USB2PHY_L1 0x0002
389 #define DELAY_PHY_PWR_CHG BIT(1)
392 #define pwd_dn_scale_mask 0x3ffe
393 #define pwd_dn_scale(x) ((x) << 1)
396 #define DYNAMIC_BURST 0x0001
399 #define EP4_FULL_FC 0x0001
402 #define STAT_SPEED_MASK 0x0006
403 #define STAT_SPEED_HIGH 0x0000
404 #define STAT_SPEED_FULL 0x0002
407 #define FW_FIX_SUSPEND BIT(14)
410 #define FW_IP_RESET_EN BIT(9)
413 #define LPM_U1U2_EN BIT(0)
416 #define TX_AGG_MAX_THRESHOLD 0x03
419 #define RX_THR_SUPPER 0x0c350180
420 #define RX_THR_HIGH 0x7a120180
421 #define RX_THR_SLOW 0xffff0180
422 #define RX_THR_B 0x00010001
425 #define TEST_MODE_DISABLE 0x00000001
426 #define TX_SIZE_ADJUST1 0x00000100
429 #define BMU_RESET_EP_IN 0x01
430 #define BMU_RESET_EP_OUT 0x02
432 /* USB_UPT_RXDMA_OWN */
433 #define OWN_UPDATE BIT(0)
434 #define OWN_CLEAR BIT(1)
437 #define FC_PATCH_TASK BIT(1)
440 #define POWER_CUT 0x0100
442 /* USB_PM_CTRL_STATUS */
443 #define RESUME_INDICATE 0x0001
446 #define FORCE_SUPER BIT(0)
449 #define FLOW_CTRL_PATCH_OPT BIT(1)
452 #define CTRL_TIMER_EN BIT(15)
455 #define RX_AGG_DISABLE 0x0010
456 #define RX_ZERO_EN 0x0080
459 #define U2P3_ENABLE 0x0001
462 #define PWR_EN 0x0001
463 #define PHASE2_EN 0x0008
464 #define UPS_EN BIT(4)
465 #define USP_PREWAKE BIT(5)
468 #define PCUT_STATUS 0x0001
470 /* USB_RX_EARLY_TIMEOUT */
471 #define COALESCE_SUPER 85000U
472 #define COALESCE_HIGH 250000U
473 #define COALESCE_SLOW 524280U
476 #define WTD1_EN BIT(0)
479 #define TIMER11_EN 0x0001
482 /* bit 4 ~ 5: fifo empty boundary */
483 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
484 /* bit 2 ~ 3: LMP timer */
485 #define LPM_TIMER_MASK 0x0c
486 #define LPM_TIMER_500MS 0x04 /* 500 ms */
487 #define LPM_TIMER_500US 0x0c /* 500 us */
488 #define ROK_EXIT_LPM 0x02
491 #define SEN_VAL_MASK 0xf800
492 #define SEN_VAL_NORMAL 0xa000
493 #define SEL_RXIDLE 0x0100
496 #define SAW_CNT_1MS_MASK 0x0fff
499 #define UPS_FLAGS_R_TUNE BIT(0)
500 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
501 #define UPS_FLAGS_250M_CKDIV BIT(2)
502 #define UPS_FLAGS_EN_ALDPS BIT(3)
503 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
504 #define ups_flags_speed(x) ((x) << 16)
505 #define UPS_FLAGS_EN_EEE BIT(20)
506 #define UPS_FLAGS_EN_500M_EEE BIT(21)
507 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
508 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
509 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
510 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
511 #define UPS_FLAGS_EN_GREEN BIT(26)
512 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
526 /* OCP_ALDPS_CONFIG */
527 #define ENPWRSAVE 0x8000
528 #define ENPDNPS 0x0200
529 #define LINKENA 0x0100
530 #define DIS_SDSAVE 0x0010
533 #define PHY_STAT_MASK 0x0007
534 #define PHY_STAT_EXT_INIT 2
535 #define PHY_STAT_LAN_ON 3
536 #define PHY_STAT_PWRDN 5
539 #define PGA_RETURN_EN BIT(1)
542 #define EEE_CLKDIV_EN 0x8000
543 #define EN_ALDPS 0x0004
544 #define EN_10M_PLLOFF 0x0001
546 /* OCP_EEE_CONFIG1 */
547 #define RG_TXLPI_MSK_HFDUP 0x8000
548 #define RG_MATCLR_EN 0x4000
549 #define EEE_10_CAP 0x2000
550 #define EEE_NWAY_EN 0x1000
551 #define TX_QUIET_EN 0x0200
552 #define RX_QUIET_EN 0x0100
553 #define sd_rise_time_mask 0x0070
554 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
555 #define RG_RXLPI_MSK_HFDUP 0x0008
556 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
558 /* OCP_EEE_CONFIG2 */
559 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
560 #define RG_DACQUIET_EN 0x0400
561 #define RG_LDVQUIET_EN 0x0200
562 #define RG_CKRSEL 0x0020
563 #define RG_EEEPRG_EN 0x0010
565 /* OCP_EEE_CONFIG3 */
566 #define fast_snr_mask 0xff80
567 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
568 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
569 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
572 /* bit[15:14] function */
573 #define FUN_ADDR 0x0000
574 #define FUN_DATA 0x4000
575 /* bit[4:0] device addr */
578 #define CTAP_SHORT_EN 0x0040
579 #define EEE10_EN 0x0010
582 #define EN_EEE_CMODE BIT(14)
583 #define EN_EEE_1000 BIT(13)
584 #define EN_EEE_100 BIT(12)
585 #define EN_10M_CLKDIV BIT(11)
586 #define EN_10M_BGOFF 0x0080
589 #define TXDIS_STATE 0x01
590 #define ABD_STATE 0x02
592 /* OCP_PHY_PATCH_STAT */
593 #define PATCH_READY BIT(6)
595 /* OCP_PHY_PATCH_CMD */
596 #define PATCH_REQUEST BIT(4)
599 #define PATCH_LOCK BIT(0)
602 #define CKADSEL_L 0x0100
603 #define ADC_EN 0x0080
604 #define EN_EMI_L 0x0040
607 #define clk_div_expo(x) (min(x, 5) << 8)
610 #define GREEN_ETH_EN BIT(15)
611 #define R_TUNE_EN BIT(11)
614 #define LPF_AUTO_TUNE 0x8000
617 #define GDAC_IB_UPALL 0x0008
620 #define AMP_DN 0x0200
623 #define RX_DRIVING_MASK 0x6000
626 #define PHY_PATCH_LOCK 0x0001
629 #define AD_MASK 0xfee0
630 #define BND_MASK 0x0004
631 #define BD_MASK 0x0001
633 #define PASS_THRU_MASK 0x1
635 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
637 enum rtl_register_content {
645 #define RTL8152_MAX_TX 4
646 #define RTL8152_MAX_RX 10
651 #define RTL8152_RX_MAX_PENDING 4096
652 #define RTL8152_RXFG_HEADSZ 256
654 #define INTR_LINK 0x0004
656 #define RTL8152_REQT_READ 0xc0
657 #define RTL8152_REQT_WRITE 0x40
658 #define RTL8152_REQ_GET_REGS 0x05
659 #define RTL8152_REQ_SET_REGS 0x05
661 #define BYTE_EN_DWORD 0xff
662 #define BYTE_EN_WORD 0x33
663 #define BYTE_EN_BYTE 0x11
664 #define BYTE_EN_SIX_BYTES 0x3f
665 #define BYTE_EN_START_MASK 0x0f
666 #define BYTE_EN_END_MASK 0xf0
668 #define RTL8153_MAX_PACKET 9216 /* 9K */
669 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
671 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
672 #define RTL8153_RMS RTL8153_MAX_PACKET
673 #define RTL8152_TX_TIMEOUT (5 * HZ)
674 #define RTL8152_NAPI_WEIGHT 64
675 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
676 sizeof(struct rx_desc) + RX_ALIGN)
692 /* Define these values to match your device */
693 #define VENDOR_ID_REALTEK 0x0bda
694 #define VENDOR_ID_MICROSOFT 0x045e
695 #define VENDOR_ID_SAMSUNG 0x04e8
696 #define VENDOR_ID_LENOVO 0x17ef
697 #define VENDOR_ID_LINKSYS 0x13b1
698 #define VENDOR_ID_NVIDIA 0x0955
699 #define VENDOR_ID_TPLINK 0x2357
701 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
702 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
704 #define MCU_TYPE_PLA 0x0100
705 #define MCU_TYPE_USB 0x0000
707 struct tally_counter {
714 __le32 tx_one_collision;
715 __le32 tx_multi_collision;
725 #define RX_LEN_MASK 0x7fff
728 #define RD_UDP_CS BIT(23)
729 #define RD_TCP_CS BIT(22)
730 #define RD_IPV6_CS BIT(20)
731 #define RD_IPV4_CS BIT(19)
734 #define IPF BIT(23) /* IP checksum fail */
735 #define UDPF BIT(22) /* UDP checksum fail */
736 #define TCPF BIT(21) /* TCP checksum fail */
737 #define RX_VLAN_TAG BIT(16)
746 #define TX_FS BIT(31) /* First segment of a packet */
747 #define TX_LS BIT(30) /* Final segment of a packet */
748 #define GTSENDV4 BIT(28)
749 #define GTSENDV6 BIT(27)
750 #define GTTCPHO_SHIFT 18
751 #define GTTCPHO_MAX 0x7fU
752 #define TX_LEN_MAX 0x3ffffU
755 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
756 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
757 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
758 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
760 #define MSS_MAX 0x7ffU
761 #define TCPHO_SHIFT 17
762 #define TCPHO_MAX 0x7ffU
763 #define TX_VLAN_TAG BIT(16)
769 struct list_head list, info_list;
771 struct r8152 *context;
777 struct list_head list;
779 struct r8152 *context;
788 struct usb_device *udev;
789 struct napi_struct napi;
790 struct usb_interface *intf;
791 struct net_device *netdev;
792 struct urb *intr_urb;
793 struct tx_agg tx_info[RTL8152_MAX_TX];
794 struct list_head rx_info, rx_used;
795 struct list_head rx_done, tx_free;
796 struct sk_buff_head tx_queue, rx_queue;
797 spinlock_t rx_lock, tx_lock;
798 struct delayed_work schedule, hw_phy_work;
799 struct mii_if_info mii;
800 struct mutex control; /* use for hw setting */
801 #ifdef CONFIG_PM_SLEEP
802 struct notifier_block pm_notifier;
804 struct tasklet_struct tx_tl;
807 void (*init)(struct r8152 *tp);
808 int (*enable)(struct r8152 *tp);
809 void (*disable)(struct r8152 *tp);
810 void (*up)(struct r8152 *tp);
811 void (*down)(struct r8152 *tp);
812 void (*unload)(struct r8152 *tp);
813 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
814 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
815 bool (*in_nway)(struct r8152 *tp);
816 void (*hw_phy_cfg)(struct r8152 *tp);
817 void (*autosuspend_en)(struct r8152 *tp, bool enable);
829 u32 eee_plloff_100:1;
830 u32 eee_plloff_giga:1;
834 u32 ctap_short_off:1;
837 #define RTL_VER_SIZE 32
841 const struct firmware *fw;
843 char version[RTL_VER_SIZE];
844 int (*pre_fw)(struct r8152 *tp);
845 int (*post_fw)(struct r8152 *tp);
873 * struct fw_block - block type and total length
874 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
875 * RTL_FW_USB and so on.
876 * @length: total length of the current block.
884 * struct fw_header - header of the firmware file
885 * @checksum: checksum of sha256 which is calculated from the whole file
886 * except the checksum field of the file. That is, calculate sha256
887 * from the version field to the end of the file.
888 * @version: version of this firmware.
889 * @blocks: the first firmware block of the file
893 char version[RTL_VER_SIZE];
894 struct fw_block blocks[];
898 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
899 * The layout of the firmware block is:
900 * <struct fw_mac> + <info> + <firmware data>.
901 * @fw_offset: offset of the firmware binary data. The start address of
902 * the data would be the address of struct fw_mac + @fw_offset.
903 * @fw_reg: the register to load the firmware. Depends on chip.
904 * @bp_ba_addr: the register to write break point base address. Depends on
906 * @bp_ba_value: break point base address. Depends on chip.
907 * @bp_en_addr: the register to write break point enabled mask. Depends
909 * @bp_en_value: break point enabled mask. Depends on the firmware.
910 * @bp_start: the start register of break points. Depends on chip.
911 * @bp_num: the break point number which needs to be set for this firmware.
912 * Depends on the firmware.
913 * @bp: break points. Depends on firmware.
914 * @fw_ver_reg: the register to store the fw version.
915 * @fw_ver_data: the firmware version of the current type.
916 * @info: additional information for debugging, and is followed by the
917 * binary data of firmware.
920 struct fw_block blk_hdr;
929 __le16 bp[16]; /* any value determined by firmware */
937 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
938 * This is used to set patch key when loading the firmware of PHY.
939 * @key_reg: the register to write the patch key.
940 * @key_data: patch key.
942 struct fw_phy_patch_key {
943 struct fw_block blk_hdr;
950 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
951 * The layout of the firmware block is:
952 * <struct fw_phy_nc> + <info> + <firmware data>.
953 * @fw_offset: offset of the firmware binary data. The start address of
954 * the data would be the address of struct fw_phy_nc + @fw_offset.
955 * @fw_reg: the register to load the firmware. Depends on chip.
956 * @ba_reg: the register to write the base address. Depends on chip.
957 * @ba_data: base address. Depends on chip.
958 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
959 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
960 * @mode_reg: the regitster of switching the mode.
961 * @mod_pre: the mode needing to be set before loading the firmware.
962 * @mod_post: the mode to be set when finishing to load the firmware.
963 * @bp_start: the start register of break points. Depends on chip.
964 * @bp_num: the break point number which needs to be set for this firmware.
965 * Depends on the firmware.
966 * @bp: break points. Depends on firmware.
967 * @info: additional information for debugging, and is followed by the
968 * binary data of firmware.
971 struct fw_block blk_hdr;
976 __le16 patch_en_addr;
977 __le16 patch_en_value;
1012 TX_CSUM_SUCCESS = 0,
1017 #define RTL_ADVERTISED_10_HALF BIT(0)
1018 #define RTL_ADVERTISED_10_FULL BIT(1)
1019 #define RTL_ADVERTISED_100_HALF BIT(2)
1020 #define RTL_ADVERTISED_100_FULL BIT(3)
1021 #define RTL_ADVERTISED_1000_HALF BIT(4)
1022 #define RTL_ADVERTISED_1000_FULL BIT(5)
1024 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1025 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1027 static const int multicast_filter_limit = 32;
1028 static unsigned int agg_buf_sz = 16384;
1030 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
1031 VLAN_ETH_HLEN - ETH_FCS_LEN)
1034 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1039 tmp = kmalloc(size, GFP_KERNEL);
1043 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1044 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1045 value, index, tmp, size, USB_CTRL_GET_TIMEOUT);
1047 memset(data, 0xff, size);
1049 memcpy(data, tmp, size);
1057 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1062 tmp = kmemdup(data, size, GFP_KERNEL);
1066 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1067 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1068 value, index, tmp, size, USB_CTRL_SET_TIMEOUT);
1075 static void rtl_set_unplug(struct r8152 *tp)
1077 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1078 set_bit(RTL8152_UNPLUG, &tp->flags);
1079 smp_mb__after_atomic();
1083 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1084 void *data, u16 type)
1089 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1092 /* both size and indix must be 4 bytes align */
1093 if ((size & 3) || !size || (index & 3) || !data)
1096 if ((u32)index + (u32)size > 0xffff)
1101 ret = get_registers(tp, index, type, limit, data);
1109 ret = get_registers(tp, index, type, size, data);
1126 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1127 u16 size, void *data, u16 type)
1130 u16 byteen_start, byteen_end, byen;
1133 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1136 /* both size and indix must be 4 bytes align */
1137 if ((size & 3) || !size || (index & 3) || !data)
1140 if ((u32)index + (u32)size > 0xffff)
1143 byteen_start = byteen & BYTE_EN_START_MASK;
1144 byteen_end = byteen & BYTE_EN_END_MASK;
1146 byen = byteen_start | (byteen_start << 4);
1147 ret = set_registers(tp, index, type | byen, 4, data);
1160 ret = set_registers(tp, index,
1161 type | BYTE_EN_DWORD,
1170 ret = set_registers(tp, index,
1171 type | BYTE_EN_DWORD,
1183 byen = byteen_end | (byteen_end >> 4);
1184 ret = set_registers(tp, index, type | byen, 4, data);
1197 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1199 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1203 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1205 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1209 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1211 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1214 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1218 generic_ocp_read(tp, index, sizeof(data), &data, type);
1220 return __le32_to_cpu(data);
1223 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1225 __le32 tmp = __cpu_to_le32(data);
1227 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1230 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1234 u16 byen = BYTE_EN_WORD;
1235 u8 shift = index & 2;
1240 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1242 data = __le32_to_cpu(tmp);
1243 data >>= (shift * 8);
1249 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1253 u16 byen = BYTE_EN_WORD;
1254 u8 shift = index & 2;
1260 mask <<= (shift * 8);
1261 data <<= (shift * 8);
1265 tmp = __cpu_to_le32(data);
1267 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1270 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1274 u8 shift = index & 3;
1278 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1280 data = __le32_to_cpu(tmp);
1281 data >>= (shift * 8);
1287 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1291 u16 byen = BYTE_EN_BYTE;
1292 u8 shift = index & 3;
1298 mask <<= (shift * 8);
1299 data <<= (shift * 8);
1303 tmp = __cpu_to_le32(data);
1305 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1308 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1310 u16 ocp_base, ocp_index;
1312 ocp_base = addr & 0xf000;
1313 if (ocp_base != tp->ocp_base) {
1314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1315 tp->ocp_base = ocp_base;
1318 ocp_index = (addr & 0x0fff) | 0xb000;
1319 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1322 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1324 u16 ocp_base, ocp_index;
1326 ocp_base = addr & 0xf000;
1327 if (ocp_base != tp->ocp_base) {
1328 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1329 tp->ocp_base = ocp_base;
1332 ocp_index = (addr & 0x0fff) | 0xb000;
1333 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1336 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1338 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1341 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1343 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1346 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1348 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1349 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1352 static u16 sram_read(struct r8152 *tp, u16 addr)
1354 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1355 return ocp_reg_read(tp, OCP_SRAM_DATA);
1358 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1360 struct r8152 *tp = netdev_priv(netdev);
1363 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1366 if (phy_id != R8152_PHY_ID)
1369 ret = r8152_mdio_read(tp, reg);
1375 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1377 struct r8152 *tp = netdev_priv(netdev);
1379 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1382 if (phy_id != R8152_PHY_ID)
1385 r8152_mdio_write(tp, reg, val);
1389 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1391 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1393 struct r8152 *tp = netdev_priv(netdev);
1394 struct sockaddr *addr = p;
1395 int ret = -EADDRNOTAVAIL;
1397 if (!is_valid_ether_addr(addr->sa_data))
1400 ret = usb_autopm_get_interface(tp->intf);
1404 mutex_lock(&tp->control);
1406 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1408 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1409 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1410 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1412 mutex_unlock(&tp->control);
1414 usb_autopm_put_interface(tp->intf);
1419 /* Devices containing proper chips can support a persistent
1420 * host system provided MAC address.
1421 * Examples of this are Dell TB15 and Dell WD15 docks
1423 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1426 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1427 union acpi_object *obj;
1430 unsigned char buf[6];
1432 acpi_object_type mac_obj_type;
1435 if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1436 mac_obj_name = "\\MACA";
1437 mac_obj_type = ACPI_TYPE_STRING;
1440 /* test for -AD variant of RTL8153 */
1441 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1442 if ((ocp_data & AD_MASK) == 0x1000) {
1443 /* test for MAC address pass-through bit */
1444 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1445 if ((ocp_data & PASS_THRU_MASK) != 1) {
1446 netif_dbg(tp, probe, tp->netdev,
1447 "No efuse for RTL8153-AD MAC pass through\n");
1451 /* test for RTL8153-BND and RTL8153-BD */
1452 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1453 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1454 netif_dbg(tp, probe, tp->netdev,
1455 "Invalid variant for MAC pass through\n");
1460 mac_obj_name = "\\_SB.AMAC";
1461 mac_obj_type = ACPI_TYPE_BUFFER;
1465 /* returns _AUXMAC_#AABBCCDDEEFF# */
1466 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1467 obj = (union acpi_object *)buffer.pointer;
1468 if (!ACPI_SUCCESS(status))
1470 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1471 netif_warn(tp, probe, tp->netdev,
1472 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1473 obj->type, obj->string.length);
1477 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1478 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1479 netif_warn(tp, probe, tp->netdev,
1480 "Invalid header when reading pass-thru MAC addr\n");
1483 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1484 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1485 netif_warn(tp, probe, tp->netdev,
1486 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1491 memcpy(sa->sa_data, buf, 6);
1492 netif_info(tp, probe, tp->netdev,
1493 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1500 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1502 struct net_device *dev = tp->netdev;
1505 sa->sa_family = dev->type;
1507 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1509 if (tp->version == RTL_VER_01) {
1510 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1512 /* if device doesn't support MAC pass through this will
1513 * be expected to be non-zero
1515 ret = vendor_mac_passthru_addr_read(tp, sa);
1517 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1523 netif_err(tp, probe, dev, "Get ether addr fail\n");
1524 } else if (!is_valid_ether_addr(sa->sa_data)) {
1525 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1527 eth_hw_addr_random(dev);
1528 ether_addr_copy(sa->sa_data, dev->dev_addr);
1529 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1537 static int set_ethernet_addr(struct r8152 *tp)
1539 struct net_device *dev = tp->netdev;
1543 ret = determine_ethernet_addr(tp, &sa);
1547 if (tp->version == RTL_VER_01)
1548 ether_addr_copy(dev->dev_addr, sa.sa_data);
1550 ret = rtl8152_set_mac_address(dev, &sa);
1555 static void read_bulk_callback(struct urb *urb)
1557 struct net_device *netdev;
1558 int status = urb->status;
1561 unsigned long flags;
1571 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1574 if (!test_bit(WORK_ENABLE, &tp->flags))
1577 netdev = tp->netdev;
1579 /* When link down, the driver would cancel all bulks. */
1580 /* This avoid the re-submitting bulk */
1581 if (!netif_carrier_ok(netdev))
1584 usb_mark_last_busy(tp->udev);
1588 if (urb->actual_length < ETH_ZLEN)
1591 spin_lock_irqsave(&tp->rx_lock, flags);
1592 list_add_tail(&agg->list, &tp->rx_done);
1593 spin_unlock_irqrestore(&tp->rx_lock, flags);
1594 napi_schedule(&tp->napi);
1598 netif_device_detach(tp->netdev);
1601 return; /* the urb is in unlink state */
1603 if (net_ratelimit())
1604 netdev_warn(netdev, "maybe reset is needed?\n");
1607 if (net_ratelimit())
1608 netdev_warn(netdev, "Rx status %d\n", status);
1612 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1615 static void write_bulk_callback(struct urb *urb)
1617 struct net_device_stats *stats;
1618 struct net_device *netdev;
1621 unsigned long flags;
1622 int status = urb->status;
1632 netdev = tp->netdev;
1633 stats = &netdev->stats;
1635 if (net_ratelimit())
1636 netdev_warn(netdev, "Tx status %d\n", status);
1637 stats->tx_errors += agg->skb_num;
1639 stats->tx_packets += agg->skb_num;
1640 stats->tx_bytes += agg->skb_len;
1643 spin_lock_irqsave(&tp->tx_lock, flags);
1644 list_add_tail(&agg->list, &tp->tx_free);
1645 spin_unlock_irqrestore(&tp->tx_lock, flags);
1647 usb_autopm_put_interface_async(tp->intf);
1649 if (!netif_carrier_ok(netdev))
1652 if (!test_bit(WORK_ENABLE, &tp->flags))
1655 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1658 if (!skb_queue_empty(&tp->tx_queue))
1659 tasklet_schedule(&tp->tx_tl);
1662 static void intr_callback(struct urb *urb)
1666 int status = urb->status;
1673 if (!test_bit(WORK_ENABLE, &tp->flags))
1676 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1680 case 0: /* success */
1682 case -ECONNRESET: /* unlink */
1684 netif_device_detach(tp->netdev);
1688 netif_info(tp, intr, tp->netdev,
1689 "Stop submitting intr, status %d\n", status);
1692 if (net_ratelimit())
1693 netif_info(tp, intr, tp->netdev,
1694 "intr status -EOVERFLOW\n");
1696 /* -EPIPE: should clear the halt */
1698 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1702 d = urb->transfer_buffer;
1703 if (INTR_LINK & __le16_to_cpu(d[0])) {
1704 if (!netif_carrier_ok(tp->netdev)) {
1705 set_bit(RTL8152_LINK_CHG, &tp->flags);
1706 schedule_delayed_work(&tp->schedule, 0);
1709 if (netif_carrier_ok(tp->netdev)) {
1710 netif_stop_queue(tp->netdev);
1711 set_bit(RTL8152_LINK_CHG, &tp->flags);
1712 schedule_delayed_work(&tp->schedule, 0);
1717 res = usb_submit_urb(urb, GFP_ATOMIC);
1718 if (res == -ENODEV) {
1720 netif_device_detach(tp->netdev);
1722 netif_err(tp, intr, tp->netdev,
1723 "can't resubmit intr, status %d\n", res);
1727 static inline void *rx_agg_align(void *data)
1729 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1732 static inline void *tx_agg_align(void *data)
1734 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1737 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1739 list_del(&agg->info_list);
1741 usb_free_urb(agg->urb);
1742 put_page(agg->page);
1745 atomic_dec(&tp->rx_count);
1748 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1750 struct net_device *netdev = tp->netdev;
1751 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1752 unsigned int order = get_order(tp->rx_buf_sz);
1753 struct rx_agg *rx_agg;
1754 unsigned long flags;
1756 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1760 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1764 rx_agg->buffer = page_address(rx_agg->page);
1766 rx_agg->urb = usb_alloc_urb(0, mflags);
1770 rx_agg->context = tp;
1772 INIT_LIST_HEAD(&rx_agg->list);
1773 INIT_LIST_HEAD(&rx_agg->info_list);
1774 spin_lock_irqsave(&tp->rx_lock, flags);
1775 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1776 spin_unlock_irqrestore(&tp->rx_lock, flags);
1778 atomic_inc(&tp->rx_count);
1783 __free_pages(rx_agg->page, order);
1789 static void free_all_mem(struct r8152 *tp)
1791 struct rx_agg *agg, *agg_next;
1792 unsigned long flags;
1795 spin_lock_irqsave(&tp->rx_lock, flags);
1797 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1798 free_rx_agg(tp, agg);
1800 spin_unlock_irqrestore(&tp->rx_lock, flags);
1802 WARN_ON(atomic_read(&tp->rx_count));
1804 for (i = 0; i < RTL8152_MAX_TX; i++) {
1805 usb_free_urb(tp->tx_info[i].urb);
1806 tp->tx_info[i].urb = NULL;
1808 kfree(tp->tx_info[i].buffer);
1809 tp->tx_info[i].buffer = NULL;
1810 tp->tx_info[i].head = NULL;
1813 usb_free_urb(tp->intr_urb);
1814 tp->intr_urb = NULL;
1816 kfree(tp->intr_buff);
1817 tp->intr_buff = NULL;
1820 static int alloc_all_mem(struct r8152 *tp)
1822 struct net_device *netdev = tp->netdev;
1823 struct usb_interface *intf = tp->intf;
1824 struct usb_host_interface *alt = intf->cur_altsetting;
1825 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1828 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1830 spin_lock_init(&tp->rx_lock);
1831 spin_lock_init(&tp->tx_lock);
1832 INIT_LIST_HEAD(&tp->rx_info);
1833 INIT_LIST_HEAD(&tp->tx_free);
1834 INIT_LIST_HEAD(&tp->rx_done);
1835 skb_queue_head_init(&tp->tx_queue);
1836 skb_queue_head_init(&tp->rx_queue);
1837 atomic_set(&tp->rx_count, 0);
1839 for (i = 0; i < RTL8152_MAX_RX; i++) {
1840 if (!alloc_rx_agg(tp, GFP_KERNEL))
1844 for (i = 0; i < RTL8152_MAX_TX; i++) {
1848 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1852 if (buf != tx_agg_align(buf)) {
1854 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1860 urb = usb_alloc_urb(0, GFP_KERNEL);
1866 INIT_LIST_HEAD(&tp->tx_info[i].list);
1867 tp->tx_info[i].context = tp;
1868 tp->tx_info[i].urb = urb;
1869 tp->tx_info[i].buffer = buf;
1870 tp->tx_info[i].head = tx_agg_align(buf);
1872 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1875 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1879 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1883 tp->intr_interval = (int)ep_intr->desc.bInterval;
1884 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1885 tp->intr_buff, INTBUFSIZE, intr_callback,
1886 tp, tp->intr_interval);
1895 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1897 struct tx_agg *agg = NULL;
1898 unsigned long flags;
1900 if (list_empty(&tp->tx_free))
1903 spin_lock_irqsave(&tp->tx_lock, flags);
1904 if (!list_empty(&tp->tx_free)) {
1905 struct list_head *cursor;
1907 cursor = tp->tx_free.next;
1908 list_del_init(cursor);
1909 agg = list_entry(cursor, struct tx_agg, list);
1911 spin_unlock_irqrestore(&tp->tx_lock, flags);
1916 /* r8152_csum_workaround()
1917 * The hw limits the value of the transport offset. When the offset is out of
1918 * range, calculate the checksum by sw.
1920 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1921 struct sk_buff_head *list)
1923 if (skb_shinfo(skb)->gso_size) {
1924 netdev_features_t features = tp->netdev->features;
1925 struct sk_buff *segs, *seg, *next;
1926 struct sk_buff_head seg_list;
1928 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1929 segs = skb_gso_segment(skb, features);
1930 if (IS_ERR(segs) || !segs)
1933 __skb_queue_head_init(&seg_list);
1935 skb_list_walk_safe(segs, seg, next) {
1936 skb_mark_not_on_list(seg);
1937 __skb_queue_tail(&seg_list, seg);
1940 skb_queue_splice(&seg_list, list);
1942 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1943 if (skb_checksum_help(skb) < 0)
1946 __skb_queue_head(list, skb);
1948 struct net_device_stats *stats;
1951 stats = &tp->netdev->stats;
1952 stats->tx_dropped++;
1957 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1959 if (skb_vlan_tag_present(skb)) {
1962 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1963 desc->opts2 |= cpu_to_le32(opts2);
1967 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1969 u32 opts2 = le32_to_cpu(desc->opts2);
1971 if (opts2 & RX_VLAN_TAG)
1972 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1973 swab16(opts2 & 0xffff));
1976 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1977 struct sk_buff *skb, u32 len, u32 transport_offset)
1979 u32 mss = skb_shinfo(skb)->gso_size;
1980 u32 opts1, opts2 = 0;
1981 int ret = TX_CSUM_SUCCESS;
1983 WARN_ON_ONCE(len > TX_LEN_MAX);
1985 opts1 = len | TX_FS | TX_LS;
1988 if (transport_offset > GTTCPHO_MAX) {
1989 netif_warn(tp, tx_err, tp->netdev,
1990 "Invalid transport offset 0x%x for TSO\n",
1996 switch (vlan_get_protocol(skb)) {
1997 case htons(ETH_P_IP):
2001 case htons(ETH_P_IPV6):
2002 if (skb_cow_head(skb, 0)) {
2006 tcp_v6_gso_csum_prep(skb);
2015 opts1 |= transport_offset << GTTCPHO_SHIFT;
2016 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2017 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2020 if (transport_offset > TCPHO_MAX) {
2021 netif_warn(tp, tx_err, tp->netdev,
2022 "Invalid transport offset 0x%x\n",
2028 switch (vlan_get_protocol(skb)) {
2029 case htons(ETH_P_IP):
2031 ip_protocol = ip_hdr(skb)->protocol;
2034 case htons(ETH_P_IPV6):
2036 ip_protocol = ipv6_hdr(skb)->nexthdr;
2040 ip_protocol = IPPROTO_RAW;
2044 if (ip_protocol == IPPROTO_TCP)
2046 else if (ip_protocol == IPPROTO_UDP)
2051 opts2 |= transport_offset << TCPHO_SHIFT;
2054 desc->opts2 = cpu_to_le32(opts2);
2055 desc->opts1 = cpu_to_le32(opts1);
2061 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2063 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2067 __skb_queue_head_init(&skb_head);
2068 spin_lock(&tx_queue->lock);
2069 skb_queue_splice_init(tx_queue, &skb_head);
2070 spin_unlock(&tx_queue->lock);
2072 tx_data = agg->head;
2075 remain = agg_buf_sz;
2077 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2078 struct tx_desc *tx_desc;
2079 struct sk_buff *skb;
2083 skb = __skb_dequeue(&skb_head);
2087 len = skb->len + sizeof(*tx_desc);
2090 __skb_queue_head(&skb_head, skb);
2094 tx_data = tx_agg_align(tx_data);
2095 tx_desc = (struct tx_desc *)tx_data;
2097 offset = (u32)skb_transport_offset(skb);
2099 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2100 r8152_csum_workaround(tp, skb, &skb_head);
2104 rtl_tx_vlan_tag(tx_desc, skb);
2106 tx_data += sizeof(*tx_desc);
2109 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2110 struct net_device_stats *stats = &tp->netdev->stats;
2112 stats->tx_dropped++;
2113 dev_kfree_skb_any(skb);
2114 tx_data -= sizeof(*tx_desc);
2119 agg->skb_len += len;
2120 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2122 dev_kfree_skb_any(skb);
2124 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2126 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2130 if (!skb_queue_empty(&skb_head)) {
2131 spin_lock(&tx_queue->lock);
2132 skb_queue_splice(&skb_head, tx_queue);
2133 spin_unlock(&tx_queue->lock);
2136 netif_tx_lock(tp->netdev);
2138 if (netif_queue_stopped(tp->netdev) &&
2139 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2140 netif_wake_queue(tp->netdev);
2142 netif_tx_unlock(tp->netdev);
2144 ret = usb_autopm_get_interface_async(tp->intf);
2148 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2149 agg->head, (int)(tx_data - (u8 *)agg->head),
2150 (usb_complete_t)write_bulk_callback, agg);
2152 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2154 usb_autopm_put_interface_async(tp->intf);
2160 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2162 u8 checksum = CHECKSUM_NONE;
2165 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2168 opts2 = le32_to_cpu(rx_desc->opts2);
2169 opts3 = le32_to_cpu(rx_desc->opts3);
2171 if (opts2 & RD_IPV4_CS) {
2173 checksum = CHECKSUM_NONE;
2174 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2175 checksum = CHECKSUM_UNNECESSARY;
2176 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2177 checksum = CHECKSUM_UNNECESSARY;
2178 } else if (opts2 & RD_IPV6_CS) {
2179 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2180 checksum = CHECKSUM_UNNECESSARY;
2181 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2182 checksum = CHECKSUM_UNNECESSARY;
2189 static inline bool rx_count_exceed(struct r8152 *tp)
2191 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2194 static inline int agg_offset(struct rx_agg *agg, void *addr)
2196 return (int)(addr - agg->buffer);
2199 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2201 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2202 unsigned long flags;
2204 spin_lock_irqsave(&tp->rx_lock, flags);
2206 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2207 if (page_count(agg->page) == 1) {
2209 list_del_init(&agg->list);
2213 if (rx_count_exceed(tp)) {
2214 list_del_init(&agg->list);
2215 free_rx_agg(tp, agg);
2221 spin_unlock_irqrestore(&tp->rx_lock, flags);
2223 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2224 agg_free = alloc_rx_agg(tp, mflags);
2229 static int rx_bottom(struct r8152 *tp, int budget)
2231 unsigned long flags;
2232 struct list_head *cursor, *next, rx_queue;
2233 int ret = 0, work_done = 0;
2234 struct napi_struct *napi = &tp->napi;
2236 if (!skb_queue_empty(&tp->rx_queue)) {
2237 while (work_done < budget) {
2238 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2239 struct net_device *netdev = tp->netdev;
2240 struct net_device_stats *stats = &netdev->stats;
2241 unsigned int pkt_len;
2247 napi_gro_receive(napi, skb);
2249 stats->rx_packets++;
2250 stats->rx_bytes += pkt_len;
2254 if (list_empty(&tp->rx_done))
2257 INIT_LIST_HEAD(&rx_queue);
2258 spin_lock_irqsave(&tp->rx_lock, flags);
2259 list_splice_init(&tp->rx_done, &rx_queue);
2260 spin_unlock_irqrestore(&tp->rx_lock, flags);
2262 list_for_each_safe(cursor, next, &rx_queue) {
2263 struct rx_desc *rx_desc;
2264 struct rx_agg *agg, *agg_free;
2269 list_del_init(cursor);
2271 agg = list_entry(cursor, struct rx_agg, list);
2273 if (urb->actual_length < ETH_ZLEN)
2276 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2278 rx_desc = agg->buffer;
2279 rx_data = agg->buffer;
2280 len_used += sizeof(struct rx_desc);
2282 while (urb->actual_length > len_used) {
2283 struct net_device *netdev = tp->netdev;
2284 struct net_device_stats *stats = &netdev->stats;
2285 unsigned int pkt_len, rx_frag_head_sz;
2286 struct sk_buff *skb;
2288 /* limite the skb numbers for rx_queue */
2289 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2292 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2293 if (pkt_len < ETH_ZLEN)
2296 len_used += pkt_len;
2297 if (urb->actual_length < len_used)
2300 pkt_len -= ETH_FCS_LEN;
2301 rx_data += sizeof(struct rx_desc);
2303 if (!agg_free || tp->rx_copybreak > pkt_len)
2304 rx_frag_head_sz = pkt_len;
2306 rx_frag_head_sz = tp->rx_copybreak;
2308 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2310 stats->rx_dropped++;
2314 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2315 memcpy(skb->data, rx_data, rx_frag_head_sz);
2316 skb_put(skb, rx_frag_head_sz);
2317 pkt_len -= rx_frag_head_sz;
2318 rx_data += rx_frag_head_sz;
2320 skb_add_rx_frag(skb, 0, agg->page,
2321 agg_offset(agg, rx_data),
2323 SKB_DATA_ALIGN(pkt_len));
2324 get_page(agg->page);
2327 skb->protocol = eth_type_trans(skb, netdev);
2328 rtl_rx_vlan_tag(rx_desc, skb);
2329 if (work_done < budget) {
2331 stats->rx_packets++;
2332 stats->rx_bytes += skb->len;
2333 napi_gro_receive(napi, skb);
2335 __skb_queue_tail(&tp->rx_queue, skb);
2339 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2340 rx_desc = (struct rx_desc *)rx_data;
2341 len_used = agg_offset(agg, rx_data);
2342 len_used += sizeof(struct rx_desc);
2345 WARN_ON(!agg_free && page_count(agg->page) > 1);
2348 spin_lock_irqsave(&tp->rx_lock, flags);
2349 if (page_count(agg->page) == 1) {
2350 list_add(&agg_free->list, &tp->rx_used);
2352 list_add_tail(&agg->list, &tp->rx_used);
2356 spin_unlock_irqrestore(&tp->rx_lock, flags);
2361 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2363 urb->actual_length = 0;
2364 list_add_tail(&agg->list, next);
2368 if (!list_empty(&rx_queue)) {
2369 spin_lock_irqsave(&tp->rx_lock, flags);
2370 list_splice_tail(&rx_queue, &tp->rx_done);
2371 spin_unlock_irqrestore(&tp->rx_lock, flags);
2378 static void tx_bottom(struct r8152 *tp)
2383 struct net_device *netdev = tp->netdev;
2386 if (skb_queue_empty(&tp->tx_queue))
2389 agg = r8152_get_tx_agg(tp);
2393 res = r8152_tx_agg_fill(tp, agg);
2397 if (res == -ENODEV) {
2399 netif_device_detach(netdev);
2401 struct net_device_stats *stats = &netdev->stats;
2402 unsigned long flags;
2404 netif_warn(tp, tx_err, netdev,
2405 "failed tx_urb %d\n", res);
2406 stats->tx_dropped += agg->skb_num;
2408 spin_lock_irqsave(&tp->tx_lock, flags);
2409 list_add_tail(&agg->list, &tp->tx_free);
2410 spin_unlock_irqrestore(&tp->tx_lock, flags);
2415 static void bottom_half(unsigned long data)
2419 tp = (struct r8152 *)data;
2421 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2424 if (!test_bit(WORK_ENABLE, &tp->flags))
2427 /* When link down, the driver would cancel all bulks. */
2428 /* This avoid the re-submitting bulk */
2429 if (!netif_carrier_ok(tp->netdev))
2432 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2437 static int r8152_poll(struct napi_struct *napi, int budget)
2439 struct r8152 *tp = container_of(napi, struct r8152, napi);
2445 work_done = rx_bottom(tp, budget);
2447 if (work_done < budget) {
2448 if (!napi_complete_done(napi, work_done))
2450 if (!list_empty(&tp->rx_done))
2451 napi_schedule(napi);
2459 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2463 /* The rx would be stopped, so skip submitting */
2464 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2465 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2468 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2469 agg->buffer, tp->rx_buf_sz,
2470 (usb_complete_t)read_bulk_callback, agg);
2472 ret = usb_submit_urb(agg->urb, mem_flags);
2473 if (ret == -ENODEV) {
2475 netif_device_detach(tp->netdev);
2477 struct urb *urb = agg->urb;
2478 unsigned long flags;
2480 urb->actual_length = 0;
2481 spin_lock_irqsave(&tp->rx_lock, flags);
2482 list_add_tail(&agg->list, &tp->rx_done);
2483 spin_unlock_irqrestore(&tp->rx_lock, flags);
2485 netif_err(tp, rx_err, tp->netdev,
2486 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2488 napi_schedule(&tp->napi);
2494 static void rtl_drop_queued_tx(struct r8152 *tp)
2496 struct net_device_stats *stats = &tp->netdev->stats;
2497 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2498 struct sk_buff *skb;
2500 if (skb_queue_empty(tx_queue))
2503 __skb_queue_head_init(&skb_head);
2504 spin_lock_bh(&tx_queue->lock);
2505 skb_queue_splice_init(tx_queue, &skb_head);
2506 spin_unlock_bh(&tx_queue->lock);
2508 while ((skb = __skb_dequeue(&skb_head))) {
2510 stats->tx_dropped++;
2514 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2516 struct r8152 *tp = netdev_priv(netdev);
2518 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2520 usb_queue_reset_device(tp->intf);
2523 static void rtl8152_set_rx_mode(struct net_device *netdev)
2525 struct r8152 *tp = netdev_priv(netdev);
2527 if (netif_carrier_ok(netdev)) {
2528 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2529 schedule_delayed_work(&tp->schedule, 0);
2533 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2535 struct r8152 *tp = netdev_priv(netdev);
2536 u32 mc_filter[2]; /* Multicast hash filter */
2540 netif_stop_queue(netdev);
2541 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2542 ocp_data &= ~RCR_ACPT_ALL;
2543 ocp_data |= RCR_AB | RCR_APM;
2545 if (netdev->flags & IFF_PROMISC) {
2546 /* Unconditionally log net taps. */
2547 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2548 ocp_data |= RCR_AM | RCR_AAP;
2549 mc_filter[1] = 0xffffffff;
2550 mc_filter[0] = 0xffffffff;
2551 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2552 (netdev->flags & IFF_ALLMULTI)) {
2553 /* Too many to filter perfectly -- accept all multicasts. */
2555 mc_filter[1] = 0xffffffff;
2556 mc_filter[0] = 0xffffffff;
2558 struct netdev_hw_addr *ha;
2562 netdev_for_each_mc_addr(ha, netdev) {
2563 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2565 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2570 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2571 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2573 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2574 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2575 netif_wake_queue(netdev);
2578 static netdev_features_t
2579 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2580 netdev_features_t features)
2582 u32 mss = skb_shinfo(skb)->gso_size;
2583 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2584 int offset = skb_transport_offset(skb);
2586 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2587 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2588 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2589 features &= ~NETIF_F_GSO_MASK;
2594 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2595 struct net_device *netdev)
2597 struct r8152 *tp = netdev_priv(netdev);
2599 skb_tx_timestamp(skb);
2601 skb_queue_tail(&tp->tx_queue, skb);
2603 if (!list_empty(&tp->tx_free)) {
2604 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2605 set_bit(SCHEDULE_TASKLET, &tp->flags);
2606 schedule_delayed_work(&tp->schedule, 0);
2608 usb_mark_last_busy(tp->udev);
2609 tasklet_schedule(&tp->tx_tl);
2611 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2612 netif_stop_queue(netdev);
2615 return NETDEV_TX_OK;
2618 static void r8152b_reset_packet_filter(struct r8152 *tp)
2622 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2623 ocp_data &= ~FMC_FCR_MCU_EN;
2624 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2625 ocp_data |= FMC_FCR_MCU_EN;
2626 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2629 static void rtl8152_nic_reset(struct r8152 *tp)
2633 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2635 for (i = 0; i < 1000; i++) {
2636 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2638 usleep_range(100, 400);
2642 static void set_tx_qlen(struct r8152 *tp)
2644 struct net_device *netdev = tp->netdev;
2646 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2647 sizeof(struct tx_desc));
2650 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2652 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2655 static void rtl_set_eee_plus(struct r8152 *tp)
2660 speed = rtl8152_get_speed(tp);
2661 if (speed & _10bps) {
2662 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2663 ocp_data |= EEEP_CR_EEEP_TX;
2664 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2666 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2667 ocp_data &= ~EEEP_CR_EEEP_TX;
2668 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2672 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2676 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2678 ocp_data |= RXDY_GATED_EN;
2680 ocp_data &= ~RXDY_GATED_EN;
2681 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2684 static int rtl_start_rx(struct r8152 *tp)
2686 struct rx_agg *agg, *agg_next;
2687 struct list_head tmp_list;
2688 unsigned long flags;
2691 INIT_LIST_HEAD(&tmp_list);
2693 spin_lock_irqsave(&tp->rx_lock, flags);
2695 INIT_LIST_HEAD(&tp->rx_done);
2696 INIT_LIST_HEAD(&tp->rx_used);
2698 list_splice_init(&tp->rx_info, &tmp_list);
2700 spin_unlock_irqrestore(&tp->rx_lock, flags);
2702 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2703 INIT_LIST_HEAD(&agg->list);
2705 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2706 if (++i > RTL8152_MAX_RX) {
2707 spin_lock_irqsave(&tp->rx_lock, flags);
2708 list_add_tail(&agg->list, &tp->rx_used);
2709 spin_unlock_irqrestore(&tp->rx_lock, flags);
2710 } else if (unlikely(ret < 0)) {
2711 spin_lock_irqsave(&tp->rx_lock, flags);
2712 list_add_tail(&agg->list, &tp->rx_done);
2713 spin_unlock_irqrestore(&tp->rx_lock, flags);
2715 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2719 spin_lock_irqsave(&tp->rx_lock, flags);
2720 WARN_ON(!list_empty(&tp->rx_info));
2721 list_splice(&tmp_list, &tp->rx_info);
2722 spin_unlock_irqrestore(&tp->rx_lock, flags);
2727 static int rtl_stop_rx(struct r8152 *tp)
2729 struct rx_agg *agg, *agg_next;
2730 struct list_head tmp_list;
2731 unsigned long flags;
2733 INIT_LIST_HEAD(&tmp_list);
2735 /* The usb_kill_urb() couldn't be used in atomic.
2736 * Therefore, move the list of rx_info to a tmp one.
2737 * Then, list_for_each_entry_safe could be used without
2741 spin_lock_irqsave(&tp->rx_lock, flags);
2742 list_splice_init(&tp->rx_info, &tmp_list);
2743 spin_unlock_irqrestore(&tp->rx_lock, flags);
2745 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2746 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2747 * equal to 1, so the other ones could be freed safely.
2749 if (page_count(agg->page) > 1)
2750 free_rx_agg(tp, agg);
2752 usb_kill_urb(agg->urb);
2755 /* Move back the list of temp to the rx_info */
2756 spin_lock_irqsave(&tp->rx_lock, flags);
2757 WARN_ON(!list_empty(&tp->rx_info));
2758 list_splice(&tmp_list, &tp->rx_info);
2759 spin_unlock_irqrestore(&tp->rx_lock, flags);
2761 while (!skb_queue_empty(&tp->rx_queue))
2762 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2767 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2769 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2770 OWN_UPDATE | OWN_CLEAR);
2773 static int rtl_enable(struct r8152 *tp)
2777 r8152b_reset_packet_filter(tp);
2779 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2780 ocp_data |= CR_RE | CR_TE;
2781 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2783 switch (tp->version) {
2786 r8153b_rx_agg_chg_indicate(tp);
2792 rxdy_gated_en(tp, false);
2797 static int rtl8152_enable(struct r8152 *tp)
2799 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2803 rtl_set_eee_plus(tp);
2805 return rtl_enable(tp);
2808 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2810 u32 ocp_data = tp->coalesce / 8;
2812 switch (tp->version) {
2817 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2823 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2824 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2826 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2828 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2837 static void r8153_set_rx_early_size(struct r8152 *tp)
2839 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2841 switch (tp->version) {
2846 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2851 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2860 static int rtl8153_enable(struct r8152 *tp)
2862 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2866 rtl_set_eee_plus(tp);
2867 r8153_set_rx_early_timeout(tp);
2868 r8153_set_rx_early_size(tp);
2870 if (tp->version == RTL_VER_09) {
2873 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2874 ocp_data &= ~FC_PATCH_TASK;
2875 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2876 usleep_range(1000, 2000);
2877 ocp_data |= FC_PATCH_TASK;
2878 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2881 return rtl_enable(tp);
2884 static void rtl_disable(struct r8152 *tp)
2889 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2890 rtl_drop_queued_tx(tp);
2894 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2895 ocp_data &= ~RCR_ACPT_ALL;
2896 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2898 rtl_drop_queued_tx(tp);
2900 for (i = 0; i < RTL8152_MAX_TX; i++)
2901 usb_kill_urb(tp->tx_info[i].urb);
2903 rxdy_gated_en(tp, true);
2905 for (i = 0; i < 1000; i++) {
2906 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2907 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2909 usleep_range(1000, 2000);
2912 for (i = 0; i < 1000; i++) {
2913 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2915 usleep_range(1000, 2000);
2920 rtl8152_nic_reset(tp);
2923 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2927 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2929 ocp_data |= POWER_CUT;
2931 ocp_data &= ~POWER_CUT;
2932 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2934 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2935 ocp_data &= ~RESUME_INDICATE;
2936 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2939 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2943 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2945 ocp_data |= CPCR_RX_VLAN;
2947 ocp_data &= ~CPCR_RX_VLAN;
2948 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2951 static int rtl8152_set_features(struct net_device *dev,
2952 netdev_features_t features)
2954 netdev_features_t changed = features ^ dev->features;
2955 struct r8152 *tp = netdev_priv(dev);
2958 ret = usb_autopm_get_interface(tp->intf);
2962 mutex_lock(&tp->control);
2964 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2965 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2966 rtl_rx_vlan_en(tp, true);
2968 rtl_rx_vlan_en(tp, false);
2971 mutex_unlock(&tp->control);
2973 usb_autopm_put_interface(tp->intf);
2979 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2981 static u32 __rtl_get_wol(struct r8152 *tp)
2986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2987 if (ocp_data & LINK_ON_WAKE_EN)
2988 wolopts |= WAKE_PHY;
2990 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2991 if (ocp_data & UWF_EN)
2992 wolopts |= WAKE_UCAST;
2993 if (ocp_data & BWF_EN)
2994 wolopts |= WAKE_BCAST;
2995 if (ocp_data & MWF_EN)
2996 wolopts |= WAKE_MCAST;
2998 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2999 if (ocp_data & MAGIC_EN)
3000 wolopts |= WAKE_MAGIC;
3005 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3009 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3011 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3012 ocp_data &= ~LINK_ON_WAKE_EN;
3013 if (wolopts & WAKE_PHY)
3014 ocp_data |= LINK_ON_WAKE_EN;
3015 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3017 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3018 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3019 if (wolopts & WAKE_UCAST)
3021 if (wolopts & WAKE_BCAST)
3023 if (wolopts & WAKE_MCAST)
3025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3027 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3029 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3030 ocp_data &= ~MAGIC_EN;
3031 if (wolopts & WAKE_MAGIC)
3032 ocp_data |= MAGIC_EN;
3033 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3035 if (wolopts & WAKE_ANY)
3036 device_set_wakeup_enable(&tp->udev->dev, true);
3038 device_set_wakeup_enable(&tp->udev->dev, false);
3041 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3046 memset(u1u2, 0xff, sizeof(u1u2));
3048 memset(u1u2, 0x00, sizeof(u1u2));
3050 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3053 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3057 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3059 ocp_data |= LPM_U1U2_EN;
3061 ocp_data &= ~LPM_U1U2_EN;
3063 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3066 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3070 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3072 ocp_data |= U2P3_ENABLE;
3074 ocp_data &= ~U2P3_ENABLE;
3075 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3078 static void r8153b_ups_flags(struct r8152 *tp)
3082 if (tp->ups_info.green)
3083 ups_flags |= UPS_FLAGS_EN_GREEN;
3085 if (tp->ups_info.aldps)
3086 ups_flags |= UPS_FLAGS_EN_ALDPS;
3088 if (tp->ups_info.eee)
3089 ups_flags |= UPS_FLAGS_EN_EEE;
3091 if (tp->ups_info.flow_control)
3092 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3094 if (tp->ups_info.eee_ckdiv)
3095 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3097 if (tp->ups_info.eee_cmod_lv)
3098 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3100 if (tp->ups_info._10m_ckdiv)
3101 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3103 if (tp->ups_info.eee_plloff_100)
3104 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3106 if (tp->ups_info.eee_plloff_giga)
3107 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3109 if (tp->ups_info._250m_ckdiv)
3110 ups_flags |= UPS_FLAGS_250M_CKDIV;
3112 if (tp->ups_info.ctap_short_off)
3113 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3115 switch (tp->ups_info.speed_duplex) {
3117 ups_flags |= ups_flags_speed(1);
3120 ups_flags |= ups_flags_speed(2);
3122 case NWAY_100M_HALF:
3123 ups_flags |= ups_flags_speed(3);
3125 case NWAY_100M_FULL:
3126 ups_flags |= ups_flags_speed(4);
3128 case NWAY_1000M_FULL:
3129 ups_flags |= ups_flags_speed(5);
3131 case FORCE_10M_HALF:
3132 ups_flags |= ups_flags_speed(6);
3134 case FORCE_10M_FULL:
3135 ups_flags |= ups_flags_speed(7);
3137 case FORCE_100M_HALF:
3138 ups_flags |= ups_flags_speed(8);
3140 case FORCE_100M_FULL:
3141 ups_flags |= ups_flags_speed(9);
3147 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3150 static void r8153b_green_en(struct r8152 *tp, bool enable)
3155 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3156 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3157 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3159 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3160 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3161 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3164 data = sram_read(tp, SRAM_GREEN_CFG);
3165 data |= GREEN_ETH_EN;
3166 sram_write(tp, SRAM_GREEN_CFG, data);
3168 tp->ups_info.green = enable;
3171 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3176 for (i = 0; i < 500; i++) {
3177 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3178 data &= PHY_STAT_MASK;
3180 if (data == desired)
3182 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3183 data == PHY_STAT_EXT_INIT) {
3188 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3195 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3197 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3200 r8153b_ups_flags(tp);
3202 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3203 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3205 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3207 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3211 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3212 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3214 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3215 ocp_data &= ~BIT(0);
3216 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3218 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3219 ocp_data &= ~PCUT_STATUS;
3220 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3222 data = r8153_phy_status(tp, 0);
3225 case PHY_STAT_PWRDN:
3226 case PHY_STAT_EXT_INIT:
3228 test_bit(GREEN_ETHERNET, &tp->flags));
3230 data = r8152_mdio_read(tp, MII_BMCR);
3231 data &= ~BMCR_PDOWN;
3233 r8152_mdio_write(tp, MII_BMCR, data);
3235 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3239 if (data != PHY_STAT_LAN_ON)
3240 netif_warn(tp, link, tp->netdev,
3247 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3251 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3253 ocp_data |= PWR_EN | PHASE2_EN;
3255 ocp_data &= ~(PWR_EN | PHASE2_EN);
3256 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3258 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3259 ocp_data &= ~PCUT_STATUS;
3260 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3263 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3267 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3269 ocp_data |= PWR_EN | PHASE2_EN;
3271 ocp_data &= ~PWR_EN;
3272 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3274 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3275 ocp_data &= ~PCUT_STATUS;
3276 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3279 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3283 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3285 ocp_data |= UPCOMING_RUNTIME_D3;
3287 ocp_data &= ~UPCOMING_RUNTIME_D3;
3288 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3290 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3291 ocp_data &= ~LINK_CHG_EVENT;
3292 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3294 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3295 ocp_data &= ~LINK_CHANGE_FLAG;
3296 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3299 static bool rtl_can_wakeup(struct r8152 *tp)
3301 struct usb_device *udev = tp->udev;
3303 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3306 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3311 __rtl_set_wol(tp, WAKE_ANY);
3313 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3315 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3316 ocp_data |= LINK_OFF_WAKE_EN;
3317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3319 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3323 __rtl_set_wol(tp, tp->saved_wolopts);
3325 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3328 ocp_data &= ~LINK_OFF_WAKE_EN;
3329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3331 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3335 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3338 r8153_u1u2en(tp, false);
3339 r8153_u2p3en(tp, false);
3340 rtl_runtime_suspend_enable(tp, true);
3342 rtl_runtime_suspend_enable(tp, false);
3344 switch (tp->version) {
3351 r8153_u2p3en(tp, true);
3355 r8153_u1u2en(tp, true);
3359 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3362 r8153_queue_wake(tp, true);
3363 r8153b_u1u2en(tp, false);
3364 r8153_u2p3en(tp, false);
3365 rtl_runtime_suspend_enable(tp, true);
3366 r8153b_ups_en(tp, true);
3368 r8153b_ups_en(tp, false);
3369 r8153_queue_wake(tp, false);
3370 rtl_runtime_suspend_enable(tp, false);
3371 if (tp->udev->speed != USB_SPEED_HIGH)
3372 r8153b_u1u2en(tp, true);
3376 static void r8153_teredo_off(struct r8152 *tp)
3380 switch (tp->version) {
3388 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3389 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3391 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3396 /* The bit 0 ~ 7 are relative with teredo settings. They are
3397 * W1C (write 1 to clear), so set all 1 to disable it.
3399 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3406 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3407 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3408 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3411 static void rtl_reset_bmu(struct r8152 *tp)
3415 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3416 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3417 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3418 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3419 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3422 /* Clear the bp to stop the firmware before loading a new one */
3423 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3425 switch (tp->version) {
3434 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3439 if (type == MCU_TYPE_USB) {
3440 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3442 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3443 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3444 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3445 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3446 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3447 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3448 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3449 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3451 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3456 ocp_write_word(tp, type, PLA_BP_0, 0);
3457 ocp_write_word(tp, type, PLA_BP_1, 0);
3458 ocp_write_word(tp, type, PLA_BP_2, 0);
3459 ocp_write_word(tp, type, PLA_BP_3, 0);
3460 ocp_write_word(tp, type, PLA_BP_4, 0);
3461 ocp_write_word(tp, type, PLA_BP_5, 0);
3462 ocp_write_word(tp, type, PLA_BP_6, 0);
3463 ocp_write_word(tp, type, PLA_BP_7, 0);
3465 /* wait 3 ms to make sure the firmware is stopped */
3466 usleep_range(3000, 6000);
3467 ocp_write_word(tp, type, PLA_BP_BA, 0);
3470 static int r8153_patch_request(struct r8152 *tp, bool request)
3475 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3477 data |= PATCH_REQUEST;
3479 data &= ~PATCH_REQUEST;
3480 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3482 for (i = 0; request && i < 5000; i++) {
3483 usleep_range(1000, 2000);
3484 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3488 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3489 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3490 r8153_patch_request(tp, false);
3497 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3499 if (r8153_patch_request(tp, true)) {
3500 dev_err(&tp->intf->dev, "patch request fail\n");
3504 sram_write(tp, key_addr, patch_key);
3505 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3510 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3514 sram_write(tp, 0x0000, 0x0000);
3516 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3517 data &= ~PATCH_LOCK;
3518 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3520 sram_write(tp, key_addr, 0x0000);
3522 r8153_patch_request(tp, false);
3524 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3529 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3532 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3535 switch (tp->version) {
3541 patch_en_addr = 0xa01a;
3549 fw_offset = __le16_to_cpu(phy->fw_offset);
3550 if (fw_offset < sizeof(*phy)) {
3551 dev_err(&tp->intf->dev, "fw_offset too small\n");
3555 length = __le32_to_cpu(phy->blk_hdr.length);
3556 if (length < fw_offset) {
3557 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3561 length -= __le16_to_cpu(phy->fw_offset);
3562 if (!length || (length & 1)) {
3563 dev_err(&tp->intf->dev, "invalid block length\n");
3567 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3568 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3572 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3573 dev_err(&tp->intf->dev, "invalid base address register\n");
3577 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3578 dev_err(&tp->intf->dev,
3579 "invalid patch mode enabled register\n");
3583 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3584 dev_err(&tp->intf->dev,
3585 "invalid register to switch the mode\n");
3589 if (__le16_to_cpu(phy->bp_start) != bp_start) {
3590 dev_err(&tp->intf->dev,
3591 "invalid start register of break point\n");
3595 if (__le16_to_cpu(phy->bp_num) > 4) {
3596 dev_err(&tp->intf->dev, "invalid break point number\n");
3605 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3607 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3612 type = __le32_to_cpu(mac->blk_hdr.type);
3613 if (type == RTL_FW_PLA) {
3614 switch (tp->version) {
3619 bp_ba_addr = PLA_BP_BA;
3621 bp_start = PLA_BP_0;
3631 bp_ba_addr = PLA_BP_BA;
3632 bp_en_addr = PLA_BP_EN;
3633 bp_start = PLA_BP_0;
3639 } else if (type == RTL_FW_USB) {
3640 switch (tp->version) {
3646 bp_ba_addr = USB_BP_BA;
3647 bp_en_addr = USB_BP_EN;
3648 bp_start = USB_BP_0;
3654 bp_ba_addr = USB_BP_BA;
3655 bp_en_addr = USB_BP2_EN;
3656 bp_start = USB_BP_0;
3669 fw_offset = __le16_to_cpu(mac->fw_offset);
3670 if (fw_offset < sizeof(*mac)) {
3671 dev_err(&tp->intf->dev, "fw_offset too small\n");
3675 length = __le32_to_cpu(mac->blk_hdr.length);
3676 if (length < fw_offset) {
3677 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3681 length -= fw_offset;
3682 if (length < 4 || (length & 3)) {
3683 dev_err(&tp->intf->dev, "invalid block length\n");
3687 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3688 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3692 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3693 dev_err(&tp->intf->dev, "invalid base address register\n");
3697 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3698 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3702 if (__le16_to_cpu(mac->bp_start) != bp_start) {
3703 dev_err(&tp->intf->dev,
3704 "invalid start register of break point\n");
3708 if (__le16_to_cpu(mac->bp_num) > max_bp) {
3709 dev_err(&tp->intf->dev, "invalid break point number\n");
3713 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3715 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3725 /* Verify the checksum for the firmware file. It is calculated from the version
3726 * field to the end of the file. Compare the result with the checksum field to
3727 * make sure the file is correct.
3729 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3730 struct fw_header *fw_hdr, size_t size)
3732 unsigned char checksum[sizeof(fw_hdr->checksum)];
3733 struct crypto_shash *alg;
3734 struct shash_desc *sdesc;
3738 alg = crypto_alloc_shash("sha256", 0, 0);
3744 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3746 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3747 crypto_shash_digestsize(alg));
3751 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3752 sdesc = kmalloc(len, GFP_KERNEL);
3759 len = size - sizeof(fw_hdr->checksum);
3760 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3765 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3766 dev_err(&tp->intf->dev, "checksum fail\n");
3771 crypto_free_shash(alg);
3776 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3778 const struct firmware *fw = rtl_fw->fw;
3779 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3780 struct fw_mac *pla = NULL, *usb = NULL;
3781 struct fw_phy_patch_key *start = NULL;
3782 struct fw_phy_nc *phy_nc = NULL;
3783 struct fw_block *stop = NULL;
3787 if (fw->size < sizeof(*fw_hdr)) {
3788 dev_err(&tp->intf->dev, "file too small\n");
3792 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3798 for (i = sizeof(*fw_hdr); i < fw->size;) {
3799 struct fw_block *block = (struct fw_block *)&fw->data[i];
3802 if ((i + sizeof(*block)) > fw->size)
3805 type = __le32_to_cpu(block->type);
3808 if (__le32_to_cpu(block->length) != sizeof(*block))
3813 dev_err(&tp->intf->dev,
3814 "multiple PLA firmware encountered");
3818 pla = (struct fw_mac *)block;
3819 if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3820 dev_err(&tp->intf->dev,
3821 "check PLA firmware failed\n");
3827 dev_err(&tp->intf->dev,
3828 "multiple USB firmware encountered");
3832 usb = (struct fw_mac *)block;
3833 if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3834 dev_err(&tp->intf->dev,
3835 "check USB firmware failed\n");
3839 case RTL_FW_PHY_START:
3840 if (start || phy_nc || stop) {
3841 dev_err(&tp->intf->dev,
3842 "check PHY_START fail\n");
3846 if (__le32_to_cpu(block->length) != sizeof(*start)) {
3847 dev_err(&tp->intf->dev,
3848 "Invalid length for PHY_START\n");
3852 start = (struct fw_phy_patch_key *)block;
3854 case RTL_FW_PHY_STOP:
3855 if (stop || !start) {
3856 dev_err(&tp->intf->dev,
3857 "Check PHY_STOP fail\n");
3861 if (__le32_to_cpu(block->length) != sizeof(*block)) {
3862 dev_err(&tp->intf->dev,
3863 "Invalid length for PHY_STOP\n");
3870 if (!start || stop) {
3871 dev_err(&tp->intf->dev,
3872 "check PHY_NC fail\n");
3877 dev_err(&tp->intf->dev,
3878 "multiple PHY NC encountered\n");
3882 phy_nc = (struct fw_phy_nc *)block;
3883 if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3884 dev_err(&tp->intf->dev,
3885 "check PHY NC firmware failed\n");
3891 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3897 i += ALIGN(__le32_to_cpu(block->length), 8);
3901 if ((phy_nc || start) && !stop) {
3902 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3911 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3913 u16 mode_reg, bp_index;
3917 mode_reg = __le16_to_cpu(phy->mode_reg);
3918 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3919 sram_write(tp, __le16_to_cpu(phy->ba_reg),
3920 __le16_to_cpu(phy->ba_data));
3922 length = __le32_to_cpu(phy->blk_hdr.length);
3923 length -= __le16_to_cpu(phy->fw_offset);
3925 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3927 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3928 for (i = 0; i < num; i++)
3929 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3931 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3932 __le16_to_cpu(phy->patch_en_value));
3934 bp_index = __le16_to_cpu(phy->bp_start);
3935 num = __le16_to_cpu(phy->bp_num);
3936 for (i = 0; i < num; i++) {
3937 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3941 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3943 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3946 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3948 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3953 switch (__le32_to_cpu(mac->blk_hdr.type)) {
3955 type = MCU_TYPE_PLA;
3958 type = MCU_TYPE_USB;
3964 rtl_clear_bp(tp, type);
3966 /* Enable backup/restore of MACDBG. This is required after clearing PLA
3967 * break points and before applying the PLA firmware.
3969 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3970 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3971 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3972 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3975 length = __le32_to_cpu(mac->blk_hdr.length);
3976 length -= __le16_to_cpu(mac->fw_offset);
3979 data += __le16_to_cpu(mac->fw_offset);
3981 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3984 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3985 __le16_to_cpu(mac->bp_ba_value));
3987 bp_index = __le16_to_cpu(mac->bp_start);
3988 bp_num = __le16_to_cpu(mac->bp_num);
3989 for (i = 0; i < bp_num; i++) {
3990 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
3994 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
3996 ocp_write_word(tp, type, bp_en_addr,
3997 __le16_to_cpu(mac->bp_en_value));
3999 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4001 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4004 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4007 static void rtl8152_apply_firmware(struct r8152 *tp)
4009 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4010 const struct firmware *fw;
4011 struct fw_header *fw_hdr;
4012 struct fw_phy_patch_key *key;
4016 if (IS_ERR_OR_NULL(rtl_fw->fw))
4020 fw_hdr = (struct fw_header *)fw->data;
4025 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4026 struct fw_block *block = (struct fw_block *)&fw->data[i];
4028 switch (__le32_to_cpu(block->type)) {
4033 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4035 case RTL_FW_PHY_START:
4036 key = (struct fw_phy_patch_key *)block;
4037 key_addr = __le16_to_cpu(key->key_reg);
4038 r8153_pre_ram_code(tp, key_addr,
4039 __le16_to_cpu(key->key_data));
4041 case RTL_FW_PHY_STOP:
4043 r8153_post_ram_code(tp, key_addr);
4046 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4052 i += ALIGN(__le32_to_cpu(block->length), 8);
4056 if (rtl_fw->post_fw)
4057 rtl_fw->post_fw(tp);
4059 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4060 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4063 static void rtl8152_release_firmware(struct r8152 *tp)
4065 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4067 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4068 release_firmware(rtl_fw->fw);
4073 static int rtl8152_request_firmware(struct r8152 *tp)
4075 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4078 if (rtl_fw->fw || !rtl_fw->fw_name) {
4079 dev_info(&tp->intf->dev, "skip request firmware\n");
4084 rc = reject_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4088 rc = rtl8152_check_firmware(tp, rtl_fw);
4090 release_firmware(rtl_fw->fw);
4094 rtl_fw->fw = ERR_PTR(rc);
4096 dev_warn(&tp->intf->dev,
4097 "unable to load firmware patch %s (%ld)\n",
4098 rtl_fw->fw_name, rc);
4104 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4107 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4108 LINKENA | DIS_SDSAVE);
4110 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4116 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4118 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4119 ocp_reg_write(tp, OCP_EEE_DATA, reg);
4120 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4123 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4127 r8152_mmd_indirect(tp, dev, reg);
4128 data = ocp_reg_read(tp, OCP_EEE_DATA);
4129 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4134 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4136 r8152_mmd_indirect(tp, dev, reg);
4137 ocp_reg_write(tp, OCP_EEE_DATA, data);
4138 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4141 static void r8152_eee_en(struct r8152 *tp, bool enable)
4143 u16 config1, config2, config3;
4146 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4147 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4148 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4149 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4152 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4153 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4154 config1 |= sd_rise_time(1);
4155 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4156 config3 |= fast_snr(42);
4158 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4159 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4161 config1 |= sd_rise_time(7);
4162 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4163 config3 |= fast_snr(511);
4166 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4167 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4168 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4169 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4172 static void r8153_eee_en(struct r8152 *tp, bool enable)
4177 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4178 config = ocp_reg_read(tp, OCP_EEE_CFG);
4181 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4184 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4185 config &= ~EEE10_EN;
4188 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4189 ocp_reg_write(tp, OCP_EEE_CFG, config);
4191 tp->ups_info.eee = enable;
4194 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4196 switch (tp->version) {
4201 r8152_eee_en(tp, true);
4202 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4205 r8152_eee_en(tp, false);
4206 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4216 r8153_eee_en(tp, true);
4217 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4219 r8153_eee_en(tp, false);
4220 ocp_reg_write(tp, OCP_EEE_ADV, 0);
4228 static void r8152b_enable_fc(struct r8152 *tp)
4232 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4233 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4234 r8152_mdio_write(tp, MII_ADVERTISE, anar);
4236 tp->ups_info.flow_control = true;
4239 static void rtl8152_disable(struct r8152 *tp)
4241 r8152_aldps_en(tp, false);
4243 r8152_aldps_en(tp, true);
4246 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4248 rtl8152_apply_firmware(tp);
4249 rtl_eee_enable(tp, tp->eee_en);
4250 r8152_aldps_en(tp, true);
4251 r8152b_enable_fc(tp);
4253 set_bit(PHY_RESET, &tp->flags);
4256 static void wait_oob_link_list_ready(struct r8152 *tp)
4261 for (i = 0; i < 1000; i++) {
4262 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4263 if (ocp_data & LINK_LIST_READY)
4265 usleep_range(1000, 2000);
4269 static void r8152b_exit_oob(struct r8152 *tp)
4273 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4274 ocp_data &= ~RCR_ACPT_ALL;
4275 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4277 rxdy_gated_en(tp, true);
4278 r8153_teredo_off(tp);
4279 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4280 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4282 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4283 ocp_data &= ~NOW_IS_OOB;
4284 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4286 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4287 ocp_data &= ~MCU_BORW_EN;
4288 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4290 wait_oob_link_list_ready(tp);
4292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4293 ocp_data |= RE_INIT_LL;
4294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4296 wait_oob_link_list_ready(tp);
4298 rtl8152_nic_reset(tp);
4300 /* rx share fifo credit full threshold */
4301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4303 if (tp->udev->speed == USB_SPEED_FULL ||
4304 tp->udev->speed == USB_SPEED_LOW) {
4305 /* rx share fifo credit near full threshold */
4306 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4308 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4311 /* rx share fifo credit near full threshold */
4312 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4314 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4318 /* TX share fifo free credit full threshold */
4319 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4321 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4322 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4323 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4324 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4326 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4328 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4330 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4331 ocp_data |= TCR0_AUTO_FIFO;
4332 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4335 static void r8152b_enter_oob(struct r8152 *tp)
4339 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4340 ocp_data &= ~NOW_IS_OOB;
4341 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4343 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4344 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4345 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4349 wait_oob_link_list_ready(tp);
4351 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4352 ocp_data |= RE_INIT_LL;
4353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4355 wait_oob_link_list_ready(tp);
4357 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4359 rtl_rx_vlan_en(tp, true);
4361 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4362 ocp_data |= ALDPS_PROXY_MODE;
4363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4365 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4366 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4367 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4369 rxdy_gated_en(tp, false);
4371 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4372 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4373 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4376 static int r8153_pre_firmware_1(struct r8152 *tp)
4380 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4381 for (i = 0; i < 104; i++) {
4382 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4384 if (!(ocp_data & WTD1_EN))
4386 usleep_range(1000, 2000);
4392 static int r8153_post_firmware_1(struct r8152 *tp)
4394 /* set USB_BP_4 to support USB_SPEED_SUPER only */
4395 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4396 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4398 /* reset UPHY timer to 36 ms */
4399 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4404 static int r8153_pre_firmware_2(struct r8152 *tp)
4408 r8153_pre_firmware_1(tp);
4410 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4411 ocp_data &= ~FW_FIX_SUSPEND;
4412 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4417 static int r8153_post_firmware_2(struct r8152 *tp)
4421 /* enable bp0 if support USB_SPEED_SUPER only */
4422 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4423 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4425 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4428 /* reset UPHY timer to 36 ms */
4429 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4431 /* enable U3P3 check, set the counter to 4 */
4432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4434 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4435 ocp_data |= FW_FIX_SUSPEND;
4436 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4438 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4439 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4440 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4445 static int r8153_post_firmware_3(struct r8152 *tp)
4449 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4450 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4451 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4453 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4454 ocp_data |= FW_IP_RESET_EN;
4455 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4460 static int r8153b_pre_firmware_1(struct r8152 *tp)
4462 /* enable fc timer and set timer to 1 second. */
4463 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4464 CTRL_TIMER_EN | (1000 / 8));
4469 static int r8153b_post_firmware_1(struct r8152 *tp)
4473 /* enable bp0 for RTL8153-BND */
4474 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4475 if (ocp_data & BND_MASK) {
4476 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4478 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4481 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4482 ocp_data |= FLOW_CTRL_PATCH_OPT;
4483 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4485 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4486 ocp_data |= FC_PATCH_TASK;
4487 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4489 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4490 ocp_data |= FW_IP_RESET_EN;
4491 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4496 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4500 data = ocp_reg_read(tp, OCP_POWER_CFG);
4503 ocp_reg_write(tp, OCP_POWER_CFG, data);
4508 ocp_reg_write(tp, OCP_POWER_CFG, data);
4509 for (i = 0; i < 20; i++) {
4510 usleep_range(1000, 2000);
4511 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4516 tp->ups_info.aldps = enable;
4519 static void r8153_hw_phy_cfg(struct r8152 *tp)
4524 /* disable ALDPS before updating the PHY parameters */
4525 r8153_aldps_en(tp, false);
4527 /* disable EEE before updating the PHY parameters */
4528 rtl_eee_enable(tp, false);
4530 rtl8152_apply_firmware(tp);
4532 if (tp->version == RTL_VER_03) {
4533 data = ocp_reg_read(tp, OCP_EEE_CFG);
4534 data &= ~CTAP_SHORT_EN;
4535 ocp_reg_write(tp, OCP_EEE_CFG, data);
4538 data = ocp_reg_read(tp, OCP_POWER_CFG);
4539 data |= EEE_CLKDIV_EN;
4540 ocp_reg_write(tp, OCP_POWER_CFG, data);
4542 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4543 data |= EN_10M_BGOFF;
4544 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4545 data = ocp_reg_read(tp, OCP_POWER_CFG);
4546 data |= EN_10M_PLLOFF;
4547 ocp_reg_write(tp, OCP_POWER_CFG, data);
4548 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4550 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4551 ocp_data |= PFM_PWM_SWITCH;
4552 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4554 /* Enable LPF corner auto tune */
4555 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4557 /* Adjust 10M Amplitude */
4558 sram_write(tp, SRAM_10M_AMP1, 0x00af);
4559 sram_write(tp, SRAM_10M_AMP2, 0x0208);
4562 rtl_eee_enable(tp, true);
4564 r8153_aldps_en(tp, true);
4565 r8152b_enable_fc(tp);
4567 switch (tp->version) {
4574 r8153_u2p3en(tp, true);
4578 set_bit(PHY_RESET, &tp->flags);
4581 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4586 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4587 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
4588 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4593 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4598 /* disable ALDPS before updating the PHY parameters */
4599 r8153_aldps_en(tp, false);
4601 /* disable EEE before updating the PHY parameters */
4602 rtl_eee_enable(tp, false);
4604 rtl8152_apply_firmware(tp);
4606 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4608 data = sram_read(tp, SRAM_GREEN_CFG);
4610 sram_write(tp, SRAM_GREEN_CFG, data);
4611 data = ocp_reg_read(tp, OCP_NCTL_CFG);
4612 data |= PGA_RETURN_EN;
4613 ocp_reg_write(tp, OCP_NCTL_CFG, data);
4615 /* ADC Bias Calibration:
4616 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4617 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4620 ocp_data = r8152_efuse_read(tp, 0x7d);
4621 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4623 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4625 /* ups mode tx-link-pulse timing adjustment:
4626 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4627 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4629 ocp_data = ocp_reg_read(tp, 0xc426);
4632 u32 swr_cnt_1ms_ini;
4634 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4635 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4636 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4637 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4640 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4641 ocp_data |= PFM_PWM_SWITCH;
4642 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4645 if (!r8153_patch_request(tp, true)) {
4646 data = ocp_reg_read(tp, OCP_POWER_CFG);
4647 data |= EEE_CLKDIV_EN;
4648 ocp_reg_write(tp, OCP_POWER_CFG, data);
4649 tp->ups_info.eee_ckdiv = true;
4651 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4652 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4653 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4654 tp->ups_info.eee_cmod_lv = true;
4655 tp->ups_info._10m_ckdiv = true;
4656 tp->ups_info.eee_plloff_giga = true;
4658 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4659 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4660 tp->ups_info._250m_ckdiv = true;
4662 r8153_patch_request(tp, false);
4666 rtl_eee_enable(tp, true);
4668 r8153_aldps_en(tp, true);
4669 r8152b_enable_fc(tp);
4671 set_bit(PHY_RESET, &tp->flags);
4674 static void r8153_first_init(struct r8152 *tp)
4678 rxdy_gated_en(tp, true);
4679 r8153_teredo_off(tp);
4681 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4682 ocp_data &= ~RCR_ACPT_ALL;
4683 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4685 rtl8152_nic_reset(tp);
4688 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4689 ocp_data &= ~NOW_IS_OOB;
4690 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4692 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4693 ocp_data &= ~MCU_BORW_EN;
4694 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4696 wait_oob_link_list_ready(tp);
4698 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4699 ocp_data |= RE_INIT_LL;
4700 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4702 wait_oob_link_list_ready(tp);
4704 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4706 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4707 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4708 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4710 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4711 ocp_data |= TCR0_AUTO_FIFO;
4712 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4714 rtl8152_nic_reset(tp);
4716 /* rx share fifo credit full threshold */
4717 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4718 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4719 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4720 /* TX share fifo free credit full threshold */
4721 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4724 static void r8153_enter_oob(struct r8152 *tp)
4728 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4729 ocp_data &= ~NOW_IS_OOB;
4730 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4735 wait_oob_link_list_ready(tp);
4737 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4738 ocp_data |= RE_INIT_LL;
4739 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4741 wait_oob_link_list_ready(tp);
4743 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4744 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4746 switch (tp->version) {
4751 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4752 ocp_data &= ~TEREDO_WAKE_MASK;
4753 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4758 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4759 * type. Set it to zero. bits[7:0] are the W1C bits about
4760 * the events. Set them to all 1 to clear them.
4762 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4769 rtl_rx_vlan_en(tp, true);
4771 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4772 ocp_data |= ALDPS_PROXY_MODE;
4773 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4775 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4776 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4777 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4779 rxdy_gated_en(tp, false);
4781 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4782 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4783 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4786 static void rtl8153_disable(struct r8152 *tp)
4788 r8153_aldps_en(tp, false);
4791 r8153_aldps_en(tp, true);
4794 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4800 if (autoneg == AUTONEG_DISABLE) {
4801 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4806 bmcr = BMCR_SPEED10;
4807 if (duplex == DUPLEX_FULL) {
4808 bmcr |= BMCR_FULLDPLX;
4809 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4811 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4815 bmcr = BMCR_SPEED100;
4816 if (duplex == DUPLEX_FULL) {
4817 bmcr |= BMCR_FULLDPLX;
4818 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4820 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4824 if (tp->mii.supports_gmii) {
4825 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4826 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4835 if (duplex == DUPLEX_FULL)
4836 tp->mii.full_duplex = 1;
4838 tp->mii.full_duplex = 0;
4840 tp->mii.force_media = 1;
4845 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4846 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4848 if (tp->mii.supports_gmii)
4849 support |= RTL_ADVERTISED_1000_FULL;
4851 if (!(advertising & support))
4854 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4855 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4856 ADVERTISE_100HALF | ADVERTISE_100FULL);
4857 if (advertising & RTL_ADVERTISED_10_HALF) {
4858 tmp1 |= ADVERTISE_10HALF;
4859 tp->ups_info.speed_duplex = NWAY_10M_HALF;
4861 if (advertising & RTL_ADVERTISED_10_FULL) {
4862 tmp1 |= ADVERTISE_10FULL;
4863 tp->ups_info.speed_duplex = NWAY_10M_FULL;
4866 if (advertising & RTL_ADVERTISED_100_HALF) {
4867 tmp1 |= ADVERTISE_100HALF;
4868 tp->ups_info.speed_duplex = NWAY_100M_HALF;
4870 if (advertising & RTL_ADVERTISED_100_FULL) {
4871 tmp1 |= ADVERTISE_100FULL;
4872 tp->ups_info.speed_duplex = NWAY_100M_FULL;
4876 r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4877 tp->mii.advertising = tmp1;
4880 if (tp->mii.supports_gmii) {
4883 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4884 tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4885 ADVERTISE_1000HALF);
4887 if (advertising & RTL_ADVERTISED_1000_FULL) {
4888 tmp1 |= ADVERTISE_1000FULL;
4889 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4893 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4896 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4898 tp->mii.force_media = 0;
4901 if (test_and_clear_bit(PHY_RESET, &tp->flags))
4904 r8152_mdio_write(tp, MII_BMCR, bmcr);
4906 if (bmcr & BMCR_RESET) {
4909 for (i = 0; i < 50; i++) {
4911 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4920 static void rtl8152_up(struct r8152 *tp)
4922 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4925 r8152_aldps_en(tp, false);
4926 r8152b_exit_oob(tp);
4927 r8152_aldps_en(tp, true);
4930 static void rtl8152_down(struct r8152 *tp)
4932 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4933 rtl_drop_queued_tx(tp);
4937 r8152_power_cut_en(tp, false);
4938 r8152_aldps_en(tp, false);
4939 r8152b_enter_oob(tp);
4940 r8152_aldps_en(tp, true);
4943 static void rtl8153_up(struct r8152 *tp)
4947 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4950 r8153_u1u2en(tp, false);
4951 r8153_u2p3en(tp, false);
4952 r8153_aldps_en(tp, false);
4953 r8153_first_init(tp);
4955 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4956 ocp_data |= LANWAKE_CLR_EN;
4957 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4959 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4960 ocp_data &= ~LANWAKE_PIN;
4961 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4963 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4964 ocp_data &= ~DELAY_PHY_PWR_CHG;
4965 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4967 r8153_aldps_en(tp, true);
4969 switch (tp->version) {
4976 r8153_u2p3en(tp, true);
4980 r8153_u1u2en(tp, true);
4983 static void rtl8153_down(struct r8152 *tp)
4987 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4988 rtl_drop_queued_tx(tp);
4992 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4993 ocp_data &= ~LANWAKE_CLR_EN;
4994 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4996 r8153_u1u2en(tp, false);
4997 r8153_u2p3en(tp, false);
4998 r8153_power_cut_en(tp, false);
4999 r8153_aldps_en(tp, false);
5000 r8153_enter_oob(tp);
5001 r8153_aldps_en(tp, true);
5004 static void rtl8153b_up(struct r8152 *tp)
5008 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5011 r8153b_u1u2en(tp, false);
5012 r8153_u2p3en(tp, false);
5013 r8153_aldps_en(tp, false);
5015 r8153_first_init(tp);
5016 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5018 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5019 ocp_data &= ~PLA_MCU_SPDWN_EN;
5020 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5022 r8153_aldps_en(tp, true);
5024 if (tp->udev->speed != USB_SPEED_HIGH)
5025 r8153b_u1u2en(tp, true);
5028 static void rtl8153b_down(struct r8152 *tp)
5032 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5033 rtl_drop_queued_tx(tp);
5037 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5038 ocp_data |= PLA_MCU_SPDWN_EN;
5039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5041 r8153b_u1u2en(tp, false);
5042 r8153_u2p3en(tp, false);
5043 r8153b_power_cut_en(tp, false);
5044 r8153_aldps_en(tp, false);
5045 r8153_enter_oob(tp);
5046 r8153_aldps_en(tp, true);
5049 static bool rtl8152_in_nway(struct r8152 *tp)
5053 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5054 tp->ocp_base = 0x2000;
5055 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
5056 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5058 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5059 if (nway_state & 0xc000)
5065 static bool rtl8153_in_nway(struct r8152 *tp)
5067 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5069 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5075 static void set_carrier(struct r8152 *tp)
5077 struct net_device *netdev = tp->netdev;
5078 struct napi_struct *napi = &tp->napi;
5081 speed = rtl8152_get_speed(tp);
5083 if (speed & LINK_STATUS) {
5084 if (!netif_carrier_ok(netdev)) {
5085 tp->rtl_ops.enable(tp);
5086 netif_stop_queue(netdev);
5088 netif_carrier_on(netdev);
5090 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5091 _rtl8152_set_rx_mode(netdev);
5092 napi_enable(&tp->napi);
5093 netif_wake_queue(netdev);
5094 netif_info(tp, link, netdev, "carrier on\n");
5095 } else if (netif_queue_stopped(netdev) &&
5096 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5097 netif_wake_queue(netdev);
5100 if (netif_carrier_ok(netdev)) {
5101 netif_carrier_off(netdev);
5102 tasklet_disable(&tp->tx_tl);
5104 tp->rtl_ops.disable(tp);
5106 tasklet_enable(&tp->tx_tl);
5107 netif_info(tp, link, netdev, "carrier off\n");
5112 static void rtl_work_func_t(struct work_struct *work)
5114 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5116 /* If the device is unplugged or !netif_running(), the workqueue
5117 * doesn't need to wake the device, and could return directly.
5119 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5122 if (usb_autopm_get_interface(tp->intf) < 0)
5125 if (!test_bit(WORK_ENABLE, &tp->flags))
5128 if (!mutex_trylock(&tp->control)) {
5129 schedule_delayed_work(&tp->schedule, 0);
5133 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5136 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5137 _rtl8152_set_rx_mode(tp->netdev);
5139 /* don't schedule tasket before linking */
5140 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5141 netif_carrier_ok(tp->netdev))
5142 tasklet_schedule(&tp->tx_tl);
5144 mutex_unlock(&tp->control);
5147 usb_autopm_put_interface(tp->intf);
5150 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5152 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5154 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5157 if (usb_autopm_get_interface(tp->intf) < 0)
5160 mutex_lock(&tp->control);
5162 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5163 tp->rtl_fw.retry = false;
5164 tp->rtl_fw.fw = NULL;
5166 /* Delay execution in case reject_firmware() is not ready yet.
5168 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5172 tp->rtl_ops.hw_phy_cfg(tp);
5174 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5178 mutex_unlock(&tp->control);
5180 usb_autopm_put_interface(tp->intf);
5183 #ifdef CONFIG_PM_SLEEP
5184 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5187 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5190 case PM_HIBERNATION_PREPARE:
5191 case PM_SUSPEND_PREPARE:
5192 usb_autopm_get_interface(tp->intf);
5195 case PM_POST_HIBERNATION:
5196 case PM_POST_SUSPEND:
5197 usb_autopm_put_interface(tp->intf);
5200 case PM_POST_RESTORE:
5201 case PM_RESTORE_PREPARE:
5210 static int rtl8152_open(struct net_device *netdev)
5212 struct r8152 *tp = netdev_priv(netdev);
5215 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5216 cancel_delayed_work_sync(&tp->hw_phy_work);
5217 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5220 res = alloc_all_mem(tp);
5224 res = usb_autopm_get_interface(tp->intf);
5228 mutex_lock(&tp->control);
5232 netif_carrier_off(netdev);
5233 netif_start_queue(netdev);
5234 set_bit(WORK_ENABLE, &tp->flags);
5236 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5239 netif_device_detach(tp->netdev);
5240 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5244 napi_enable(&tp->napi);
5245 tasklet_enable(&tp->tx_tl);
5247 mutex_unlock(&tp->control);
5249 usb_autopm_put_interface(tp->intf);
5250 #ifdef CONFIG_PM_SLEEP
5251 tp->pm_notifier.notifier_call = rtl_notifier;
5252 register_pm_notifier(&tp->pm_notifier);
5257 mutex_unlock(&tp->control);
5258 usb_autopm_put_interface(tp->intf);
5265 static int rtl8152_close(struct net_device *netdev)
5267 struct r8152 *tp = netdev_priv(netdev);
5270 #ifdef CONFIG_PM_SLEEP
5271 unregister_pm_notifier(&tp->pm_notifier);
5273 tasklet_disable(&tp->tx_tl);
5274 clear_bit(WORK_ENABLE, &tp->flags);
5275 usb_kill_urb(tp->intr_urb);
5276 cancel_delayed_work_sync(&tp->schedule);
5277 napi_disable(&tp->napi);
5278 netif_stop_queue(netdev);
5280 res = usb_autopm_get_interface(tp->intf);
5281 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5282 rtl_drop_queued_tx(tp);
5285 mutex_lock(&tp->control);
5287 tp->rtl_ops.down(tp);
5289 mutex_unlock(&tp->control);
5293 usb_autopm_put_interface(tp->intf);
5300 static void rtl_tally_reset(struct r8152 *tp)
5304 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5305 ocp_data |= TALLY_RESET;
5306 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5309 static void r8152b_init(struct r8152 *tp)
5314 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5317 data = r8152_mdio_read(tp, MII_BMCR);
5318 if (data & BMCR_PDOWN) {
5319 data &= ~BMCR_PDOWN;
5320 r8152_mdio_write(tp, MII_BMCR, data);
5323 r8152_aldps_en(tp, false);
5325 if (tp->version == RTL_VER_01) {
5326 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5327 ocp_data &= ~LED_MODE_MASK;
5328 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5331 r8152_power_cut_en(tp, false);
5333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5334 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5335 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5336 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5337 ocp_data &= ~MCU_CLK_RATIO_MASK;
5338 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5339 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5340 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5341 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5342 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5344 rtl_tally_reset(tp);
5346 /* enable rx aggregation */
5347 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5348 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5349 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5352 static void r8153_init(struct r8152 *tp)
5358 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5361 r8153_u1u2en(tp, false);
5363 for (i = 0; i < 500; i++) {
5364 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5369 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5373 data = r8153_phy_status(tp, 0);
5375 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5376 tp->version == RTL_VER_05)
5377 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5379 data = r8152_mdio_read(tp, MII_BMCR);
5380 if (data & BMCR_PDOWN) {
5381 data &= ~BMCR_PDOWN;
5382 r8152_mdio_write(tp, MII_BMCR, data);
5385 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5387 r8153_u2p3en(tp, false);
5389 if (tp->version == RTL_VER_04) {
5390 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5391 ocp_data &= ~pwd_dn_scale_mask;
5392 ocp_data |= pwd_dn_scale(96);
5393 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5395 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5396 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5397 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5398 } else if (tp->version == RTL_VER_05) {
5399 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5400 ocp_data &= ~ECM_ALDPS;
5401 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5403 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5404 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5405 ocp_data &= ~DYNAMIC_BURST;
5407 ocp_data |= DYNAMIC_BURST;
5408 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5409 } else if (tp->version == RTL_VER_06) {
5410 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5411 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5412 ocp_data &= ~DYNAMIC_BURST;
5414 ocp_data |= DYNAMIC_BURST;
5415 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5417 r8153_queue_wake(tp, false);
5419 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5420 if (rtl8152_get_speed(tp) & LINK_STATUS)
5421 ocp_data |= CUR_LINK_OK;
5423 ocp_data &= ~CUR_LINK_OK;
5424 ocp_data |= POLL_LINK_CHG;
5425 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5428 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5429 ocp_data |= EP4_FULL_FC;
5430 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5432 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5433 ocp_data &= ~TIMER11_EN;
5434 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5437 ocp_data &= ~LED_MODE_MASK;
5438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5440 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5441 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5442 ocp_data |= LPM_TIMER_500MS;
5444 ocp_data |= LPM_TIMER_500US;
5445 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5447 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5448 ocp_data &= ~SEN_VAL_MASK;
5449 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5450 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5452 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5454 /* MAC clock speed down */
5455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
5456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
5457 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
5458 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
5460 r8153_power_cut_en(tp, false);
5461 rtl_runtime_suspend_enable(tp, false);
5462 r8153_u1u2en(tp, true);
5463 usb_enable_lpm(tp->udev);
5465 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5466 ocp_data |= LANWAKE_CLR_EN;
5467 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5469 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5470 ocp_data &= ~LANWAKE_PIN;
5471 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5473 /* rx aggregation */
5474 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5475 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5476 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5477 ocp_data |= RX_AGG_DISABLE;
5479 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5481 rtl_tally_reset(tp);
5483 switch (tp->udev->speed) {
5484 case USB_SPEED_SUPER:
5485 case USB_SPEED_SUPER_PLUS:
5486 tp->coalesce = COALESCE_SUPER;
5488 case USB_SPEED_HIGH:
5489 tp->coalesce = COALESCE_HIGH;
5492 tp->coalesce = COALESCE_SLOW;
5497 static void r8153b_init(struct r8152 *tp)
5503 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5506 r8153b_u1u2en(tp, false);
5508 for (i = 0; i < 500; i++) {
5509 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5514 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5518 data = r8153_phy_status(tp, 0);
5520 data = r8152_mdio_read(tp, MII_BMCR);
5521 if (data & BMCR_PDOWN) {
5522 data &= ~BMCR_PDOWN;
5523 r8152_mdio_write(tp, MII_BMCR, data);
5526 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5528 r8153_u2p3en(tp, false);
5530 /* MSC timer = 0xfff * 8ms = 32760 ms */
5531 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5533 /* U1/U2/L1 idle timer. 500 us */
5534 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5536 r8153b_power_cut_en(tp, false);
5537 r8153b_ups_en(tp, false);
5538 r8153_queue_wake(tp, false);
5539 rtl_runtime_suspend_enable(tp, false);
5541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5542 if (rtl8152_get_speed(tp) & LINK_STATUS)
5543 ocp_data |= CUR_LINK_OK;
5545 ocp_data &= ~CUR_LINK_OK;
5546 ocp_data |= POLL_LINK_CHG;
5547 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5549 if (tp->udev->speed != USB_SPEED_HIGH)
5550 r8153b_u1u2en(tp, true);
5551 usb_enable_lpm(tp->udev);
5553 /* MAC clock speed down */
5554 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5555 ocp_data |= MAC_CLK_SPDWN_EN;
5556 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5558 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5559 ocp_data &= ~PLA_MCU_SPDWN_EN;
5560 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5562 if (tp->version == RTL_VER_09) {
5563 /* Disable Test IO for 32QFN */
5564 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5565 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5566 ocp_data |= TEST_IO_OFF;
5567 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5571 set_bit(GREEN_ETHERNET, &tp->flags);
5573 /* rx aggregation */
5574 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5575 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5576 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5578 rtl_tally_reset(tp);
5580 tp->coalesce = 15000; /* 15 us */
5583 static int rtl8152_pre_reset(struct usb_interface *intf)
5585 struct r8152 *tp = usb_get_intfdata(intf);
5586 struct net_device *netdev;
5591 netdev = tp->netdev;
5592 if (!netif_running(netdev))
5595 netif_stop_queue(netdev);
5596 tasklet_disable(&tp->tx_tl);
5597 clear_bit(WORK_ENABLE, &tp->flags);
5598 usb_kill_urb(tp->intr_urb);
5599 cancel_delayed_work_sync(&tp->schedule);
5600 napi_disable(&tp->napi);
5601 if (netif_carrier_ok(netdev)) {
5602 mutex_lock(&tp->control);
5603 tp->rtl_ops.disable(tp);
5604 mutex_unlock(&tp->control);
5610 static int rtl8152_post_reset(struct usb_interface *intf)
5612 struct r8152 *tp = usb_get_intfdata(intf);
5613 struct net_device *netdev;
5619 /* reset the MAC adddress in case of policy change */
5620 if (determine_ethernet_addr(tp, &sa) >= 0) {
5622 dev_set_mac_address (tp->netdev, &sa, NULL);
5626 netdev = tp->netdev;
5627 if (!netif_running(netdev))
5630 set_bit(WORK_ENABLE, &tp->flags);
5631 if (netif_carrier_ok(netdev)) {
5632 mutex_lock(&tp->control);
5633 tp->rtl_ops.enable(tp);
5635 _rtl8152_set_rx_mode(netdev);
5636 mutex_unlock(&tp->control);
5639 napi_enable(&tp->napi);
5640 tasklet_enable(&tp->tx_tl);
5641 netif_wake_queue(netdev);
5642 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5644 if (!list_empty(&tp->rx_done))
5645 napi_schedule(&tp->napi);
5650 static bool delay_autosuspend(struct r8152 *tp)
5652 bool sw_linking = !!netif_carrier_ok(tp->netdev);
5653 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5655 /* This means a linking change occurs and the driver doesn't detect it,
5656 * yet. If the driver has disabled tx/rx and hw is linking on, the
5657 * device wouldn't wake up by receiving any packet.
5659 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5662 /* If the linking down is occurred by nway, the device may miss the
5663 * linking change event. And it wouldn't wake when linking on.
5665 if (!sw_linking && tp->rtl_ops.in_nway(tp))
5667 else if (!skb_queue_empty(&tp->tx_queue))
5673 static int rtl8152_runtime_resume(struct r8152 *tp)
5675 struct net_device *netdev = tp->netdev;
5677 if (netif_running(netdev) && netdev->flags & IFF_UP) {
5678 struct napi_struct *napi = &tp->napi;
5680 tp->rtl_ops.autosuspend_en(tp, false);
5682 set_bit(WORK_ENABLE, &tp->flags);
5684 if (netif_carrier_ok(netdev)) {
5685 if (rtl8152_get_speed(tp) & LINK_STATUS) {
5688 netif_carrier_off(netdev);
5689 tp->rtl_ops.disable(tp);
5690 netif_info(tp, link, netdev, "linking down\n");
5695 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5696 smp_mb__after_atomic();
5698 if (!list_empty(&tp->rx_done))
5699 napi_schedule(&tp->napi);
5701 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5703 if (netdev->flags & IFF_UP)
5704 tp->rtl_ops.autosuspend_en(tp, false);
5706 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5712 static int rtl8152_system_resume(struct r8152 *tp)
5714 struct net_device *netdev = tp->netdev;
5716 netif_device_attach(netdev);
5718 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5720 netif_carrier_off(netdev);
5721 set_bit(WORK_ENABLE, &tp->flags);
5722 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5728 static int rtl8152_runtime_suspend(struct r8152 *tp)
5730 struct net_device *netdev = tp->netdev;
5733 set_bit(SELECTIVE_SUSPEND, &tp->flags);
5734 smp_mb__after_atomic();
5736 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5739 if (netif_carrier_ok(netdev)) {
5742 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5743 ocp_data = rcr & ~RCR_ACPT_ALL;
5744 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5745 rxdy_gated_en(tp, true);
5746 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5748 if (!(ocp_data & RXFIFO_EMPTY)) {
5749 rxdy_gated_en(tp, false);
5750 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5751 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5752 smp_mb__after_atomic();
5758 clear_bit(WORK_ENABLE, &tp->flags);
5759 usb_kill_urb(tp->intr_urb);
5761 tp->rtl_ops.autosuspend_en(tp, true);
5763 if (netif_carrier_ok(netdev)) {
5764 struct napi_struct *napi = &tp->napi;
5768 rxdy_gated_en(tp, false);
5769 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5773 if (delay_autosuspend(tp)) {
5774 rtl8152_runtime_resume(tp);
5783 static int rtl8152_system_suspend(struct r8152 *tp)
5785 struct net_device *netdev = tp->netdev;
5787 netif_device_detach(netdev);
5789 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5790 struct napi_struct *napi = &tp->napi;
5792 clear_bit(WORK_ENABLE, &tp->flags);
5793 usb_kill_urb(tp->intr_urb);
5794 tasklet_disable(&tp->tx_tl);
5796 cancel_delayed_work_sync(&tp->schedule);
5797 tp->rtl_ops.down(tp);
5799 tasklet_enable(&tp->tx_tl);
5805 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5807 struct r8152 *tp = usb_get_intfdata(intf);
5810 mutex_lock(&tp->control);
5812 if (PMSG_IS_AUTO(message))
5813 ret = rtl8152_runtime_suspend(tp);
5815 ret = rtl8152_system_suspend(tp);
5817 mutex_unlock(&tp->control);
5822 static int rtl8152_resume(struct usb_interface *intf)
5824 struct r8152 *tp = usb_get_intfdata(intf);
5827 mutex_lock(&tp->control);
5829 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5830 ret = rtl8152_runtime_resume(tp);
5832 ret = rtl8152_system_resume(tp);
5834 mutex_unlock(&tp->control);
5839 static int rtl8152_reset_resume(struct usb_interface *intf)
5841 struct r8152 *tp = usb_get_intfdata(intf);
5843 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5844 tp->rtl_ops.init(tp);
5845 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5846 set_ethernet_addr(tp);
5847 return rtl8152_resume(intf);
5850 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5852 struct r8152 *tp = netdev_priv(dev);
5854 if (usb_autopm_get_interface(tp->intf) < 0)
5857 if (!rtl_can_wakeup(tp)) {
5861 mutex_lock(&tp->control);
5862 wol->supported = WAKE_ANY;
5863 wol->wolopts = __rtl_get_wol(tp);
5864 mutex_unlock(&tp->control);
5867 usb_autopm_put_interface(tp->intf);
5870 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5872 struct r8152 *tp = netdev_priv(dev);
5875 if (!rtl_can_wakeup(tp))
5878 if (wol->wolopts & ~WAKE_ANY)
5881 ret = usb_autopm_get_interface(tp->intf);
5885 mutex_lock(&tp->control);
5887 __rtl_set_wol(tp, wol->wolopts);
5888 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5890 mutex_unlock(&tp->control);
5892 usb_autopm_put_interface(tp->intf);
5898 static u32 rtl8152_get_msglevel(struct net_device *dev)
5900 struct r8152 *tp = netdev_priv(dev);
5902 return tp->msg_enable;
5905 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5907 struct r8152 *tp = netdev_priv(dev);
5909 tp->msg_enable = value;
5912 static void rtl8152_get_drvinfo(struct net_device *netdev,
5913 struct ethtool_drvinfo *info)
5915 struct r8152 *tp = netdev_priv(netdev);
5917 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5918 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5919 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5920 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5921 strlcpy(info->fw_version, tp->rtl_fw.version,
5922 sizeof(info->fw_version));
5926 int rtl8152_get_link_ksettings(struct net_device *netdev,
5927 struct ethtool_link_ksettings *cmd)
5929 struct r8152 *tp = netdev_priv(netdev);
5932 if (!tp->mii.mdio_read)
5935 ret = usb_autopm_get_interface(tp->intf);
5939 mutex_lock(&tp->control);
5941 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5943 mutex_unlock(&tp->control);
5945 usb_autopm_put_interface(tp->intf);
5951 static int rtl8152_set_link_ksettings(struct net_device *dev,
5952 const struct ethtool_link_ksettings *cmd)
5954 struct r8152 *tp = netdev_priv(dev);
5955 u32 advertising = 0;
5958 ret = usb_autopm_get_interface(tp->intf);
5962 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5963 cmd->link_modes.advertising))
5964 advertising |= RTL_ADVERTISED_10_HALF;
5966 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5967 cmd->link_modes.advertising))
5968 advertising |= RTL_ADVERTISED_10_FULL;
5970 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5971 cmd->link_modes.advertising))
5972 advertising |= RTL_ADVERTISED_100_HALF;
5974 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5975 cmd->link_modes.advertising))
5976 advertising |= RTL_ADVERTISED_100_FULL;
5978 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5979 cmd->link_modes.advertising))
5980 advertising |= RTL_ADVERTISED_1000_HALF;
5982 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5983 cmd->link_modes.advertising))
5984 advertising |= RTL_ADVERTISED_1000_FULL;
5986 mutex_lock(&tp->control);
5988 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5989 cmd->base.duplex, advertising);
5991 tp->autoneg = cmd->base.autoneg;
5992 tp->speed = cmd->base.speed;
5993 tp->duplex = cmd->base.duplex;
5994 tp->advertising = advertising;
5997 mutex_unlock(&tp->control);
5999 usb_autopm_put_interface(tp->intf);
6005 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6012 "tx_single_collisions",
6013 "tx_multi_collisions",
6021 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6025 return ARRAY_SIZE(rtl8152_gstrings);
6031 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6032 struct ethtool_stats *stats, u64 *data)
6034 struct r8152 *tp = netdev_priv(dev);
6035 struct tally_counter tally;
6037 if (usb_autopm_get_interface(tp->intf) < 0)
6040 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6042 usb_autopm_put_interface(tp->intf);
6044 data[0] = le64_to_cpu(tally.tx_packets);
6045 data[1] = le64_to_cpu(tally.rx_packets);
6046 data[2] = le64_to_cpu(tally.tx_errors);
6047 data[3] = le32_to_cpu(tally.rx_errors);
6048 data[4] = le16_to_cpu(tally.rx_missed);
6049 data[5] = le16_to_cpu(tally.align_errors);
6050 data[6] = le32_to_cpu(tally.tx_one_collision);
6051 data[7] = le32_to_cpu(tally.tx_multi_collision);
6052 data[8] = le64_to_cpu(tally.rx_unicast);
6053 data[9] = le64_to_cpu(tally.rx_broadcast);
6054 data[10] = le32_to_cpu(tally.rx_multicast);
6055 data[11] = le16_to_cpu(tally.tx_aborted);
6056 data[12] = le16_to_cpu(tally.tx_underrun);
6059 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6061 switch (stringset) {
6063 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
6068 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6070 u32 lp, adv, supported = 0;
6073 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6074 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6076 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6077 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6079 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6080 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6082 eee->eee_enabled = tp->eee_en;
6083 eee->eee_active = !!(supported & adv & lp);
6084 eee->supported = supported;
6085 eee->advertised = tp->eee_adv;
6086 eee->lp_advertised = lp;
6091 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6093 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6095 tp->eee_en = eee->eee_enabled;
6098 rtl_eee_enable(tp, tp->eee_en);
6103 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6105 u32 lp, adv, supported = 0;
6108 val = ocp_reg_read(tp, OCP_EEE_ABLE);
6109 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6111 val = ocp_reg_read(tp, OCP_EEE_ADV);
6112 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6114 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6115 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6117 eee->eee_enabled = tp->eee_en;
6118 eee->eee_active = !!(supported & adv & lp);
6119 eee->supported = supported;
6120 eee->advertised = tp->eee_adv;
6121 eee->lp_advertised = lp;
6127 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6129 struct r8152 *tp = netdev_priv(net);
6132 ret = usb_autopm_get_interface(tp->intf);
6136 mutex_lock(&tp->control);
6138 ret = tp->rtl_ops.eee_get(tp, edata);
6140 mutex_unlock(&tp->control);
6142 usb_autopm_put_interface(tp->intf);
6149 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6151 struct r8152 *tp = netdev_priv(net);
6154 ret = usb_autopm_get_interface(tp->intf);
6158 mutex_lock(&tp->control);
6160 ret = tp->rtl_ops.eee_set(tp, edata);
6162 ret = mii_nway_restart(&tp->mii);
6164 mutex_unlock(&tp->control);
6166 usb_autopm_put_interface(tp->intf);
6172 static int rtl8152_nway_reset(struct net_device *dev)
6174 struct r8152 *tp = netdev_priv(dev);
6177 ret = usb_autopm_get_interface(tp->intf);
6181 mutex_lock(&tp->control);
6183 ret = mii_nway_restart(&tp->mii);
6185 mutex_unlock(&tp->control);
6187 usb_autopm_put_interface(tp->intf);
6193 static int rtl8152_get_coalesce(struct net_device *netdev,
6194 struct ethtool_coalesce *coalesce)
6196 struct r8152 *tp = netdev_priv(netdev);
6198 switch (tp->version) {
6207 coalesce->rx_coalesce_usecs = tp->coalesce;
6212 static int rtl8152_set_coalesce(struct net_device *netdev,
6213 struct ethtool_coalesce *coalesce)
6215 struct r8152 *tp = netdev_priv(netdev);
6218 switch (tp->version) {
6227 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6230 ret = usb_autopm_get_interface(tp->intf);
6234 mutex_lock(&tp->control);
6236 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6237 tp->coalesce = coalesce->rx_coalesce_usecs;
6239 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6240 netif_stop_queue(netdev);
6241 napi_disable(&tp->napi);
6242 tp->rtl_ops.disable(tp);
6243 tp->rtl_ops.enable(tp);
6245 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6246 _rtl8152_set_rx_mode(netdev);
6247 napi_enable(&tp->napi);
6248 netif_wake_queue(netdev);
6252 mutex_unlock(&tp->control);
6254 usb_autopm_put_interface(tp->intf);
6259 static int rtl8152_get_tunable(struct net_device *netdev,
6260 const struct ethtool_tunable *tunable, void *d)
6262 struct r8152 *tp = netdev_priv(netdev);
6264 switch (tunable->id) {
6265 case ETHTOOL_RX_COPYBREAK:
6266 *(u32 *)d = tp->rx_copybreak;
6275 static int rtl8152_set_tunable(struct net_device *netdev,
6276 const struct ethtool_tunable *tunable,
6279 struct r8152 *tp = netdev_priv(netdev);
6282 switch (tunable->id) {
6283 case ETHTOOL_RX_COPYBREAK:
6285 if (val < ETH_ZLEN) {
6286 netif_err(tp, rx_err, netdev,
6287 "Invalid rx copy break value\n");
6291 if (tp->rx_copybreak != val) {
6292 if (netdev->flags & IFF_UP) {
6293 mutex_lock(&tp->control);
6294 napi_disable(&tp->napi);
6295 tp->rx_copybreak = val;
6296 napi_enable(&tp->napi);
6297 mutex_unlock(&tp->control);
6299 tp->rx_copybreak = val;
6310 static void rtl8152_get_ringparam(struct net_device *netdev,
6311 struct ethtool_ringparam *ring)
6313 struct r8152 *tp = netdev_priv(netdev);
6315 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6316 ring->rx_pending = tp->rx_pending;
6319 static int rtl8152_set_ringparam(struct net_device *netdev,
6320 struct ethtool_ringparam *ring)
6322 struct r8152 *tp = netdev_priv(netdev);
6324 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6327 if (tp->rx_pending != ring->rx_pending) {
6328 if (netdev->flags & IFF_UP) {
6329 mutex_lock(&tp->control);
6330 napi_disable(&tp->napi);
6331 tp->rx_pending = ring->rx_pending;
6332 napi_enable(&tp->napi);
6333 mutex_unlock(&tp->control);
6335 tp->rx_pending = ring->rx_pending;
6342 static const struct ethtool_ops ops = {
6343 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6344 .get_drvinfo = rtl8152_get_drvinfo,
6345 .get_link = ethtool_op_get_link,
6346 .nway_reset = rtl8152_nway_reset,
6347 .get_msglevel = rtl8152_get_msglevel,
6348 .set_msglevel = rtl8152_set_msglevel,
6349 .get_wol = rtl8152_get_wol,
6350 .set_wol = rtl8152_set_wol,
6351 .get_strings = rtl8152_get_strings,
6352 .get_sset_count = rtl8152_get_sset_count,
6353 .get_ethtool_stats = rtl8152_get_ethtool_stats,
6354 .get_coalesce = rtl8152_get_coalesce,
6355 .set_coalesce = rtl8152_set_coalesce,
6356 .get_eee = rtl_ethtool_get_eee,
6357 .set_eee = rtl_ethtool_set_eee,
6358 .get_link_ksettings = rtl8152_get_link_ksettings,
6359 .set_link_ksettings = rtl8152_set_link_ksettings,
6360 .get_tunable = rtl8152_get_tunable,
6361 .set_tunable = rtl8152_set_tunable,
6362 .get_ringparam = rtl8152_get_ringparam,
6363 .set_ringparam = rtl8152_set_ringparam,
6366 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6368 struct r8152 *tp = netdev_priv(netdev);
6369 struct mii_ioctl_data *data = if_mii(rq);
6372 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6375 res = usb_autopm_get_interface(tp->intf);
6381 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6385 mutex_lock(&tp->control);
6386 data->val_out = r8152_mdio_read(tp, data->reg_num);
6387 mutex_unlock(&tp->control);
6391 if (!capable(CAP_NET_ADMIN)) {
6395 mutex_lock(&tp->control);
6396 r8152_mdio_write(tp, data->reg_num, data->val_in);
6397 mutex_unlock(&tp->control);
6404 usb_autopm_put_interface(tp->intf);
6410 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6412 struct r8152 *tp = netdev_priv(dev);
6415 switch (tp->version) {
6425 ret = usb_autopm_get_interface(tp->intf);
6429 mutex_lock(&tp->control);
6433 if (netif_running(dev)) {
6434 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6438 if (netif_carrier_ok(dev))
6439 r8153_set_rx_early_size(tp);
6442 mutex_unlock(&tp->control);
6444 usb_autopm_put_interface(tp->intf);
6449 static const struct net_device_ops rtl8152_netdev_ops = {
6450 .ndo_open = rtl8152_open,
6451 .ndo_stop = rtl8152_close,
6452 .ndo_do_ioctl = rtl8152_ioctl,
6453 .ndo_start_xmit = rtl8152_start_xmit,
6454 .ndo_tx_timeout = rtl8152_tx_timeout,
6455 .ndo_set_features = rtl8152_set_features,
6456 .ndo_set_rx_mode = rtl8152_set_rx_mode,
6457 .ndo_set_mac_address = rtl8152_set_mac_address,
6458 .ndo_change_mtu = rtl8152_change_mtu,
6459 .ndo_validate_addr = eth_validate_addr,
6460 .ndo_features_check = rtl8152_features_check,
6463 static void rtl8152_unload(struct r8152 *tp)
6465 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6468 if (tp->version != RTL_VER_01)
6469 r8152_power_cut_en(tp, true);
6472 static void rtl8153_unload(struct r8152 *tp)
6474 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6477 r8153_power_cut_en(tp, false);
6480 static void rtl8153b_unload(struct r8152 *tp)
6482 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6485 r8153b_power_cut_en(tp, false);
6488 static int rtl_ops_init(struct r8152 *tp)
6490 struct rtl_ops *ops = &tp->rtl_ops;
6493 switch (tp->version) {
6497 ops->init = r8152b_init;
6498 ops->enable = rtl8152_enable;
6499 ops->disable = rtl8152_disable;
6500 ops->up = rtl8152_up;
6501 ops->down = rtl8152_down;
6502 ops->unload = rtl8152_unload;
6503 ops->eee_get = r8152_get_eee;
6504 ops->eee_set = r8152_set_eee;
6505 ops->in_nway = rtl8152_in_nway;
6506 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
6507 ops->autosuspend_en = rtl_runtime_suspend_enable;
6508 tp->rx_buf_sz = 16 * 1024;
6510 tp->eee_adv = MDIO_EEE_100TX;
6517 ops->init = r8153_init;
6518 ops->enable = rtl8153_enable;
6519 ops->disable = rtl8153_disable;
6520 ops->up = rtl8153_up;
6521 ops->down = rtl8153_down;
6522 ops->unload = rtl8153_unload;
6523 ops->eee_get = r8153_get_eee;
6524 ops->eee_set = r8152_set_eee;
6525 ops->in_nway = rtl8153_in_nway;
6526 ops->hw_phy_cfg = r8153_hw_phy_cfg;
6527 ops->autosuspend_en = rtl8153_runtime_enable;
6528 if (tp->udev->speed < USB_SPEED_SUPER)
6529 tp->rx_buf_sz = 16 * 1024;
6531 tp->rx_buf_sz = 32 * 1024;
6533 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6538 ops->init = r8153b_init;
6539 ops->enable = rtl8153_enable;
6540 ops->disable = rtl8153_disable;
6541 ops->up = rtl8153b_up;
6542 ops->down = rtl8153b_down;
6543 ops->unload = rtl8153b_unload;
6544 ops->eee_get = r8153_get_eee;
6545 ops->eee_set = r8152_set_eee;
6546 ops->in_nway = rtl8153_in_nway;
6547 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
6548 ops->autosuspend_en = rtl8153b_runtime_enable;
6549 tp->rx_buf_sz = 32 * 1024;
6551 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6556 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6563 #define FIRMWARE_8153A_2 "/*(DEBLOBBED)*/"
6564 #define FIRMWARE_8153A_3 "/*(DEBLOBBED)*/"
6565 #define FIRMWARE_8153A_4 "/*(DEBLOBBED)*/"
6566 #define FIRMWARE_8153B_2 "/*(DEBLOBBED)*/"
6570 static int rtl_fw_init(struct r8152 *tp)
6572 struct rtl_fw *rtl_fw = &tp->rtl_fw;
6574 switch (tp->version) {
6576 rtl_fw->fw_name = FIRMWARE_8153A_2;
6577 rtl_fw->pre_fw = r8153_pre_firmware_1;
6578 rtl_fw->post_fw = r8153_post_firmware_1;
6581 rtl_fw->fw_name = FIRMWARE_8153A_3;
6582 rtl_fw->pre_fw = r8153_pre_firmware_2;
6583 rtl_fw->post_fw = r8153_post_firmware_2;
6586 rtl_fw->fw_name = FIRMWARE_8153A_4;
6587 rtl_fw->post_fw = r8153_post_firmware_3;
6590 rtl_fw->fw_name = FIRMWARE_8153B_2;
6591 rtl_fw->pre_fw = r8153b_pre_firmware_1;
6592 rtl_fw->post_fw = r8153b_post_firmware_1;
6601 static u8 rtl_get_version(struct usb_interface *intf)
6603 struct usb_device *udev = interface_to_usbdev(intf);
6609 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6613 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6614 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6615 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),
6616 USB_CTRL_GET_TIMEOUT);
6618 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6624 version = RTL_VER_01;
6627 version = RTL_VER_02;
6630 version = RTL_VER_03;
6633 version = RTL_VER_04;
6636 version = RTL_VER_05;
6639 version = RTL_VER_06;
6642 version = RTL_VER_07;
6645 version = RTL_VER_08;
6648 version = RTL_VER_09;
6651 version = RTL_VER_UNKNOWN;
6652 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6656 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6661 static int rtl8152_probe(struct usb_interface *intf,
6662 const struct usb_device_id *id)
6664 struct usb_device *udev = interface_to_usbdev(intf);
6665 u8 version = rtl_get_version(intf);
6667 struct net_device *netdev;
6670 if (version == RTL_VER_UNKNOWN)
6673 if (udev->actconfig->desc.bConfigurationValue != 1) {
6674 usb_driver_set_configuration(udev, 1);
6678 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6681 usb_reset_device(udev);
6682 netdev = alloc_etherdev(sizeof(struct r8152));
6684 dev_err(&intf->dev, "Out of memory\n");
6688 SET_NETDEV_DEV(netdev, &intf->dev);
6689 tp = netdev_priv(netdev);
6690 tp->msg_enable = 0x7FFF;
6693 tp->netdev = netdev;
6695 tp->version = version;
6701 tp->mii.supports_gmii = 0;
6704 tp->mii.supports_gmii = 1;
6708 ret = rtl_ops_init(tp);
6714 mutex_init(&tp->control);
6715 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6716 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6717 tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6718 tasklet_disable(&tp->tx_tl);
6720 netdev->netdev_ops = &rtl8152_netdev_ops;
6721 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6723 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6724 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6725 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6726 NETIF_F_HW_VLAN_CTAG_TX;
6727 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6728 NETIF_F_TSO | NETIF_F_FRAGLIST |
6729 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6730 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6731 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6732 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6733 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6735 if (tp->version == RTL_VER_01) {
6736 netdev->features &= ~NETIF_F_RXCSUM;
6737 netdev->hw_features &= ~NETIF_F_RXCSUM;
6740 if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6741 switch (le16_to_cpu(udev->descriptor.idProduct)) {
6742 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6743 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6744 set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6748 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6749 (!strcmp(udev->serial, "000001000000") ||
6750 !strcmp(udev->serial, "000002000000"))) {
6751 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6752 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6755 netdev->ethtool_ops = &ops;
6756 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6758 /* MTU range: 68 - 1500 or 9194 */
6759 netdev->min_mtu = ETH_MIN_MTU;
6760 switch (tp->version) {
6763 netdev->max_mtu = ETH_DATA_LEN;
6766 netdev->max_mtu = RTL8153_MAX_MTU;
6770 tp->mii.dev = netdev;
6771 tp->mii.mdio_read = read_mii_word;
6772 tp->mii.mdio_write = write_mii_word;
6773 tp->mii.phy_id_mask = 0x3f;
6774 tp->mii.reg_num_mask = 0x1f;
6775 tp->mii.phy_id = R8152_PHY_ID;
6777 tp->autoneg = AUTONEG_ENABLE;
6778 tp->speed = SPEED_100;
6779 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6780 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6781 if (tp->mii.supports_gmii) {
6782 tp->speed = SPEED_1000;
6783 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6785 tp->duplex = DUPLEX_FULL;
6787 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6788 tp->rx_pending = 10 * RTL8152_MAX_RX;
6790 intf->needs_remote_wakeup = 1;
6792 if (!rtl_can_wakeup(tp))
6793 __rtl_set_wol(tp, 0);
6795 tp->saved_wolopts = __rtl_get_wol(tp);
6797 tp->rtl_ops.init(tp);
6798 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6799 /* Retry in case reject_firmware() is not ready yet. */
6800 tp->rtl_fw.retry = true;
6802 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6803 set_ethernet_addr(tp);
6805 usb_set_intfdata(intf, tp);
6806 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6808 ret = register_netdev(netdev);
6810 netif_err(tp, probe, netdev, "couldn't register the device\n");
6814 if (tp->saved_wolopts)
6815 device_set_wakeup_enable(&udev->dev, true);
6817 device_set_wakeup_enable(&udev->dev, false);
6819 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6824 tasklet_kill(&tp->tx_tl);
6825 cancel_delayed_work_sync(&tp->hw_phy_work);
6826 if (tp->rtl_ops.unload)
6827 tp->rtl_ops.unload(tp);
6828 rtl8152_release_firmware(tp);
6829 usb_set_intfdata(intf, NULL);
6831 free_netdev(netdev);
6835 static void rtl8152_disconnect(struct usb_interface *intf)
6837 struct r8152 *tp = usb_get_intfdata(intf);
6839 usb_set_intfdata(intf, NULL);
6843 unregister_netdev(tp->netdev);
6844 tasklet_kill(&tp->tx_tl);
6845 cancel_delayed_work_sync(&tp->hw_phy_work);
6846 tp->rtl_ops.unload(tp);
6847 rtl8152_release_firmware(tp);
6848 free_netdev(tp->netdev);
6852 #define REALTEK_USB_DEVICE(vend, prod) \
6853 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6854 USB_DEVICE_ID_MATCH_INT_CLASS, \
6855 .idVendor = (vend), \
6856 .idProduct = (prod), \
6857 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6860 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6861 USB_DEVICE_ID_MATCH_DEVICE, \
6862 .idVendor = (vend), \
6863 .idProduct = (prod), \
6864 .bInterfaceClass = USB_CLASS_COMM, \
6865 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6866 .bInterfaceProtocol = USB_CDC_PROTO_NONE
6868 /* table of devices that work with this driver */
6869 static const struct usb_device_id rtl8152_table[] = {
6870 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6871 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6872 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6873 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6874 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6875 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6876 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6877 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
6878 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3054)},
6879 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
6880 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
6881 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)},
6882 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
6883 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
6884 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
6885 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e)},
6886 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
6887 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6888 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
6889 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
6893 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6895 static struct usb_driver rtl8152_driver = {
6897 .id_table = rtl8152_table,
6898 .probe = rtl8152_probe,
6899 .disconnect = rtl8152_disconnect,
6900 .suspend = rtl8152_suspend,
6901 .resume = rtl8152_resume,
6902 .reset_resume = rtl8152_reset_resume,
6903 .pre_reset = rtl8152_pre_reset,
6904 .post_reset = rtl8152_post_reset,
6905 .supports_autosuspend = 1,
6906 .disable_hub_initiated_lpm = 1,
6909 module_usb_driver(rtl8152_driver);
6911 MODULE_AUTHOR(DRIVER_AUTHOR);
6912 MODULE_DESCRIPTION(DRIVER_DESC);
6913 MODULE_LICENSE("GPL");
6914 MODULE_VERSION(DRIVER_VERSION);