2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "09"
34 /* Information for net */
35 #define NET_VERSION "9"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_AFE_CTRL2 0xd824
133 #define USB_UPS_CFG 0xd842
134 #define USB_UPS_FLAGS 0xd848
135 #define USB_WDT11_CTRL 0xe43c
136 #define USB_BP_BA 0xfc26
137 #define USB_BP_0 0xfc28
138 #define USB_BP_1 0xfc2a
139 #define USB_BP_2 0xfc2c
140 #define USB_BP_3 0xfc2e
141 #define USB_BP_4 0xfc30
142 #define USB_BP_5 0xfc32
143 #define USB_BP_6 0xfc34
144 #define USB_BP_7 0xfc36
145 #define USB_BP_EN 0xfc38
146 #define USB_BP_8 0xfc38
147 #define USB_BP_9 0xfc3a
148 #define USB_BP_10 0xfc3c
149 #define USB_BP_11 0xfc3e
150 #define USB_BP_12 0xfc40
151 #define USB_BP_13 0xfc42
152 #define USB_BP_14 0xfc44
153 #define USB_BP_15 0xfc46
154 #define USB_BP2_EN 0xfc48
157 #define OCP_ALDPS_CONFIG 0x2010
158 #define OCP_EEE_CONFIG1 0x2080
159 #define OCP_EEE_CONFIG2 0x2092
160 #define OCP_EEE_CONFIG3 0x2094
161 #define OCP_BASE_MII 0xa400
162 #define OCP_EEE_AR 0xa41a
163 #define OCP_EEE_DATA 0xa41c
164 #define OCP_PHY_STATUS 0xa420
165 #define OCP_NCTL_CFG 0xa42c
166 #define OCP_POWER_CFG 0xa430
167 #define OCP_EEE_CFG 0xa432
168 #define OCP_SRAM_ADDR 0xa436
169 #define OCP_SRAM_DATA 0xa438
170 #define OCP_DOWN_SPEED 0xa442
171 #define OCP_EEE_ABLE 0xa5c4
172 #define OCP_EEE_ADV 0xa5d0
173 #define OCP_EEE_LPABLE 0xa5d2
174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT 0xb800
176 #define OCP_PHY_PATCH_CMD 0xb820
177 #define OCP_ADC_IOFFSET 0xbcfc
178 #define OCP_ADC_CFG 0xbc06
179 #define OCP_SYSCLK_CFG 0xc416
182 #define SRAM_GREEN_CFG 0x8011
183 #define SRAM_LPF_CFG 0x8012
184 #define SRAM_10M_AMP1 0x8080
185 #define SRAM_10M_AMP2 0x8082
186 #define SRAM_IMPEDANCE 0x8084
189 #define RCR_AAP 0x00000001
190 #define RCR_APM 0x00000002
191 #define RCR_AM 0x00000004
192 #define RCR_AB 0x00000008
193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL 0x00080002
197 #define RXFIFO_THR1_OOB 0x01800003
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL 0x00000060
201 #define RXFIFO_THR2_HIGH 0x00000038
202 #define RXFIFO_THR2_OOB 0x0000004a
203 #define RXFIFO_THR2_NORMAL 0x00a0
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL 0x00000078
207 #define RXFIFO_THR3_HIGH 0x00000048
208 #define RXFIFO_THR3_OOB 0x0000005a
209 #define RXFIFO_THR3_NORMAL 0x0110
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL 0x00400008
213 #define TXFIFO_THR_NORMAL2 0x01000008
216 #define ECM_ALDPS 0x0002
219 #define FMC_FCR_MCU_EN 0x0001
222 #define EEEP_CR_EEEP_TX 0x0002
225 #define WDT6_SET_MODE 0x0010
228 #define TCR0_TX_EMPTY 0x0800
229 #define TCR0_AUTO_FIFO 0x0080
232 #define VERSION_MASK 0x7cf0
235 #define MTPS_JUMBO (12 * 1024 / 64)
236 #define MTPS_DEFAULT (6 * 1024 / 64)
239 #define TALLY_RESET 0x0001
247 #define CRWECR_NORAML 0x00
248 #define CRWECR_CONFIG 0xc0
251 #define NOW_IS_OOB 0x80
252 #define TXFIFO_EMPTY 0x20
253 #define RXFIFO_EMPTY 0x10
254 #define LINK_LIST_READY 0x02
255 #define DIS_MCU_CLROOB 0x01
256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
259 #define RXDY_GATED_EN 0x0008
262 #define RE_INIT_LL 0x8000
263 #define MCU_BORW_EN 0x4000
266 #define CPCR_RX_VLAN 0x0040
269 #define MAGIC_EN 0x0001
272 #define TEREDO_SEL 0x8000
273 #define TEREDO_WAKE_MASK 0x7f00
274 #define TEREDO_RS_EVENT_MASK 0x00fe
275 #define OOB_TEREDO_EN 0x0001
278 #define ALDPS_PROXY_MODE 0x0001
281 #define EFUSE_READ_CMD BIT(15)
282 #define EFUSE_DATA_BIT16 BIT(7)
285 #define LINK_ON_WAKE_EN 0x0010
286 #define LINK_OFF_WAKE_EN 0x0008
289 #define BWF_EN 0x0040
290 #define MWF_EN 0x0020
291 #define UWF_EN 0x0010
292 #define LAN_WAKE_EN 0x0002
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK 0x0700
298 #define TX_10M_IDLE_EN 0x0080
299 #define PFM_PWM_SWITCH 0x0040
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN 0x00004000
303 #define MCU_CLK_RATIO 0x07010f07
304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO 0x0f87
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO 0x8007
309 #define MAC_CLK_SPDWN_EN BIT(15)
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN 0x0100
313 #define SUSPEND_SPDWN_EN 0x0004
314 #define U1U2_SPDWN_EN 0x0002
315 #define L1_SPDWN_EN 0x0001
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN 0x1000
319 #define RXDV_SPDWN_EN 0x0800
320 #define TX10MIDLE_EN 0x0100
321 #define TP100_SPDWN_EN 0x0020
322 #define TP500_SPDWN_EN 0x0010
323 #define TP1000_SPDWN_EN 0x0008
324 #define EEE_SPDWN_EN 0x0001
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK 0x0001
328 #define SPEED_DOWN_MSK 0x0002
329 #define SPDWN_RXDV_MSK 0x0004
330 #define SPDWN_LINKCHG_MSK 0x0008
333 #define PHYAR_FLAG 0x80000000
336 #define EEE_RX_EN 0x0001
337 #define EEE_TX_EN 0x0002
340 #define AUTOLOAD_DONE 0x0002
343 #define USB2PHY_SUSPEND 0x0001
344 #define USB2PHY_L1 0x0002
347 #define pwd_dn_scale_mask 0x3ffe
348 #define pwd_dn_scale(x) ((x) << 1)
351 #define DYNAMIC_BURST 0x0001
354 #define EP4_FULL_FC 0x0001
357 #define STAT_SPEED_MASK 0x0006
358 #define STAT_SPEED_HIGH 0x0000
359 #define STAT_SPEED_FULL 0x0002
362 #define LPM_U1U2_EN BIT(0)
365 #define TX_AGG_MAX_THRESHOLD 0x03
368 #define RX_THR_SUPPER 0x0c350180
369 #define RX_THR_HIGH 0x7a120180
370 #define RX_THR_SLOW 0xffff0180
371 #define RX_THR_B 0x00010001
374 #define TEST_MODE_DISABLE 0x00000001
375 #define TX_SIZE_ADJUST1 0x00000100
378 #define BMU_RESET_EP_IN 0x01
379 #define BMU_RESET_EP_OUT 0x02
381 /* USB_UPT_RXDMA_OWN */
382 #define OWN_UPDATE BIT(0)
383 #define OWN_CLEAR BIT(1)
386 #define POWER_CUT 0x0100
388 /* USB_PM_CTRL_STATUS */
389 #define RESUME_INDICATE 0x0001
392 #define RX_AGG_DISABLE 0x0010
393 #define RX_ZERO_EN 0x0080
396 #define U2P3_ENABLE 0x0001
399 #define PWR_EN 0x0001
400 #define PHASE2_EN 0x0008
401 #define UPS_EN BIT(4)
402 #define USP_PREWAKE BIT(5)
405 #define PCUT_STATUS 0x0001
407 /* USB_RX_EARLY_TIMEOUT */
408 #define COALESCE_SUPER 85000U
409 #define COALESCE_HIGH 250000U
410 #define COALESCE_SLOW 524280U
413 #define TIMER11_EN 0x0001
416 /* bit 4 ~ 5: fifo empty boundary */
417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
418 /* bit 2 ~ 3: LMP timer */
419 #define LPM_TIMER_MASK 0x0c
420 #define LPM_TIMER_500MS 0x04 /* 500 ms */
421 #define LPM_TIMER_500US 0x0c /* 500 us */
422 #define ROK_EXIT_LPM 0x02
425 #define SEN_VAL_MASK 0xf800
426 #define SEN_VAL_NORMAL 0xa000
427 #define SEL_RXIDLE 0x0100
430 #define SAW_CNT_1MS_MASK 0x0fff
433 #define UPS_FLAGS_R_TUNE BIT(0)
434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
435 #define UPS_FLAGS_250M_CKDIV BIT(2)
436 #define UPS_FLAGS_EN_ALDPS BIT(3)
437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
438 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
439 #define ups_flags_speed(x) ((x) << 16)
440 #define UPS_FLAGS_EN_EEE BIT(20)
441 #define UPS_FLAGS_EN_500M_EEE BIT(21)
442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
445 #define UPS_FLAGS_EN_GREEN BIT(26)
446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
460 /* OCP_ALDPS_CONFIG */
461 #define ENPWRSAVE 0x8000
462 #define ENPDNPS 0x0200
463 #define LINKENA 0x0100
464 #define DIS_SDSAVE 0x0010
467 #define PHY_STAT_MASK 0x0007
468 #define PHY_STAT_EXT_INIT 2
469 #define PHY_STAT_LAN_ON 3
470 #define PHY_STAT_PWRDN 5
473 #define PGA_RETURN_EN BIT(1)
476 #define EEE_CLKDIV_EN 0x8000
477 #define EN_ALDPS 0x0004
478 #define EN_10M_PLLOFF 0x0001
480 /* OCP_EEE_CONFIG1 */
481 #define RG_TXLPI_MSK_HFDUP 0x8000
482 #define RG_MATCLR_EN 0x4000
483 #define EEE_10_CAP 0x2000
484 #define EEE_NWAY_EN 0x1000
485 #define TX_QUIET_EN 0x0200
486 #define RX_QUIET_EN 0x0100
487 #define sd_rise_time_mask 0x0070
488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
489 #define RG_RXLPI_MSK_HFDUP 0x0008
490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
492 /* OCP_EEE_CONFIG2 */
493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN 0x0400
495 #define RG_LDVQUIET_EN 0x0200
496 #define RG_CKRSEL 0x0020
497 #define RG_EEEPRG_EN 0x0010
499 /* OCP_EEE_CONFIG3 */
500 #define fast_snr_mask 0xff80
501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
506 /* bit[15:14] function */
507 #define FUN_ADDR 0x0000
508 #define FUN_DATA 0x4000
509 /* bit[4:0] device addr */
512 #define CTAP_SHORT_EN 0x0040
513 #define EEE10_EN 0x0010
516 #define EN_EEE_CMODE BIT(14)
517 #define EN_EEE_1000 BIT(13)
518 #define EN_EEE_100 BIT(12)
519 #define EN_10M_CLKDIV BIT(11)
520 #define EN_10M_BGOFF 0x0080
523 #define TXDIS_STATE 0x01
524 #define ABD_STATE 0x02
526 /* OCP_PHY_PATCH_STAT */
527 #define PATCH_READY BIT(6)
529 /* OCP_PHY_PATCH_CMD */
530 #define PATCH_REQUEST BIT(4)
533 #define CKADSEL_L 0x0100
534 #define ADC_EN 0x0080
535 #define EN_EMI_L 0x0040
538 #define clk_div_expo(x) (min(x, 5) << 8)
541 #define GREEN_ETH_EN BIT(15)
542 #define R_TUNE_EN BIT(11)
545 #define LPF_AUTO_TUNE 0x8000
548 #define GDAC_IB_UPALL 0x0008
551 #define AMP_DN 0x0200
554 #define RX_DRIVING_MASK 0x6000
557 #define AD_MASK 0xfee0
559 #define PASS_THRU_MASK 0x1
561 enum rtl_register_content {
569 #define RTL8152_MAX_TX 4
570 #define RTL8152_MAX_RX 10
575 #define INTR_LINK 0x0004
577 #define RTL8152_REQT_READ 0xc0
578 #define RTL8152_REQT_WRITE 0x40
579 #define RTL8152_REQ_GET_REGS 0x05
580 #define RTL8152_REQ_SET_REGS 0x05
582 #define BYTE_EN_DWORD 0xff
583 #define BYTE_EN_WORD 0x33
584 #define BYTE_EN_BYTE 0x11
585 #define BYTE_EN_SIX_BYTES 0x3f
586 #define BYTE_EN_START_MASK 0x0f
587 #define BYTE_EN_END_MASK 0xf0
589 #define RTL8153_MAX_PACKET 9216 /* 9K */
590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
593 #define RTL8153_RMS RTL8153_MAX_PACKET
594 #define RTL8152_TX_TIMEOUT (5 * HZ)
595 #define RTL8152_NAPI_WEIGHT 64
596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
597 sizeof(struct rx_desc) + RX_ALIGN)
611 /* Define these values to match your device */
612 #define VENDOR_ID_REALTEK 0x0bda
613 #define VENDOR_ID_MICROSOFT 0x045e
614 #define VENDOR_ID_SAMSUNG 0x04e8
615 #define VENDOR_ID_LENOVO 0x17ef
616 #define VENDOR_ID_LINKSYS 0x13b1
617 #define VENDOR_ID_NVIDIA 0x0955
618 #define VENDOR_ID_TPLINK 0x2357
620 #define MCU_TYPE_PLA 0x0100
621 #define MCU_TYPE_USB 0x0000
623 struct tally_counter {
630 __le32 tx_one_collision;
631 __le32 tx_multi_collision;
641 #define RX_LEN_MASK 0x7fff
644 #define RD_UDP_CS BIT(23)
645 #define RD_TCP_CS BIT(22)
646 #define RD_IPV6_CS BIT(20)
647 #define RD_IPV4_CS BIT(19)
650 #define IPF BIT(23) /* IP checksum fail */
651 #define UDPF BIT(22) /* UDP checksum fail */
652 #define TCPF BIT(21) /* TCP checksum fail */
653 #define RX_VLAN_TAG BIT(16)
662 #define TX_FS BIT(31) /* First segment of a packet */
663 #define TX_LS BIT(30) /* Final segment of a packet */
664 #define GTSENDV4 BIT(28)
665 #define GTSENDV6 BIT(27)
666 #define GTTCPHO_SHIFT 18
667 #define GTTCPHO_MAX 0x7fU
668 #define TX_LEN_MAX 0x3ffffU
671 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
672 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
673 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
674 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
676 #define MSS_MAX 0x7ffU
677 #define TCPHO_SHIFT 17
678 #define TCPHO_MAX 0x7ffU
679 #define TX_VLAN_TAG BIT(16)
685 struct list_head list;
687 struct r8152 *context;
693 struct list_head list;
695 struct r8152 *context;
704 struct usb_device *udev;
705 struct napi_struct napi;
706 struct usb_interface *intf;
707 struct net_device *netdev;
708 struct urb *intr_urb;
709 struct tx_agg tx_info[RTL8152_MAX_TX];
710 struct rx_agg rx_info[RTL8152_MAX_RX];
711 struct list_head rx_done, tx_free;
712 struct sk_buff_head tx_queue, rx_queue;
713 spinlock_t rx_lock, tx_lock;
714 struct delayed_work schedule, hw_phy_work;
715 struct mii_if_info mii;
716 struct mutex control; /* use for hw setting */
717 #ifdef CONFIG_PM_SLEEP
718 struct notifier_block pm_notifier;
722 void (*init)(struct r8152 *);
723 int (*enable)(struct r8152 *);
724 void (*disable)(struct r8152 *);
725 void (*up)(struct r8152 *);
726 void (*down)(struct r8152 *);
727 void (*unload)(struct r8152 *);
728 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
729 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
730 bool (*in_nway)(struct r8152 *);
731 void (*hw_phy_cfg)(struct r8152 *);
732 void (*autosuspend_en)(struct r8152 *tp, bool enable);
768 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
769 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
771 static const int multicast_filter_limit = 32;
772 static unsigned int agg_buf_sz = 16384;
774 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
775 VLAN_ETH_HLEN - ETH_FCS_LEN)
778 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
783 tmp = kmalloc(size, GFP_KERNEL);
787 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
788 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
789 value, index, tmp, size, 500);
791 memset(data, 0xff, size);
793 memcpy(data, tmp, size);
801 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
806 tmp = kmemdup(data, size, GFP_KERNEL);
810 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
811 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
812 value, index, tmp, size, 500);
819 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
820 void *data, u16 type)
825 if (test_bit(RTL8152_UNPLUG, &tp->flags))
828 /* both size and indix must be 4 bytes align */
829 if ((size & 3) || !size || (index & 3) || !data)
832 if ((u32)index + (u32)size > 0xffff)
837 ret = get_registers(tp, index, type, limit, data);
845 ret = get_registers(tp, index, type, size, data);
857 set_bit(RTL8152_UNPLUG, &tp->flags);
862 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
863 u16 size, void *data, u16 type)
866 u16 byteen_start, byteen_end, byen;
869 if (test_bit(RTL8152_UNPLUG, &tp->flags))
872 /* both size and indix must be 4 bytes align */
873 if ((size & 3) || !size || (index & 3) || !data)
876 if ((u32)index + (u32)size > 0xffff)
879 byteen_start = byteen & BYTE_EN_START_MASK;
880 byteen_end = byteen & BYTE_EN_END_MASK;
882 byen = byteen_start | (byteen_start << 4);
883 ret = set_registers(tp, index, type | byen, 4, data);
896 ret = set_registers(tp, index,
897 type | BYTE_EN_DWORD,
906 ret = set_registers(tp, index,
907 type | BYTE_EN_DWORD,
919 byen = byteen_end | (byteen_end >> 4);
920 ret = set_registers(tp, index, type | byen, 4, data);
927 set_bit(RTL8152_UNPLUG, &tp->flags);
933 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
935 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
939 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
941 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
945 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
947 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
950 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
954 generic_ocp_read(tp, index, sizeof(data), &data, type);
956 return __le32_to_cpu(data);
959 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
961 __le32 tmp = __cpu_to_le32(data);
963 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
966 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
970 u16 byen = BYTE_EN_WORD;
971 u8 shift = index & 2;
976 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
978 data = __le32_to_cpu(tmp);
979 data >>= (shift * 8);
985 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
989 u16 byen = BYTE_EN_WORD;
990 u8 shift = index & 2;
996 mask <<= (shift * 8);
997 data <<= (shift * 8);
1001 tmp = __cpu_to_le32(data);
1003 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1006 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1010 u8 shift = index & 3;
1014 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1016 data = __le32_to_cpu(tmp);
1017 data >>= (shift * 8);
1023 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1027 u16 byen = BYTE_EN_BYTE;
1028 u8 shift = index & 3;
1034 mask <<= (shift * 8);
1035 data <<= (shift * 8);
1039 tmp = __cpu_to_le32(data);
1041 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1044 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1046 u16 ocp_base, ocp_index;
1048 ocp_base = addr & 0xf000;
1049 if (ocp_base != tp->ocp_base) {
1050 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1051 tp->ocp_base = ocp_base;
1054 ocp_index = (addr & 0x0fff) | 0xb000;
1055 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1058 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1060 u16 ocp_base, ocp_index;
1062 ocp_base = addr & 0xf000;
1063 if (ocp_base != tp->ocp_base) {
1064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1065 tp->ocp_base = ocp_base;
1068 ocp_index = (addr & 0x0fff) | 0xb000;
1069 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1072 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1074 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1077 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1079 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1082 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1084 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1085 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1088 static u16 sram_read(struct r8152 *tp, u16 addr)
1090 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1091 return ocp_reg_read(tp, OCP_SRAM_DATA);
1094 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1096 struct r8152 *tp = netdev_priv(netdev);
1099 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1102 if (phy_id != R8152_PHY_ID)
1105 ret = r8152_mdio_read(tp, reg);
1111 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1113 struct r8152 *tp = netdev_priv(netdev);
1115 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1118 if (phy_id != R8152_PHY_ID)
1121 r8152_mdio_write(tp, reg, val);
1125 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1127 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1129 struct r8152 *tp = netdev_priv(netdev);
1130 struct sockaddr *addr = p;
1131 int ret = -EADDRNOTAVAIL;
1133 if (!is_valid_ether_addr(addr->sa_data))
1136 ret = usb_autopm_get_interface(tp->intf);
1140 mutex_lock(&tp->control);
1142 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1144 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1145 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1146 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1148 mutex_unlock(&tp->control);
1150 usb_autopm_put_interface(tp->intf);
1155 /* Devices containing RTL8153-AD can support a persistent
1156 * host system provided MAC address.
1157 * Examples of this are Dell TB15 and Dell WD15 docks
1159 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1162 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1163 union acpi_object *obj;
1166 unsigned char buf[6];
1168 /* test for -AD variant of RTL8153 */
1169 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1170 if ((ocp_data & AD_MASK) != 0x1000)
1173 /* test for MAC address pass-through bit */
1174 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1175 if ((ocp_data & PASS_THRU_MASK) != 1)
1178 /* returns _AUXMAC_#AABBCCDDEEFF# */
1179 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1180 obj = (union acpi_object *)buffer.pointer;
1181 if (!ACPI_SUCCESS(status))
1183 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1184 netif_warn(tp, probe, tp->netdev,
1185 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1186 obj->type, obj->string.length);
1189 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1190 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1191 netif_warn(tp, probe, tp->netdev,
1192 "Invalid header when reading pass-thru MAC addr\n");
1195 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1196 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1197 netif_warn(tp, probe, tp->netdev,
1198 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1203 memcpy(sa->sa_data, buf, 6);
1204 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1205 netif_info(tp, probe, tp->netdev,
1206 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1213 static int set_ethernet_addr(struct r8152 *tp)
1215 struct net_device *dev = tp->netdev;
1219 if (tp->version == RTL_VER_01) {
1220 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1222 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1223 * or system doesn't provide valid _SB.AMAC this will be
1224 * be expected to non-zero
1226 ret = vendor_mac_passthru_addr_read(tp, &sa);
1228 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1232 netif_err(tp, probe, dev, "Get ether addr fail\n");
1233 } else if (!is_valid_ether_addr(sa.sa_data)) {
1234 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1236 eth_hw_addr_random(dev);
1237 ether_addr_copy(sa.sa_data, dev->dev_addr);
1238 ret = rtl8152_set_mac_address(dev, &sa);
1239 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1242 if (tp->version == RTL_VER_01)
1243 ether_addr_copy(dev->dev_addr, sa.sa_data);
1245 ret = rtl8152_set_mac_address(dev, &sa);
1251 static void read_bulk_callback(struct urb *urb)
1253 struct net_device *netdev;
1254 int status = urb->status;
1266 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1269 if (!test_bit(WORK_ENABLE, &tp->flags))
1272 netdev = tp->netdev;
1274 /* When link down, the driver would cancel all bulks. */
1275 /* This avoid the re-submitting bulk */
1276 if (!netif_carrier_ok(netdev))
1279 usb_mark_last_busy(tp->udev);
1283 if (urb->actual_length < ETH_ZLEN)
1286 spin_lock(&tp->rx_lock);
1287 list_add_tail(&agg->list, &tp->rx_done);
1288 spin_unlock(&tp->rx_lock);
1289 napi_schedule(&tp->napi);
1292 set_bit(RTL8152_UNPLUG, &tp->flags);
1293 netif_device_detach(tp->netdev);
1296 return; /* the urb is in unlink state */
1298 if (net_ratelimit())
1299 netdev_warn(netdev, "maybe reset is needed?\n");
1302 if (net_ratelimit())
1303 netdev_warn(netdev, "Rx status %d\n", status);
1307 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1310 static void write_bulk_callback(struct urb *urb)
1312 struct net_device_stats *stats;
1313 struct net_device *netdev;
1316 int status = urb->status;
1326 netdev = tp->netdev;
1327 stats = &netdev->stats;
1329 if (net_ratelimit())
1330 netdev_warn(netdev, "Tx status %d\n", status);
1331 stats->tx_errors += agg->skb_num;
1333 stats->tx_packets += agg->skb_num;
1334 stats->tx_bytes += agg->skb_len;
1337 spin_lock(&tp->tx_lock);
1338 list_add_tail(&agg->list, &tp->tx_free);
1339 spin_unlock(&tp->tx_lock);
1341 usb_autopm_put_interface_async(tp->intf);
1343 if (!netif_carrier_ok(netdev))
1346 if (!test_bit(WORK_ENABLE, &tp->flags))
1349 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1352 if (!skb_queue_empty(&tp->tx_queue))
1353 napi_schedule(&tp->napi);
1356 static void intr_callback(struct urb *urb)
1360 int status = urb->status;
1367 if (!test_bit(WORK_ENABLE, &tp->flags))
1370 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1374 case 0: /* success */
1376 case -ECONNRESET: /* unlink */
1378 netif_device_detach(tp->netdev);
1381 netif_info(tp, intr, tp->netdev,
1382 "Stop submitting intr, status %d\n", status);
1385 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1387 /* -EPIPE: should clear the halt */
1389 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1393 d = urb->transfer_buffer;
1394 if (INTR_LINK & __le16_to_cpu(d[0])) {
1395 if (!netif_carrier_ok(tp->netdev)) {
1396 set_bit(RTL8152_LINK_CHG, &tp->flags);
1397 schedule_delayed_work(&tp->schedule, 0);
1400 if (netif_carrier_ok(tp->netdev)) {
1401 netif_stop_queue(tp->netdev);
1402 set_bit(RTL8152_LINK_CHG, &tp->flags);
1403 schedule_delayed_work(&tp->schedule, 0);
1408 res = usb_submit_urb(urb, GFP_ATOMIC);
1409 if (res == -ENODEV) {
1410 set_bit(RTL8152_UNPLUG, &tp->flags);
1411 netif_device_detach(tp->netdev);
1413 netif_err(tp, intr, tp->netdev,
1414 "can't resubmit intr, status %d\n", res);
1418 static inline void *rx_agg_align(void *data)
1420 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1423 static inline void *tx_agg_align(void *data)
1425 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1428 static void free_all_mem(struct r8152 *tp)
1432 for (i = 0; i < RTL8152_MAX_RX; i++) {
1433 usb_free_urb(tp->rx_info[i].urb);
1434 tp->rx_info[i].urb = NULL;
1436 kfree(tp->rx_info[i].buffer);
1437 tp->rx_info[i].buffer = NULL;
1438 tp->rx_info[i].head = NULL;
1441 for (i = 0; i < RTL8152_MAX_TX; i++) {
1442 usb_free_urb(tp->tx_info[i].urb);
1443 tp->tx_info[i].urb = NULL;
1445 kfree(tp->tx_info[i].buffer);
1446 tp->tx_info[i].buffer = NULL;
1447 tp->tx_info[i].head = NULL;
1450 usb_free_urb(tp->intr_urb);
1451 tp->intr_urb = NULL;
1453 kfree(tp->intr_buff);
1454 tp->intr_buff = NULL;
1457 static int alloc_all_mem(struct r8152 *tp)
1459 struct net_device *netdev = tp->netdev;
1460 struct usb_interface *intf = tp->intf;
1461 struct usb_host_interface *alt = intf->cur_altsetting;
1462 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1467 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1469 spin_lock_init(&tp->rx_lock);
1470 spin_lock_init(&tp->tx_lock);
1471 INIT_LIST_HEAD(&tp->tx_free);
1472 INIT_LIST_HEAD(&tp->rx_done);
1473 skb_queue_head_init(&tp->tx_queue);
1474 skb_queue_head_init(&tp->rx_queue);
1476 for (i = 0; i < RTL8152_MAX_RX; i++) {
1477 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1481 if (buf != rx_agg_align(buf)) {
1483 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1489 urb = usb_alloc_urb(0, GFP_KERNEL);
1495 INIT_LIST_HEAD(&tp->rx_info[i].list);
1496 tp->rx_info[i].context = tp;
1497 tp->rx_info[i].urb = urb;
1498 tp->rx_info[i].buffer = buf;
1499 tp->rx_info[i].head = rx_agg_align(buf);
1502 for (i = 0; i < RTL8152_MAX_TX; i++) {
1503 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1507 if (buf != tx_agg_align(buf)) {
1509 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1515 urb = usb_alloc_urb(0, GFP_KERNEL);
1521 INIT_LIST_HEAD(&tp->tx_info[i].list);
1522 tp->tx_info[i].context = tp;
1523 tp->tx_info[i].urb = urb;
1524 tp->tx_info[i].buffer = buf;
1525 tp->tx_info[i].head = tx_agg_align(buf);
1527 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1530 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1534 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1538 tp->intr_interval = (int)ep_intr->desc.bInterval;
1539 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1540 tp->intr_buff, INTBUFSIZE, intr_callback,
1541 tp, tp->intr_interval);
1550 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1552 struct tx_agg *agg = NULL;
1553 unsigned long flags;
1555 if (list_empty(&tp->tx_free))
1558 spin_lock_irqsave(&tp->tx_lock, flags);
1559 if (!list_empty(&tp->tx_free)) {
1560 struct list_head *cursor;
1562 cursor = tp->tx_free.next;
1563 list_del_init(cursor);
1564 agg = list_entry(cursor, struct tx_agg, list);
1566 spin_unlock_irqrestore(&tp->tx_lock, flags);
1571 /* r8152_csum_workaround()
1572 * The hw limites the value the transport offset. When the offset is out of the
1573 * range, calculate the checksum by sw.
1575 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1576 struct sk_buff_head *list)
1578 if (skb_shinfo(skb)->gso_size) {
1579 netdev_features_t features = tp->netdev->features;
1580 struct sk_buff_head seg_list;
1581 struct sk_buff *segs, *nskb;
1583 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1584 segs = skb_gso_segment(skb, features);
1585 if (IS_ERR(segs) || !segs)
1588 __skb_queue_head_init(&seg_list);
1594 __skb_queue_tail(&seg_list, nskb);
1597 skb_queue_splice(&seg_list, list);
1599 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1600 if (skb_checksum_help(skb) < 0)
1603 __skb_queue_head(list, skb);
1605 struct net_device_stats *stats;
1608 stats = &tp->netdev->stats;
1609 stats->tx_dropped++;
1614 /* msdn_giant_send_check()
1615 * According to the document of microsoft, the TCP Pseudo Header excludes the
1616 * packet length for IPv6 TCP large packets.
1618 static int msdn_giant_send_check(struct sk_buff *skb)
1620 const struct ipv6hdr *ipv6h;
1624 ret = skb_cow_head(skb, 0);
1628 ipv6h = ipv6_hdr(skb);
1632 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1637 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1639 if (skb_vlan_tag_present(skb)) {
1642 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1643 desc->opts2 |= cpu_to_le32(opts2);
1647 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1649 u32 opts2 = le32_to_cpu(desc->opts2);
1651 if (opts2 & RX_VLAN_TAG)
1652 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1653 swab16(opts2 & 0xffff));
1656 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1657 struct sk_buff *skb, u32 len, u32 transport_offset)
1659 u32 mss = skb_shinfo(skb)->gso_size;
1660 u32 opts1, opts2 = 0;
1661 int ret = TX_CSUM_SUCCESS;
1663 WARN_ON_ONCE(len > TX_LEN_MAX);
1665 opts1 = len | TX_FS | TX_LS;
1668 if (transport_offset > GTTCPHO_MAX) {
1669 netif_warn(tp, tx_err, tp->netdev,
1670 "Invalid transport offset 0x%x for TSO\n",
1676 switch (vlan_get_protocol(skb)) {
1677 case htons(ETH_P_IP):
1681 case htons(ETH_P_IPV6):
1682 if (msdn_giant_send_check(skb)) {
1694 opts1 |= transport_offset << GTTCPHO_SHIFT;
1695 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1696 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1699 if (transport_offset > TCPHO_MAX) {
1700 netif_warn(tp, tx_err, tp->netdev,
1701 "Invalid transport offset 0x%x\n",
1707 switch (vlan_get_protocol(skb)) {
1708 case htons(ETH_P_IP):
1710 ip_protocol = ip_hdr(skb)->protocol;
1713 case htons(ETH_P_IPV6):
1715 ip_protocol = ipv6_hdr(skb)->nexthdr;
1719 ip_protocol = IPPROTO_RAW;
1723 if (ip_protocol == IPPROTO_TCP)
1725 else if (ip_protocol == IPPROTO_UDP)
1730 opts2 |= transport_offset << TCPHO_SHIFT;
1733 desc->opts2 = cpu_to_le32(opts2);
1734 desc->opts1 = cpu_to_le32(opts1);
1740 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1742 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1746 __skb_queue_head_init(&skb_head);
1747 spin_lock(&tx_queue->lock);
1748 skb_queue_splice_init(tx_queue, &skb_head);
1749 spin_unlock(&tx_queue->lock);
1751 tx_data = agg->head;
1754 remain = agg_buf_sz;
1756 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1757 struct tx_desc *tx_desc;
1758 struct sk_buff *skb;
1762 skb = __skb_dequeue(&skb_head);
1766 len = skb->len + sizeof(*tx_desc);
1769 __skb_queue_head(&skb_head, skb);
1773 tx_data = tx_agg_align(tx_data);
1774 tx_desc = (struct tx_desc *)tx_data;
1776 offset = (u32)skb_transport_offset(skb);
1778 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1779 r8152_csum_workaround(tp, skb, &skb_head);
1783 rtl_tx_vlan_tag(tx_desc, skb);
1785 tx_data += sizeof(*tx_desc);
1788 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1789 struct net_device_stats *stats = &tp->netdev->stats;
1791 stats->tx_dropped++;
1792 dev_kfree_skb_any(skb);
1793 tx_data -= sizeof(*tx_desc);
1798 agg->skb_len += len;
1799 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1801 dev_kfree_skb_any(skb);
1803 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1806 if (!skb_queue_empty(&skb_head)) {
1807 spin_lock(&tx_queue->lock);
1808 skb_queue_splice(&skb_head, tx_queue);
1809 spin_unlock(&tx_queue->lock);
1812 netif_tx_lock(tp->netdev);
1814 if (netif_queue_stopped(tp->netdev) &&
1815 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1816 netif_wake_queue(tp->netdev);
1818 netif_tx_unlock(tp->netdev);
1820 ret = usb_autopm_get_interface_async(tp->intf);
1824 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1825 agg->head, (int)(tx_data - (u8 *)agg->head),
1826 (usb_complete_t)write_bulk_callback, agg);
1828 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1830 usb_autopm_put_interface_async(tp->intf);
1836 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1838 u8 checksum = CHECKSUM_NONE;
1841 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1844 opts2 = le32_to_cpu(rx_desc->opts2);
1845 opts3 = le32_to_cpu(rx_desc->opts3);
1847 if (opts2 & RD_IPV4_CS) {
1849 checksum = CHECKSUM_NONE;
1850 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1851 checksum = CHECKSUM_NONE;
1852 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1853 checksum = CHECKSUM_NONE;
1855 checksum = CHECKSUM_UNNECESSARY;
1856 } else if (opts2 & RD_IPV6_CS) {
1857 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1858 checksum = CHECKSUM_UNNECESSARY;
1859 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1860 checksum = CHECKSUM_UNNECESSARY;
1867 static int rx_bottom(struct r8152 *tp, int budget)
1869 unsigned long flags;
1870 struct list_head *cursor, *next, rx_queue;
1871 int ret = 0, work_done = 0;
1872 struct napi_struct *napi = &tp->napi;
1874 if (!skb_queue_empty(&tp->rx_queue)) {
1875 while (work_done < budget) {
1876 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1877 struct net_device *netdev = tp->netdev;
1878 struct net_device_stats *stats = &netdev->stats;
1879 unsigned int pkt_len;
1885 napi_gro_receive(napi, skb);
1887 stats->rx_packets++;
1888 stats->rx_bytes += pkt_len;
1892 if (list_empty(&tp->rx_done))
1895 INIT_LIST_HEAD(&rx_queue);
1896 spin_lock_irqsave(&tp->rx_lock, flags);
1897 list_splice_init(&tp->rx_done, &rx_queue);
1898 spin_unlock_irqrestore(&tp->rx_lock, flags);
1900 list_for_each_safe(cursor, next, &rx_queue) {
1901 struct rx_desc *rx_desc;
1907 list_del_init(cursor);
1909 agg = list_entry(cursor, struct rx_agg, list);
1911 if (urb->actual_length < ETH_ZLEN)
1914 rx_desc = agg->head;
1915 rx_data = agg->head;
1916 len_used += sizeof(struct rx_desc);
1918 while (urb->actual_length > len_used) {
1919 struct net_device *netdev = tp->netdev;
1920 struct net_device_stats *stats = &netdev->stats;
1921 unsigned int pkt_len;
1922 struct sk_buff *skb;
1924 /* limite the skb numbers for rx_queue */
1925 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1928 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1929 if (pkt_len < ETH_ZLEN)
1932 len_used += pkt_len;
1933 if (urb->actual_length < len_used)
1936 pkt_len -= ETH_FCS_LEN;
1937 rx_data += sizeof(struct rx_desc);
1939 skb = napi_alloc_skb(napi, pkt_len);
1941 stats->rx_dropped++;
1945 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1946 memcpy(skb->data, rx_data, pkt_len);
1947 skb_put(skb, pkt_len);
1948 skb->protocol = eth_type_trans(skb, netdev);
1949 rtl_rx_vlan_tag(rx_desc, skb);
1950 if (work_done < budget) {
1951 napi_gro_receive(napi, skb);
1953 stats->rx_packets++;
1954 stats->rx_bytes += pkt_len;
1956 __skb_queue_tail(&tp->rx_queue, skb);
1960 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1961 rx_desc = (struct rx_desc *)rx_data;
1962 len_used = (int)(rx_data - (u8 *)agg->head);
1963 len_used += sizeof(struct rx_desc);
1968 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1970 urb->actual_length = 0;
1971 list_add_tail(&agg->list, next);
1975 if (!list_empty(&rx_queue)) {
1976 spin_lock_irqsave(&tp->rx_lock, flags);
1977 list_splice_tail(&rx_queue, &tp->rx_done);
1978 spin_unlock_irqrestore(&tp->rx_lock, flags);
1985 static void tx_bottom(struct r8152 *tp)
1992 if (skb_queue_empty(&tp->tx_queue))
1995 agg = r8152_get_tx_agg(tp);
1999 res = r8152_tx_agg_fill(tp, agg);
2001 struct net_device *netdev = tp->netdev;
2003 if (res == -ENODEV) {
2004 set_bit(RTL8152_UNPLUG, &tp->flags);
2005 netif_device_detach(netdev);
2007 struct net_device_stats *stats = &netdev->stats;
2008 unsigned long flags;
2010 netif_warn(tp, tx_err, netdev,
2011 "failed tx_urb %d\n", res);
2012 stats->tx_dropped += agg->skb_num;
2014 spin_lock_irqsave(&tp->tx_lock, flags);
2015 list_add_tail(&agg->list, &tp->tx_free);
2016 spin_unlock_irqrestore(&tp->tx_lock, flags);
2022 static void bottom_half(struct r8152 *tp)
2024 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2027 if (!test_bit(WORK_ENABLE, &tp->flags))
2030 /* When link down, the driver would cancel all bulks. */
2031 /* This avoid the re-submitting bulk */
2032 if (!netif_carrier_ok(tp->netdev))
2035 clear_bit(SCHEDULE_NAPI, &tp->flags);
2040 static int r8152_poll(struct napi_struct *napi, int budget)
2042 struct r8152 *tp = container_of(napi, struct r8152, napi);
2045 work_done = rx_bottom(tp, budget);
2048 if (work_done < budget) {
2049 if (!napi_complete_done(napi, work_done))
2051 if (!list_empty(&tp->rx_done))
2052 napi_schedule(napi);
2053 else if (!skb_queue_empty(&tp->tx_queue) &&
2054 !list_empty(&tp->tx_free))
2055 napi_schedule(napi);
2063 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2067 /* The rx would be stopped, so skip submitting */
2068 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2069 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2072 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2073 agg->head, agg_buf_sz,
2074 (usb_complete_t)read_bulk_callback, agg);
2076 ret = usb_submit_urb(agg->urb, mem_flags);
2077 if (ret == -ENODEV) {
2078 set_bit(RTL8152_UNPLUG, &tp->flags);
2079 netif_device_detach(tp->netdev);
2081 struct urb *urb = agg->urb;
2082 unsigned long flags;
2084 urb->actual_length = 0;
2085 spin_lock_irqsave(&tp->rx_lock, flags);
2086 list_add_tail(&agg->list, &tp->rx_done);
2087 spin_unlock_irqrestore(&tp->rx_lock, flags);
2089 netif_err(tp, rx_err, tp->netdev,
2090 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2092 napi_schedule(&tp->napi);
2098 static void rtl_drop_queued_tx(struct r8152 *tp)
2100 struct net_device_stats *stats = &tp->netdev->stats;
2101 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2102 struct sk_buff *skb;
2104 if (skb_queue_empty(tx_queue))
2107 __skb_queue_head_init(&skb_head);
2108 spin_lock_bh(&tx_queue->lock);
2109 skb_queue_splice_init(tx_queue, &skb_head);
2110 spin_unlock_bh(&tx_queue->lock);
2112 while ((skb = __skb_dequeue(&skb_head))) {
2114 stats->tx_dropped++;
2118 static void rtl8152_tx_timeout(struct net_device *netdev)
2120 struct r8152 *tp = netdev_priv(netdev);
2122 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2124 usb_queue_reset_device(tp->intf);
2127 static void rtl8152_set_rx_mode(struct net_device *netdev)
2129 struct r8152 *tp = netdev_priv(netdev);
2131 if (netif_carrier_ok(netdev)) {
2132 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2133 schedule_delayed_work(&tp->schedule, 0);
2137 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2139 struct r8152 *tp = netdev_priv(netdev);
2140 u32 mc_filter[2]; /* Multicast hash filter */
2144 netif_stop_queue(netdev);
2145 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2146 ocp_data &= ~RCR_ACPT_ALL;
2147 ocp_data |= RCR_AB | RCR_APM;
2149 if (netdev->flags & IFF_PROMISC) {
2150 /* Unconditionally log net taps. */
2151 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2152 ocp_data |= RCR_AM | RCR_AAP;
2153 mc_filter[1] = 0xffffffff;
2154 mc_filter[0] = 0xffffffff;
2155 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2156 (netdev->flags & IFF_ALLMULTI)) {
2157 /* Too many to filter perfectly -- accept all multicasts. */
2159 mc_filter[1] = 0xffffffff;
2160 mc_filter[0] = 0xffffffff;
2162 struct netdev_hw_addr *ha;
2166 netdev_for_each_mc_addr(ha, netdev) {
2167 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2169 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2174 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2175 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2177 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2178 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2179 netif_wake_queue(netdev);
2182 static netdev_features_t
2183 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2184 netdev_features_t features)
2186 u32 mss = skb_shinfo(skb)->gso_size;
2187 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2188 int offset = skb_transport_offset(skb);
2190 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2191 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2192 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2193 features &= ~NETIF_F_GSO_MASK;
2198 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2199 struct net_device *netdev)
2201 struct r8152 *tp = netdev_priv(netdev);
2203 skb_tx_timestamp(skb);
2205 skb_queue_tail(&tp->tx_queue, skb);
2207 if (!list_empty(&tp->tx_free)) {
2208 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2209 set_bit(SCHEDULE_NAPI, &tp->flags);
2210 schedule_delayed_work(&tp->schedule, 0);
2212 usb_mark_last_busy(tp->udev);
2213 napi_schedule(&tp->napi);
2215 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2216 netif_stop_queue(netdev);
2219 return NETDEV_TX_OK;
2222 static void r8152b_reset_packet_filter(struct r8152 *tp)
2226 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2227 ocp_data &= ~FMC_FCR_MCU_EN;
2228 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2229 ocp_data |= FMC_FCR_MCU_EN;
2230 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2233 static void rtl8152_nic_reset(struct r8152 *tp)
2237 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2239 for (i = 0; i < 1000; i++) {
2240 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2242 usleep_range(100, 400);
2246 static void set_tx_qlen(struct r8152 *tp)
2248 struct net_device *netdev = tp->netdev;
2250 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2251 sizeof(struct tx_desc));
2254 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2256 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2259 static void rtl_set_eee_plus(struct r8152 *tp)
2264 speed = rtl8152_get_speed(tp);
2265 if (speed & _10bps) {
2266 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2267 ocp_data |= EEEP_CR_EEEP_TX;
2268 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2270 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2271 ocp_data &= ~EEEP_CR_EEEP_TX;
2272 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2276 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2280 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2282 ocp_data |= RXDY_GATED_EN;
2284 ocp_data &= ~RXDY_GATED_EN;
2285 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2288 static int rtl_start_rx(struct r8152 *tp)
2292 INIT_LIST_HEAD(&tp->rx_done);
2293 for (i = 0; i < RTL8152_MAX_RX; i++) {
2294 INIT_LIST_HEAD(&tp->rx_info[i].list);
2295 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2300 if (ret && ++i < RTL8152_MAX_RX) {
2301 struct list_head rx_queue;
2302 unsigned long flags;
2304 INIT_LIST_HEAD(&rx_queue);
2307 struct rx_agg *agg = &tp->rx_info[i++];
2308 struct urb *urb = agg->urb;
2310 urb->actual_length = 0;
2311 list_add_tail(&agg->list, &rx_queue);
2312 } while (i < RTL8152_MAX_RX);
2314 spin_lock_irqsave(&tp->rx_lock, flags);
2315 list_splice_tail(&rx_queue, &tp->rx_done);
2316 spin_unlock_irqrestore(&tp->rx_lock, flags);
2322 static int rtl_stop_rx(struct r8152 *tp)
2326 for (i = 0; i < RTL8152_MAX_RX; i++)
2327 usb_kill_urb(tp->rx_info[i].urb);
2329 while (!skb_queue_empty(&tp->rx_queue))
2330 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2335 static int rtl_enable(struct r8152 *tp)
2339 r8152b_reset_packet_filter(tp);
2341 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2342 ocp_data |= CR_RE | CR_TE;
2343 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2345 rxdy_gated_en(tp, false);
2350 static int rtl8152_enable(struct r8152 *tp)
2352 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2356 rtl_set_eee_plus(tp);
2358 return rtl_enable(tp);
2361 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2363 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2364 OWN_UPDATE | OWN_CLEAR);
2367 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2369 u32 ocp_data = tp->coalesce / 8;
2371 switch (tp->version) {
2376 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2382 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2383 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2385 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2387 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2389 r8153b_rx_agg_chg_indicate(tp);
2397 static void r8153_set_rx_early_size(struct r8152 *tp)
2399 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2401 switch (tp->version) {
2406 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2411 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2413 r8153b_rx_agg_chg_indicate(tp);
2421 static int rtl8153_enable(struct r8152 *tp)
2423 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2427 rtl_set_eee_plus(tp);
2428 r8153_set_rx_early_timeout(tp);
2429 r8153_set_rx_early_size(tp);
2431 return rtl_enable(tp);
2434 static void rtl_disable(struct r8152 *tp)
2439 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2440 rtl_drop_queued_tx(tp);
2444 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2445 ocp_data &= ~RCR_ACPT_ALL;
2446 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2448 rtl_drop_queued_tx(tp);
2450 for (i = 0; i < RTL8152_MAX_TX; i++)
2451 usb_kill_urb(tp->tx_info[i].urb);
2453 rxdy_gated_en(tp, true);
2455 for (i = 0; i < 1000; i++) {
2456 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2457 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2459 usleep_range(1000, 2000);
2462 for (i = 0; i < 1000; i++) {
2463 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2465 usleep_range(1000, 2000);
2470 rtl8152_nic_reset(tp);
2473 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2477 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2479 ocp_data |= POWER_CUT;
2481 ocp_data &= ~POWER_CUT;
2482 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2484 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2485 ocp_data &= ~RESUME_INDICATE;
2486 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2489 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2493 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2495 ocp_data |= CPCR_RX_VLAN;
2497 ocp_data &= ~CPCR_RX_VLAN;
2498 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2501 static int rtl8152_set_features(struct net_device *dev,
2502 netdev_features_t features)
2504 netdev_features_t changed = features ^ dev->features;
2505 struct r8152 *tp = netdev_priv(dev);
2508 ret = usb_autopm_get_interface(tp->intf);
2512 mutex_lock(&tp->control);
2514 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2515 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2516 rtl_rx_vlan_en(tp, true);
2518 rtl_rx_vlan_en(tp, false);
2521 mutex_unlock(&tp->control);
2523 usb_autopm_put_interface(tp->intf);
2529 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2531 static u32 __rtl_get_wol(struct r8152 *tp)
2536 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2537 if (ocp_data & LINK_ON_WAKE_EN)
2538 wolopts |= WAKE_PHY;
2540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2541 if (ocp_data & UWF_EN)
2542 wolopts |= WAKE_UCAST;
2543 if (ocp_data & BWF_EN)
2544 wolopts |= WAKE_BCAST;
2545 if (ocp_data & MWF_EN)
2546 wolopts |= WAKE_MCAST;
2548 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2549 if (ocp_data & MAGIC_EN)
2550 wolopts |= WAKE_MAGIC;
2555 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2559 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2561 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2562 ocp_data &= ~LINK_ON_WAKE_EN;
2563 if (wolopts & WAKE_PHY)
2564 ocp_data |= LINK_ON_WAKE_EN;
2565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2567 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2568 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2569 if (wolopts & WAKE_UCAST)
2571 if (wolopts & WAKE_BCAST)
2573 if (wolopts & WAKE_MCAST)
2575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2577 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2579 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2580 ocp_data &= ~MAGIC_EN;
2581 if (wolopts & WAKE_MAGIC)
2582 ocp_data |= MAGIC_EN;
2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2585 if (wolopts & WAKE_ANY)
2586 device_set_wakeup_enable(&tp->udev->dev, true);
2588 device_set_wakeup_enable(&tp->udev->dev, false);
2591 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2596 memset(u1u2, 0xff, sizeof(u1u2));
2598 memset(u1u2, 0x00, sizeof(u1u2));
2600 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2603 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2607 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2609 ocp_data |= LPM_U1U2_EN;
2611 ocp_data &= ~LPM_U1U2_EN;
2613 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2616 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2620 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2622 ocp_data |= U2P3_ENABLE;
2624 ocp_data &= ~U2P3_ENABLE;
2625 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2628 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2632 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2635 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2638 static void r8153b_green_en(struct r8152 *tp, bool enable)
2643 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2644 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2645 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2647 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2648 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2649 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2652 data = sram_read(tp, SRAM_GREEN_CFG);
2653 data |= GREEN_ETH_EN;
2654 sram_write(tp, SRAM_GREEN_CFG, data);
2656 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2659 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2664 for (i = 0; i < 500; i++) {
2665 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2666 data &= PHY_STAT_MASK;
2668 if (data == desired)
2670 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2671 data == PHY_STAT_EXT_INIT) {
2676 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2683 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2685 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2688 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2689 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2691 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2693 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2697 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2698 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2700 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2701 ocp_data &= ~BIT(0);
2702 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2704 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2705 ocp_data &= ~PCUT_STATUS;
2706 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2708 data = r8153_phy_status(tp, 0);
2711 case PHY_STAT_PWRDN:
2712 case PHY_STAT_EXT_INIT:
2714 test_bit(GREEN_ETHERNET, &tp->flags));
2716 data = r8152_mdio_read(tp, MII_BMCR);
2717 data &= ~BMCR_PDOWN;
2719 r8152_mdio_write(tp, MII_BMCR, data);
2721 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2724 if (data != PHY_STAT_LAN_ON)
2725 netif_warn(tp, link, tp->netdev,
2732 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2736 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2738 ocp_data |= PWR_EN | PHASE2_EN;
2740 ocp_data &= ~(PWR_EN | PHASE2_EN);
2741 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2743 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2744 ocp_data &= ~PCUT_STATUS;
2745 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2748 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2752 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2754 ocp_data |= PWR_EN | PHASE2_EN;
2756 ocp_data &= ~PWR_EN;
2757 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2759 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2760 ocp_data &= ~PCUT_STATUS;
2761 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2764 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2768 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2772 ocp_data &= ~BIT(0);
2773 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2775 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2776 ocp_data &= ~BIT(0);
2777 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2780 static bool rtl_can_wakeup(struct r8152 *tp)
2782 struct usb_device *udev = tp->udev;
2784 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2787 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2792 __rtl_set_wol(tp, WAKE_ANY);
2794 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2796 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2797 ocp_data |= LINK_OFF_WAKE_EN;
2798 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2800 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2804 __rtl_set_wol(tp, tp->saved_wolopts);
2806 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2808 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2809 ocp_data &= ~LINK_OFF_WAKE_EN;
2810 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2812 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2816 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2819 r8153_u1u2en(tp, false);
2820 r8153_u2p3en(tp, false);
2821 rtl_runtime_suspend_enable(tp, true);
2823 rtl_runtime_suspend_enable(tp, false);
2825 switch (tp->version) {
2832 r8153_u2p3en(tp, true);
2836 r8153_u1u2en(tp, true);
2840 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2843 r8153b_queue_wake(tp, true);
2844 r8153b_u1u2en(tp, false);
2845 r8153_u2p3en(tp, false);
2846 rtl_runtime_suspend_enable(tp, true);
2847 r8153b_ups_en(tp, true);
2849 r8153b_ups_en(tp, false);
2850 r8153b_queue_wake(tp, false);
2851 rtl_runtime_suspend_enable(tp, false);
2852 r8153_u2p3en(tp, true);
2853 r8153b_u1u2en(tp, true);
2857 static void r8153_teredo_off(struct r8152 *tp)
2861 switch (tp->version) {
2869 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2870 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2872 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2877 /* The bit 0 ~ 7 are relative with teredo settings. They are
2878 * W1C (write 1 to clear), so set all 1 to disable it.
2880 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2887 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2888 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2889 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2892 static void rtl_reset_bmu(struct r8152 *tp)
2896 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2897 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2898 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2899 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2900 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2903 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2906 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2907 LINKENA | DIS_SDSAVE);
2909 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2915 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2917 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2918 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2919 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2922 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2926 r8152_mmd_indirect(tp, dev, reg);
2927 data = ocp_reg_read(tp, OCP_EEE_DATA);
2928 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2933 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2935 r8152_mmd_indirect(tp, dev, reg);
2936 ocp_reg_write(tp, OCP_EEE_DATA, data);
2937 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2940 static void r8152_eee_en(struct r8152 *tp, bool enable)
2942 u16 config1, config2, config3;
2945 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2946 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2947 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2948 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2951 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2952 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2953 config1 |= sd_rise_time(1);
2954 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2955 config3 |= fast_snr(42);
2957 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2958 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2960 config1 |= sd_rise_time(7);
2961 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2962 config3 |= fast_snr(511);
2965 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2966 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2967 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2968 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2971 static void r8152b_enable_eee(struct r8152 *tp)
2973 r8152_eee_en(tp, true);
2974 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2977 static void r8152b_enable_fc(struct r8152 *tp)
2981 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2982 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2983 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2986 static void rtl8152_disable(struct r8152 *tp)
2988 r8152_aldps_en(tp, false);
2990 r8152_aldps_en(tp, true);
2993 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2995 r8152b_enable_eee(tp);
2996 r8152_aldps_en(tp, true);
2997 r8152b_enable_fc(tp);
2999 set_bit(PHY_RESET, &tp->flags);
3002 static void r8152b_exit_oob(struct r8152 *tp)
3007 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3008 ocp_data &= ~RCR_ACPT_ALL;
3009 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3011 rxdy_gated_en(tp, true);
3012 r8153_teredo_off(tp);
3013 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3014 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3016 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3017 ocp_data &= ~NOW_IS_OOB;
3018 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3020 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3021 ocp_data &= ~MCU_BORW_EN;
3022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3024 for (i = 0; i < 1000; i++) {
3025 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3026 if (ocp_data & LINK_LIST_READY)
3028 usleep_range(1000, 2000);
3031 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3032 ocp_data |= RE_INIT_LL;
3033 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3035 for (i = 0; i < 1000; i++) {
3036 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3037 if (ocp_data & LINK_LIST_READY)
3039 usleep_range(1000, 2000);
3042 rtl8152_nic_reset(tp);
3044 /* rx share fifo credit full threshold */
3045 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3047 if (tp->udev->speed == USB_SPEED_FULL ||
3048 tp->udev->speed == USB_SPEED_LOW) {
3049 /* rx share fifo credit near full threshold */
3050 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3052 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3055 /* rx share fifo credit near full threshold */
3056 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3058 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3062 /* TX share fifo free credit full threshold */
3063 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3065 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3066 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3067 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3068 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3070 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3072 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3074 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3075 ocp_data |= TCR0_AUTO_FIFO;
3076 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3079 static void r8152b_enter_oob(struct r8152 *tp)
3084 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3085 ocp_data &= ~NOW_IS_OOB;
3086 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3088 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3089 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3090 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3094 for (i = 0; i < 1000; i++) {
3095 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3096 if (ocp_data & LINK_LIST_READY)
3098 usleep_range(1000, 2000);
3101 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3102 ocp_data |= RE_INIT_LL;
3103 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3105 for (i = 0; i < 1000; i++) {
3106 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3107 if (ocp_data & LINK_LIST_READY)
3109 usleep_range(1000, 2000);
3112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3114 rtl_rx_vlan_en(tp, true);
3116 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3117 ocp_data |= ALDPS_PROXY_MODE;
3118 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3120 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3121 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3122 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3124 rxdy_gated_en(tp, false);
3126 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3127 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3128 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3131 static int r8153_patch_request(struct r8152 *tp, bool request)
3136 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3138 data |= PATCH_REQUEST;
3140 data &= ~PATCH_REQUEST;
3141 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3143 for (i = 0; request && i < 5000; i++) {
3144 usleep_range(1000, 2000);
3145 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3149 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3150 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3151 r8153_patch_request(tp, false);
3158 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3162 data = ocp_reg_read(tp, OCP_POWER_CFG);
3165 ocp_reg_write(tp, OCP_POWER_CFG, data);
3170 ocp_reg_write(tp, OCP_POWER_CFG, data);
3171 for (i = 0; i < 20; i++) {
3172 usleep_range(1000, 2000);
3173 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3179 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3181 r8153_aldps_en(tp, enable);
3184 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3186 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3189 static void r8153_eee_en(struct r8152 *tp, bool enable)
3194 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3195 config = ocp_reg_read(tp, OCP_EEE_CFG);
3198 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3201 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3202 config &= ~EEE10_EN;
3205 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3206 ocp_reg_write(tp, OCP_EEE_CFG, config);
3209 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3211 r8153_eee_en(tp, enable);
3214 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3216 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3219 static void r8153b_enable_fc(struct r8152 *tp)
3221 r8152b_enable_fc(tp);
3222 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3225 static void r8153_hw_phy_cfg(struct r8152 *tp)
3230 /* disable ALDPS before updating the PHY parameters */
3231 r8153_aldps_en(tp, false);
3233 /* disable EEE before updating the PHY parameters */
3234 r8153_eee_en(tp, false);
3235 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3237 if (tp->version == RTL_VER_03) {
3238 data = ocp_reg_read(tp, OCP_EEE_CFG);
3239 data &= ~CTAP_SHORT_EN;
3240 ocp_reg_write(tp, OCP_EEE_CFG, data);
3243 data = ocp_reg_read(tp, OCP_POWER_CFG);
3244 data |= EEE_CLKDIV_EN;
3245 ocp_reg_write(tp, OCP_POWER_CFG, data);
3247 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3248 data |= EN_10M_BGOFF;
3249 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3250 data = ocp_reg_read(tp, OCP_POWER_CFG);
3251 data |= EN_10M_PLLOFF;
3252 ocp_reg_write(tp, OCP_POWER_CFG, data);
3253 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3255 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3256 ocp_data |= PFM_PWM_SWITCH;
3257 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3259 /* Enable LPF corner auto tune */
3260 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3262 /* Adjust 10M Amplitude */
3263 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3264 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3266 r8153_eee_en(tp, true);
3267 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3269 r8153_aldps_en(tp, true);
3270 r8152b_enable_fc(tp);
3272 switch (tp->version) {
3279 r8153_u2p3en(tp, true);
3283 set_bit(PHY_RESET, &tp->flags);
3286 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3291 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3292 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3293 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3298 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3300 u32 ocp_data, ups_flags = 0;
3303 /* disable ALDPS before updating the PHY parameters */
3304 r8153b_aldps_en(tp, false);
3306 /* disable EEE before updating the PHY parameters */
3307 r8153b_eee_en(tp, false);
3308 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3310 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3312 data = sram_read(tp, SRAM_GREEN_CFG);
3314 sram_write(tp, SRAM_GREEN_CFG, data);
3315 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3316 data |= PGA_RETURN_EN;
3317 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3319 /* ADC Bias Calibration:
3320 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3321 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3324 ocp_data = r8152_efuse_read(tp, 0x7d);
3325 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3327 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3329 /* ups mode tx-link-pulse timing adjustment:
3330 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3331 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3333 ocp_data = ocp_reg_read(tp, 0xc426);
3336 u32 swr_cnt_1ms_ini;
3338 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3339 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3340 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3341 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3344 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3345 ocp_data |= PFM_PWM_SWITCH;
3346 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3349 if (!r8153_patch_request(tp, true)) {
3350 data = ocp_reg_read(tp, OCP_POWER_CFG);
3351 data |= EEE_CLKDIV_EN;
3352 ocp_reg_write(tp, OCP_POWER_CFG, data);
3354 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3355 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3356 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3358 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3359 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3361 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3362 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3363 UPS_FLAGS_EEE_PLLOFF_GIGA;
3365 r8153_patch_request(tp, false);
3368 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3370 r8153b_eee_en(tp, true);
3371 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3373 r8153b_aldps_en(tp, true);
3374 r8153b_enable_fc(tp);
3375 r8153_u2p3en(tp, true);
3377 set_bit(PHY_RESET, &tp->flags);
3380 static void r8153_first_init(struct r8152 *tp)
3385 rxdy_gated_en(tp, true);
3386 r8153_teredo_off(tp);
3388 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3389 ocp_data &= ~RCR_ACPT_ALL;
3390 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3392 rtl8152_nic_reset(tp);
3395 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3396 ocp_data &= ~NOW_IS_OOB;
3397 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3399 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3400 ocp_data &= ~MCU_BORW_EN;
3401 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3403 for (i = 0; i < 1000; i++) {
3404 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3405 if (ocp_data & LINK_LIST_READY)
3407 usleep_range(1000, 2000);
3410 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3411 ocp_data |= RE_INIT_LL;
3412 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3414 for (i = 0; i < 1000; i++) {
3415 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3416 if (ocp_data & LINK_LIST_READY)
3418 usleep_range(1000, 2000);
3421 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3423 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3424 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3425 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3427 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3428 ocp_data |= TCR0_AUTO_FIFO;
3429 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3431 rtl8152_nic_reset(tp);
3433 /* rx share fifo credit full threshold */
3434 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3437 /* TX share fifo free credit full threshold */
3438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3441 static void r8153_enter_oob(struct r8152 *tp)
3446 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3447 ocp_data &= ~NOW_IS_OOB;
3448 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3453 for (i = 0; i < 1000; i++) {
3454 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3455 if (ocp_data & LINK_LIST_READY)
3457 usleep_range(1000, 2000);
3460 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3461 ocp_data |= RE_INIT_LL;
3462 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3464 for (i = 0; i < 1000; i++) {
3465 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3466 if (ocp_data & LINK_LIST_READY)
3468 usleep_range(1000, 2000);
3471 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3474 switch (tp->version) {
3479 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3480 ocp_data &= ~TEREDO_WAKE_MASK;
3481 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3486 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3487 * type. Set it to zero. bits[7:0] are the W1C bits about
3488 * the events. Set them to all 1 to clear them.
3490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3497 rtl_rx_vlan_en(tp, true);
3499 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3500 ocp_data |= ALDPS_PROXY_MODE;
3501 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3503 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3504 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3505 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3507 rxdy_gated_en(tp, false);
3509 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3510 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3511 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3514 static void rtl8153_disable(struct r8152 *tp)
3516 r8153_aldps_en(tp, false);
3519 r8153_aldps_en(tp, true);
3522 static void rtl8153b_disable(struct r8152 *tp)
3524 r8153b_aldps_en(tp, false);
3527 r8153b_aldps_en(tp, true);
3530 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3532 u16 bmcr, anar, gbcr;
3533 enum spd_duplex speed_duplex;
3536 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3537 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3538 ADVERTISE_100HALF | ADVERTISE_100FULL);
3539 if (tp->mii.supports_gmii) {
3540 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3541 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3546 if (autoneg == AUTONEG_DISABLE) {
3547 if (speed == SPEED_10) {
3549 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3550 speed_duplex = FORCE_10M_HALF;
3551 } else if (speed == SPEED_100) {
3552 bmcr = BMCR_SPEED100;
3553 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3554 speed_duplex = FORCE_100M_HALF;
3555 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3556 bmcr = BMCR_SPEED1000;
3557 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3558 speed_duplex = NWAY_1000M_FULL;
3564 if (duplex == DUPLEX_FULL) {
3565 bmcr |= BMCR_FULLDPLX;
3566 if (speed != SPEED_1000)
3570 if (speed == SPEED_10) {
3571 if (duplex == DUPLEX_FULL) {
3572 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3573 speed_duplex = NWAY_10M_FULL;
3575 anar |= ADVERTISE_10HALF;
3576 speed_duplex = NWAY_10M_HALF;
3578 } else if (speed == SPEED_100) {
3579 if (duplex == DUPLEX_FULL) {
3580 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3581 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3582 speed_duplex = NWAY_100M_FULL;
3584 anar |= ADVERTISE_10HALF;
3585 anar |= ADVERTISE_100HALF;
3586 speed_duplex = NWAY_100M_HALF;
3588 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3589 if (duplex == DUPLEX_FULL) {
3590 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3591 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3592 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3594 anar |= ADVERTISE_10HALF;
3595 anar |= ADVERTISE_100HALF;
3596 gbcr |= ADVERTISE_1000HALF;
3598 speed_duplex = NWAY_1000M_FULL;
3604 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3607 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3610 if (tp->mii.supports_gmii)
3611 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3613 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3614 r8152_mdio_write(tp, MII_BMCR, bmcr);
3616 switch (tp->version) {
3619 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3620 UPS_FLAGS_SPEED_MASK);
3627 if (bmcr & BMCR_RESET) {
3630 for (i = 0; i < 50; i++) {
3632 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3641 static void rtl8152_up(struct r8152 *tp)
3643 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3646 r8152_aldps_en(tp, false);
3647 r8152b_exit_oob(tp);
3648 r8152_aldps_en(tp, true);
3651 static void rtl8152_down(struct r8152 *tp)
3653 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3654 rtl_drop_queued_tx(tp);
3658 r8152_power_cut_en(tp, false);
3659 r8152_aldps_en(tp, false);
3660 r8152b_enter_oob(tp);
3661 r8152_aldps_en(tp, true);
3664 static void rtl8153_up(struct r8152 *tp)
3666 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3669 r8153_u1u2en(tp, false);
3670 r8153_u2p3en(tp, false);
3671 r8153_aldps_en(tp, false);
3672 r8153_first_init(tp);
3673 r8153_aldps_en(tp, true);
3675 switch (tp->version) {
3682 r8153_u2p3en(tp, true);
3686 r8153_u1u2en(tp, true);
3689 static void rtl8153_down(struct r8152 *tp)
3691 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3692 rtl_drop_queued_tx(tp);
3696 r8153_u1u2en(tp, false);
3697 r8153_u2p3en(tp, false);
3698 r8153_power_cut_en(tp, false);
3699 r8153_aldps_en(tp, false);
3700 r8153_enter_oob(tp);
3701 r8153_aldps_en(tp, true);
3704 static void rtl8153b_up(struct r8152 *tp)
3706 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3709 r8153b_u1u2en(tp, false);
3710 r8153_u2p3en(tp, false);
3711 r8153b_aldps_en(tp, false);
3713 r8153_first_init(tp);
3714 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3716 r8153b_aldps_en(tp, true);
3717 r8153_u2p3en(tp, true);
3718 r8153b_u1u2en(tp, true);
3721 static void rtl8153b_down(struct r8152 *tp)
3723 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3724 rtl_drop_queued_tx(tp);
3728 r8153b_u1u2en(tp, false);
3729 r8153_u2p3en(tp, false);
3730 r8153b_power_cut_en(tp, false);
3731 r8153b_aldps_en(tp, false);
3732 r8153_enter_oob(tp);
3733 r8153b_aldps_en(tp, true);
3736 static bool rtl8152_in_nway(struct r8152 *tp)
3740 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3741 tp->ocp_base = 0x2000;
3742 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3743 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3745 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3746 if (nway_state & 0xc000)
3752 static bool rtl8153_in_nway(struct r8152 *tp)
3754 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3756 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3762 static void set_carrier(struct r8152 *tp)
3764 struct net_device *netdev = tp->netdev;
3765 struct napi_struct *napi = &tp->napi;
3768 speed = rtl8152_get_speed(tp);
3770 if (speed & LINK_STATUS) {
3771 if (!netif_carrier_ok(netdev)) {
3772 tp->rtl_ops.enable(tp);
3773 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3774 netif_stop_queue(netdev);
3776 netif_carrier_on(netdev);
3778 napi_enable(&tp->napi);
3779 netif_wake_queue(netdev);
3780 netif_info(tp, link, netdev, "carrier on\n");
3781 } else if (netif_queue_stopped(netdev) &&
3782 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3783 netif_wake_queue(netdev);
3786 if (netif_carrier_ok(netdev)) {
3787 netif_carrier_off(netdev);
3789 tp->rtl_ops.disable(tp);
3791 netif_info(tp, link, netdev, "carrier off\n");
3796 static void rtl_work_func_t(struct work_struct *work)
3798 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3800 /* If the device is unplugged or !netif_running(), the workqueue
3801 * doesn't need to wake the device, and could return directly.
3803 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3806 if (usb_autopm_get_interface(tp->intf) < 0)
3809 if (!test_bit(WORK_ENABLE, &tp->flags))
3812 if (!mutex_trylock(&tp->control)) {
3813 schedule_delayed_work(&tp->schedule, 0);
3817 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3820 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3821 _rtl8152_set_rx_mode(tp->netdev);
3823 /* don't schedule napi before linking */
3824 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3825 netif_carrier_ok(tp->netdev))
3826 napi_schedule(&tp->napi);
3828 mutex_unlock(&tp->control);
3831 usb_autopm_put_interface(tp->intf);
3834 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3836 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3838 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3841 if (usb_autopm_get_interface(tp->intf) < 0)
3844 mutex_lock(&tp->control);
3846 tp->rtl_ops.hw_phy_cfg(tp);
3848 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3850 mutex_unlock(&tp->control);
3852 usb_autopm_put_interface(tp->intf);
3855 #ifdef CONFIG_PM_SLEEP
3856 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3859 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3862 case PM_HIBERNATION_PREPARE:
3863 case PM_SUSPEND_PREPARE:
3864 usb_autopm_get_interface(tp->intf);
3867 case PM_POST_HIBERNATION:
3868 case PM_POST_SUSPEND:
3869 usb_autopm_put_interface(tp->intf);
3872 case PM_POST_RESTORE:
3873 case PM_RESTORE_PREPARE:
3882 static int rtl8152_open(struct net_device *netdev)
3884 struct r8152 *tp = netdev_priv(netdev);
3887 res = alloc_all_mem(tp);
3891 res = usb_autopm_get_interface(tp->intf);
3895 mutex_lock(&tp->control);
3899 netif_carrier_off(netdev);
3900 netif_start_queue(netdev);
3901 set_bit(WORK_ENABLE, &tp->flags);
3903 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3906 netif_device_detach(tp->netdev);
3907 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3911 napi_enable(&tp->napi);
3913 mutex_unlock(&tp->control);
3915 usb_autopm_put_interface(tp->intf);
3916 #ifdef CONFIG_PM_SLEEP
3917 tp->pm_notifier.notifier_call = rtl_notifier;
3918 register_pm_notifier(&tp->pm_notifier);
3923 mutex_unlock(&tp->control);
3924 usb_autopm_put_interface(tp->intf);
3931 static int rtl8152_close(struct net_device *netdev)
3933 struct r8152 *tp = netdev_priv(netdev);
3936 #ifdef CONFIG_PM_SLEEP
3937 unregister_pm_notifier(&tp->pm_notifier);
3939 if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3940 napi_disable(&tp->napi);
3941 clear_bit(WORK_ENABLE, &tp->flags);
3942 usb_kill_urb(tp->intr_urb);
3943 cancel_delayed_work_sync(&tp->schedule);
3944 netif_stop_queue(netdev);
3946 res = usb_autopm_get_interface(tp->intf);
3947 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3948 rtl_drop_queued_tx(tp);
3951 mutex_lock(&tp->control);
3953 tp->rtl_ops.down(tp);
3955 mutex_unlock(&tp->control);
3959 usb_autopm_put_interface(tp->intf);
3966 static void rtl_tally_reset(struct r8152 *tp)
3970 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3971 ocp_data |= TALLY_RESET;
3972 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3975 static void r8152b_init(struct r8152 *tp)
3980 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3983 data = r8152_mdio_read(tp, MII_BMCR);
3984 if (data & BMCR_PDOWN) {
3985 data &= ~BMCR_PDOWN;
3986 r8152_mdio_write(tp, MII_BMCR, data);
3989 r8152_aldps_en(tp, false);
3991 if (tp->version == RTL_VER_01) {
3992 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3993 ocp_data &= ~LED_MODE_MASK;
3994 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3997 r8152_power_cut_en(tp, false);
3999 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4000 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4001 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4002 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4003 ocp_data &= ~MCU_CLK_RATIO_MASK;
4004 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4005 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4006 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4007 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4008 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4010 rtl_tally_reset(tp);
4012 /* enable rx aggregation */
4013 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4014 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4015 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4018 static void r8153_init(struct r8152 *tp)
4024 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4027 r8153_u1u2en(tp, false);
4029 for (i = 0; i < 500; i++) {
4030 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4035 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4039 data = r8153_phy_status(tp, 0);
4041 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4042 tp->version == RTL_VER_05)
4043 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4045 data = r8152_mdio_read(tp, MII_BMCR);
4046 if (data & BMCR_PDOWN) {
4047 data &= ~BMCR_PDOWN;
4048 r8152_mdio_write(tp, MII_BMCR, data);
4051 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4053 r8153_u2p3en(tp, false);
4055 if (tp->version == RTL_VER_04) {
4056 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4057 ocp_data &= ~pwd_dn_scale_mask;
4058 ocp_data |= pwd_dn_scale(96);
4059 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4061 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4062 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4063 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4064 } else if (tp->version == RTL_VER_05) {
4065 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4066 ocp_data &= ~ECM_ALDPS;
4067 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4069 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4070 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4071 ocp_data &= ~DYNAMIC_BURST;
4073 ocp_data |= DYNAMIC_BURST;
4074 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4075 } else if (tp->version == RTL_VER_06) {
4076 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4077 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4078 ocp_data &= ~DYNAMIC_BURST;
4080 ocp_data |= DYNAMIC_BURST;
4081 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4084 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4085 ocp_data |= EP4_FULL_FC;
4086 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4088 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4089 ocp_data &= ~TIMER11_EN;
4090 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4092 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4093 ocp_data &= ~LED_MODE_MASK;
4094 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4096 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4097 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4098 ocp_data |= LPM_TIMER_500MS;
4100 ocp_data |= LPM_TIMER_500US;
4101 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4103 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4104 ocp_data &= ~SEN_VAL_MASK;
4105 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4106 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4108 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4110 /* MAC clock speed down */
4111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
4112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
4113 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
4114 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
4116 r8153_power_cut_en(tp, false);
4117 r8153_u1u2en(tp, true);
4118 usb_enable_lpm(tp->udev);
4120 /* rx aggregation */
4121 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4122 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4123 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4125 rtl_tally_reset(tp);
4127 switch (tp->udev->speed) {
4128 case USB_SPEED_SUPER:
4129 case USB_SPEED_SUPER_PLUS:
4130 tp->coalesce = COALESCE_SUPER;
4132 case USB_SPEED_HIGH:
4133 tp->coalesce = COALESCE_HIGH;
4136 tp->coalesce = COALESCE_SLOW;
4141 static void r8153b_init(struct r8152 *tp)
4147 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4150 r8153b_u1u2en(tp, false);
4152 for (i = 0; i < 500; i++) {
4153 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4158 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4162 data = r8153_phy_status(tp, 0);
4164 data = r8152_mdio_read(tp, MII_BMCR);
4165 if (data & BMCR_PDOWN) {
4166 data &= ~BMCR_PDOWN;
4167 r8152_mdio_write(tp, MII_BMCR, data);
4170 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4172 r8153_u2p3en(tp, false);
4174 /* MSC timer = 0xfff * 8ms = 32760 ms */
4175 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4177 /* U1/U2/L1 idle timer. 500 us */
4178 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4180 r8153b_power_cut_en(tp, false);
4181 r8153b_ups_en(tp, false);
4182 r8153b_queue_wake(tp, false);
4183 rtl_runtime_suspend_enable(tp, false);
4184 r8153b_u1u2en(tp, true);
4185 usb_enable_lpm(tp->udev);
4187 /* MAC clock speed down */
4188 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4189 ocp_data |= MAC_CLK_SPDWN_EN;
4190 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4192 set_bit(GREEN_ETHERNET, &tp->flags);
4194 /* rx aggregation */
4195 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4196 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4197 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4199 rtl_tally_reset(tp);
4201 tp->coalesce = 15000; /* 15 us */
4204 static int rtl8152_pre_reset(struct usb_interface *intf)
4206 struct r8152 *tp = usb_get_intfdata(intf);
4207 struct net_device *netdev;
4212 netdev = tp->netdev;
4213 if (!netif_running(netdev))
4216 netif_stop_queue(netdev);
4217 napi_disable(&tp->napi);
4218 clear_bit(WORK_ENABLE, &tp->flags);
4219 usb_kill_urb(tp->intr_urb);
4220 cancel_delayed_work_sync(&tp->schedule);
4221 if (netif_carrier_ok(netdev)) {
4222 mutex_lock(&tp->control);
4223 tp->rtl_ops.disable(tp);
4224 mutex_unlock(&tp->control);
4230 static int rtl8152_post_reset(struct usb_interface *intf)
4232 struct r8152 *tp = usb_get_intfdata(intf);
4233 struct net_device *netdev;
4238 netdev = tp->netdev;
4239 if (!netif_running(netdev))
4242 set_bit(WORK_ENABLE, &tp->flags);
4243 if (netif_carrier_ok(netdev)) {
4244 mutex_lock(&tp->control);
4245 tp->rtl_ops.enable(tp);
4247 rtl8152_set_rx_mode(netdev);
4248 mutex_unlock(&tp->control);
4251 napi_enable(&tp->napi);
4252 netif_wake_queue(netdev);
4253 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4255 if (!list_empty(&tp->rx_done))
4256 napi_schedule(&tp->napi);
4261 static bool delay_autosuspend(struct r8152 *tp)
4263 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4264 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4266 /* This means a linking change occurs and the driver doesn't detect it,
4267 * yet. If the driver has disabled tx/rx and hw is linking on, the
4268 * device wouldn't wake up by receiving any packet.
4270 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4273 /* If the linking down is occurred by nway, the device may miss the
4274 * linking change event. And it wouldn't wake when linking on.
4276 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4278 else if (!skb_queue_empty(&tp->tx_queue))
4284 static int rtl8152_runtime_resume(struct r8152 *tp)
4286 struct net_device *netdev = tp->netdev;
4288 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4289 struct napi_struct *napi = &tp->napi;
4291 tp->rtl_ops.autosuspend_en(tp, false);
4293 set_bit(WORK_ENABLE, &tp->flags);
4295 if (netif_carrier_ok(netdev)) {
4296 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4299 netif_carrier_off(netdev);
4300 tp->rtl_ops.disable(tp);
4301 netif_info(tp, link, netdev, "linking down\n");
4306 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4307 smp_mb__after_atomic();
4309 if (!list_empty(&tp->rx_done))
4310 napi_schedule(&tp->napi);
4312 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4314 if (netdev->flags & IFF_UP)
4315 tp->rtl_ops.autosuspend_en(tp, false);
4317 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4323 static int rtl8152_system_resume(struct r8152 *tp)
4325 struct net_device *netdev = tp->netdev;
4327 netif_device_attach(netdev);
4329 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4331 netif_carrier_off(netdev);
4332 set_bit(WORK_ENABLE, &tp->flags);
4333 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4339 static int rtl8152_runtime_suspend(struct r8152 *tp)
4341 struct net_device *netdev = tp->netdev;
4344 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4345 smp_mb__after_atomic();
4347 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4350 if (netif_carrier_ok(netdev)) {
4353 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4354 ocp_data = rcr & ~RCR_ACPT_ALL;
4355 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4356 rxdy_gated_en(tp, true);
4357 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4359 if (!(ocp_data & RXFIFO_EMPTY)) {
4360 rxdy_gated_en(tp, false);
4361 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4362 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4363 smp_mb__after_atomic();
4369 clear_bit(WORK_ENABLE, &tp->flags);
4370 usb_kill_urb(tp->intr_urb);
4372 tp->rtl_ops.autosuspend_en(tp, true);
4374 if (netif_carrier_ok(netdev)) {
4375 struct napi_struct *napi = &tp->napi;
4379 rxdy_gated_en(tp, false);
4380 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4384 if (delay_autosuspend(tp)) {
4385 rtl8152_runtime_resume(tp);
4394 static int rtl8152_system_suspend(struct r8152 *tp)
4396 struct net_device *netdev = tp->netdev;
4399 netif_device_detach(netdev);
4401 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4402 struct napi_struct *napi = &tp->napi;
4404 clear_bit(WORK_ENABLE, &tp->flags);
4405 usb_kill_urb(tp->intr_urb);
4407 cancel_delayed_work_sync(&tp->schedule);
4408 tp->rtl_ops.down(tp);
4415 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4417 struct r8152 *tp = usb_get_intfdata(intf);
4420 mutex_lock(&tp->control);
4422 if (PMSG_IS_AUTO(message))
4423 ret = rtl8152_runtime_suspend(tp);
4425 ret = rtl8152_system_suspend(tp);
4427 mutex_unlock(&tp->control);
4432 static int rtl8152_resume(struct usb_interface *intf)
4434 struct r8152 *tp = usb_get_intfdata(intf);
4437 mutex_lock(&tp->control);
4439 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4440 ret = rtl8152_runtime_resume(tp);
4442 ret = rtl8152_system_resume(tp);
4444 mutex_unlock(&tp->control);
4449 static int rtl8152_reset_resume(struct usb_interface *intf)
4451 struct r8152 *tp = usb_get_intfdata(intf);
4453 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4454 tp->rtl_ops.init(tp);
4455 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4456 set_ethernet_addr(tp);
4457 return rtl8152_resume(intf);
4460 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4462 struct r8152 *tp = netdev_priv(dev);
4464 if (usb_autopm_get_interface(tp->intf) < 0)
4467 if (!rtl_can_wakeup(tp)) {
4471 mutex_lock(&tp->control);
4472 wol->supported = WAKE_ANY;
4473 wol->wolopts = __rtl_get_wol(tp);
4474 mutex_unlock(&tp->control);
4477 usb_autopm_put_interface(tp->intf);
4480 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4482 struct r8152 *tp = netdev_priv(dev);
4485 if (!rtl_can_wakeup(tp))
4488 if (wol->wolopts & ~WAKE_ANY)
4491 ret = usb_autopm_get_interface(tp->intf);
4495 mutex_lock(&tp->control);
4497 __rtl_set_wol(tp, wol->wolopts);
4498 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4500 mutex_unlock(&tp->control);
4502 usb_autopm_put_interface(tp->intf);
4508 static u32 rtl8152_get_msglevel(struct net_device *dev)
4510 struct r8152 *tp = netdev_priv(dev);
4512 return tp->msg_enable;
4515 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4517 struct r8152 *tp = netdev_priv(dev);
4519 tp->msg_enable = value;
4522 static void rtl8152_get_drvinfo(struct net_device *netdev,
4523 struct ethtool_drvinfo *info)
4525 struct r8152 *tp = netdev_priv(netdev);
4527 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4528 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4529 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4533 int rtl8152_get_link_ksettings(struct net_device *netdev,
4534 struct ethtool_link_ksettings *cmd)
4536 struct r8152 *tp = netdev_priv(netdev);
4539 if (!tp->mii.mdio_read)
4542 ret = usb_autopm_get_interface(tp->intf);
4546 mutex_lock(&tp->control);
4548 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4550 mutex_unlock(&tp->control);
4552 usb_autopm_put_interface(tp->intf);
4558 static int rtl8152_set_link_ksettings(struct net_device *dev,
4559 const struct ethtool_link_ksettings *cmd)
4561 struct r8152 *tp = netdev_priv(dev);
4564 ret = usb_autopm_get_interface(tp->intf);
4568 mutex_lock(&tp->control);
4570 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4573 tp->autoneg = cmd->base.autoneg;
4574 tp->speed = cmd->base.speed;
4575 tp->duplex = cmd->base.duplex;
4578 mutex_unlock(&tp->control);
4580 usb_autopm_put_interface(tp->intf);
4586 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4593 "tx_single_collisions",
4594 "tx_multi_collisions",
4602 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4606 return ARRAY_SIZE(rtl8152_gstrings);
4612 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4613 struct ethtool_stats *stats, u64 *data)
4615 struct r8152 *tp = netdev_priv(dev);
4616 struct tally_counter tally;
4618 if (usb_autopm_get_interface(tp->intf) < 0)
4621 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4623 usb_autopm_put_interface(tp->intf);
4625 data[0] = le64_to_cpu(tally.tx_packets);
4626 data[1] = le64_to_cpu(tally.rx_packets);
4627 data[2] = le64_to_cpu(tally.tx_errors);
4628 data[3] = le32_to_cpu(tally.rx_errors);
4629 data[4] = le16_to_cpu(tally.rx_missed);
4630 data[5] = le16_to_cpu(tally.align_errors);
4631 data[6] = le32_to_cpu(tally.tx_one_collision);
4632 data[7] = le32_to_cpu(tally.tx_multi_collision);
4633 data[8] = le64_to_cpu(tally.rx_unicast);
4634 data[9] = le64_to_cpu(tally.rx_broadcast);
4635 data[10] = le32_to_cpu(tally.rx_multicast);
4636 data[11] = le16_to_cpu(tally.tx_aborted);
4637 data[12] = le16_to_cpu(tally.tx_underrun);
4640 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4642 switch (stringset) {
4644 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
4649 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4651 u32 ocp_data, lp, adv, supported = 0;
4654 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4655 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4657 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4658 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4660 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4661 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4663 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4664 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4666 eee->eee_enabled = !!ocp_data;
4667 eee->eee_active = !!(supported & adv & lp);
4668 eee->supported = supported;
4669 eee->advertised = adv;
4670 eee->lp_advertised = lp;
4675 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4677 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4679 r8152_eee_en(tp, eee->eee_enabled);
4681 if (!eee->eee_enabled)
4684 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4689 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4691 u32 ocp_data, lp, adv, supported = 0;
4694 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4695 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4697 val = ocp_reg_read(tp, OCP_EEE_ADV);
4698 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4700 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4701 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4703 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4704 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4706 eee->eee_enabled = !!ocp_data;
4707 eee->eee_active = !!(supported & adv & lp);
4708 eee->supported = supported;
4709 eee->advertised = adv;
4710 eee->lp_advertised = lp;
4715 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4717 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4719 r8153_eee_en(tp, eee->eee_enabled);
4721 if (!eee->eee_enabled)
4724 ocp_reg_write(tp, OCP_EEE_ADV, val);
4729 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4731 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4733 r8153b_eee_en(tp, eee->eee_enabled);
4735 if (!eee->eee_enabled)
4738 ocp_reg_write(tp, OCP_EEE_ADV, val);
4744 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4746 struct r8152 *tp = netdev_priv(net);
4749 ret = usb_autopm_get_interface(tp->intf);
4753 mutex_lock(&tp->control);
4755 ret = tp->rtl_ops.eee_get(tp, edata);
4757 mutex_unlock(&tp->control);
4759 usb_autopm_put_interface(tp->intf);
4766 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4768 struct r8152 *tp = netdev_priv(net);
4771 ret = usb_autopm_get_interface(tp->intf);
4775 mutex_lock(&tp->control);
4777 ret = tp->rtl_ops.eee_set(tp, edata);
4779 ret = mii_nway_restart(&tp->mii);
4781 mutex_unlock(&tp->control);
4783 usb_autopm_put_interface(tp->intf);
4789 static int rtl8152_nway_reset(struct net_device *dev)
4791 struct r8152 *tp = netdev_priv(dev);
4794 ret = usb_autopm_get_interface(tp->intf);
4798 mutex_lock(&tp->control);
4800 ret = mii_nway_restart(&tp->mii);
4802 mutex_unlock(&tp->control);
4804 usb_autopm_put_interface(tp->intf);
4810 static int rtl8152_get_coalesce(struct net_device *netdev,
4811 struct ethtool_coalesce *coalesce)
4813 struct r8152 *tp = netdev_priv(netdev);
4815 switch (tp->version) {
4824 coalesce->rx_coalesce_usecs = tp->coalesce;
4829 static int rtl8152_set_coalesce(struct net_device *netdev,
4830 struct ethtool_coalesce *coalesce)
4832 struct r8152 *tp = netdev_priv(netdev);
4835 switch (tp->version) {
4844 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4847 ret = usb_autopm_get_interface(tp->intf);
4851 mutex_lock(&tp->control);
4853 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4854 tp->coalesce = coalesce->rx_coalesce_usecs;
4856 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4857 r8153_set_rx_early_timeout(tp);
4860 mutex_unlock(&tp->control);
4862 usb_autopm_put_interface(tp->intf);
4867 static const struct ethtool_ops ops = {
4868 .get_drvinfo = rtl8152_get_drvinfo,
4869 .get_link = ethtool_op_get_link,
4870 .nway_reset = rtl8152_nway_reset,
4871 .get_msglevel = rtl8152_get_msglevel,
4872 .set_msglevel = rtl8152_set_msglevel,
4873 .get_wol = rtl8152_get_wol,
4874 .set_wol = rtl8152_set_wol,
4875 .get_strings = rtl8152_get_strings,
4876 .get_sset_count = rtl8152_get_sset_count,
4877 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4878 .get_coalesce = rtl8152_get_coalesce,
4879 .set_coalesce = rtl8152_set_coalesce,
4880 .get_eee = rtl_ethtool_get_eee,
4881 .set_eee = rtl_ethtool_set_eee,
4882 .get_link_ksettings = rtl8152_get_link_ksettings,
4883 .set_link_ksettings = rtl8152_set_link_ksettings,
4886 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4888 struct r8152 *tp = netdev_priv(netdev);
4889 struct mii_ioctl_data *data = if_mii(rq);
4892 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4895 res = usb_autopm_get_interface(tp->intf);
4901 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4905 mutex_lock(&tp->control);
4906 data->val_out = r8152_mdio_read(tp, data->reg_num);
4907 mutex_unlock(&tp->control);
4911 if (!capable(CAP_NET_ADMIN)) {
4915 mutex_lock(&tp->control);
4916 r8152_mdio_write(tp, data->reg_num, data->val_in);
4917 mutex_unlock(&tp->control);
4924 usb_autopm_put_interface(tp->intf);
4930 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4932 struct r8152 *tp = netdev_priv(dev);
4935 switch (tp->version) {
4945 ret = usb_autopm_get_interface(tp->intf);
4949 mutex_lock(&tp->control);
4953 if (netif_running(dev)) {
4954 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4956 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4958 if (netif_carrier_ok(dev))
4959 r8153_set_rx_early_size(tp);
4962 mutex_unlock(&tp->control);
4964 usb_autopm_put_interface(tp->intf);
4969 static const struct net_device_ops rtl8152_netdev_ops = {
4970 .ndo_open = rtl8152_open,
4971 .ndo_stop = rtl8152_close,
4972 .ndo_do_ioctl = rtl8152_ioctl,
4973 .ndo_start_xmit = rtl8152_start_xmit,
4974 .ndo_tx_timeout = rtl8152_tx_timeout,
4975 .ndo_set_features = rtl8152_set_features,
4976 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4977 .ndo_set_mac_address = rtl8152_set_mac_address,
4978 .ndo_change_mtu = rtl8152_change_mtu,
4979 .ndo_validate_addr = eth_validate_addr,
4980 .ndo_features_check = rtl8152_features_check,
4983 static void rtl8152_unload(struct r8152 *tp)
4985 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4988 if (tp->version != RTL_VER_01)
4989 r8152_power_cut_en(tp, true);
4992 static void rtl8153_unload(struct r8152 *tp)
4994 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4997 r8153_power_cut_en(tp, false);
5000 static void rtl8153b_unload(struct r8152 *tp)
5002 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5005 r8153b_power_cut_en(tp, false);
5008 static int rtl_ops_init(struct r8152 *tp)
5010 struct rtl_ops *ops = &tp->rtl_ops;
5013 switch (tp->version) {
5017 ops->init = r8152b_init;
5018 ops->enable = rtl8152_enable;
5019 ops->disable = rtl8152_disable;
5020 ops->up = rtl8152_up;
5021 ops->down = rtl8152_down;
5022 ops->unload = rtl8152_unload;
5023 ops->eee_get = r8152_get_eee;
5024 ops->eee_set = r8152_set_eee;
5025 ops->in_nway = rtl8152_in_nway;
5026 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5027 ops->autosuspend_en = rtl_runtime_suspend_enable;
5034 ops->init = r8153_init;
5035 ops->enable = rtl8153_enable;
5036 ops->disable = rtl8153_disable;
5037 ops->up = rtl8153_up;
5038 ops->down = rtl8153_down;
5039 ops->unload = rtl8153_unload;
5040 ops->eee_get = r8153_get_eee;
5041 ops->eee_set = r8153_set_eee;
5042 ops->in_nway = rtl8153_in_nway;
5043 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5044 ops->autosuspend_en = rtl8153_runtime_enable;
5049 ops->init = r8153b_init;
5050 ops->enable = rtl8153_enable;
5051 ops->disable = rtl8153b_disable;
5052 ops->up = rtl8153b_up;
5053 ops->down = rtl8153b_down;
5054 ops->unload = rtl8153b_unload;
5055 ops->eee_get = r8153_get_eee;
5056 ops->eee_set = r8153b_set_eee;
5057 ops->in_nway = rtl8153_in_nway;
5058 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5059 ops->autosuspend_en = rtl8153b_runtime_enable;
5064 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5071 static u8 rtl_get_version(struct usb_interface *intf)
5073 struct usb_device *udev = interface_to_usbdev(intf);
5079 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5083 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5084 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5085 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5087 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5093 version = RTL_VER_01;
5096 version = RTL_VER_02;
5099 version = RTL_VER_03;
5102 version = RTL_VER_04;
5105 version = RTL_VER_05;
5108 version = RTL_VER_06;
5111 version = RTL_VER_07;
5114 version = RTL_VER_08;
5117 version = RTL_VER_09;
5120 version = RTL_VER_UNKNOWN;
5121 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5125 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5130 static int rtl8152_probe(struct usb_interface *intf,
5131 const struct usb_device_id *id)
5133 struct usb_device *udev = interface_to_usbdev(intf);
5134 u8 version = rtl_get_version(intf);
5136 struct net_device *netdev;
5139 if (version == RTL_VER_UNKNOWN)
5142 if (udev->actconfig->desc.bConfigurationValue != 1) {
5143 usb_driver_set_configuration(udev, 1);
5147 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
5150 usb_reset_device(udev);
5151 netdev = alloc_etherdev(sizeof(struct r8152));
5153 dev_err(&intf->dev, "Out of memory\n");
5157 SET_NETDEV_DEV(netdev, &intf->dev);
5158 tp = netdev_priv(netdev);
5159 tp->msg_enable = 0x7FFF;
5162 tp->netdev = netdev;
5164 tp->version = version;
5170 tp->mii.supports_gmii = 0;
5173 tp->mii.supports_gmii = 1;
5177 ret = rtl_ops_init(tp);
5181 mutex_init(&tp->control);
5182 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5183 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5185 netdev->netdev_ops = &rtl8152_netdev_ops;
5186 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5188 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5189 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5190 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5191 NETIF_F_HW_VLAN_CTAG_TX;
5192 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5193 NETIF_F_TSO | NETIF_F_FRAGLIST |
5194 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5195 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5196 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5197 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5198 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5200 if (tp->version == RTL_VER_01) {
5201 netdev->features &= ~NETIF_F_RXCSUM;
5202 netdev->hw_features &= ~NETIF_F_RXCSUM;
5205 netdev->ethtool_ops = &ops;
5206 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5208 /* MTU range: 68 - 1500 or 9194 */
5209 netdev->min_mtu = ETH_MIN_MTU;
5210 switch (tp->version) {
5213 netdev->max_mtu = ETH_DATA_LEN;
5216 netdev->max_mtu = RTL8153_MAX_MTU;
5220 tp->mii.dev = netdev;
5221 tp->mii.mdio_read = read_mii_word;
5222 tp->mii.mdio_write = write_mii_word;
5223 tp->mii.phy_id_mask = 0x3f;
5224 tp->mii.reg_num_mask = 0x1f;
5225 tp->mii.phy_id = R8152_PHY_ID;
5227 tp->autoneg = AUTONEG_ENABLE;
5228 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5229 tp->duplex = DUPLEX_FULL;
5231 intf->needs_remote_wakeup = 1;
5233 if (!rtl_can_wakeup(tp))
5234 __rtl_set_wol(tp, 0);
5236 tp->saved_wolopts = __rtl_get_wol(tp);
5238 tp->rtl_ops.init(tp);
5239 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5240 set_ethernet_addr(tp);
5242 usb_set_intfdata(intf, tp);
5243 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5245 ret = register_netdev(netdev);
5247 netif_err(tp, probe, netdev, "couldn't register the device\n");
5251 if (tp->saved_wolopts)
5252 device_set_wakeup_enable(&udev->dev, true);
5254 device_set_wakeup_enable(&udev->dev, false);
5256 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5261 netif_napi_del(&tp->napi);
5262 usb_set_intfdata(intf, NULL);
5264 free_netdev(netdev);
5268 static void rtl8152_disconnect(struct usb_interface *intf)
5270 struct r8152 *tp = usb_get_intfdata(intf);
5272 usb_set_intfdata(intf, NULL);
5274 struct usb_device *udev = tp->udev;
5276 if (udev->state == USB_STATE_NOTATTACHED)
5277 set_bit(RTL8152_UNPLUG, &tp->flags);
5279 netif_napi_del(&tp->napi);
5280 unregister_netdev(tp->netdev);
5281 cancel_delayed_work_sync(&tp->hw_phy_work);
5282 tp->rtl_ops.unload(tp);
5283 free_netdev(tp->netdev);
5287 #define REALTEK_USB_DEVICE(vend, prod) \
5288 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5289 USB_DEVICE_ID_MATCH_INT_CLASS, \
5290 .idVendor = (vend), \
5291 .idProduct = (prod), \
5292 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5295 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5296 USB_DEVICE_ID_MATCH_DEVICE, \
5297 .idVendor = (vend), \
5298 .idProduct = (prod), \
5299 .bInterfaceClass = USB_CLASS_COMM, \
5300 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5301 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5303 /* table of devices that work with this driver */
5304 static const struct usb_device_id rtl8152_table[] = {
5305 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5306 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5307 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5308 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5309 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5310 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
5311 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5312 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5313 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5314 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5315 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5316 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5317 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5318 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e)},
5319 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
5320 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5321 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5322 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5326 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5328 static struct usb_driver rtl8152_driver = {
5330 .id_table = rtl8152_table,
5331 .probe = rtl8152_probe,
5332 .disconnect = rtl8152_disconnect,
5333 .suspend = rtl8152_suspend,
5334 .resume = rtl8152_resume,
5335 .reset_resume = rtl8152_reset_resume,
5336 .pre_reset = rtl8152_pre_reset,
5337 .post_reset = rtl8152_post_reset,
5338 .supports_autosuspend = 1,
5339 .disable_hub_initiated_lpm = 1,
5342 module_usb_driver(rtl8152_driver);
5344 MODULE_AUTHOR(DRIVER_AUTHOR);
5345 MODULE_DESCRIPTION(DRIVER_DESC);
5346 MODULE_LICENSE("GPL");
5347 MODULE_VERSION(DRIVER_VERSION);