2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "09"
34 /* Information for net */
35 #define NET_VERSION "9"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_AFE_CTRL2 0xd824
133 #define USB_UPS_CFG 0xd842
134 #define USB_UPS_FLAGS 0xd848
135 #define USB_WDT11_CTRL 0xe43c
136 #define USB_BP_BA 0xfc26
137 #define USB_BP_0 0xfc28
138 #define USB_BP_1 0xfc2a
139 #define USB_BP_2 0xfc2c
140 #define USB_BP_3 0xfc2e
141 #define USB_BP_4 0xfc30
142 #define USB_BP_5 0xfc32
143 #define USB_BP_6 0xfc34
144 #define USB_BP_7 0xfc36
145 #define USB_BP_EN 0xfc38
146 #define USB_BP_8 0xfc38
147 #define USB_BP_9 0xfc3a
148 #define USB_BP_10 0xfc3c
149 #define USB_BP_11 0xfc3e
150 #define USB_BP_12 0xfc40
151 #define USB_BP_13 0xfc42
152 #define USB_BP_14 0xfc44
153 #define USB_BP_15 0xfc46
154 #define USB_BP2_EN 0xfc48
157 #define OCP_ALDPS_CONFIG 0x2010
158 #define OCP_EEE_CONFIG1 0x2080
159 #define OCP_EEE_CONFIG2 0x2092
160 #define OCP_EEE_CONFIG3 0x2094
161 #define OCP_BASE_MII 0xa400
162 #define OCP_EEE_AR 0xa41a
163 #define OCP_EEE_DATA 0xa41c
164 #define OCP_PHY_STATUS 0xa420
165 #define OCP_NCTL_CFG 0xa42c
166 #define OCP_POWER_CFG 0xa430
167 #define OCP_EEE_CFG 0xa432
168 #define OCP_SRAM_ADDR 0xa436
169 #define OCP_SRAM_DATA 0xa438
170 #define OCP_DOWN_SPEED 0xa442
171 #define OCP_EEE_ABLE 0xa5c4
172 #define OCP_EEE_ADV 0xa5d0
173 #define OCP_EEE_LPABLE 0xa5d2
174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT 0xb800
176 #define OCP_PHY_PATCH_CMD 0xb820
177 #define OCP_ADC_IOFFSET 0xbcfc
178 #define OCP_ADC_CFG 0xbc06
179 #define OCP_SYSCLK_CFG 0xc416
182 #define SRAM_GREEN_CFG 0x8011
183 #define SRAM_LPF_CFG 0x8012
184 #define SRAM_10M_AMP1 0x8080
185 #define SRAM_10M_AMP2 0x8082
186 #define SRAM_IMPEDANCE 0x8084
189 #define RCR_AAP 0x00000001
190 #define RCR_APM 0x00000002
191 #define RCR_AM 0x00000004
192 #define RCR_AB 0x00000008
193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL 0x00080002
197 #define RXFIFO_THR1_OOB 0x01800003
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL 0x00000060
201 #define RXFIFO_THR2_HIGH 0x00000038
202 #define RXFIFO_THR2_OOB 0x0000004a
203 #define RXFIFO_THR2_NORMAL 0x00a0
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL 0x00000078
207 #define RXFIFO_THR3_HIGH 0x00000048
208 #define RXFIFO_THR3_OOB 0x0000005a
209 #define RXFIFO_THR3_NORMAL 0x0110
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL 0x00400008
213 #define TXFIFO_THR_NORMAL2 0x01000008
216 #define ECM_ALDPS 0x0002
219 #define FMC_FCR_MCU_EN 0x0001
222 #define EEEP_CR_EEEP_TX 0x0002
225 #define WDT6_SET_MODE 0x0010
228 #define TCR0_TX_EMPTY 0x0800
229 #define TCR0_AUTO_FIFO 0x0080
232 #define VERSION_MASK 0x7cf0
235 #define MTPS_JUMBO (12 * 1024 / 64)
236 #define MTPS_DEFAULT (6 * 1024 / 64)
239 #define TALLY_RESET 0x0001
247 #define CRWECR_NORAML 0x00
248 #define CRWECR_CONFIG 0xc0
251 #define NOW_IS_OOB 0x80
252 #define TXFIFO_EMPTY 0x20
253 #define RXFIFO_EMPTY 0x10
254 #define LINK_LIST_READY 0x02
255 #define DIS_MCU_CLROOB 0x01
256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
259 #define RXDY_GATED_EN 0x0008
262 #define RE_INIT_LL 0x8000
263 #define MCU_BORW_EN 0x4000
266 #define CPCR_RX_VLAN 0x0040
269 #define MAGIC_EN 0x0001
272 #define TEREDO_SEL 0x8000
273 #define TEREDO_WAKE_MASK 0x7f00
274 #define TEREDO_RS_EVENT_MASK 0x00fe
275 #define OOB_TEREDO_EN 0x0001
278 #define ALDPS_PROXY_MODE 0x0001
281 #define EFUSE_READ_CMD BIT(15)
282 #define EFUSE_DATA_BIT16 BIT(7)
285 #define LINK_ON_WAKE_EN 0x0010
286 #define LINK_OFF_WAKE_EN 0x0008
289 #define BWF_EN 0x0040
290 #define MWF_EN 0x0020
291 #define UWF_EN 0x0010
292 #define LAN_WAKE_EN 0x0002
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK 0x0700
298 #define TX_10M_IDLE_EN 0x0080
299 #define PFM_PWM_SWITCH 0x0040
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN 0x00004000
303 #define MCU_CLK_RATIO 0x07010f07
304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO 0x0f87
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO 0x8007
309 #define MAC_CLK_SPDWN_EN BIT(15)
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN 0x0100
313 #define SUSPEND_SPDWN_EN 0x0004
314 #define U1U2_SPDWN_EN 0x0002
315 #define L1_SPDWN_EN 0x0001
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN 0x1000
319 #define RXDV_SPDWN_EN 0x0800
320 #define TX10MIDLE_EN 0x0100
321 #define TP100_SPDWN_EN 0x0020
322 #define TP500_SPDWN_EN 0x0010
323 #define TP1000_SPDWN_EN 0x0008
324 #define EEE_SPDWN_EN 0x0001
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK 0x0001
328 #define SPEED_DOWN_MSK 0x0002
329 #define SPDWN_RXDV_MSK 0x0004
330 #define SPDWN_LINKCHG_MSK 0x0008
333 #define PHYAR_FLAG 0x80000000
336 #define EEE_RX_EN 0x0001
337 #define EEE_TX_EN 0x0002
340 #define AUTOLOAD_DONE 0x0002
343 #define USB2PHY_SUSPEND 0x0001
344 #define USB2PHY_L1 0x0002
347 #define pwd_dn_scale_mask 0x3ffe
348 #define pwd_dn_scale(x) ((x) << 1)
351 #define DYNAMIC_BURST 0x0001
354 #define EP4_FULL_FC 0x0001
357 #define STAT_SPEED_MASK 0x0006
358 #define STAT_SPEED_HIGH 0x0000
359 #define STAT_SPEED_FULL 0x0002
362 #define LPM_U1U2_EN BIT(0)
365 #define TX_AGG_MAX_THRESHOLD 0x03
368 #define RX_THR_SUPPER 0x0c350180
369 #define RX_THR_HIGH 0x7a120180
370 #define RX_THR_SLOW 0xffff0180
371 #define RX_THR_B 0x00010001
374 #define TEST_MODE_DISABLE 0x00000001
375 #define TX_SIZE_ADJUST1 0x00000100
378 #define BMU_RESET_EP_IN 0x01
379 #define BMU_RESET_EP_OUT 0x02
381 /* USB_UPT_RXDMA_OWN */
382 #define OWN_UPDATE BIT(0)
383 #define OWN_CLEAR BIT(1)
386 #define POWER_CUT 0x0100
388 /* USB_PM_CTRL_STATUS */
389 #define RESUME_INDICATE 0x0001
392 #define RX_AGG_DISABLE 0x0010
393 #define RX_ZERO_EN 0x0080
396 #define U2P3_ENABLE 0x0001
399 #define PWR_EN 0x0001
400 #define PHASE2_EN 0x0008
401 #define UPS_EN BIT(4)
402 #define USP_PREWAKE BIT(5)
405 #define PCUT_STATUS 0x0001
407 /* USB_RX_EARLY_TIMEOUT */
408 #define COALESCE_SUPER 85000U
409 #define COALESCE_HIGH 250000U
410 #define COALESCE_SLOW 524280U
413 #define TIMER11_EN 0x0001
416 /* bit 4 ~ 5: fifo empty boundary */
417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
418 /* bit 2 ~ 3: LMP timer */
419 #define LPM_TIMER_MASK 0x0c
420 #define LPM_TIMER_500MS 0x04 /* 500 ms */
421 #define LPM_TIMER_500US 0x0c /* 500 us */
422 #define ROK_EXIT_LPM 0x02
425 #define SEN_VAL_MASK 0xf800
426 #define SEN_VAL_NORMAL 0xa000
427 #define SEL_RXIDLE 0x0100
430 #define SAW_CNT_1MS_MASK 0x0fff
433 #define UPS_FLAGS_R_TUNE BIT(0)
434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
435 #define UPS_FLAGS_250M_CKDIV BIT(2)
436 #define UPS_FLAGS_EN_ALDPS BIT(3)
437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
438 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
439 #define ups_flags_speed(x) ((x) << 16)
440 #define UPS_FLAGS_EN_EEE BIT(20)
441 #define UPS_FLAGS_EN_500M_EEE BIT(21)
442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
445 #define UPS_FLAGS_EN_GREEN BIT(26)
446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
460 /* OCP_ALDPS_CONFIG */
461 #define ENPWRSAVE 0x8000
462 #define ENPDNPS 0x0200
463 #define LINKENA 0x0100
464 #define DIS_SDSAVE 0x0010
467 #define PHY_STAT_MASK 0x0007
468 #define PHY_STAT_EXT_INIT 2
469 #define PHY_STAT_LAN_ON 3
470 #define PHY_STAT_PWRDN 5
473 #define PGA_RETURN_EN BIT(1)
476 #define EEE_CLKDIV_EN 0x8000
477 #define EN_ALDPS 0x0004
478 #define EN_10M_PLLOFF 0x0001
480 /* OCP_EEE_CONFIG1 */
481 #define RG_TXLPI_MSK_HFDUP 0x8000
482 #define RG_MATCLR_EN 0x4000
483 #define EEE_10_CAP 0x2000
484 #define EEE_NWAY_EN 0x1000
485 #define TX_QUIET_EN 0x0200
486 #define RX_QUIET_EN 0x0100
487 #define sd_rise_time_mask 0x0070
488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
489 #define RG_RXLPI_MSK_HFDUP 0x0008
490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
492 /* OCP_EEE_CONFIG2 */
493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN 0x0400
495 #define RG_LDVQUIET_EN 0x0200
496 #define RG_CKRSEL 0x0020
497 #define RG_EEEPRG_EN 0x0010
499 /* OCP_EEE_CONFIG3 */
500 #define fast_snr_mask 0xff80
501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
506 /* bit[15:14] function */
507 #define FUN_ADDR 0x0000
508 #define FUN_DATA 0x4000
509 /* bit[4:0] device addr */
512 #define CTAP_SHORT_EN 0x0040
513 #define EEE10_EN 0x0010
516 #define EN_EEE_CMODE BIT(14)
517 #define EN_EEE_1000 BIT(13)
518 #define EN_EEE_100 BIT(12)
519 #define EN_10M_CLKDIV BIT(11)
520 #define EN_10M_BGOFF 0x0080
523 #define TXDIS_STATE 0x01
524 #define ABD_STATE 0x02
526 /* OCP_PHY_PATCH_STAT */
527 #define PATCH_READY BIT(6)
529 /* OCP_PHY_PATCH_CMD */
530 #define PATCH_REQUEST BIT(4)
533 #define CKADSEL_L 0x0100
534 #define ADC_EN 0x0080
535 #define EN_EMI_L 0x0040
538 #define clk_div_expo(x) (min(x, 5) << 8)
541 #define GREEN_ETH_EN BIT(15)
542 #define R_TUNE_EN BIT(11)
545 #define LPF_AUTO_TUNE 0x8000
548 #define GDAC_IB_UPALL 0x0008
551 #define AMP_DN 0x0200
554 #define RX_DRIVING_MASK 0x6000
557 #define AD_MASK 0xfee0
559 #define PASS_THRU_MASK 0x1
561 enum rtl_register_content {
569 #define RTL8152_MAX_TX 4
570 #define RTL8152_MAX_RX 10
575 #define INTR_LINK 0x0004
577 #define RTL8152_REQT_READ 0xc0
578 #define RTL8152_REQT_WRITE 0x40
579 #define RTL8152_REQ_GET_REGS 0x05
580 #define RTL8152_REQ_SET_REGS 0x05
582 #define BYTE_EN_DWORD 0xff
583 #define BYTE_EN_WORD 0x33
584 #define BYTE_EN_BYTE 0x11
585 #define BYTE_EN_SIX_BYTES 0x3f
586 #define BYTE_EN_START_MASK 0x0f
587 #define BYTE_EN_END_MASK 0xf0
589 #define RTL8153_MAX_PACKET 9216 /* 9K */
590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
593 #define RTL8153_RMS RTL8153_MAX_PACKET
594 #define RTL8152_TX_TIMEOUT (5 * HZ)
595 #define RTL8152_NAPI_WEIGHT 64
596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
597 sizeof(struct rx_desc) + RX_ALIGN)
612 /* Define these values to match your device */
613 #define VENDOR_ID_REALTEK 0x0bda
614 #define VENDOR_ID_MICROSOFT 0x045e
615 #define VENDOR_ID_SAMSUNG 0x04e8
616 #define VENDOR_ID_LENOVO 0x17ef
617 #define VENDOR_ID_LINKSYS 0x13b1
618 #define VENDOR_ID_NVIDIA 0x0955
619 #define VENDOR_ID_TPLINK 0x2357
621 #define MCU_TYPE_PLA 0x0100
622 #define MCU_TYPE_USB 0x0000
624 struct tally_counter {
631 __le32 tx_one_collision;
632 __le32 tx_multi_collision;
642 #define RX_LEN_MASK 0x7fff
645 #define RD_UDP_CS BIT(23)
646 #define RD_TCP_CS BIT(22)
647 #define RD_IPV6_CS BIT(20)
648 #define RD_IPV4_CS BIT(19)
651 #define IPF BIT(23) /* IP checksum fail */
652 #define UDPF BIT(22) /* UDP checksum fail */
653 #define TCPF BIT(21) /* TCP checksum fail */
654 #define RX_VLAN_TAG BIT(16)
663 #define TX_FS BIT(31) /* First segment of a packet */
664 #define TX_LS BIT(30) /* Final segment of a packet */
665 #define GTSENDV4 BIT(28)
666 #define GTSENDV6 BIT(27)
667 #define GTTCPHO_SHIFT 18
668 #define GTTCPHO_MAX 0x7fU
669 #define TX_LEN_MAX 0x3ffffU
672 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
673 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
674 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
675 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
677 #define MSS_MAX 0x7ffU
678 #define TCPHO_SHIFT 17
679 #define TCPHO_MAX 0x7ffU
680 #define TX_VLAN_TAG BIT(16)
686 struct list_head list;
688 struct r8152 *context;
694 struct list_head list;
696 struct r8152 *context;
705 struct usb_device *udev;
706 struct napi_struct napi;
707 struct usb_interface *intf;
708 struct net_device *netdev;
709 struct urb *intr_urb;
710 struct tx_agg tx_info[RTL8152_MAX_TX];
711 struct rx_agg rx_info[RTL8152_MAX_RX];
712 struct list_head rx_done, tx_free;
713 struct sk_buff_head tx_queue, rx_queue;
714 spinlock_t rx_lock, tx_lock;
715 struct delayed_work schedule, hw_phy_work;
716 struct mii_if_info mii;
717 struct mutex control; /* use for hw setting */
718 #ifdef CONFIG_PM_SLEEP
719 struct notifier_block pm_notifier;
723 void (*init)(struct r8152 *);
724 int (*enable)(struct r8152 *);
725 void (*disable)(struct r8152 *);
726 void (*up)(struct r8152 *);
727 void (*down)(struct r8152 *);
728 void (*unload)(struct r8152 *);
729 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
730 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
731 bool (*in_nway)(struct r8152 *);
732 void (*hw_phy_cfg)(struct r8152 *);
733 void (*autosuspend_en)(struct r8152 *tp, bool enable);
769 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
770 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
772 static const int multicast_filter_limit = 32;
773 static unsigned int agg_buf_sz = 16384;
775 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
776 VLAN_ETH_HLEN - ETH_FCS_LEN)
779 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
784 tmp = kmalloc(size, GFP_KERNEL);
788 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
789 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
790 value, index, tmp, size, 500);
792 memset(data, 0xff, size);
794 memcpy(data, tmp, size);
802 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
807 tmp = kmemdup(data, size, GFP_KERNEL);
811 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
812 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
813 value, index, tmp, size, 500);
820 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
821 void *data, u16 type)
826 if (test_bit(RTL8152_UNPLUG, &tp->flags))
829 /* both size and indix must be 4 bytes align */
830 if ((size & 3) || !size || (index & 3) || !data)
833 if ((u32)index + (u32)size > 0xffff)
838 ret = get_registers(tp, index, type, limit, data);
846 ret = get_registers(tp, index, type, size, data);
858 set_bit(RTL8152_UNPLUG, &tp->flags);
863 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
864 u16 size, void *data, u16 type)
867 u16 byteen_start, byteen_end, byen;
870 if (test_bit(RTL8152_UNPLUG, &tp->flags))
873 /* both size and indix must be 4 bytes align */
874 if ((size & 3) || !size || (index & 3) || !data)
877 if ((u32)index + (u32)size > 0xffff)
880 byteen_start = byteen & BYTE_EN_START_MASK;
881 byteen_end = byteen & BYTE_EN_END_MASK;
883 byen = byteen_start | (byteen_start << 4);
884 ret = set_registers(tp, index, type | byen, 4, data);
897 ret = set_registers(tp, index,
898 type | BYTE_EN_DWORD,
907 ret = set_registers(tp, index,
908 type | BYTE_EN_DWORD,
920 byen = byteen_end | (byteen_end >> 4);
921 ret = set_registers(tp, index, type | byen, 4, data);
928 set_bit(RTL8152_UNPLUG, &tp->flags);
934 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
936 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
940 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
942 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
946 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
948 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
951 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
955 generic_ocp_read(tp, index, sizeof(data), &data, type);
957 return __le32_to_cpu(data);
960 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
962 __le32 tmp = __cpu_to_le32(data);
964 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
967 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
971 u16 byen = BYTE_EN_WORD;
972 u8 shift = index & 2;
977 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
979 data = __le32_to_cpu(tmp);
980 data >>= (shift * 8);
986 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
990 u16 byen = BYTE_EN_WORD;
991 u8 shift = index & 2;
997 mask <<= (shift * 8);
998 data <<= (shift * 8);
1002 tmp = __cpu_to_le32(data);
1004 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1007 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1011 u8 shift = index & 3;
1015 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1017 data = __le32_to_cpu(tmp);
1018 data >>= (shift * 8);
1024 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1028 u16 byen = BYTE_EN_BYTE;
1029 u8 shift = index & 3;
1035 mask <<= (shift * 8);
1036 data <<= (shift * 8);
1040 tmp = __cpu_to_le32(data);
1042 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1045 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1047 u16 ocp_base, ocp_index;
1049 ocp_base = addr & 0xf000;
1050 if (ocp_base != tp->ocp_base) {
1051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1052 tp->ocp_base = ocp_base;
1055 ocp_index = (addr & 0x0fff) | 0xb000;
1056 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1059 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1061 u16 ocp_base, ocp_index;
1063 ocp_base = addr & 0xf000;
1064 if (ocp_base != tp->ocp_base) {
1065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1066 tp->ocp_base = ocp_base;
1069 ocp_index = (addr & 0x0fff) | 0xb000;
1070 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1073 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1075 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1078 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1080 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1083 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1085 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1086 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1089 static u16 sram_read(struct r8152 *tp, u16 addr)
1091 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1092 return ocp_reg_read(tp, OCP_SRAM_DATA);
1095 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1097 struct r8152 *tp = netdev_priv(netdev);
1100 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1103 if (phy_id != R8152_PHY_ID)
1106 ret = r8152_mdio_read(tp, reg);
1112 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1114 struct r8152 *tp = netdev_priv(netdev);
1116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1119 if (phy_id != R8152_PHY_ID)
1122 r8152_mdio_write(tp, reg, val);
1126 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1128 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1130 struct r8152 *tp = netdev_priv(netdev);
1131 struct sockaddr *addr = p;
1132 int ret = -EADDRNOTAVAIL;
1134 if (!is_valid_ether_addr(addr->sa_data))
1137 ret = usb_autopm_get_interface(tp->intf);
1141 mutex_lock(&tp->control);
1143 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1146 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1149 mutex_unlock(&tp->control);
1151 usb_autopm_put_interface(tp->intf);
1156 /* Devices containing RTL8153-AD can support a persistent
1157 * host system provided MAC address.
1158 * Examples of this are Dell TB15 and Dell WD15 docks
1160 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1163 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1164 union acpi_object *obj;
1167 unsigned char buf[6];
1169 /* test for -AD variant of RTL8153 */
1170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1171 if ((ocp_data & AD_MASK) != 0x1000)
1174 /* test for MAC address pass-through bit */
1175 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1176 if ((ocp_data & PASS_THRU_MASK) != 1)
1179 /* returns _AUXMAC_#AABBCCDDEEFF# */
1180 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1181 obj = (union acpi_object *)buffer.pointer;
1182 if (!ACPI_SUCCESS(status))
1184 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1185 netif_warn(tp, probe, tp->netdev,
1186 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1187 obj->type, obj->string.length);
1190 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1191 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1192 netif_warn(tp, probe, tp->netdev,
1193 "Invalid header when reading pass-thru MAC addr\n");
1196 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1197 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1198 netif_warn(tp, probe, tp->netdev,
1199 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1204 memcpy(sa->sa_data, buf, 6);
1205 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1206 netif_info(tp, probe, tp->netdev,
1207 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1214 static int set_ethernet_addr(struct r8152 *tp)
1216 struct net_device *dev = tp->netdev;
1220 if (tp->version == RTL_VER_01) {
1221 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1223 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1224 * or system doesn't provide valid _SB.AMAC this will be
1225 * be expected to non-zero
1227 ret = vendor_mac_passthru_addr_read(tp, &sa);
1229 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1233 netif_err(tp, probe, dev, "Get ether addr fail\n");
1234 } else if (!is_valid_ether_addr(sa.sa_data)) {
1235 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1237 eth_hw_addr_random(dev);
1238 ether_addr_copy(sa.sa_data, dev->dev_addr);
1239 ret = rtl8152_set_mac_address(dev, &sa);
1240 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1243 if (tp->version == RTL_VER_01)
1244 ether_addr_copy(dev->dev_addr, sa.sa_data);
1246 ret = rtl8152_set_mac_address(dev, &sa);
1252 static void read_bulk_callback(struct urb *urb)
1254 struct net_device *netdev;
1255 int status = urb->status;
1258 unsigned long flags;
1268 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1271 if (!test_bit(WORK_ENABLE, &tp->flags))
1274 netdev = tp->netdev;
1276 /* When link down, the driver would cancel all bulks. */
1277 /* This avoid the re-submitting bulk */
1278 if (!netif_carrier_ok(netdev))
1281 usb_mark_last_busy(tp->udev);
1285 if (urb->actual_length < ETH_ZLEN)
1288 spin_lock_irqsave(&tp->rx_lock, flags);
1289 list_add_tail(&agg->list, &tp->rx_done);
1290 spin_unlock_irqrestore(&tp->rx_lock, flags);
1291 napi_schedule(&tp->napi);
1294 set_bit(RTL8152_UNPLUG, &tp->flags);
1295 netif_device_detach(tp->netdev);
1298 return; /* the urb is in unlink state */
1300 if (net_ratelimit())
1301 netdev_warn(netdev, "maybe reset is needed?\n");
1304 if (net_ratelimit())
1305 netdev_warn(netdev, "Rx status %d\n", status);
1309 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1312 static void write_bulk_callback(struct urb *urb)
1314 struct net_device_stats *stats;
1315 struct net_device *netdev;
1318 unsigned long flags;
1319 int status = urb->status;
1329 netdev = tp->netdev;
1330 stats = &netdev->stats;
1332 if (net_ratelimit())
1333 netdev_warn(netdev, "Tx status %d\n", status);
1334 stats->tx_errors += agg->skb_num;
1336 stats->tx_packets += agg->skb_num;
1337 stats->tx_bytes += agg->skb_len;
1340 spin_lock_irqsave(&tp->tx_lock, flags);
1341 list_add_tail(&agg->list, &tp->tx_free);
1342 spin_unlock_irqrestore(&tp->tx_lock, flags);
1344 usb_autopm_put_interface_async(tp->intf);
1346 if (!netif_carrier_ok(netdev))
1349 if (!test_bit(WORK_ENABLE, &tp->flags))
1352 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1355 if (!skb_queue_empty(&tp->tx_queue))
1356 napi_schedule(&tp->napi);
1359 static void intr_callback(struct urb *urb)
1363 int status = urb->status;
1370 if (!test_bit(WORK_ENABLE, &tp->flags))
1373 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1377 case 0: /* success */
1379 case -ECONNRESET: /* unlink */
1381 netif_device_detach(tp->netdev);
1385 netif_info(tp, intr, tp->netdev,
1386 "Stop submitting intr, status %d\n", status);
1389 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1391 /* -EPIPE: should clear the halt */
1393 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1397 d = urb->transfer_buffer;
1398 if (INTR_LINK & __le16_to_cpu(d[0])) {
1399 if (!netif_carrier_ok(tp->netdev)) {
1400 set_bit(RTL8152_LINK_CHG, &tp->flags);
1401 schedule_delayed_work(&tp->schedule, 0);
1404 if (netif_carrier_ok(tp->netdev)) {
1405 netif_stop_queue(tp->netdev);
1406 set_bit(RTL8152_LINK_CHG, &tp->flags);
1407 schedule_delayed_work(&tp->schedule, 0);
1412 res = usb_submit_urb(urb, GFP_ATOMIC);
1413 if (res == -ENODEV) {
1414 set_bit(RTL8152_UNPLUG, &tp->flags);
1415 netif_device_detach(tp->netdev);
1417 netif_err(tp, intr, tp->netdev,
1418 "can't resubmit intr, status %d\n", res);
1422 static inline void *rx_agg_align(void *data)
1424 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1427 static inline void *tx_agg_align(void *data)
1429 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1432 static void free_all_mem(struct r8152 *tp)
1436 for (i = 0; i < RTL8152_MAX_RX; i++) {
1437 usb_free_urb(tp->rx_info[i].urb);
1438 tp->rx_info[i].urb = NULL;
1440 kfree(tp->rx_info[i].buffer);
1441 tp->rx_info[i].buffer = NULL;
1442 tp->rx_info[i].head = NULL;
1445 for (i = 0; i < RTL8152_MAX_TX; i++) {
1446 usb_free_urb(tp->tx_info[i].urb);
1447 tp->tx_info[i].urb = NULL;
1449 kfree(tp->tx_info[i].buffer);
1450 tp->tx_info[i].buffer = NULL;
1451 tp->tx_info[i].head = NULL;
1454 usb_free_urb(tp->intr_urb);
1455 tp->intr_urb = NULL;
1457 kfree(tp->intr_buff);
1458 tp->intr_buff = NULL;
1461 static int alloc_all_mem(struct r8152 *tp)
1463 struct net_device *netdev = tp->netdev;
1464 struct usb_interface *intf = tp->intf;
1465 struct usb_host_interface *alt = intf->cur_altsetting;
1466 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1471 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1473 spin_lock_init(&tp->rx_lock);
1474 spin_lock_init(&tp->tx_lock);
1475 INIT_LIST_HEAD(&tp->tx_free);
1476 INIT_LIST_HEAD(&tp->rx_done);
1477 skb_queue_head_init(&tp->tx_queue);
1478 skb_queue_head_init(&tp->rx_queue);
1480 for (i = 0; i < RTL8152_MAX_RX; i++) {
1481 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1485 if (buf != rx_agg_align(buf)) {
1487 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1493 urb = usb_alloc_urb(0, GFP_KERNEL);
1499 INIT_LIST_HEAD(&tp->rx_info[i].list);
1500 tp->rx_info[i].context = tp;
1501 tp->rx_info[i].urb = urb;
1502 tp->rx_info[i].buffer = buf;
1503 tp->rx_info[i].head = rx_agg_align(buf);
1506 for (i = 0; i < RTL8152_MAX_TX; i++) {
1507 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1511 if (buf != tx_agg_align(buf)) {
1513 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1519 urb = usb_alloc_urb(0, GFP_KERNEL);
1525 INIT_LIST_HEAD(&tp->tx_info[i].list);
1526 tp->tx_info[i].context = tp;
1527 tp->tx_info[i].urb = urb;
1528 tp->tx_info[i].buffer = buf;
1529 tp->tx_info[i].head = tx_agg_align(buf);
1531 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1534 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1538 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1542 tp->intr_interval = (int)ep_intr->desc.bInterval;
1543 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1544 tp->intr_buff, INTBUFSIZE, intr_callback,
1545 tp, tp->intr_interval);
1554 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1556 struct tx_agg *agg = NULL;
1557 unsigned long flags;
1559 if (list_empty(&tp->tx_free))
1562 spin_lock_irqsave(&tp->tx_lock, flags);
1563 if (!list_empty(&tp->tx_free)) {
1564 struct list_head *cursor;
1566 cursor = tp->tx_free.next;
1567 list_del_init(cursor);
1568 agg = list_entry(cursor, struct tx_agg, list);
1570 spin_unlock_irqrestore(&tp->tx_lock, flags);
1575 /* r8152_csum_workaround()
1576 * The hw limites the value the transport offset. When the offset is out of the
1577 * range, calculate the checksum by sw.
1579 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1580 struct sk_buff_head *list)
1582 if (skb_shinfo(skb)->gso_size) {
1583 netdev_features_t features = tp->netdev->features;
1584 struct sk_buff_head seg_list;
1585 struct sk_buff *segs, *nskb;
1587 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1588 segs = skb_gso_segment(skb, features);
1589 if (IS_ERR(segs) || !segs)
1592 __skb_queue_head_init(&seg_list);
1598 __skb_queue_tail(&seg_list, nskb);
1601 skb_queue_splice(&seg_list, list);
1603 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1604 if (skb_checksum_help(skb) < 0)
1607 __skb_queue_head(list, skb);
1609 struct net_device_stats *stats;
1612 stats = &tp->netdev->stats;
1613 stats->tx_dropped++;
1618 /* msdn_giant_send_check()
1619 * According to the document of microsoft, the TCP Pseudo Header excludes the
1620 * packet length for IPv6 TCP large packets.
1622 static int msdn_giant_send_check(struct sk_buff *skb)
1624 const struct ipv6hdr *ipv6h;
1628 ret = skb_cow_head(skb, 0);
1632 ipv6h = ipv6_hdr(skb);
1636 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1641 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1643 if (skb_vlan_tag_present(skb)) {
1646 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1647 desc->opts2 |= cpu_to_le32(opts2);
1651 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1653 u32 opts2 = le32_to_cpu(desc->opts2);
1655 if (opts2 & RX_VLAN_TAG)
1656 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1657 swab16(opts2 & 0xffff));
1660 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1661 struct sk_buff *skb, u32 len, u32 transport_offset)
1663 u32 mss = skb_shinfo(skb)->gso_size;
1664 u32 opts1, opts2 = 0;
1665 int ret = TX_CSUM_SUCCESS;
1667 WARN_ON_ONCE(len > TX_LEN_MAX);
1669 opts1 = len | TX_FS | TX_LS;
1672 if (transport_offset > GTTCPHO_MAX) {
1673 netif_warn(tp, tx_err, tp->netdev,
1674 "Invalid transport offset 0x%x for TSO\n",
1680 switch (vlan_get_protocol(skb)) {
1681 case htons(ETH_P_IP):
1685 case htons(ETH_P_IPV6):
1686 if (msdn_giant_send_check(skb)) {
1698 opts1 |= transport_offset << GTTCPHO_SHIFT;
1699 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1700 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1703 if (transport_offset > TCPHO_MAX) {
1704 netif_warn(tp, tx_err, tp->netdev,
1705 "Invalid transport offset 0x%x\n",
1711 switch (vlan_get_protocol(skb)) {
1712 case htons(ETH_P_IP):
1714 ip_protocol = ip_hdr(skb)->protocol;
1717 case htons(ETH_P_IPV6):
1719 ip_protocol = ipv6_hdr(skb)->nexthdr;
1723 ip_protocol = IPPROTO_RAW;
1727 if (ip_protocol == IPPROTO_TCP)
1729 else if (ip_protocol == IPPROTO_UDP)
1734 opts2 |= transport_offset << TCPHO_SHIFT;
1737 desc->opts2 = cpu_to_le32(opts2);
1738 desc->opts1 = cpu_to_le32(opts1);
1744 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1746 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1750 __skb_queue_head_init(&skb_head);
1751 spin_lock(&tx_queue->lock);
1752 skb_queue_splice_init(tx_queue, &skb_head);
1753 spin_unlock(&tx_queue->lock);
1755 tx_data = agg->head;
1758 remain = agg_buf_sz;
1760 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1761 struct tx_desc *tx_desc;
1762 struct sk_buff *skb;
1766 skb = __skb_dequeue(&skb_head);
1770 len = skb->len + sizeof(*tx_desc);
1773 __skb_queue_head(&skb_head, skb);
1777 tx_data = tx_agg_align(tx_data);
1778 tx_desc = (struct tx_desc *)tx_data;
1780 offset = (u32)skb_transport_offset(skb);
1782 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1783 r8152_csum_workaround(tp, skb, &skb_head);
1787 rtl_tx_vlan_tag(tx_desc, skb);
1789 tx_data += sizeof(*tx_desc);
1792 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1793 struct net_device_stats *stats = &tp->netdev->stats;
1795 stats->tx_dropped++;
1796 dev_kfree_skb_any(skb);
1797 tx_data -= sizeof(*tx_desc);
1802 agg->skb_len += len;
1803 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1805 dev_kfree_skb_any(skb);
1807 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1809 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1813 if (!skb_queue_empty(&skb_head)) {
1814 spin_lock(&tx_queue->lock);
1815 skb_queue_splice(&skb_head, tx_queue);
1816 spin_unlock(&tx_queue->lock);
1819 netif_tx_lock(tp->netdev);
1821 if (netif_queue_stopped(tp->netdev) &&
1822 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1823 netif_wake_queue(tp->netdev);
1825 netif_tx_unlock(tp->netdev);
1827 ret = usb_autopm_get_interface_async(tp->intf);
1831 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1832 agg->head, (int)(tx_data - (u8 *)agg->head),
1833 (usb_complete_t)write_bulk_callback, agg);
1835 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1837 usb_autopm_put_interface_async(tp->intf);
1843 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1845 u8 checksum = CHECKSUM_NONE;
1848 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1851 opts2 = le32_to_cpu(rx_desc->opts2);
1852 opts3 = le32_to_cpu(rx_desc->opts3);
1854 if (opts2 & RD_IPV4_CS) {
1856 checksum = CHECKSUM_NONE;
1857 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1858 checksum = CHECKSUM_UNNECESSARY;
1859 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1860 checksum = CHECKSUM_UNNECESSARY;
1861 } else if (opts2 & RD_IPV6_CS) {
1862 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1863 checksum = CHECKSUM_UNNECESSARY;
1864 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1865 checksum = CHECKSUM_UNNECESSARY;
1872 static int rx_bottom(struct r8152 *tp, int budget)
1874 unsigned long flags;
1875 struct list_head *cursor, *next, rx_queue;
1876 int ret = 0, work_done = 0;
1877 struct napi_struct *napi = &tp->napi;
1879 if (!skb_queue_empty(&tp->rx_queue)) {
1880 while (work_done < budget) {
1881 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1882 struct net_device *netdev = tp->netdev;
1883 struct net_device_stats *stats = &netdev->stats;
1884 unsigned int pkt_len;
1890 napi_gro_receive(napi, skb);
1892 stats->rx_packets++;
1893 stats->rx_bytes += pkt_len;
1897 if (list_empty(&tp->rx_done))
1900 INIT_LIST_HEAD(&rx_queue);
1901 spin_lock_irqsave(&tp->rx_lock, flags);
1902 list_splice_init(&tp->rx_done, &rx_queue);
1903 spin_unlock_irqrestore(&tp->rx_lock, flags);
1905 list_for_each_safe(cursor, next, &rx_queue) {
1906 struct rx_desc *rx_desc;
1912 list_del_init(cursor);
1914 agg = list_entry(cursor, struct rx_agg, list);
1916 if (urb->actual_length < ETH_ZLEN)
1919 rx_desc = agg->head;
1920 rx_data = agg->head;
1921 len_used += sizeof(struct rx_desc);
1923 while (urb->actual_length > len_used) {
1924 struct net_device *netdev = tp->netdev;
1925 struct net_device_stats *stats = &netdev->stats;
1926 unsigned int pkt_len;
1927 struct sk_buff *skb;
1929 /* limite the skb numbers for rx_queue */
1930 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1933 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1934 if (pkt_len < ETH_ZLEN)
1937 len_used += pkt_len;
1938 if (urb->actual_length < len_used)
1941 pkt_len -= ETH_FCS_LEN;
1942 rx_data += sizeof(struct rx_desc);
1944 skb = napi_alloc_skb(napi, pkt_len);
1946 stats->rx_dropped++;
1950 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1951 memcpy(skb->data, rx_data, pkt_len);
1952 skb_put(skb, pkt_len);
1953 skb->protocol = eth_type_trans(skb, netdev);
1954 rtl_rx_vlan_tag(rx_desc, skb);
1955 if (work_done < budget) {
1956 napi_gro_receive(napi, skb);
1958 stats->rx_packets++;
1959 stats->rx_bytes += pkt_len;
1961 __skb_queue_tail(&tp->rx_queue, skb);
1965 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1966 rx_desc = (struct rx_desc *)rx_data;
1967 len_used = (int)(rx_data - (u8 *)agg->head);
1968 len_used += sizeof(struct rx_desc);
1973 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1975 urb->actual_length = 0;
1976 list_add_tail(&agg->list, next);
1980 if (!list_empty(&rx_queue)) {
1981 spin_lock_irqsave(&tp->rx_lock, flags);
1982 list_splice_tail(&rx_queue, &tp->rx_done);
1983 spin_unlock_irqrestore(&tp->rx_lock, flags);
1990 static void tx_bottom(struct r8152 *tp)
1997 if (skb_queue_empty(&tp->tx_queue))
2000 agg = r8152_get_tx_agg(tp);
2004 res = r8152_tx_agg_fill(tp, agg);
2006 struct net_device *netdev = tp->netdev;
2008 if (res == -ENODEV) {
2009 set_bit(RTL8152_UNPLUG, &tp->flags);
2010 netif_device_detach(netdev);
2012 struct net_device_stats *stats = &netdev->stats;
2013 unsigned long flags;
2015 netif_warn(tp, tx_err, netdev,
2016 "failed tx_urb %d\n", res);
2017 stats->tx_dropped += agg->skb_num;
2019 spin_lock_irqsave(&tp->tx_lock, flags);
2020 list_add_tail(&agg->list, &tp->tx_free);
2021 spin_unlock_irqrestore(&tp->tx_lock, flags);
2027 static void bottom_half(struct r8152 *tp)
2029 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2032 if (!test_bit(WORK_ENABLE, &tp->flags))
2035 /* When link down, the driver would cancel all bulks. */
2036 /* This avoid the re-submitting bulk */
2037 if (!netif_carrier_ok(tp->netdev))
2040 clear_bit(SCHEDULE_NAPI, &tp->flags);
2045 static int r8152_poll(struct napi_struct *napi, int budget)
2047 struct r8152 *tp = container_of(napi, struct r8152, napi);
2050 work_done = rx_bottom(tp, budget);
2053 if (work_done < budget) {
2054 if (!napi_complete_done(napi, work_done))
2056 if (!list_empty(&tp->rx_done))
2057 napi_schedule(napi);
2058 else if (!skb_queue_empty(&tp->tx_queue) &&
2059 !list_empty(&tp->tx_free))
2060 napi_schedule(napi);
2068 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2072 /* The rx would be stopped, so skip submitting */
2073 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2074 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2077 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2078 agg->head, agg_buf_sz,
2079 (usb_complete_t)read_bulk_callback, agg);
2081 ret = usb_submit_urb(agg->urb, mem_flags);
2082 if (ret == -ENODEV) {
2083 set_bit(RTL8152_UNPLUG, &tp->flags);
2084 netif_device_detach(tp->netdev);
2086 struct urb *urb = agg->urb;
2087 unsigned long flags;
2089 urb->actual_length = 0;
2090 spin_lock_irqsave(&tp->rx_lock, flags);
2091 list_add_tail(&agg->list, &tp->rx_done);
2092 spin_unlock_irqrestore(&tp->rx_lock, flags);
2094 netif_err(tp, rx_err, tp->netdev,
2095 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2097 napi_schedule(&tp->napi);
2103 static void rtl_drop_queued_tx(struct r8152 *tp)
2105 struct net_device_stats *stats = &tp->netdev->stats;
2106 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2107 struct sk_buff *skb;
2109 if (skb_queue_empty(tx_queue))
2112 __skb_queue_head_init(&skb_head);
2113 spin_lock_bh(&tx_queue->lock);
2114 skb_queue_splice_init(tx_queue, &skb_head);
2115 spin_unlock_bh(&tx_queue->lock);
2117 while ((skb = __skb_dequeue(&skb_head))) {
2119 stats->tx_dropped++;
2123 static void rtl8152_tx_timeout(struct net_device *netdev)
2125 struct r8152 *tp = netdev_priv(netdev);
2127 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2129 usb_queue_reset_device(tp->intf);
2132 static void rtl8152_set_rx_mode(struct net_device *netdev)
2134 struct r8152 *tp = netdev_priv(netdev);
2136 if (netif_carrier_ok(netdev)) {
2137 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2138 schedule_delayed_work(&tp->schedule, 0);
2142 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2144 struct r8152 *tp = netdev_priv(netdev);
2145 u32 mc_filter[2]; /* Multicast hash filter */
2149 netif_stop_queue(netdev);
2150 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2151 ocp_data &= ~RCR_ACPT_ALL;
2152 ocp_data |= RCR_AB | RCR_APM;
2154 if (netdev->flags & IFF_PROMISC) {
2155 /* Unconditionally log net taps. */
2156 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2157 ocp_data |= RCR_AM | RCR_AAP;
2158 mc_filter[1] = 0xffffffff;
2159 mc_filter[0] = 0xffffffff;
2160 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2161 (netdev->flags & IFF_ALLMULTI)) {
2162 /* Too many to filter perfectly -- accept all multicasts. */
2164 mc_filter[1] = 0xffffffff;
2165 mc_filter[0] = 0xffffffff;
2167 struct netdev_hw_addr *ha;
2171 netdev_for_each_mc_addr(ha, netdev) {
2172 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2174 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2179 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2180 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2182 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2183 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2184 netif_wake_queue(netdev);
2187 static netdev_features_t
2188 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2189 netdev_features_t features)
2191 u32 mss = skb_shinfo(skb)->gso_size;
2192 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2193 int offset = skb_transport_offset(skb);
2195 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2196 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2197 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2198 features &= ~NETIF_F_GSO_MASK;
2203 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2204 struct net_device *netdev)
2206 struct r8152 *tp = netdev_priv(netdev);
2208 skb_tx_timestamp(skb);
2210 skb_queue_tail(&tp->tx_queue, skb);
2212 if (!list_empty(&tp->tx_free)) {
2213 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2214 set_bit(SCHEDULE_NAPI, &tp->flags);
2215 schedule_delayed_work(&tp->schedule, 0);
2217 usb_mark_last_busy(tp->udev);
2218 napi_schedule(&tp->napi);
2220 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2221 netif_stop_queue(netdev);
2224 return NETDEV_TX_OK;
2227 static void r8152b_reset_packet_filter(struct r8152 *tp)
2231 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2232 ocp_data &= ~FMC_FCR_MCU_EN;
2233 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2234 ocp_data |= FMC_FCR_MCU_EN;
2235 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2238 static void rtl8152_nic_reset(struct r8152 *tp)
2242 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2244 for (i = 0; i < 1000; i++) {
2245 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2247 usleep_range(100, 400);
2251 static void set_tx_qlen(struct r8152 *tp)
2253 struct net_device *netdev = tp->netdev;
2255 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2256 sizeof(struct tx_desc));
2259 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2261 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2264 static void rtl_set_eee_plus(struct r8152 *tp)
2269 speed = rtl8152_get_speed(tp);
2270 if (speed & _10bps) {
2271 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2272 ocp_data |= EEEP_CR_EEEP_TX;
2273 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2275 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2276 ocp_data &= ~EEEP_CR_EEEP_TX;
2277 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2281 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2285 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2287 ocp_data |= RXDY_GATED_EN;
2289 ocp_data &= ~RXDY_GATED_EN;
2290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2293 static int rtl_start_rx(struct r8152 *tp)
2297 INIT_LIST_HEAD(&tp->rx_done);
2298 for (i = 0; i < RTL8152_MAX_RX; i++) {
2299 INIT_LIST_HEAD(&tp->rx_info[i].list);
2300 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2305 if (ret && ++i < RTL8152_MAX_RX) {
2306 struct list_head rx_queue;
2307 unsigned long flags;
2309 INIT_LIST_HEAD(&rx_queue);
2312 struct rx_agg *agg = &tp->rx_info[i++];
2313 struct urb *urb = agg->urb;
2315 urb->actual_length = 0;
2316 list_add_tail(&agg->list, &rx_queue);
2317 } while (i < RTL8152_MAX_RX);
2319 spin_lock_irqsave(&tp->rx_lock, flags);
2320 list_splice_tail(&rx_queue, &tp->rx_done);
2321 spin_unlock_irqrestore(&tp->rx_lock, flags);
2327 static int rtl_stop_rx(struct r8152 *tp)
2331 for (i = 0; i < RTL8152_MAX_RX; i++)
2332 usb_kill_urb(tp->rx_info[i].urb);
2334 while (!skb_queue_empty(&tp->rx_queue))
2335 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2340 static int rtl_enable(struct r8152 *tp)
2344 r8152b_reset_packet_filter(tp);
2346 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2347 ocp_data |= CR_RE | CR_TE;
2348 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2350 rxdy_gated_en(tp, false);
2355 static int rtl8152_enable(struct r8152 *tp)
2357 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2361 rtl_set_eee_plus(tp);
2363 return rtl_enable(tp);
2366 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2368 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2369 OWN_UPDATE | OWN_CLEAR);
2372 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2374 u32 ocp_data = tp->coalesce / 8;
2376 switch (tp->version) {
2381 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2387 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2388 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2390 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2392 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2394 r8153b_rx_agg_chg_indicate(tp);
2402 static void r8153_set_rx_early_size(struct r8152 *tp)
2404 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2406 switch (tp->version) {
2411 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2416 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2418 r8153b_rx_agg_chg_indicate(tp);
2426 static int rtl8153_enable(struct r8152 *tp)
2428 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2432 rtl_set_eee_plus(tp);
2433 r8153_set_rx_early_timeout(tp);
2434 r8153_set_rx_early_size(tp);
2436 return rtl_enable(tp);
2439 static void rtl_disable(struct r8152 *tp)
2444 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2445 rtl_drop_queued_tx(tp);
2449 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2450 ocp_data &= ~RCR_ACPT_ALL;
2451 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2453 rtl_drop_queued_tx(tp);
2455 for (i = 0; i < RTL8152_MAX_TX; i++)
2456 usb_kill_urb(tp->tx_info[i].urb);
2458 rxdy_gated_en(tp, true);
2460 for (i = 0; i < 1000; i++) {
2461 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2462 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2464 usleep_range(1000, 2000);
2467 for (i = 0; i < 1000; i++) {
2468 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2470 usleep_range(1000, 2000);
2475 rtl8152_nic_reset(tp);
2478 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2482 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2484 ocp_data |= POWER_CUT;
2486 ocp_data &= ~POWER_CUT;
2487 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2489 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2490 ocp_data &= ~RESUME_INDICATE;
2491 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2494 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2498 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2500 ocp_data |= CPCR_RX_VLAN;
2502 ocp_data &= ~CPCR_RX_VLAN;
2503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2506 static int rtl8152_set_features(struct net_device *dev,
2507 netdev_features_t features)
2509 netdev_features_t changed = features ^ dev->features;
2510 struct r8152 *tp = netdev_priv(dev);
2513 ret = usb_autopm_get_interface(tp->intf);
2517 mutex_lock(&tp->control);
2519 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2520 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2521 rtl_rx_vlan_en(tp, true);
2523 rtl_rx_vlan_en(tp, false);
2526 mutex_unlock(&tp->control);
2528 usb_autopm_put_interface(tp->intf);
2534 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2536 static u32 __rtl_get_wol(struct r8152 *tp)
2541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2542 if (ocp_data & LINK_ON_WAKE_EN)
2543 wolopts |= WAKE_PHY;
2545 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2546 if (ocp_data & UWF_EN)
2547 wolopts |= WAKE_UCAST;
2548 if (ocp_data & BWF_EN)
2549 wolopts |= WAKE_BCAST;
2550 if (ocp_data & MWF_EN)
2551 wolopts |= WAKE_MCAST;
2553 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2554 if (ocp_data & MAGIC_EN)
2555 wolopts |= WAKE_MAGIC;
2560 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2564 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2566 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2567 ocp_data &= ~LINK_ON_WAKE_EN;
2568 if (wolopts & WAKE_PHY)
2569 ocp_data |= LINK_ON_WAKE_EN;
2570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2572 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2573 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2574 if (wolopts & WAKE_UCAST)
2576 if (wolopts & WAKE_BCAST)
2578 if (wolopts & WAKE_MCAST)
2580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2582 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2584 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2585 ocp_data &= ~MAGIC_EN;
2586 if (wolopts & WAKE_MAGIC)
2587 ocp_data |= MAGIC_EN;
2588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2590 if (wolopts & WAKE_ANY)
2591 device_set_wakeup_enable(&tp->udev->dev, true);
2593 device_set_wakeup_enable(&tp->udev->dev, false);
2596 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2601 memset(u1u2, 0xff, sizeof(u1u2));
2603 memset(u1u2, 0x00, sizeof(u1u2));
2605 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2608 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2612 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2614 ocp_data |= LPM_U1U2_EN;
2616 ocp_data &= ~LPM_U1U2_EN;
2618 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2621 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2625 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2627 ocp_data |= U2P3_ENABLE;
2629 ocp_data &= ~U2P3_ENABLE;
2630 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2633 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2637 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2640 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2643 static void r8153b_green_en(struct r8152 *tp, bool enable)
2648 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2649 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2650 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2652 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2653 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2654 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2657 data = sram_read(tp, SRAM_GREEN_CFG);
2658 data |= GREEN_ETH_EN;
2659 sram_write(tp, SRAM_GREEN_CFG, data);
2661 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2664 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2669 for (i = 0; i < 500; i++) {
2670 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2671 data &= PHY_STAT_MASK;
2673 if (data == desired)
2675 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2676 data == PHY_STAT_EXT_INIT) {
2681 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2688 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2690 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2693 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2694 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2696 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2698 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2702 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2703 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2705 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2706 ocp_data &= ~BIT(0);
2707 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2709 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2710 ocp_data &= ~PCUT_STATUS;
2711 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2713 data = r8153_phy_status(tp, 0);
2716 case PHY_STAT_PWRDN:
2717 case PHY_STAT_EXT_INIT:
2719 test_bit(GREEN_ETHERNET, &tp->flags));
2721 data = r8152_mdio_read(tp, MII_BMCR);
2722 data &= ~BMCR_PDOWN;
2724 r8152_mdio_write(tp, MII_BMCR, data);
2726 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2730 if (data != PHY_STAT_LAN_ON)
2731 netif_warn(tp, link, tp->netdev,
2738 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2742 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2744 ocp_data |= PWR_EN | PHASE2_EN;
2746 ocp_data &= ~(PWR_EN | PHASE2_EN);
2747 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2749 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2750 ocp_data &= ~PCUT_STATUS;
2751 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2754 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2758 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2760 ocp_data |= PWR_EN | PHASE2_EN;
2762 ocp_data &= ~PWR_EN;
2763 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2765 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2766 ocp_data &= ~PCUT_STATUS;
2767 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2770 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2774 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2778 ocp_data &= ~BIT(0);
2779 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2781 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2782 ocp_data &= ~BIT(0);
2783 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2786 static bool rtl_can_wakeup(struct r8152 *tp)
2788 struct usb_device *udev = tp->udev;
2790 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2793 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2798 __rtl_set_wol(tp, WAKE_ANY);
2800 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2802 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2803 ocp_data |= LINK_OFF_WAKE_EN;
2804 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2806 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2810 __rtl_set_wol(tp, tp->saved_wolopts);
2812 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2814 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2815 ocp_data &= ~LINK_OFF_WAKE_EN;
2816 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2818 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2822 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2825 r8153_u1u2en(tp, false);
2826 r8153_u2p3en(tp, false);
2827 rtl_runtime_suspend_enable(tp, true);
2829 rtl_runtime_suspend_enable(tp, false);
2831 switch (tp->version) {
2838 r8153_u2p3en(tp, true);
2842 r8153_u1u2en(tp, true);
2846 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2849 r8153b_queue_wake(tp, true);
2850 r8153b_u1u2en(tp, false);
2851 r8153_u2p3en(tp, false);
2852 rtl_runtime_suspend_enable(tp, true);
2853 r8153b_ups_en(tp, true);
2855 r8153b_ups_en(tp, false);
2856 r8153b_queue_wake(tp, false);
2857 rtl_runtime_suspend_enable(tp, false);
2858 r8153_u2p3en(tp, true);
2859 r8153b_u1u2en(tp, true);
2863 static void r8153_teredo_off(struct r8152 *tp)
2867 switch (tp->version) {
2875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2876 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2878 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2883 /* The bit 0 ~ 7 are relative with teredo settings. They are
2884 * W1C (write 1 to clear), so set all 1 to disable it.
2886 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2894 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2895 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2898 static void rtl_reset_bmu(struct r8152 *tp)
2902 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2903 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2904 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2905 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2906 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2909 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2912 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2913 LINKENA | DIS_SDSAVE);
2915 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2921 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2923 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2924 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2925 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2928 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2932 r8152_mmd_indirect(tp, dev, reg);
2933 data = ocp_reg_read(tp, OCP_EEE_DATA);
2934 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2939 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2941 r8152_mmd_indirect(tp, dev, reg);
2942 ocp_reg_write(tp, OCP_EEE_DATA, data);
2943 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2946 static void r8152_eee_en(struct r8152 *tp, bool enable)
2948 u16 config1, config2, config3;
2951 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2952 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2953 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2954 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2957 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2958 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2959 config1 |= sd_rise_time(1);
2960 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2961 config3 |= fast_snr(42);
2963 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2964 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2966 config1 |= sd_rise_time(7);
2967 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2968 config3 |= fast_snr(511);
2971 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2972 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2973 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2974 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2977 static void r8152b_enable_eee(struct r8152 *tp)
2979 r8152_eee_en(tp, true);
2980 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2983 static void r8152b_enable_fc(struct r8152 *tp)
2987 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2988 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2989 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2992 static void rtl8152_disable(struct r8152 *tp)
2994 r8152_aldps_en(tp, false);
2996 r8152_aldps_en(tp, true);
2999 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3001 r8152b_enable_eee(tp);
3002 r8152_aldps_en(tp, true);
3003 r8152b_enable_fc(tp);
3005 set_bit(PHY_RESET, &tp->flags);
3008 static void r8152b_exit_oob(struct r8152 *tp)
3013 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3014 ocp_data &= ~RCR_ACPT_ALL;
3015 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3017 rxdy_gated_en(tp, true);
3018 r8153_teredo_off(tp);
3019 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3020 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3022 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3023 ocp_data &= ~NOW_IS_OOB;
3024 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3026 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3027 ocp_data &= ~MCU_BORW_EN;
3028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3030 for (i = 0; i < 1000; i++) {
3031 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3032 if (ocp_data & LINK_LIST_READY)
3034 usleep_range(1000, 2000);
3037 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3038 ocp_data |= RE_INIT_LL;
3039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3041 for (i = 0; i < 1000; i++) {
3042 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3043 if (ocp_data & LINK_LIST_READY)
3045 usleep_range(1000, 2000);
3048 rtl8152_nic_reset(tp);
3050 /* rx share fifo credit full threshold */
3051 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3053 if (tp->udev->speed == USB_SPEED_FULL ||
3054 tp->udev->speed == USB_SPEED_LOW) {
3055 /* rx share fifo credit near full threshold */
3056 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3058 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3061 /* rx share fifo credit near full threshold */
3062 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3064 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3068 /* TX share fifo free credit full threshold */
3069 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3071 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3072 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3073 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3074 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3076 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3078 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3080 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3081 ocp_data |= TCR0_AUTO_FIFO;
3082 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3085 static void r8152b_enter_oob(struct r8152 *tp)
3090 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3091 ocp_data &= ~NOW_IS_OOB;
3092 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3094 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3095 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3096 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3100 for (i = 0; i < 1000; i++) {
3101 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3102 if (ocp_data & LINK_LIST_READY)
3104 usleep_range(1000, 2000);
3107 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3108 ocp_data |= RE_INIT_LL;
3109 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3111 for (i = 0; i < 1000; i++) {
3112 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3113 if (ocp_data & LINK_LIST_READY)
3115 usleep_range(1000, 2000);
3118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3120 rtl_rx_vlan_en(tp, true);
3122 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3123 ocp_data |= ALDPS_PROXY_MODE;
3124 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3126 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3127 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3128 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3130 rxdy_gated_en(tp, false);
3132 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3133 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3134 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3137 static int r8153_patch_request(struct r8152 *tp, bool request)
3142 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3144 data |= PATCH_REQUEST;
3146 data &= ~PATCH_REQUEST;
3147 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3149 for (i = 0; request && i < 5000; i++) {
3150 usleep_range(1000, 2000);
3151 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3155 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3156 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3157 r8153_patch_request(tp, false);
3164 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3168 data = ocp_reg_read(tp, OCP_POWER_CFG);
3171 ocp_reg_write(tp, OCP_POWER_CFG, data);
3176 ocp_reg_write(tp, OCP_POWER_CFG, data);
3177 for (i = 0; i < 20; i++) {
3178 usleep_range(1000, 2000);
3179 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3185 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3187 r8153_aldps_en(tp, enable);
3190 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3192 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3195 static void r8153_eee_en(struct r8152 *tp, bool enable)
3200 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3201 config = ocp_reg_read(tp, OCP_EEE_CFG);
3204 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3207 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3208 config &= ~EEE10_EN;
3211 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3212 ocp_reg_write(tp, OCP_EEE_CFG, config);
3215 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3217 r8153_eee_en(tp, enable);
3220 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3222 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3225 static void r8153b_enable_fc(struct r8152 *tp)
3227 r8152b_enable_fc(tp);
3228 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3231 static void r8153_hw_phy_cfg(struct r8152 *tp)
3236 /* disable ALDPS before updating the PHY parameters */
3237 r8153_aldps_en(tp, false);
3239 /* disable EEE before updating the PHY parameters */
3240 r8153_eee_en(tp, false);
3241 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3243 if (tp->version == RTL_VER_03) {
3244 data = ocp_reg_read(tp, OCP_EEE_CFG);
3245 data &= ~CTAP_SHORT_EN;
3246 ocp_reg_write(tp, OCP_EEE_CFG, data);
3249 data = ocp_reg_read(tp, OCP_POWER_CFG);
3250 data |= EEE_CLKDIV_EN;
3251 ocp_reg_write(tp, OCP_POWER_CFG, data);
3253 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3254 data |= EN_10M_BGOFF;
3255 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3256 data = ocp_reg_read(tp, OCP_POWER_CFG);
3257 data |= EN_10M_PLLOFF;
3258 ocp_reg_write(tp, OCP_POWER_CFG, data);
3259 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3261 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3262 ocp_data |= PFM_PWM_SWITCH;
3263 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3265 /* Enable LPF corner auto tune */
3266 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3268 /* Adjust 10M Amplitude */
3269 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3270 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3272 r8153_eee_en(tp, true);
3273 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3275 r8153_aldps_en(tp, true);
3276 r8152b_enable_fc(tp);
3278 switch (tp->version) {
3285 r8153_u2p3en(tp, true);
3289 set_bit(PHY_RESET, &tp->flags);
3292 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3296 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3297 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3298 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3299 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3304 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3306 u32 ocp_data, ups_flags = 0;
3309 /* disable ALDPS before updating the PHY parameters */
3310 r8153b_aldps_en(tp, false);
3312 /* disable EEE before updating the PHY parameters */
3313 r8153b_eee_en(tp, false);
3314 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3316 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3318 data = sram_read(tp, SRAM_GREEN_CFG);
3320 sram_write(tp, SRAM_GREEN_CFG, data);
3321 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3322 data |= PGA_RETURN_EN;
3323 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3325 /* ADC Bias Calibration:
3326 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3327 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3330 ocp_data = r8152_efuse_read(tp, 0x7d);
3331 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3333 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3335 /* ups mode tx-link-pulse timing adjustment:
3336 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3337 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3339 ocp_data = ocp_reg_read(tp, 0xc426);
3342 u32 swr_cnt_1ms_ini;
3344 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3345 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3346 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3347 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3350 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3351 ocp_data |= PFM_PWM_SWITCH;
3352 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3355 if (!r8153_patch_request(tp, true)) {
3356 data = ocp_reg_read(tp, OCP_POWER_CFG);
3357 data |= EEE_CLKDIV_EN;
3358 ocp_reg_write(tp, OCP_POWER_CFG, data);
3360 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3361 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3362 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3364 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3365 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3367 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3368 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3369 UPS_FLAGS_EEE_PLLOFF_GIGA;
3371 r8153_patch_request(tp, false);
3374 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3376 r8153b_eee_en(tp, true);
3377 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3379 r8153b_aldps_en(tp, true);
3380 r8153b_enable_fc(tp);
3381 r8153_u2p3en(tp, true);
3383 set_bit(PHY_RESET, &tp->flags);
3386 static void r8153_first_init(struct r8152 *tp)
3391 rxdy_gated_en(tp, true);
3392 r8153_teredo_off(tp);
3394 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3395 ocp_data &= ~RCR_ACPT_ALL;
3396 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3398 rtl8152_nic_reset(tp);
3401 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3402 ocp_data &= ~NOW_IS_OOB;
3403 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3405 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3406 ocp_data &= ~MCU_BORW_EN;
3407 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3409 for (i = 0; i < 1000; i++) {
3410 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3411 if (ocp_data & LINK_LIST_READY)
3413 usleep_range(1000, 2000);
3416 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3417 ocp_data |= RE_INIT_LL;
3418 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3420 for (i = 0; i < 1000; i++) {
3421 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3422 if (ocp_data & LINK_LIST_READY)
3424 usleep_range(1000, 2000);
3427 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3429 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3430 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3431 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3433 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3434 ocp_data |= TCR0_AUTO_FIFO;
3435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3437 rtl8152_nic_reset(tp);
3439 /* rx share fifo credit full threshold */
3440 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3441 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3442 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3443 /* TX share fifo free credit full threshold */
3444 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3447 static void r8153_enter_oob(struct r8152 *tp)
3452 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3453 ocp_data &= ~NOW_IS_OOB;
3454 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3459 for (i = 0; i < 1000; i++) {
3460 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3461 if (ocp_data & LINK_LIST_READY)
3463 usleep_range(1000, 2000);
3466 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3467 ocp_data |= RE_INIT_LL;
3468 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3470 for (i = 0; i < 1000; i++) {
3471 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3472 if (ocp_data & LINK_LIST_READY)
3474 usleep_range(1000, 2000);
3477 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3478 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3480 switch (tp->version) {
3485 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3486 ocp_data &= ~TEREDO_WAKE_MASK;
3487 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3492 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3493 * type. Set it to zero. bits[7:0] are the W1C bits about
3494 * the events. Set them to all 1 to clear them.
3496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3503 rtl_rx_vlan_en(tp, true);
3505 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3506 ocp_data |= ALDPS_PROXY_MODE;
3507 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3510 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3511 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3513 rxdy_gated_en(tp, false);
3515 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3516 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3517 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3520 static void rtl8153_disable(struct r8152 *tp)
3522 r8153_aldps_en(tp, false);
3525 r8153_aldps_en(tp, true);
3528 static void rtl8153b_disable(struct r8152 *tp)
3530 r8153b_aldps_en(tp, false);
3533 r8153b_aldps_en(tp, true);
3536 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3538 u16 bmcr, anar, gbcr;
3539 enum spd_duplex speed_duplex;
3542 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3543 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3544 ADVERTISE_100HALF | ADVERTISE_100FULL);
3545 if (tp->mii.supports_gmii) {
3546 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3547 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3552 if (autoneg == AUTONEG_DISABLE) {
3553 if (speed == SPEED_10) {
3555 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3556 speed_duplex = FORCE_10M_HALF;
3557 } else if (speed == SPEED_100) {
3558 bmcr = BMCR_SPEED100;
3559 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3560 speed_duplex = FORCE_100M_HALF;
3561 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3562 bmcr = BMCR_SPEED1000;
3563 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3564 speed_duplex = NWAY_1000M_FULL;
3570 if (duplex == DUPLEX_FULL) {
3571 bmcr |= BMCR_FULLDPLX;
3572 if (speed != SPEED_1000)
3576 if (speed == SPEED_10) {
3577 if (duplex == DUPLEX_FULL) {
3578 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3579 speed_duplex = NWAY_10M_FULL;
3581 anar |= ADVERTISE_10HALF;
3582 speed_duplex = NWAY_10M_HALF;
3584 } else if (speed == SPEED_100) {
3585 if (duplex == DUPLEX_FULL) {
3586 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3587 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3588 speed_duplex = NWAY_100M_FULL;
3590 anar |= ADVERTISE_10HALF;
3591 anar |= ADVERTISE_100HALF;
3592 speed_duplex = NWAY_100M_HALF;
3594 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3595 if (duplex == DUPLEX_FULL) {
3596 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3597 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3598 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3600 anar |= ADVERTISE_10HALF;
3601 anar |= ADVERTISE_100HALF;
3602 gbcr |= ADVERTISE_1000HALF;
3604 speed_duplex = NWAY_1000M_FULL;
3610 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3613 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3616 if (tp->mii.supports_gmii)
3617 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3619 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3620 r8152_mdio_write(tp, MII_BMCR, bmcr);
3622 switch (tp->version) {
3625 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3626 UPS_FLAGS_SPEED_MASK);
3633 if (bmcr & BMCR_RESET) {
3636 for (i = 0; i < 50; i++) {
3638 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3647 static void rtl8152_up(struct r8152 *tp)
3649 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3652 r8152_aldps_en(tp, false);
3653 r8152b_exit_oob(tp);
3654 r8152_aldps_en(tp, true);
3657 static void rtl8152_down(struct r8152 *tp)
3659 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3660 rtl_drop_queued_tx(tp);
3664 r8152_power_cut_en(tp, false);
3665 r8152_aldps_en(tp, false);
3666 r8152b_enter_oob(tp);
3667 r8152_aldps_en(tp, true);
3670 static void rtl8153_up(struct r8152 *tp)
3672 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3675 r8153_u1u2en(tp, false);
3676 r8153_u2p3en(tp, false);
3677 r8153_aldps_en(tp, false);
3678 r8153_first_init(tp);
3679 r8153_aldps_en(tp, true);
3681 switch (tp->version) {
3688 r8153_u2p3en(tp, true);
3692 r8153_u1u2en(tp, true);
3695 static void rtl8153_down(struct r8152 *tp)
3697 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3698 rtl_drop_queued_tx(tp);
3702 r8153_u1u2en(tp, false);
3703 r8153_u2p3en(tp, false);
3704 r8153_power_cut_en(tp, false);
3705 r8153_aldps_en(tp, false);
3706 r8153_enter_oob(tp);
3707 r8153_aldps_en(tp, true);
3710 static void rtl8153b_up(struct r8152 *tp)
3712 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3715 r8153b_u1u2en(tp, false);
3716 r8153_u2p3en(tp, false);
3717 r8153b_aldps_en(tp, false);
3719 r8153_first_init(tp);
3720 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3722 r8153b_aldps_en(tp, true);
3723 r8153_u2p3en(tp, true);
3724 r8153b_u1u2en(tp, true);
3727 static void rtl8153b_down(struct r8152 *tp)
3729 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3730 rtl_drop_queued_tx(tp);
3734 r8153b_u1u2en(tp, false);
3735 r8153_u2p3en(tp, false);
3736 r8153b_power_cut_en(tp, false);
3737 r8153b_aldps_en(tp, false);
3738 r8153_enter_oob(tp);
3739 r8153b_aldps_en(tp, true);
3742 static bool rtl8152_in_nway(struct r8152 *tp)
3746 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3747 tp->ocp_base = 0x2000;
3748 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3749 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3751 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3752 if (nway_state & 0xc000)
3758 static bool rtl8153_in_nway(struct r8152 *tp)
3760 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3762 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3768 static void set_carrier(struct r8152 *tp)
3770 struct net_device *netdev = tp->netdev;
3771 struct napi_struct *napi = &tp->napi;
3774 speed = rtl8152_get_speed(tp);
3776 if (speed & LINK_STATUS) {
3777 if (!netif_carrier_ok(netdev)) {
3778 tp->rtl_ops.enable(tp);
3779 netif_stop_queue(netdev);
3781 netif_carrier_on(netdev);
3783 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3784 _rtl8152_set_rx_mode(netdev);
3785 napi_enable(&tp->napi);
3786 netif_wake_queue(netdev);
3787 netif_info(tp, link, netdev, "carrier on\n");
3788 } else if (netif_queue_stopped(netdev) &&
3789 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3790 netif_wake_queue(netdev);
3793 if (netif_carrier_ok(netdev)) {
3794 netif_carrier_off(netdev);
3796 tp->rtl_ops.disable(tp);
3798 netif_info(tp, link, netdev, "carrier off\n");
3803 static void rtl_work_func_t(struct work_struct *work)
3805 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3807 /* If the device is unplugged or !netif_running(), the workqueue
3808 * doesn't need to wake the device, and could return directly.
3810 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3813 if (usb_autopm_get_interface(tp->intf) < 0)
3816 if (!test_bit(WORK_ENABLE, &tp->flags))
3819 if (!mutex_trylock(&tp->control)) {
3820 schedule_delayed_work(&tp->schedule, 0);
3824 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3827 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3828 _rtl8152_set_rx_mode(tp->netdev);
3830 /* don't schedule napi before linking */
3831 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3832 netif_carrier_ok(tp->netdev))
3833 napi_schedule(&tp->napi);
3835 mutex_unlock(&tp->control);
3838 usb_autopm_put_interface(tp->intf);
3841 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3843 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3845 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3848 if (usb_autopm_get_interface(tp->intf) < 0)
3851 mutex_lock(&tp->control);
3853 tp->rtl_ops.hw_phy_cfg(tp);
3855 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3857 mutex_unlock(&tp->control);
3859 usb_autopm_put_interface(tp->intf);
3862 #ifdef CONFIG_PM_SLEEP
3863 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3866 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3869 case PM_HIBERNATION_PREPARE:
3870 case PM_SUSPEND_PREPARE:
3871 usb_autopm_get_interface(tp->intf);
3874 case PM_POST_HIBERNATION:
3875 case PM_POST_SUSPEND:
3876 usb_autopm_put_interface(tp->intf);
3879 case PM_POST_RESTORE:
3880 case PM_RESTORE_PREPARE:
3889 static int rtl8152_open(struct net_device *netdev)
3891 struct r8152 *tp = netdev_priv(netdev);
3894 res = alloc_all_mem(tp);
3898 res = usb_autopm_get_interface(tp->intf);
3902 mutex_lock(&tp->control);
3906 netif_carrier_off(netdev);
3907 netif_start_queue(netdev);
3908 set_bit(WORK_ENABLE, &tp->flags);
3910 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3913 netif_device_detach(tp->netdev);
3914 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3918 napi_enable(&tp->napi);
3920 mutex_unlock(&tp->control);
3922 usb_autopm_put_interface(tp->intf);
3923 #ifdef CONFIG_PM_SLEEP
3924 tp->pm_notifier.notifier_call = rtl_notifier;
3925 register_pm_notifier(&tp->pm_notifier);
3930 mutex_unlock(&tp->control);
3931 usb_autopm_put_interface(tp->intf);
3938 static int rtl8152_close(struct net_device *netdev)
3940 struct r8152 *tp = netdev_priv(netdev);
3943 #ifdef CONFIG_PM_SLEEP
3944 unregister_pm_notifier(&tp->pm_notifier);
3946 if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3947 napi_disable(&tp->napi);
3948 clear_bit(WORK_ENABLE, &tp->flags);
3949 usb_kill_urb(tp->intr_urb);
3950 cancel_delayed_work_sync(&tp->schedule);
3951 netif_stop_queue(netdev);
3953 res = usb_autopm_get_interface(tp->intf);
3954 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3955 rtl_drop_queued_tx(tp);
3958 mutex_lock(&tp->control);
3960 tp->rtl_ops.down(tp);
3962 mutex_unlock(&tp->control);
3966 usb_autopm_put_interface(tp->intf);
3973 static void rtl_tally_reset(struct r8152 *tp)
3977 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3978 ocp_data |= TALLY_RESET;
3979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3982 static void r8152b_init(struct r8152 *tp)
3987 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3990 data = r8152_mdio_read(tp, MII_BMCR);
3991 if (data & BMCR_PDOWN) {
3992 data &= ~BMCR_PDOWN;
3993 r8152_mdio_write(tp, MII_BMCR, data);
3996 r8152_aldps_en(tp, false);
3998 if (tp->version == RTL_VER_01) {
3999 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4000 ocp_data &= ~LED_MODE_MASK;
4001 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4004 r8152_power_cut_en(tp, false);
4006 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4007 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4008 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4009 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4010 ocp_data &= ~MCU_CLK_RATIO_MASK;
4011 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4012 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4013 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4014 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4015 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4017 rtl_tally_reset(tp);
4019 /* enable rx aggregation */
4020 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4021 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4022 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4025 static void r8153_init(struct r8152 *tp)
4031 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4034 r8153_u1u2en(tp, false);
4036 for (i = 0; i < 500; i++) {
4037 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4042 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4046 data = r8153_phy_status(tp, 0);
4048 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4049 tp->version == RTL_VER_05)
4050 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4052 data = r8152_mdio_read(tp, MII_BMCR);
4053 if (data & BMCR_PDOWN) {
4054 data &= ~BMCR_PDOWN;
4055 r8152_mdio_write(tp, MII_BMCR, data);
4058 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4060 r8153_u2p3en(tp, false);
4062 if (tp->version == RTL_VER_04) {
4063 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4064 ocp_data &= ~pwd_dn_scale_mask;
4065 ocp_data |= pwd_dn_scale(96);
4066 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4068 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4069 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4070 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4071 } else if (tp->version == RTL_VER_05) {
4072 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4073 ocp_data &= ~ECM_ALDPS;
4074 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4076 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4077 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4078 ocp_data &= ~DYNAMIC_BURST;
4080 ocp_data |= DYNAMIC_BURST;
4081 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4082 } else if (tp->version == RTL_VER_06) {
4083 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4084 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4085 ocp_data &= ~DYNAMIC_BURST;
4087 ocp_data |= DYNAMIC_BURST;
4088 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4091 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4092 ocp_data |= EP4_FULL_FC;
4093 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4095 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4096 ocp_data &= ~TIMER11_EN;
4097 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4099 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4100 ocp_data &= ~LED_MODE_MASK;
4101 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4103 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4104 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4105 ocp_data |= LPM_TIMER_500MS;
4107 ocp_data |= LPM_TIMER_500US;
4108 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4110 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4111 ocp_data &= ~SEN_VAL_MASK;
4112 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4113 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4115 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4117 /* MAC clock speed down */
4118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
4119 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
4120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
4121 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
4123 r8153_power_cut_en(tp, false);
4124 r8153_u1u2en(tp, true);
4125 usb_enable_lpm(tp->udev);
4127 /* rx aggregation */
4128 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4129 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4130 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4131 ocp_data |= RX_AGG_DISABLE;
4133 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4135 rtl_tally_reset(tp);
4137 switch (tp->udev->speed) {
4138 case USB_SPEED_SUPER:
4139 case USB_SPEED_SUPER_PLUS:
4140 tp->coalesce = COALESCE_SUPER;
4142 case USB_SPEED_HIGH:
4143 tp->coalesce = COALESCE_HIGH;
4146 tp->coalesce = COALESCE_SLOW;
4151 static void r8153b_init(struct r8152 *tp)
4157 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4160 r8153b_u1u2en(tp, false);
4162 for (i = 0; i < 500; i++) {
4163 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4168 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4172 data = r8153_phy_status(tp, 0);
4174 data = r8152_mdio_read(tp, MII_BMCR);
4175 if (data & BMCR_PDOWN) {
4176 data &= ~BMCR_PDOWN;
4177 r8152_mdio_write(tp, MII_BMCR, data);
4180 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4182 r8153_u2p3en(tp, false);
4184 /* MSC timer = 0xfff * 8ms = 32760 ms */
4185 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4187 /* U1/U2/L1 idle timer. 500 us */
4188 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4190 r8153b_power_cut_en(tp, false);
4191 r8153b_ups_en(tp, false);
4192 r8153b_queue_wake(tp, false);
4193 rtl_runtime_suspend_enable(tp, false);
4194 r8153b_u1u2en(tp, true);
4195 usb_enable_lpm(tp->udev);
4197 /* MAC clock speed down */
4198 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4199 ocp_data |= MAC_CLK_SPDWN_EN;
4200 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4202 set_bit(GREEN_ETHERNET, &tp->flags);
4204 /* rx aggregation */
4205 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4206 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4207 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4209 rtl_tally_reset(tp);
4211 tp->coalesce = 15000; /* 15 us */
4214 static int rtl8152_pre_reset(struct usb_interface *intf)
4216 struct r8152 *tp = usb_get_intfdata(intf);
4217 struct net_device *netdev;
4222 netdev = tp->netdev;
4223 if (!netif_running(netdev))
4226 netif_stop_queue(netdev);
4227 napi_disable(&tp->napi);
4228 clear_bit(WORK_ENABLE, &tp->flags);
4229 usb_kill_urb(tp->intr_urb);
4230 cancel_delayed_work_sync(&tp->schedule);
4231 if (netif_carrier_ok(netdev)) {
4232 mutex_lock(&tp->control);
4233 tp->rtl_ops.disable(tp);
4234 mutex_unlock(&tp->control);
4240 static int rtl8152_post_reset(struct usb_interface *intf)
4242 struct r8152 *tp = usb_get_intfdata(intf);
4243 struct net_device *netdev;
4248 netdev = tp->netdev;
4249 if (!netif_running(netdev))
4252 set_bit(WORK_ENABLE, &tp->flags);
4253 if (netif_carrier_ok(netdev)) {
4254 mutex_lock(&tp->control);
4255 tp->rtl_ops.enable(tp);
4257 _rtl8152_set_rx_mode(netdev);
4258 mutex_unlock(&tp->control);
4261 napi_enable(&tp->napi);
4262 netif_wake_queue(netdev);
4263 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4265 if (!list_empty(&tp->rx_done))
4266 napi_schedule(&tp->napi);
4271 static bool delay_autosuspend(struct r8152 *tp)
4273 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4274 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4276 /* This means a linking change occurs and the driver doesn't detect it,
4277 * yet. If the driver has disabled tx/rx and hw is linking on, the
4278 * device wouldn't wake up by receiving any packet.
4280 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4283 /* If the linking down is occurred by nway, the device may miss the
4284 * linking change event. And it wouldn't wake when linking on.
4286 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4288 else if (!skb_queue_empty(&tp->tx_queue))
4294 static int rtl8152_runtime_resume(struct r8152 *tp)
4296 struct net_device *netdev = tp->netdev;
4298 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4299 struct napi_struct *napi = &tp->napi;
4301 tp->rtl_ops.autosuspend_en(tp, false);
4303 set_bit(WORK_ENABLE, &tp->flags);
4305 if (netif_carrier_ok(netdev)) {
4306 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4309 netif_carrier_off(netdev);
4310 tp->rtl_ops.disable(tp);
4311 netif_info(tp, link, netdev, "linking down\n");
4316 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4317 smp_mb__after_atomic();
4319 if (!list_empty(&tp->rx_done))
4320 napi_schedule(&tp->napi);
4322 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4324 if (netdev->flags & IFF_UP)
4325 tp->rtl_ops.autosuspend_en(tp, false);
4327 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4333 static int rtl8152_system_resume(struct r8152 *tp)
4335 struct net_device *netdev = tp->netdev;
4337 netif_device_attach(netdev);
4339 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4341 netif_carrier_off(netdev);
4342 set_bit(WORK_ENABLE, &tp->flags);
4343 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4349 static int rtl8152_runtime_suspend(struct r8152 *tp)
4351 struct net_device *netdev = tp->netdev;
4354 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4355 smp_mb__after_atomic();
4357 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4360 if (netif_carrier_ok(netdev)) {
4363 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4364 ocp_data = rcr & ~RCR_ACPT_ALL;
4365 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4366 rxdy_gated_en(tp, true);
4367 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4369 if (!(ocp_data & RXFIFO_EMPTY)) {
4370 rxdy_gated_en(tp, false);
4371 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4372 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4373 smp_mb__after_atomic();
4379 clear_bit(WORK_ENABLE, &tp->flags);
4380 usb_kill_urb(tp->intr_urb);
4382 tp->rtl_ops.autosuspend_en(tp, true);
4384 if (netif_carrier_ok(netdev)) {
4385 struct napi_struct *napi = &tp->napi;
4389 rxdy_gated_en(tp, false);
4390 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4394 if (delay_autosuspend(tp)) {
4395 rtl8152_runtime_resume(tp);
4404 static int rtl8152_system_suspend(struct r8152 *tp)
4406 struct net_device *netdev = tp->netdev;
4408 netif_device_detach(netdev);
4410 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4411 struct napi_struct *napi = &tp->napi;
4413 clear_bit(WORK_ENABLE, &tp->flags);
4414 usb_kill_urb(tp->intr_urb);
4416 cancel_delayed_work_sync(&tp->schedule);
4417 tp->rtl_ops.down(tp);
4424 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4426 struct r8152 *tp = usb_get_intfdata(intf);
4429 mutex_lock(&tp->control);
4431 if (PMSG_IS_AUTO(message))
4432 ret = rtl8152_runtime_suspend(tp);
4434 ret = rtl8152_system_suspend(tp);
4436 mutex_unlock(&tp->control);
4441 static int rtl8152_resume(struct usb_interface *intf)
4443 struct r8152 *tp = usb_get_intfdata(intf);
4446 mutex_lock(&tp->control);
4448 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4449 ret = rtl8152_runtime_resume(tp);
4451 ret = rtl8152_system_resume(tp);
4453 mutex_unlock(&tp->control);
4458 static int rtl8152_reset_resume(struct usb_interface *intf)
4460 struct r8152 *tp = usb_get_intfdata(intf);
4462 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4463 tp->rtl_ops.init(tp);
4464 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4465 set_ethernet_addr(tp);
4466 return rtl8152_resume(intf);
4469 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4471 struct r8152 *tp = netdev_priv(dev);
4473 if (usb_autopm_get_interface(tp->intf) < 0)
4476 if (!rtl_can_wakeup(tp)) {
4480 mutex_lock(&tp->control);
4481 wol->supported = WAKE_ANY;
4482 wol->wolopts = __rtl_get_wol(tp);
4483 mutex_unlock(&tp->control);
4486 usb_autopm_put_interface(tp->intf);
4489 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4491 struct r8152 *tp = netdev_priv(dev);
4494 if (!rtl_can_wakeup(tp))
4497 if (wol->wolopts & ~WAKE_ANY)
4500 ret = usb_autopm_get_interface(tp->intf);
4504 mutex_lock(&tp->control);
4506 __rtl_set_wol(tp, wol->wolopts);
4507 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4509 mutex_unlock(&tp->control);
4511 usb_autopm_put_interface(tp->intf);
4517 static u32 rtl8152_get_msglevel(struct net_device *dev)
4519 struct r8152 *tp = netdev_priv(dev);
4521 return tp->msg_enable;
4524 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4526 struct r8152 *tp = netdev_priv(dev);
4528 tp->msg_enable = value;
4531 static void rtl8152_get_drvinfo(struct net_device *netdev,
4532 struct ethtool_drvinfo *info)
4534 struct r8152 *tp = netdev_priv(netdev);
4536 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4537 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4538 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4542 int rtl8152_get_link_ksettings(struct net_device *netdev,
4543 struct ethtool_link_ksettings *cmd)
4545 struct r8152 *tp = netdev_priv(netdev);
4548 if (!tp->mii.mdio_read)
4551 ret = usb_autopm_get_interface(tp->intf);
4555 mutex_lock(&tp->control);
4557 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4559 mutex_unlock(&tp->control);
4561 usb_autopm_put_interface(tp->intf);
4567 static int rtl8152_set_link_ksettings(struct net_device *dev,
4568 const struct ethtool_link_ksettings *cmd)
4570 struct r8152 *tp = netdev_priv(dev);
4573 ret = usb_autopm_get_interface(tp->intf);
4577 mutex_lock(&tp->control);
4579 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4582 tp->autoneg = cmd->base.autoneg;
4583 tp->speed = cmd->base.speed;
4584 tp->duplex = cmd->base.duplex;
4587 mutex_unlock(&tp->control);
4589 usb_autopm_put_interface(tp->intf);
4595 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4602 "tx_single_collisions",
4603 "tx_multi_collisions",
4611 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4615 return ARRAY_SIZE(rtl8152_gstrings);
4621 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4622 struct ethtool_stats *stats, u64 *data)
4624 struct r8152 *tp = netdev_priv(dev);
4625 struct tally_counter tally;
4627 if (usb_autopm_get_interface(tp->intf) < 0)
4630 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4632 usb_autopm_put_interface(tp->intf);
4634 data[0] = le64_to_cpu(tally.tx_packets);
4635 data[1] = le64_to_cpu(tally.rx_packets);
4636 data[2] = le64_to_cpu(tally.tx_errors);
4637 data[3] = le32_to_cpu(tally.rx_errors);
4638 data[4] = le16_to_cpu(tally.rx_missed);
4639 data[5] = le16_to_cpu(tally.align_errors);
4640 data[6] = le32_to_cpu(tally.tx_one_collision);
4641 data[7] = le32_to_cpu(tally.tx_multi_collision);
4642 data[8] = le64_to_cpu(tally.rx_unicast);
4643 data[9] = le64_to_cpu(tally.rx_broadcast);
4644 data[10] = le32_to_cpu(tally.rx_multicast);
4645 data[11] = le16_to_cpu(tally.tx_aborted);
4646 data[12] = le16_to_cpu(tally.tx_underrun);
4649 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4651 switch (stringset) {
4653 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
4658 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4660 u32 ocp_data, lp, adv, supported = 0;
4663 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4664 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4666 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4667 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4669 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4670 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4672 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4673 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4675 eee->eee_enabled = !!ocp_data;
4676 eee->eee_active = !!(supported & adv & lp);
4677 eee->supported = supported;
4678 eee->advertised = adv;
4679 eee->lp_advertised = lp;
4684 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4686 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4688 r8152_eee_en(tp, eee->eee_enabled);
4690 if (!eee->eee_enabled)
4693 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4698 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4700 u32 ocp_data, lp, adv, supported = 0;
4703 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4704 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4706 val = ocp_reg_read(tp, OCP_EEE_ADV);
4707 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4709 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4710 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4712 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4713 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4715 eee->eee_enabled = !!ocp_data;
4716 eee->eee_active = !!(supported & adv & lp);
4717 eee->supported = supported;
4718 eee->advertised = adv;
4719 eee->lp_advertised = lp;
4724 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4726 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4728 r8153_eee_en(tp, eee->eee_enabled);
4730 if (!eee->eee_enabled)
4733 ocp_reg_write(tp, OCP_EEE_ADV, val);
4738 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4740 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4742 r8153b_eee_en(tp, eee->eee_enabled);
4744 if (!eee->eee_enabled)
4747 ocp_reg_write(tp, OCP_EEE_ADV, val);
4753 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4755 struct r8152 *tp = netdev_priv(net);
4758 ret = usb_autopm_get_interface(tp->intf);
4762 mutex_lock(&tp->control);
4764 ret = tp->rtl_ops.eee_get(tp, edata);
4766 mutex_unlock(&tp->control);
4768 usb_autopm_put_interface(tp->intf);
4775 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4777 struct r8152 *tp = netdev_priv(net);
4780 ret = usb_autopm_get_interface(tp->intf);
4784 mutex_lock(&tp->control);
4786 ret = tp->rtl_ops.eee_set(tp, edata);
4788 ret = mii_nway_restart(&tp->mii);
4790 mutex_unlock(&tp->control);
4792 usb_autopm_put_interface(tp->intf);
4798 static int rtl8152_nway_reset(struct net_device *dev)
4800 struct r8152 *tp = netdev_priv(dev);
4803 ret = usb_autopm_get_interface(tp->intf);
4807 mutex_lock(&tp->control);
4809 ret = mii_nway_restart(&tp->mii);
4811 mutex_unlock(&tp->control);
4813 usb_autopm_put_interface(tp->intf);
4819 static int rtl8152_get_coalesce(struct net_device *netdev,
4820 struct ethtool_coalesce *coalesce)
4822 struct r8152 *tp = netdev_priv(netdev);
4824 switch (tp->version) {
4833 coalesce->rx_coalesce_usecs = tp->coalesce;
4838 static int rtl8152_set_coalesce(struct net_device *netdev,
4839 struct ethtool_coalesce *coalesce)
4841 struct r8152 *tp = netdev_priv(netdev);
4844 switch (tp->version) {
4853 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4856 ret = usb_autopm_get_interface(tp->intf);
4860 mutex_lock(&tp->control);
4862 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4863 tp->coalesce = coalesce->rx_coalesce_usecs;
4865 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4866 r8153_set_rx_early_timeout(tp);
4869 mutex_unlock(&tp->control);
4871 usb_autopm_put_interface(tp->intf);
4876 static const struct ethtool_ops ops = {
4877 .get_drvinfo = rtl8152_get_drvinfo,
4878 .get_link = ethtool_op_get_link,
4879 .nway_reset = rtl8152_nway_reset,
4880 .get_msglevel = rtl8152_get_msglevel,
4881 .set_msglevel = rtl8152_set_msglevel,
4882 .get_wol = rtl8152_get_wol,
4883 .set_wol = rtl8152_set_wol,
4884 .get_strings = rtl8152_get_strings,
4885 .get_sset_count = rtl8152_get_sset_count,
4886 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4887 .get_coalesce = rtl8152_get_coalesce,
4888 .set_coalesce = rtl8152_set_coalesce,
4889 .get_eee = rtl_ethtool_get_eee,
4890 .set_eee = rtl_ethtool_set_eee,
4891 .get_link_ksettings = rtl8152_get_link_ksettings,
4892 .set_link_ksettings = rtl8152_set_link_ksettings,
4895 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4897 struct r8152 *tp = netdev_priv(netdev);
4898 struct mii_ioctl_data *data = if_mii(rq);
4901 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4904 res = usb_autopm_get_interface(tp->intf);
4910 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4914 mutex_lock(&tp->control);
4915 data->val_out = r8152_mdio_read(tp, data->reg_num);
4916 mutex_unlock(&tp->control);
4920 if (!capable(CAP_NET_ADMIN)) {
4924 mutex_lock(&tp->control);
4925 r8152_mdio_write(tp, data->reg_num, data->val_in);
4926 mutex_unlock(&tp->control);
4933 usb_autopm_put_interface(tp->intf);
4939 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4941 struct r8152 *tp = netdev_priv(dev);
4944 switch (tp->version) {
4954 ret = usb_autopm_get_interface(tp->intf);
4958 mutex_lock(&tp->control);
4962 if (netif_running(dev)) {
4963 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4965 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4967 if (netif_carrier_ok(dev))
4968 r8153_set_rx_early_size(tp);
4971 mutex_unlock(&tp->control);
4973 usb_autopm_put_interface(tp->intf);
4978 static const struct net_device_ops rtl8152_netdev_ops = {
4979 .ndo_open = rtl8152_open,
4980 .ndo_stop = rtl8152_close,
4981 .ndo_do_ioctl = rtl8152_ioctl,
4982 .ndo_start_xmit = rtl8152_start_xmit,
4983 .ndo_tx_timeout = rtl8152_tx_timeout,
4984 .ndo_set_features = rtl8152_set_features,
4985 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4986 .ndo_set_mac_address = rtl8152_set_mac_address,
4987 .ndo_change_mtu = rtl8152_change_mtu,
4988 .ndo_validate_addr = eth_validate_addr,
4989 .ndo_features_check = rtl8152_features_check,
4992 static void rtl8152_unload(struct r8152 *tp)
4994 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4997 if (tp->version != RTL_VER_01)
4998 r8152_power_cut_en(tp, true);
5001 static void rtl8153_unload(struct r8152 *tp)
5003 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5006 r8153_power_cut_en(tp, false);
5009 static void rtl8153b_unload(struct r8152 *tp)
5011 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5014 r8153b_power_cut_en(tp, false);
5017 static int rtl_ops_init(struct r8152 *tp)
5019 struct rtl_ops *ops = &tp->rtl_ops;
5022 switch (tp->version) {
5026 ops->init = r8152b_init;
5027 ops->enable = rtl8152_enable;
5028 ops->disable = rtl8152_disable;
5029 ops->up = rtl8152_up;
5030 ops->down = rtl8152_down;
5031 ops->unload = rtl8152_unload;
5032 ops->eee_get = r8152_get_eee;
5033 ops->eee_set = r8152_set_eee;
5034 ops->in_nway = rtl8152_in_nway;
5035 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5036 ops->autosuspend_en = rtl_runtime_suspend_enable;
5043 ops->init = r8153_init;
5044 ops->enable = rtl8153_enable;
5045 ops->disable = rtl8153_disable;
5046 ops->up = rtl8153_up;
5047 ops->down = rtl8153_down;
5048 ops->unload = rtl8153_unload;
5049 ops->eee_get = r8153_get_eee;
5050 ops->eee_set = r8153_set_eee;
5051 ops->in_nway = rtl8153_in_nway;
5052 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5053 ops->autosuspend_en = rtl8153_runtime_enable;
5058 ops->init = r8153b_init;
5059 ops->enable = rtl8153_enable;
5060 ops->disable = rtl8153b_disable;
5061 ops->up = rtl8153b_up;
5062 ops->down = rtl8153b_down;
5063 ops->unload = rtl8153b_unload;
5064 ops->eee_get = r8153_get_eee;
5065 ops->eee_set = r8153b_set_eee;
5066 ops->in_nway = rtl8153_in_nway;
5067 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5068 ops->autosuspend_en = rtl8153b_runtime_enable;
5073 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5080 static u8 rtl_get_version(struct usb_interface *intf)
5082 struct usb_device *udev = interface_to_usbdev(intf);
5088 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5092 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5093 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5094 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5096 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5102 version = RTL_VER_01;
5105 version = RTL_VER_02;
5108 version = RTL_VER_03;
5111 version = RTL_VER_04;
5114 version = RTL_VER_05;
5117 version = RTL_VER_06;
5120 version = RTL_VER_07;
5123 version = RTL_VER_08;
5126 version = RTL_VER_09;
5129 version = RTL_VER_UNKNOWN;
5130 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5134 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5139 static int rtl8152_probe(struct usb_interface *intf,
5140 const struct usb_device_id *id)
5142 struct usb_device *udev = interface_to_usbdev(intf);
5143 u8 version = rtl_get_version(intf);
5145 struct net_device *netdev;
5148 if (version == RTL_VER_UNKNOWN)
5151 if (udev->actconfig->desc.bConfigurationValue != 1) {
5152 usb_driver_set_configuration(udev, 1);
5156 if (intf->cur_altsetting->desc.bNumEndpoints < 3)
5159 usb_reset_device(udev);
5160 netdev = alloc_etherdev(sizeof(struct r8152));
5162 dev_err(&intf->dev, "Out of memory\n");
5166 SET_NETDEV_DEV(netdev, &intf->dev);
5167 tp = netdev_priv(netdev);
5168 tp->msg_enable = 0x7FFF;
5171 tp->netdev = netdev;
5173 tp->version = version;
5179 tp->mii.supports_gmii = 0;
5182 tp->mii.supports_gmii = 1;
5186 ret = rtl_ops_init(tp);
5190 mutex_init(&tp->control);
5191 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5192 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5194 netdev->netdev_ops = &rtl8152_netdev_ops;
5195 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5197 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5198 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5199 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5200 NETIF_F_HW_VLAN_CTAG_TX;
5201 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5202 NETIF_F_TSO | NETIF_F_FRAGLIST |
5203 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5204 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5205 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5206 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5207 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5209 if (tp->version == RTL_VER_01) {
5210 netdev->features &= ~NETIF_F_RXCSUM;
5211 netdev->hw_features &= ~NETIF_F_RXCSUM;
5214 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5215 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5216 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5217 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5220 netdev->ethtool_ops = &ops;
5221 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5223 /* MTU range: 68 - 1500 or 9194 */
5224 netdev->min_mtu = ETH_MIN_MTU;
5225 switch (tp->version) {
5228 netdev->max_mtu = ETH_DATA_LEN;
5231 netdev->max_mtu = RTL8153_MAX_MTU;
5235 tp->mii.dev = netdev;
5236 tp->mii.mdio_read = read_mii_word;
5237 tp->mii.mdio_write = write_mii_word;
5238 tp->mii.phy_id_mask = 0x3f;
5239 tp->mii.reg_num_mask = 0x1f;
5240 tp->mii.phy_id = R8152_PHY_ID;
5242 tp->autoneg = AUTONEG_ENABLE;
5243 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5244 tp->duplex = DUPLEX_FULL;
5246 intf->needs_remote_wakeup = 1;
5248 if (!rtl_can_wakeup(tp))
5249 __rtl_set_wol(tp, 0);
5251 tp->saved_wolopts = __rtl_get_wol(tp);
5253 tp->rtl_ops.init(tp);
5254 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5255 set_ethernet_addr(tp);
5257 usb_set_intfdata(intf, tp);
5258 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5260 ret = register_netdev(netdev);
5262 netif_err(tp, probe, netdev, "couldn't register the device\n");
5266 if (tp->saved_wolopts)
5267 device_set_wakeup_enable(&udev->dev, true);
5269 device_set_wakeup_enable(&udev->dev, false);
5271 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5276 netif_napi_del(&tp->napi);
5277 usb_set_intfdata(intf, NULL);
5279 free_netdev(netdev);
5283 static void rtl8152_disconnect(struct usb_interface *intf)
5285 struct r8152 *tp = usb_get_intfdata(intf);
5287 usb_set_intfdata(intf, NULL);
5289 struct usb_device *udev = tp->udev;
5291 if (udev->state == USB_STATE_NOTATTACHED)
5292 set_bit(RTL8152_UNPLUG, &tp->flags);
5294 netif_napi_del(&tp->napi);
5295 unregister_netdev(tp->netdev);
5296 cancel_delayed_work_sync(&tp->hw_phy_work);
5297 tp->rtl_ops.unload(tp);
5298 free_netdev(tp->netdev);
5302 #define REALTEK_USB_DEVICE(vend, prod) \
5303 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5304 USB_DEVICE_ID_MATCH_INT_CLASS, \
5305 .idVendor = (vend), \
5306 .idProduct = (prod), \
5307 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5310 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5311 USB_DEVICE_ID_MATCH_DEVICE, \
5312 .idVendor = (vend), \
5313 .idProduct = (prod), \
5314 .bInterfaceClass = USB_CLASS_COMM, \
5315 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5316 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5318 /* table of devices that work with this driver */
5319 static const struct usb_device_id rtl8152_table[] = {
5320 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5321 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5322 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5323 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5324 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5325 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
5326 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5327 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5328 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5329 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5330 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5331 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5332 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5333 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e)},
5334 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
5335 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5336 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5337 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5341 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5343 static struct usb_driver rtl8152_driver = {
5345 .id_table = rtl8152_table,
5346 .probe = rtl8152_probe,
5347 .disconnect = rtl8152_disconnect,
5348 .suspend = rtl8152_suspend,
5349 .resume = rtl8152_resume,
5350 .reset_resume = rtl8152_reset_resume,
5351 .pre_reset = rtl8152_pre_reset,
5352 .post_reset = rtl8152_post_reset,
5353 .supports_autosuspend = 1,
5354 .disable_hub_initiated_lpm = 1,
5357 module_usb_driver(rtl8152_driver);
5359 MODULE_AUTHOR(DRIVER_AUTHOR);
5360 MODULE_DESCRIPTION(DRIVER_DESC);
5361 MODULE_LICENSE("GPL");
5362 MODULE_VERSION(DRIVER_VERSION);