drivers/net/phy/mscc/mscc_main.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Driver for Microsemi VSC85xx PHYs
   4  *
   5  * Author: Nagaraju Lakkaraju
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2016 Microsemi Corporation
   8  */
   9
  10 #include <linux/firmware.h>
  11 #include <linux/jiffies.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/mdio.h>
  15 #include <linux/mii.h>
  16 #include <linux/phy.h>
  17 #include <linux/of.h>
  18 #include <linux/netdevice.h>
  19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  20
  21 #include "mscc.h"
  22
  23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
  24         {
  25                 .string = "phy_receive_errors",
  26                 .reg    = MSCC_PHY_ERR_RX_CNT,
  27                 .page   = MSCC_PHY_PAGE_STANDARD,
  28                 .mask   = ERR_CNT_MASK,
  29         }, {
  30                 .string = "phy_false_carrier",
  31                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
  32                 .page   = MSCC_PHY_PAGE_STANDARD,
  33                 .mask   = ERR_CNT_MASK,
  34         }, {
  35                 .string = "phy_cu_media_link_disconnect",
  36                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
  37                 .page   = MSCC_PHY_PAGE_STANDARD,
  38                 .mask   = ERR_CNT_MASK,
  39         }, {
  40                 .string = "phy_cu_media_crc_good_count",
  41                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
  42                 .page   = MSCC_PHY_PAGE_EXTENDED,
  43                 .mask   = VALID_CRC_CNT_CRC_MASK,
  44         }, {
  45                 .string = "phy_cu_media_crc_error_count",
  46                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
  47                 .page   = MSCC_PHY_PAGE_EXTENDED,
  48                 .mask   = ERR_CNT_MASK,
  49         },
  50 };
  51
  52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
  53         {
  54                 .string = "phy_receive_errors",
  55                 .reg    = MSCC_PHY_ERR_RX_CNT,
  56                 .page   = MSCC_PHY_PAGE_STANDARD,
  57                 .mask   = ERR_CNT_MASK,
  58         }, {
  59                 .string = "phy_false_carrier",
  60                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
  61                 .page   = MSCC_PHY_PAGE_STANDARD,
  62                 .mask   = ERR_CNT_MASK,
  63         }, {
  64                 .string = "phy_cu_media_link_disconnect",
  65                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
  66                 .page   = MSCC_PHY_PAGE_STANDARD,
  67                 .mask   = ERR_CNT_MASK,
  68         }, {
  69                 .string = "phy_cu_media_crc_good_count",
  70                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
  71                 .page   = MSCC_PHY_PAGE_EXTENDED,
  72                 .mask   = VALID_CRC_CNT_CRC_MASK,
  73         }, {
  74                 .string = "phy_cu_media_crc_error_count",
  75                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
  76                 .page   = MSCC_PHY_PAGE_EXTENDED,
  77                 .mask   = ERR_CNT_MASK,
  78         }, {
  79                 .string = "phy_serdes_tx_good_pkt_count",
  80                 .reg    = MSCC_PHY_SERDES_TX_VALID_CNT,
  81                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  82                 .mask   = VALID_CRC_CNT_CRC_MASK,
  83         }, {
  84                 .string = "phy_serdes_tx_bad_crc_count",
  85                 .reg    = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
  86                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  87                 .mask   = ERR_CNT_MASK,
  88         }, {
  89                 .string = "phy_serdes_rx_good_pkt_count",
  90                 .reg    = MSCC_PHY_SERDES_RX_VALID_CNT,
  91                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  92                 .mask   = VALID_CRC_CNT_CRC_MASK,
  93         }, {
  94                 .string = "phy_serdes_rx_bad_crc_count",
  95                 .reg    = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
  96                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
  97                 .mask   = ERR_CNT_MASK,
  98         },
  99 };
 100
 101 #if IS_ENABLED(CONFIG_OF_MDIO)
 102 static const struct vsc8531_edge_rate_table edge_table[] = {
 103         {MSCC_VDDMAC_3300, { 0, 2,  4,  7, 10, 17, 29, 53} },
 104         {MSCC_VDDMAC_2500, { 0, 3,  6, 10, 14, 23, 37, 63} },
 105         {MSCC_VDDMAC_1800, { 0, 5,  9, 16, 23, 35, 52, 76} },
 106         {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
 107 };
 108 #endif
 109
 110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
 111 {
 112         return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
 113 }
 114
 115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
 116 {
 117         return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
 118 }
 119
 120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
 121 {
 122         struct vsc8531_private *priv = phydev->priv;
 123
 124         if (!priv)
 125                 return 0;
 126
 127         return priv->nstats;
 128 }
 129
 130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
 131 {
 132         struct vsc8531_private *priv = phydev->priv;
 133         int i;
 134
 135         if (!priv)
 136                 return;
 137
 138         for (i = 0; i < priv->nstats; i++)
 139                 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
 140                         ETH_GSTRING_LEN);
 141 }
 142
 143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
 144 {
 145         struct vsc8531_private *priv = phydev->priv;
 146         int val;
 147
 148         val = phy_read_paged(phydev, priv->hw_stats[i].page,
 149                              priv->hw_stats[i].reg);
 150         if (val < 0)
 151                 return U64_MAX;
 152
 153         val = val & priv->hw_stats[i].mask;
 154         priv->stats[i] += val;
 155
 156         return priv->stats[i];
 157 }
 158
 159 static void vsc85xx_get_stats(struct phy_device *phydev,
 160                               struct ethtool_stats *stats, u64 *data)
 161 {
 162         struct vsc8531_private *priv = phydev->priv;
 163         int i;
 164
 165         if (!priv)
 166                 return;
 167
 168         for (i = 0; i < priv->nstats; i++)
 169                 data[i] = vsc85xx_get_stat(phydev, i);
 170 }
 171
 172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
 173                                 u8 led_num,
 174                                 u8 mode)
 175 {
 176         int rc;
 177         u16 reg_val;
 178
 179         mutex_lock(&phydev->lock);
 180         reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
 181         reg_val &= ~LED_MODE_SEL_MASK(led_num);
 182         reg_val |= LED_MODE_SEL(led_num, (u16)mode);
 183         rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
 184         mutex_unlock(&phydev->lock);
 185
 186         return rc;
 187 }
 188
 189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 190 {
 191         u16 reg_val;
 192
 193         reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
 194         if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
 195                 *mdix = ETH_TP_MDI_X;
 196         else
 197                 *mdix = ETH_TP_MDI;
 198
 199         return 0;
 200 }
 201
 202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
 203 {
 204         int rc;
 205         u16 reg_val;
 206
 207         reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
 208         if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
 209                 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
 210                             DISABLE_POLARITY_CORR_MASK  |
 211                             DISABLE_HP_AUTO_MDIX_MASK);
 212         } else {
 213                 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
 214                              DISABLE_POLARITY_CORR_MASK  |
 215                              DISABLE_HP_AUTO_MDIX_MASK);
 216         }
 217         rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
 218         if (rc)
 219                 return rc;
 220
 221         reg_val = 0;
 222
 223         if (mdix == ETH_TP_MDI)
 224                 reg_val = FORCE_MDI_CROSSOVER_MDI;
 225         else if (mdix == ETH_TP_MDI_X)
 226                 reg_val = FORCE_MDI_CROSSOVER_MDIX;
 227
 228         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 229                               MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
 230                               reg_val);
 231         if (rc < 0)
 232                 return rc;
 233
 234         return genphy_restart_aneg(phydev);
 235 }
 236
 237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
 238 {
 239         int reg_val;
 240
 241         reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 242                                  MSCC_PHY_ACTIPHY_CNTL);
 243         if (reg_val < 0)
 244                 return reg_val;
 245
 246         reg_val &= DOWNSHIFT_CNTL_MASK;
 247         if (!(reg_val & DOWNSHIFT_EN))
 248                 *count = DOWNSHIFT_DEV_DISABLE;
 249         else
 250                 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
 251
 252         return 0;
 253 }
 254
 255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
 256 {
 257         if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
 258                 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
 259                 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 260         } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
 261                 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
 262                 return -ERANGE;
 263         } else if (count) {
 264                 /* Downshift count is either 2,3,4 or 5 */
 265                 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 266         }
 267
 268         return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 269                                 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
 270                                 count);
 271 }
 272
 273 static int vsc85xx_wol_set(struct phy_device *phydev,
 274                            struct ethtool_wolinfo *wol)
 275 {
 276         int rc;
 277         u16 reg_val;
 278         u8  i;
 279         u16 pwd[3] = {0, 0, 0};
 280         struct ethtool_wolinfo *wol_conf = wol;
 281         u8 *mac_addr = phydev->attached_dev->dev_addr;
 282
 283         mutex_lock(&phydev->lock);
 284         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 285         if (rc < 0) {
 286                 rc = phy_restore_page(phydev, rc, rc);
 287                 goto out_unlock;
 288         }
 289
 290         if (wol->wolopts & WAKE_MAGIC) {
 291                 /* Store the device address for the magic packet */
 292                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 293                         pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
 294                                  mac_addr[5 - i * 2];
 295                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
 296                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
 297                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
 298         } else {
 299                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
 300                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
 301                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
 302         }
 303
 304         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 305                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 306                         pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
 307                                  wol_conf->sopass[5 - i * 2];
 308                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
 309                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
 310                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
 311         } else {
 312                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
 313                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
 314                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
 315         }
 316
 317         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 318         if (wol_conf->wolopts & WAKE_MAGICSECURE)
 319                 reg_val |= SECURE_ON_ENABLE;
 320         else
 321                 reg_val &= ~SECURE_ON_ENABLE;
 322         __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
 323
 324         rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 325         if (rc < 0)
 326                 goto out_unlock;
 327
 328         if (wol->wolopts & WAKE_MAGIC) {
 329                 /* Enable the WOL interrupt */
 330                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 331                 reg_val |= MII_VSC85XX_INT_MASK_WOL;
 332                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 333                 if (rc)
 334                         goto out_unlock;
 335         } else {
 336                 /* Disable the WOL interrupt */
 337                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 338                 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
 339                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 340                 if (rc)
 341                         goto out_unlock;
 342         }
 343         /* Clear WOL iterrupt status */
 344         reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
 345
 346 out_unlock:
 347         mutex_unlock(&phydev->lock);
 348
 349         return rc;
 350 }
 351
 352 static void vsc85xx_wol_get(struct phy_device *phydev,
 353                             struct ethtool_wolinfo *wol)
 354 {
 355         int rc;
 356         u16 reg_val;
 357         u8  i;
 358         u16 pwd[3] = {0, 0, 0};
 359         struct ethtool_wolinfo *wol_conf = wol;
 360
 361         mutex_lock(&phydev->lock);
 362         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 363         if (rc < 0)
 364                 goto out_unlock;
 365
 366         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 367         if (reg_val & SECURE_ON_ENABLE)
 368                 wol_conf->wolopts |= WAKE_MAGICSECURE;
 369         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 370                 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
 371                 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
 372                 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
 373                 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
 374                         wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
 375                         wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
 376                                                             >> 8;
 377                 }
 378         }
 379
 380 out_unlock:
 381         phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 382         mutex_unlock(&phydev->lock);
 383 }
 384
 385 #if IS_ENABLED(CONFIG_OF_MDIO)
 386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 387 {
 388         u32 vdd, sd;
 389         int i, j;
 390         struct device *dev = &phydev->mdio.dev;
 391         struct device_node *of_node = dev->of_node;
 392         u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
 393
 394         if (!of_node)
 395                 return -ENODEV;
 396
 397         if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
 398                 vdd = MSCC_VDDMAC_3300;
 399
 400         if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
 401                 sd = 0;
 402
 403         for (i = 0; i < ARRAY_SIZE(edge_table); i++)
 404                 if (edge_table[i].vddmac == vdd)
 405                         for (j = 0; j < sd_array_size; j++)
 406                                 if (edge_table[i].slowdown[j] == sd)
 407                                         return (sd_array_size - j - 1);
 408
 409         return -EINVAL;
 410 }
 411
 412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 413                                    char *led,
 414                                    u32 default_mode)
 415 {
 416         struct vsc8531_private *priv = phydev->priv;
 417         struct device *dev = &phydev->mdio.dev;
 418         struct device_node *of_node = dev->of_node;
 419         u32 led_mode;
 420         int err;
 421
 422         if (!of_node)
 423                 return -ENODEV;
 424
 425         led_mode = default_mode;
 426         err = of_property_read_u32(of_node, led, &led_mode);
 427         if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
 428                 phydev_err(phydev, "DT %s invalid\n", led);
 429                 return -EINVAL;
 430         }
 431
 432         return led_mode;
 433 }
 434
 435 #else
 436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 437 {
 438         return 0;
 439 }
 440
 441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 442                                    char *led,
 443                                    u8 default_mode)
 444 {
 445         return default_mode;
 446 }
 447 #endif /* CONFIG_OF_MDIO */
 448
 449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
 450                                     u32 *default_mode)
 451 {
 452         struct vsc8531_private *priv = phydev->priv;
 453         char led_dt_prop[28];
 454         int i, ret;
 455
 456         for (i = 0; i < priv->nleds; i++) {
 457                 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
 458                 if (ret < 0)
 459                         return ret;
 460
 461                 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
 462                                               default_mode[i]);
 463                 if (ret < 0)
 464                         return ret;
 465                 priv->leds_mode[i] = ret;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
 472 {
 473         int rc;
 474
 475         mutex_lock(&phydev->lock);
 476         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 477                               MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
 478                               edge_rate << EDGE_RATE_CNTL_POS);
 479         mutex_unlock(&phydev->lock);
 480
 481         return rc;
 482 }
 483
 484 static int vsc85xx_mac_if_set(struct phy_device *phydev,
 485                               phy_interface_t interface)
 486 {
 487         int rc;
 488         u16 reg_val;
 489
 490         mutex_lock(&phydev->lock);
 491         reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
 492         reg_val &= ~(MAC_IF_SELECTION_MASK);
 493         switch (interface) {
 494         case PHY_INTERFACE_MODE_RGMII_TXID:
 495         case PHY_INTERFACE_MODE_RGMII_RXID:
 496         case PHY_INTERFACE_MODE_RGMII_ID:
 497         case PHY_INTERFACE_MODE_RGMII:
 498                 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
 499                 break;
 500         case PHY_INTERFACE_MODE_RMII:
 501                 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
 502                 break;
 503         case PHY_INTERFACE_MODE_MII:
 504         case PHY_INTERFACE_MODE_GMII:
 505                 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
 506                 break;
 507         default:
 508                 rc = -EINVAL;
 509                 goto out_unlock;
 510         }
 511         rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
 512         if (rc)
 513                 goto out_unlock;
 514
 515         rc = genphy_soft_reset(phydev);
 516
 517 out_unlock:
 518         mutex_unlock(&phydev->lock);
 519
 520         return rc;
 521 }
 522
 523 /* Set the RGMII RX and TX clock skews individually, according to the PHY
 524  * interface type, to:
 525  *  * 0.2 ns (their default, and lowest, hardware value) if delays should
 526  *    not be enabled
 527  *  * 2.0 ns (which causes the data to be sampled at exactly half way between
 528  *    clock transitions at 1000 Mbps) if delays should be enabled
 529  */
 530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
 531                                    u16 rgmii_rx_delay_mask,
 532                                    u16 rgmii_tx_delay_mask)
 533 {
 534         u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
 535         u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
 536         u16 reg_val = 0;
 537         int rc;
 538
 539         mutex_lock(&phydev->lock);
 540
 541         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 542             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 543                 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
 544         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 545             phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 546                 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
 547
 548         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 549                               rgmii_cntl,
 550                               rgmii_rx_delay_mask | rgmii_tx_delay_mask,
 551                               reg_val);
 552
 553         mutex_unlock(&phydev->lock);
 554
 555         return rc;
 556 }
 557
 558 static int vsc85xx_default_config(struct phy_device *phydev)
 559 {
 560         int rc;
 561
 562         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 563
 564         if (phy_interface_mode_is_rgmii(phydev->interface)) {
 565                 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL,
 566                                              VSC8502_RGMII_RX_DELAY_MASK,
 567                                              VSC8502_RGMII_TX_DELAY_MASK);
 568                 if (rc)
 569                         return rc;
 570         }
 571
 572         return 0;
 573 }
 574
 575 static int vsc85xx_get_tunable(struct phy_device *phydev,
 576                                struct ethtool_tunable *tuna, void *data)
 577 {
 578         switch (tuna->id) {
 579         case ETHTOOL_PHY_DOWNSHIFT:
 580                 return vsc85xx_downshift_get(phydev, (u8 *)data);
 581         default:
 582                 return -EINVAL;
 583         }
 584 }
 585
 586 static int vsc85xx_set_tunable(struct phy_device *phydev,
 587                                struct ethtool_tunable *tuna,
 588                                const void *data)
 589 {
 590         switch (tuna->id) {
 591         case ETHTOOL_PHY_DOWNSHIFT:
 592                 return vsc85xx_downshift_set(phydev, *(u8 *)data);
 593         default:
 594                 return -EINVAL;
 595         }
 596 }
 597
 598 /* mdiobus lock should be locked when using this function */
 599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
 600 {
 601         __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 602         __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 603         __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 604 }
 605
 606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
 607 {
 608         int rc;
 609         static const struct reg_val init_seq[] = {
 610                 {0x0f90, 0x00688980},
 611                 {0x0696, 0x00000003},
 612                 {0x07fa, 0x0050100f},
 613                 {0x1686, 0x00000004},
 614         };
 615         unsigned int i;
 616         int oldpage;
 617
 618         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
 619                               MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
 620                               SMI_BROADCAST_WR_EN);
 621         if (rc < 0)
 622                 return rc;
 623         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 624                               MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
 625         if (rc < 0)
 626                 return rc;
 627         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 628                               MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
 629         if (rc < 0)
 630                 return rc;
 631         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
 632                               MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
 633         if (rc < 0)
 634                 return rc;
 635
 636         mutex_lock(&phydev->lock);
 637         oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
 638         if (oldpage < 0)
 639                 goto out_unlock;
 640
 641         for (i = 0; i < ARRAY_SIZE(init_seq); i++)
 642                 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
 643
 644 out_unlock:
 645         oldpage = phy_restore_page(phydev, oldpage, oldpage);
 646         mutex_unlock(&phydev->lock);
 647
 648         return oldpage;
 649 }
 650
 651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
 652 {
 653         static const struct reg_val init_eee[] = {
 654                 {0x0f82, 0x0012b00a},
 655                 {0x1686, 0x00000004},
 656                 {0x168c, 0x00d2c46f},
 657                 {0x17a2, 0x00000620},
 658                 {0x16a0, 0x00eeffdd},
 659                 {0x16a6, 0x00071448},
 660                 {0x16a4, 0x0013132f},
 661                 {0x16a8, 0x00000000},
 662                 {0x0ffc, 0x00c0a028},
 663                 {0x0fe8, 0x0091b06c},
 664                 {0x0fea, 0x00041600},
 665                 {0x0f80, 0x00000af4},
 666                 {0x0fec, 0x00901809},
 667                 {0x0fee, 0x0000a6a1},
 668                 {0x0ffe, 0x00b01007},
 669                 {0x16b0, 0x00eeff00},
 670                 {0x16b2, 0x00007000},
 671                 {0x16b4, 0x00000814},
 672         };
 673         unsigned int i;
 674         int oldpage;
 675
 676         mutex_lock(&phydev->lock);
 677         oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
 678         if (oldpage < 0)
 679                 goto out_unlock;
 680
 681         for (i = 0; i < ARRAY_SIZE(init_eee); i++)
 682                 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
 683
 684 out_unlock:
 685         oldpage = phy_restore_page(phydev, oldpage, oldpage);
 686         mutex_unlock(&phydev->lock);
 687
 688         return oldpage;
 689 }
 690
 691 /* phydev->bus->mdio_lock should be locked when using this function */
 692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
 693 {
 694         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 695                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 696                 dump_stack();
 697         }
 698
 699         return __phy_package_write(phydev, regnum, val);
 700 }
 701
 702 /* phydev->bus->mdio_lock should be locked when using this function */
 703 static int phy_base_read(struct phy_device *phydev, u32 regnum)
 704 {
 705         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 706                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 707                 dump_stack();
 708         }
 709
 710         return __phy_package_read(phydev, regnum);
 711 }
 712
 713 static u32 vsc85xx_csr_read(struct phy_device *phydev,
 714                             enum csr_target target, u32 reg)
 715 {
 716         unsigned long deadline;
 717         u32 val, val_l, val_h;
 718
 719         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
 720
 721         /* CSR registers are grouped under different Target IDs.
 722          * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
 723          * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
 724          * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
 725          * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
 726          */
 727
 728         /* Setup the Target ID */
 729         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
 730                        MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
 731
 732         if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
 733                 /* non-MACsec access */
 734                 target &= 0x3;
 735         else
 736                 target = 0;
 737
 738         /* Trigger CSR Action - Read into the CSR's */
 739         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
 740                        MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
 741                        MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
 742                        MSCC_PHY_CSR_CNTL_19_TARGET(target));
 743
 744         /* Wait for register access*/
 745         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
 746         do {
 747                 usleep_range(500, 1000);
 748                 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
 749         } while (time_before(jiffies, deadline) &&
 750                 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
 751
 752         if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
 753                 return 0xffffffff;
 754
 755         /* Read the Least Significant Word (LSW) (17) */
 756         val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
 757
 758         /* Read the Most Significant Word (MSW) (18) */
 759         val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
 760
 761         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 762                        MSCC_PHY_PAGE_STANDARD);
 763
 764         return (val_h << 16) | val_l;
 765 }
 766
 767 static int vsc85xx_csr_write(struct phy_device *phydev,
 768                              enum csr_target target, u32 reg, u32 val)
 769 {
 770         unsigned long deadline;
 771
 772         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
 773
 774         /* CSR registers are grouped under different Target IDs.
 775          * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
 776          * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
 777          * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
 778          * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
 779          */
 780
 781         /* Setup the Target ID */
 782         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
 783                        MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
 784
 785         /* Write the Least Significant Word (LSW) (17) */
 786         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
 787
 788         /* Write the Most Significant Word (MSW) (18) */
 789         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
 790
 791         if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
 792                 /* non-MACsec access */
 793                 target &= 0x3;
 794         else
 795                 target = 0;
 796
 797         /* Trigger CSR Action - Write into the CSR's */
 798         phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
 799                        MSCC_PHY_CSR_CNTL_19_CMD |
 800                        MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
 801                        MSCC_PHY_CSR_CNTL_19_TARGET(target));
 802
 803         /* Wait for register access */
 804         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
 805         do {
 806                 usleep_range(500, 1000);
 807                 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
 808         } while (time_before(jiffies, deadline) &&
 809                  !(val & MSCC_PHY_CSR_CNTL_19_CMD));
 810
 811         if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
 812                 return -ETIMEDOUT;
 813
 814         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 815                        MSCC_PHY_PAGE_STANDARD);
 816
 817         return 0;
 818 }
 819
 820 /* bus->mdio_lock should be locked when using this function */
 821 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
 822 {
 823         phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 824         phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 825         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 826 }
 827
 828 /* bus->mdio_lock should be locked when using this function */
 829 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
 830 {
 831         unsigned long deadline;
 832         u16 reg_val;
 833
 834         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 835                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 836
 837         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
 838
 839         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
 840         do {
 841                 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
 842         } while (time_before(jiffies, deadline) &&
 843                  (reg_val & PROC_CMD_NCOMPLETED) &&
 844                  !(reg_val & PROC_CMD_FAILED));
 845
 846         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 847
 848         if (reg_val & PROC_CMD_FAILED)
 849                 return -EIO;
 850
 851         if (reg_val & PROC_CMD_NCOMPLETED)
 852                 return -ETIMEDOUT;
 853
 854         return 0;
 855 }
 856
 857 /* bus->mdio_lock should be locked when using this function */
 858 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
 859                                         bool patch_en)
 860 {
 861         u32 enable, release;
 862
 863         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 864                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 865
 866         enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
 867         release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
 868                 MICRO_CLK_EN;
 869
 870         if (patch_en) {
 871                 enable |= MICRO_PATCH_EN;
 872                 release |= MICRO_PATCH_EN;
 873
 874                 /* Clear all patches */
 875                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
 876         }
 877
 878         /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
 879          * override and addr. auto-incr; operate at 125 MHz
 880          */
 881         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
 882         /* Release 8051 Micro SW reset */
 883         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
 884
 885         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 886
 887         return 0;
 888 }
 889
 890 /* bus->mdio_lock should be locked when using this function */
 891 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
 892 {
 893         int ret;
 894         u16 reg;
 895
 896         ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
 897         if (ret)
 898                 return ret;
 899
 900         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 901                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 902
 903         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 904         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
 905         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 906
 907         phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
 908         phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
 909
 910         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 911         reg |= EN_PATCH_RAM_TRAP_ADDR(4);
 912         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 913
 914         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
 915
 916         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
 917         reg &= ~MICRO_NSOFT_RESET;
 918         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
 919
 920         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
 921                        PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
 922                        PROC_CMD_READ);
 923
 924         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
 925         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
 926         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
 927
 928         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 929
 930         return 0;
 931 }
 932
 933 /* bus->mdio_lock should be locked when using this function */
 934 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
 935                               u16 *crc)
 936 {
 937         int ret;
 938
 939         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
 940
 941         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
 942         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
 943
 944         /* Start Micro command */
 945         ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
 946         if (ret)
 947                 goto out;
 948
 949         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
 950
 951         *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
 952
 953 out:
 954         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 955
 956         return ret;
 957 }
 958
 959 /* bus->mdio_lock should be locked when using this function */
 960 static int vsc8584_patch_fw(struct phy_device *phydev,
 961                             const struct firmware *fw)
 962 {
 963         int i, ret;
 964
 965         ret = vsc8584_micro_assert_reset(phydev);
 966         if (ret) {
 967                 dev_err(&phydev->mdio.dev,
 968                         "%s: failed to assert reset of micro\n", __func__);
 969                 return ret;
 970         }
 971
 972         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 973                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 974
 975         /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
 976          * Disable the 8051 Micro clock
 977          */
 978         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
 979                        AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
 980                        MICRO_CLK_DIVIDE(2));
 981         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
 982                        INT_MEM_DATA(2));
 983         phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
 984
 985         for (i = 0; i < fw->size; i++)
 986                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
 987                                INT_MEM_WRITE_EN | fw->data[i]);
 988
 989         /* Clear internal memory access */
 990         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
 991
 992         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 993
 994         return 0;
 995 }
 996
 997 /* bus->mdio_lock should be locked when using this function */
 998 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
 999 {
1000         u16 reg;
1001         bool ret;
1002
1003         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1004                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1005
1006         reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1007         if (reg != 0x3eb7) {
1008                 ret = false;
1009                 goto out;
1010         }
1011
1012         reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1013         if (reg != 0x4012) {
1014                 ret = false;
1015                 goto out;
1016         }
1017
1018         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1019         if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1020                 ret = false;
1021                 goto out;
1022         }
1023
1024         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1025         if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM |  DW8051_CLK_EN |
1026              MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1027                 ret = false;
1028                 goto out;
1029         }
1030
1031         ret = true;
1032 out:
1033         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1034
1035         return ret;
1036 }
1037
1038 /* bus->mdio_lock should be locked when using this function */
1039 static int vsc8574_config_pre_init(struct phy_device *phydev)
1040 {
1041         static const struct reg_val pre_init1[] = {
1042                 {0x0fae, 0x000401bd},
1043                 {0x0fac, 0x000f000f},
1044                 {0x17a0, 0x00a0f147},
1045                 {0x0fe4, 0x00052f54},
1046                 {0x1792, 0x0027303d},
1047                 {0x07fe, 0x00000704},
1048                 {0x0fe0, 0x00060150},
1049                 {0x0f82, 0x0012b00a},
1050                 {0x0f80, 0x00000d74},
1051                 {0x02e0, 0x00000012},
1052                 {0x03a2, 0x00050208},
1053                 {0x03b2, 0x00009186},
1054                 {0x0fb0, 0x000e3700},
1055                 {0x1688, 0x00049f81},
1056                 {0x0fd2, 0x0000ffff},
1057                 {0x168a, 0x00039fa2},
1058                 {0x1690, 0x0020640b},
1059                 {0x0258, 0x00002220},
1060                 {0x025a, 0x00002a20},
1061                 {0x025c, 0x00003060},
1062                 {0x025e, 0x00003fa0},
1063                 {0x03a6, 0x0000e0f0},
1064                 {0x0f92, 0x00001489},
1065                 {0x16a2, 0x00007000},
1066                 {0x16a6, 0x00071448},
1067                 {0x16a0, 0x00eeffdd},
1068                 {0x0fe8, 0x0091b06c},
1069                 {0x0fea, 0x00041600},
1070                 {0x16b0, 0x00eeff00},
1071                 {0x16b2, 0x00007000},
1072                 {0x16b4, 0x00000814},
1073                 {0x0f90, 0x00688980},
1074                 {0x03a4, 0x0000d8f0},
1075                 {0x0fc0, 0x00000400},
1076                 {0x07fa, 0x0050100f},
1077                 {0x0796, 0x00000003},
1078                 {0x07f8, 0x00c3ff98},
1079                 {0x0fa4, 0x0018292a},
1080                 {0x168c, 0x00d2c46f},
1081                 {0x17a2, 0x00000620},
1082                 {0x16a4, 0x0013132f},
1083                 {0x16a8, 0x00000000},
1084                 {0x0ffc, 0x00c0a028},
1085                 {0x0fec, 0x00901c09},
1086                 {0x0fee, 0x0004a6a1},
1087                 {0x0ffe, 0x00b01807},
1088         };
1089         static const struct reg_val pre_init2[] = {
1090                 {0x0486, 0x0008a518},
1091                 {0x0488, 0x006dc696},
1092                 {0x048a, 0x00000912},
1093                 {0x048e, 0x00000db6},
1094                 {0x049c, 0x00596596},
1095                 {0x049e, 0x00000514},
1096                 {0x04a2, 0x00410280},
1097                 {0x04a4, 0x00000000},
1098                 {0x04a6, 0x00000000},
1099                 {0x04a8, 0x00000000},
1100                 {0x04aa, 0x00000000},
1101                 {0x04ae, 0x007df7dd},
1102                 {0x04b0, 0x006d95d4},
1103                 {0x04b2, 0x00492410},
1104         };
1105         struct device *dev = &phydev->mdio.dev;
1106         const struct firmware *fw;
1107         unsigned int i;
1108         u16 crc, reg;
1109         bool serdes_init;
1110         int ret;
1111
1112         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1113
1114         /* all writes below are broadcasted to all PHYs in the same package */
1115         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1116         reg |= SMI_BROADCAST_WR_EN;
1117         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1118
1119         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1120
1121         /* The below register writes are tweaking analog and electrical
1122          * configuration that were determined through characterization by PHY
1123          * engineers. These don't mean anything more than "these are the best
1124          * values".
1125          */
1126         phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1127
1128         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1129
1130         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1131         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1132         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1133         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1134
1135         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1136         reg |= TR_CLK_DISABLE;
1137         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1138
1139         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1140
1141         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1142                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1143
1144         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1145
1146         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1147
1148         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1149
1150         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1151                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1152
1153         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1154
1155         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1156         reg &= ~TR_CLK_DISABLE;
1157         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1158
1159         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1160
1161         /* end of write broadcasting */
1162         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1163         reg &= ~SMI_BROADCAST_WR_EN;
1164         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1165
1166         ret = reject_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1167         if (ret) {
1168                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1169                         MSCC_VSC8574_REVB_INT8051_FW, ret);
1170                 return ret;
1171         }
1172
1173         /* Add one byte to size for the one added by the patch_fw function */
1174         ret = vsc8584_get_fw_crc(phydev,
1175                                  MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1176                                  fw->size + 1, &crc);
1177         if (ret)
1178                 goto out;
1179
1180         if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1181                 serdes_init = vsc8574_is_serdes_init(phydev);
1182
1183                 if (!serdes_init) {
1184                         ret = vsc8584_micro_assert_reset(phydev);
1185                         if (ret) {
1186                                 dev_err(dev,
1187                                         "%s: failed to assert reset of micro\n",
1188                                         __func__);
1189                                 goto out;
1190                         }
1191                 }
1192         } else {
1193                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1194
1195                 serdes_init = false;
1196
1197                 if (vsc8584_patch_fw(phydev, fw))
1198                         dev_warn(dev,
1199                                  "failed to patch FW, expect non-optimal device\n");
1200         }
1201
1202         if (!serdes_init) {
1203                 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1204                                MSCC_PHY_PAGE_EXTENDED_GPIO);
1205
1206                 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1207                 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1208                 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1209                                EN_PATCH_RAM_TRAP_ADDR(1));
1210
1211                 vsc8584_micro_deassert_reset(phydev, false);
1212
1213                 /* Add one byte to size for the one added by the patch_fw
1214                  * function
1215                  */
1216                 ret = vsc8584_get_fw_crc(phydev,
1217                                          MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1218                                          fw->size + 1, &crc);
1219                 if (ret)
1220                         goto out;
1221
1222                 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1223                         dev_warn(dev,
1224                                  "FW CRC after patching is not the expected one, expect non-optimal device\n");
1225         }
1226
1227         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1228                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1229
1230         ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1231                           PROC_CMD_PHY_INIT);
1232
1233 out:
1234         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1235
1236         release_firmware(fw);
1237
1238         return ret;
1239 }
1240
1241 /* Access LCPLL Cfg_2 */
1242 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev,
1243                                   bool disable_fsm)
1244 {
1245         u32 rd_dat;
1246
1247         rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
1248         rd_dat &= ~BIT(PHY_S6G_CFG2_FSM_DIS);
1249         rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS);
1250         vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat);
1251 }
1252
1253 /* trigger a read to the spcified MCB */
1254 static int vsc8584_mcb_rd_trig(struct phy_device *phydev,
1255                                u32 mcb_reg_addr, u8 mcb_slave_num)
1256 {
1257         u32 rd_dat = 0;
1258
1259         /* read MCB */
1260         vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1261                           (0x40000000 | (1L << mcb_slave_num)));
1262
1263         return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1264                                  !(rd_dat & 0x40000000),
1265                                  4000, 200000, 0,
1266                                  phydev, MACRO_CTRL, mcb_reg_addr);
1267 }
1268
1269 /* trigger a write to the spcified MCB */
1270 static int vsc8584_mcb_wr_trig(struct phy_device *phydev,
1271                                u32 mcb_reg_addr,
1272                                u8 mcb_slave_num)
1273 {
1274         u32 rd_dat = 0;
1275
1276         /* write back MCB */
1277         vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1278                           (0x80000000 | (1L << mcb_slave_num)));
1279
1280         return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1281                                  !(rd_dat & 0x80000000),
1282                                  4000, 200000, 0,
1283                                  phydev, MACRO_CTRL, mcb_reg_addr);
1284 }
1285
1286 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */
1287 static int vsc8584_pll5g_reset(struct phy_device *phydev)
1288 {
1289         bool dis_fsm;
1290         int ret = 0;
1291
1292         ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1293         if (ret < 0)
1294                 goto done;
1295         dis_fsm = 1;
1296
1297         /* Reset LCPLL */
1298         vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1299
1300         /* write back LCPLL MCB */
1301         ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1302         if (ret < 0)
1303                 goto done;
1304
1305         /* 10 mSec sleep while LCPLL is hold in reset */
1306         usleep_range(10000, 20000);
1307
1308         /* read LCPLL MCB into CSRs */
1309         ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1310         if (ret < 0)
1311                 goto done;
1312         dis_fsm = 0;
1313
1314         /* Release the Reset of LCPLL */
1315         vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1316
1317         /* write back LCPLL MCB */
1318         ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1319         if (ret < 0)
1320                 goto done;
1321
1322         usleep_range(110000, 200000);
1323 done:
1324         return ret;
1325 }
1326
1327 /* bus->mdio_lock should be locked when using this function */
1328 static int vsc8584_config_pre_init(struct phy_device *phydev)
1329 {
1330         static const struct reg_val pre_init1[] = {
1331                 {0x07fa, 0x0050100f},
1332                 {0x1688, 0x00049f81},
1333                 {0x0f90, 0x00688980},
1334                 {0x03a4, 0x0000d8f0},
1335                 {0x0fc0, 0x00000400},
1336                 {0x0f82, 0x0012b002},
1337                 {0x1686, 0x00000004},
1338                 {0x168c, 0x00d2c46f},
1339                 {0x17a2, 0x00000620},
1340                 {0x16a0, 0x00eeffdd},
1341                 {0x16a6, 0x00071448},
1342                 {0x16a4, 0x0013132f},
1343                 {0x16a8, 0x00000000},
1344                 {0x0ffc, 0x00c0a028},
1345                 {0x0fe8, 0x0091b06c},
1346                 {0x0fea, 0x00041600},
1347                 {0x0f80, 0x00fffaff},
1348                 {0x0fec, 0x00901809},
1349                 {0x0ffe, 0x00b01007},
1350                 {0x16b0, 0x00eeff00},
1351                 {0x16b2, 0x00007000},
1352                 {0x16b4, 0x00000814},
1353         };
1354         static const struct reg_val pre_init2[] = {
1355                 {0x0486, 0x0008a518},
1356                 {0x0488, 0x006dc696},
1357                 {0x048a, 0x00000912},
1358         };
1359         const struct firmware *fw;
1360         struct device *dev = &phydev->mdio.dev;
1361         unsigned int i;
1362         u16 crc, reg;
1363         int ret;
1364
1365         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1366
1367         /* all writes below are broadcasted to all PHYs in the same package */
1368         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1369         reg |= SMI_BROADCAST_WR_EN;
1370         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1371
1372         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1373
1374         reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);
1375         reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1376         phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1377
1378         /* The below register writes are tweaking analog and electrical
1379          * configuration that were determined through characterization by PHY
1380          * engineers. These don't mean anything more than "these are the best
1381          * values".
1382          */
1383         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1384
1385         phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1386
1387         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1388
1389         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1390
1391         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1392         reg |= TR_CLK_DISABLE;
1393         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1394
1395         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1396
1397         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1398
1399         reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1400         reg &= ~0x007f;
1401         reg |= 0x0019;
1402         phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1403
1404         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1405
1406         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1407                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1408
1409         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1410
1411         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1412
1413         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1414
1415         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1416                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1417
1418         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1419
1420         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1421         reg &= ~TR_CLK_DISABLE;
1422         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1423
1424         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1425
1426         /* end of write broadcasting */
1427         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1428         reg &= ~SMI_BROADCAST_WR_EN;
1429         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1430
1431         ret = reject_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1432         if (ret) {
1433                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1434                         MSCC_VSC8584_REVB_INT8051_FW, ret);
1435                 return ret;
1436         }
1437
1438         /* Add one byte to size for the one added by the patch_fw function */
1439         ret = vsc8584_get_fw_crc(phydev,
1440                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1441                                  fw->size + 1, &crc);
1442         if (ret)
1443                 goto out;
1444
1445         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1446                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1447                 if (vsc8584_patch_fw(phydev, fw))
1448                         dev_warn(dev,
1449                                  "failed to patch FW, expect non-optimal device\n");
1450         }
1451
1452         vsc8584_micro_deassert_reset(phydev, false);
1453
1454         /* Add one byte to size for the one added by the patch_fw function */
1455         ret = vsc8584_get_fw_crc(phydev,
1456                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1457                                  fw->size + 1, &crc);
1458         if (ret)
1459                 goto out;
1460
1461         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1462                 dev_warn(dev,
1463                          "FW CRC after patching is not the expected one, expect non-optimal device\n");
1464
1465         ret = vsc8584_micro_assert_reset(phydev);
1466         if (ret)
1467                 goto out;
1468
1469         vsc8584_micro_deassert_reset(phydev, true);
1470
1471 out:
1472         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1473
1474         release_firmware(fw);
1475
1476         return ret;
1477 }
1478
1479 static void vsc8584_get_base_addr(struct phy_device *phydev)
1480 {
1481         struct vsc8531_private *vsc8531 = phydev->priv;
1482         u16 val, addr;
1483
1484         phy_lock_mdio_bus(phydev);
1485         __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1486
1487         addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1488         addr >>= PHY_CNTL_4_ADDR_POS;
1489
1490         val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1491
1492         __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1493         phy_unlock_mdio_bus(phydev);
1494
1495         /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
1496          * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
1497          * the base PHY for timestamping operations.
1498          */
1499         vsc8531->ts_base_addr = phydev->mdio.addr;
1500         vsc8531->ts_base_phy = addr;
1501
1502         if (val & PHY_ADDR_REVERSED) {
1503                 vsc8531->base_addr = phydev->mdio.addr + addr;
1504                 if (addr > 1) {
1505                         vsc8531->ts_base_addr += 2;
1506                         vsc8531->ts_base_phy += 2;
1507                 }
1508         } else {
1509                 vsc8531->base_addr = phydev->mdio.addr - addr;
1510                 if (addr > 1) {
1511                         vsc8531->ts_base_addr -= 2;
1512                         vsc8531->ts_base_phy -= 2;
1513                 }
1514         }
1515
1516         vsc8531->addr = addr;
1517 }
1518
1519 static int vsc8584_config_init(struct phy_device *phydev)
1520 {
1521         struct vsc8531_private *vsc8531 = phydev->priv;
1522         int ret, i;
1523         u16 val;
1524
1525         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1526
1527         phy_lock_mdio_bus(phydev);
1528
1529         /* Some parts of the init sequence are identical for every PHY in the
1530          * package. Some parts are modifying the GPIO register bank which is a
1531          * set of registers that are affecting all PHYs, a few resetting the
1532          * microprocessor common to all PHYs. The CRC check responsible of the
1533          * checking the firmware within the 8051 microprocessor can only be
1534          * accessed via the PHY whose internal address in the package is 0.
1535          * All PHYs' interrupts mask register has to be zeroed before enabling
1536          * any PHY's interrupt in this register.
1537          * For all these reasons, we need to do the init sequence once and only
1538          * once whatever is the first PHY in the package that is initialized and
1539          * do the correct init sequence for all PHYs that are package-critical
1540          * in this pre-init function.
1541          */
1542         if (phy_package_init_once(phydev)) {
1543                 /* The following switch statement assumes that the lowest
1544                  * nibble of the phy_id_mask is always 0. This works because
1545                  * the lowest nibble of the PHY_ID's below are also 0.
1546                  */
1547                 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1548
1549                 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1550                 case PHY_ID_VSC8504:
1551                 case PHY_ID_VSC8552:
1552                 case PHY_ID_VSC8572:
1553                 case PHY_ID_VSC8574:
1554                         ret = vsc8574_config_pre_init(phydev);
1555                         break;
1556                 case PHY_ID_VSC856X:
1557                 case PHY_ID_VSC8575:
1558                 case PHY_ID_VSC8582:
1559                 case PHY_ID_VSC8584:
1560                         ret = vsc8584_config_pre_init(phydev);
1561                         break;
1562                 default:
1563                         ret = -EINVAL;
1564                         break;
1565                 }
1566
1567                 if (ret)
1568                         goto err;
1569         }
1570
1571         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1572                              MSCC_PHY_PAGE_EXTENDED_GPIO);
1573         if (ret)
1574                 goto err;
1575
1576         val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1577         val &= ~MAC_CFG_MASK;
1578         if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1579                 val |= MAC_CFG_QSGMII;
1580         } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1581                 val |= MAC_CFG_SGMII;
1582         } else if (phy_interface_is_rgmii(phydev)) {
1583                 val |= MAC_CFG_RGMII;
1584         } else {
1585                 ret = -EINVAL;
1586                 goto err;
1587         }
1588
1589         ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1590         if (ret)
1591                 goto err;
1592
1593         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1594                              MSCC_PHY_PAGE_STANDARD);
1595         if (ret)
1596                 goto err;
1597
1598         if (!phy_interface_is_rgmii(phydev)) {
1599                 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1600                         PROC_CMD_READ_MOD_WRITE_PORT;
1601                 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1602                         val |= PROC_CMD_QSGMII_MAC;
1603                 else
1604                         val |= PROC_CMD_SGMII_MAC;
1605
1606                 ret = vsc8584_cmd(phydev, val);
1607                 if (ret)
1608                         goto err;
1609
1610                 usleep_range(10000, 20000);
1611         }
1612
1613         /* Disable SerDes for 100Base-FX */
1614         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1615                           PROC_CMD_FIBER_PORT(vsc8531->addr) |
1616                           PROC_CMD_FIBER_DISABLE |
1617                           PROC_CMD_READ_MOD_WRITE_PORT |
1618                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1619         if (ret)
1620                 goto err;
1621
1622         /* Disable SerDes for 1000Base-X */
1623         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1624                           PROC_CMD_FIBER_PORT(vsc8531->addr) |
1625                           PROC_CMD_FIBER_DISABLE |
1626                           PROC_CMD_READ_MOD_WRITE_PORT |
1627                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1628         if (ret)
1629                 goto err;
1630
1631         phy_unlock_mdio_bus(phydev);
1632
1633         ret = vsc8584_macsec_init(phydev);
1634         if (ret)
1635                 return ret;
1636
1637         ret = vsc8584_ptp_init(phydev);
1638         if (ret)
1639                 return ret;
1640
1641         val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1642         val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1643         val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1644                (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS);
1645         ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1646         if (ret)
1647                 return ret;
1648
1649         if (phy_interface_is_rgmii(phydev)) {
1650                 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL,
1651                                               VSC8572_RGMII_RX_DELAY_MASK,
1652                                               VSC8572_RGMII_TX_DELAY_MASK);
1653                 if (ret)
1654                         return ret;
1655         }
1656
1657         ret = genphy_soft_reset(phydev);
1658         if (ret)
1659                 return ret;
1660
1661         for (i = 0; i < vsc8531->nleds; i++) {
1662                 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1663                 if (ret)
1664                         return ret;
1665         }
1666
1667         return 0;
1668
1669 err:
1670         phy_unlock_mdio_bus(phydev);
1671         return ret;
1672 }
1673
1674 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1675 {
1676         irqreturn_t ret;
1677         int irq_status;
1678
1679         irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1680         if (irq_status < 0)
1681                 return IRQ_NONE;
1682
1683         /* Timestamping IRQ does not set a bit in the global INT_STATUS, so
1684          * irq_status would be 0.
1685          */
1686         ret = vsc8584_handle_ts_interrupt(phydev);
1687         if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
1688                 return ret;
1689
1690         if (irq_status & MII_VSC85XX_INT_MASK_EXT)
1691                 vsc8584_handle_macsec_interrupt(phydev);
1692
1693         if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG)
1694                 phy_mac_interrupt(phydev);
1695
1696         return IRQ_HANDLED;
1697 }
1698
1699 static int vsc85xx_config_init(struct phy_device *phydev)
1700 {
1701         int rc, i, phy_id;
1702         struct vsc8531_private *vsc8531 = phydev->priv;
1703
1704         rc = vsc85xx_default_config(phydev);
1705         if (rc)
1706                 return rc;
1707
1708         rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1709         if (rc)
1710                 return rc;
1711
1712         rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1713         if (rc)
1714                 return rc;
1715
1716         phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1717         if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1718             PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1719                 rc = vsc8531_pre_init_seq_set(phydev);
1720                 if (rc)
1721                         return rc;
1722         }
1723
1724         rc = vsc85xx_eee_init_seq_set(phydev);
1725         if (rc)
1726                 return rc;
1727
1728         for (i = 0; i < vsc8531->nleds; i++) {
1729                 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1730                 if (rc)
1731                         return rc;
1732         }
1733
1734         return 0;
1735 }
1736
1737 static int vsc8584_did_interrupt(struct phy_device *phydev)
1738 {
1739         int rc = 0;
1740
1741         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1742                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1743
1744         return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1745 }
1746
1747 static int vsc8514_config_pre_init(struct phy_device *phydev)
1748 {
1749         /* These are the settings to override the silicon default
1750          * values to handle hardware performance of PHY. They
1751          * are set at Power-On state and remain until PHY Reset.
1752          */
1753         static const struct reg_val pre_init1[] = {
1754                 {0x0f90, 0x00688980},
1755                 {0x0786, 0x00000003},
1756                 {0x07fa, 0x0050100f},
1757                 {0x0f82, 0x0012b002},
1758                 {0x1686, 0x00000004},
1759                 {0x168c, 0x00d2c46f},
1760                 {0x17a2, 0x00000620},
1761                 {0x16a0, 0x00eeffdd},
1762                 {0x16a6, 0x00071448},
1763                 {0x16a4, 0x0013132f},
1764                 {0x16a8, 0x00000000},
1765                 {0x0ffc, 0x00c0a028},
1766                 {0x0fe8, 0x0091b06c},
1767                 {0x0fea, 0x00041600},
1768                 {0x0f80, 0x00fffaff},
1769                 {0x0fec, 0x00901809},
1770                 {0x0ffe, 0x00b01007},
1771                 {0x16b0, 0x00eeff00},
1772                 {0x16b2, 0x00007000},
1773                 {0x16b4, 0x00000814},
1774         };
1775         struct device *dev = &phydev->mdio.dev;
1776         unsigned int i;
1777         u16 reg;
1778         int ret;
1779
1780         ret = vsc8584_pll5g_reset(phydev);
1781         if (ret < 0) {
1782                 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret);
1783                 return ret;
1784         }
1785
1786         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1787
1788         /* all writes below are broadcasted to all PHYs in the same package */
1789         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1790         reg |= SMI_BROADCAST_WR_EN;
1791         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1792
1793         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1794
1795         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1796         reg |= BIT(15);
1797         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1798
1799         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1800
1801         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1802                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1803
1804         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1805
1806         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1807         reg &= ~BIT(15);
1808         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1809
1810         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1811
1812         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1813         reg &= ~SMI_BROADCAST_WR_EN;
1814         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1815
1816         return 0;
1817 }
1818
1819 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1820                                u32 op)
1821 {
1822         unsigned long deadline;
1823         u32 val;
1824         int ret;
1825
1826         ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1827                                 op | (1 << mcb));
1828         if (ret)
1829                 return -EINVAL;
1830
1831         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1832         do {
1833                 usleep_range(500, 1000);
1834                 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1835
1836                 if (val == 0xffffffff)
1837                         return -EIO;
1838
1839         } while (time_before(jiffies, deadline) && (val & op));
1840
1841         if (val & op)
1842                 return -ETIMEDOUT;
1843
1844         return 0;
1845 }
1846
1847 /* Trigger a read to the specified MCB */
1848 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1849 {
1850         return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1851 }
1852
1853 /* Trigger a write to the specified MCB */
1854 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1855 {
1856         return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1857 }
1858
1859 static int vsc8514_config_init(struct phy_device *phydev)
1860 {
1861         struct vsc8531_private *vsc8531 = phydev->priv;
1862         unsigned long deadline;
1863         int ret, i;
1864         u16 val;
1865         u32 reg;
1866
1867         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1868
1869         phy_lock_mdio_bus(phydev);
1870
1871         /* Some parts of the init sequence are identical for every PHY in the
1872          * package. Some parts are modifying the GPIO register bank which is a
1873          * set of registers that are affecting all PHYs, a few resetting the
1874          * microprocessor common to all PHYs.
1875          * All PHYs' interrupts mask register has to be zeroed before enabling
1876          * any PHY's interrupt in this register.
1877          * For all these reasons, we need to do the init sequence once and only
1878          * once whatever is the first PHY in the package that is initialized and
1879          * do the correct init sequence for all PHYs that are package-critical
1880          * in this pre-init function.
1881          */
1882         if (phy_package_init_once(phydev))
1883                 vsc8514_config_pre_init(phydev);
1884
1885         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1886                              MSCC_PHY_PAGE_EXTENDED_GPIO);
1887         if (ret)
1888                 goto err;
1889
1890         val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1891
1892         val &= ~MAC_CFG_MASK;
1893         val |= MAC_CFG_QSGMII;
1894         ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1895         if (ret)
1896                 goto err;
1897
1898         ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1899                              MSCC_PHY_PAGE_STANDARD);
1900         if (ret)
1901                 goto err;
1902
1903         ret = vsc8584_cmd(phydev,
1904                           PROC_CMD_MCB_ACCESS_MAC_CONF |
1905                           PROC_CMD_RST_CONF_PORT |
1906                           PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
1907         if (ret)
1908                 goto err;
1909
1910         /* 6g mcb */
1911         phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1912         /* lcpll mcb */
1913         phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1914         /* pll5gcfg0 */
1915         ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1916                                 PHY_S6G_PLL5G_CFG0, 0x7036f145);
1917         if (ret)
1918                 goto err;
1919
1920         phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1921         /* pllcfg */
1922         ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1923                                 PHY_S6G_PLL_CFG,
1924                                 (3 << PHY_S6G_PLL_ENA_OFFS_POS) |
1925                                 (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS)
1926                                 | (0 << PHY_S6G_PLL_FSM_ENA_POS));
1927         if (ret)
1928                 goto err;
1929
1930         /* commoncfg */
1931         ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1932                                 PHY_S6G_COMMON_CFG,
1933                                 (0 << PHY_S6G_SYS_RST_POS) |
1934                                 (0 << PHY_S6G_ENA_LANE_POS) |
1935                                 (0 << PHY_S6G_ENA_LOOP_POS) |
1936                                 (0 << PHY_S6G_QRATE_POS) |
1937                                 (3 << PHY_S6G_IF_MODE_POS));
1938         if (ret)
1939                 goto err;
1940
1941         /* misccfg */
1942         ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1943                                 PHY_S6G_MISC_CFG, 1);
1944         if (ret)
1945                 goto err;
1946
1947         /* gpcfg */
1948         ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1949                                 PHY_S6G_GPC_CFG, 768);
1950         if (ret)
1951                 goto err;
1952
1953         phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0);
1954
1955         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1956         do {
1957                 usleep_range(500, 1000);
1958                 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1959                                    0); /* read 6G MCB into CSRs */
1960                 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1961                                        PHY_S6G_PLL_STATUS);
1962                 if (reg == 0xffffffff) {
1963                         phy_unlock_mdio_bus(phydev);
1964                         return -EIO;
1965                 }
1966
1967         } while (time_before(jiffies, deadline) && (reg & BIT(12)));
1968
1969         if (reg & BIT(12)) {
1970                 phy_unlock_mdio_bus(phydev);
1971                 return -ETIMEDOUT;
1972         }
1973
1974         /* misccfg */
1975         ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1976                                 PHY_S6G_MISC_CFG, 0);
1977         if (ret)
1978                 goto err;
1979
1980         phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1981
1982         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1983         do {
1984                 usleep_range(500, 1000);
1985                 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1986                                    0); /* read 6G MCB into CSRs */
1987                 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1988                                        PHY_S6G_IB_STATUS0);
1989                 if (reg == 0xffffffff) {
1990                         phy_unlock_mdio_bus(phydev);
1991                         return -EIO;
1992                 }
1993
1994         } while (time_before(jiffies, deadline) && !(reg & BIT(8)));
1995
1996         if (!(reg & BIT(8))) {
1997                 phy_unlock_mdio_bus(phydev);
1998                 return -ETIMEDOUT;
1999         }
2000
2001         phy_unlock_mdio_bus(phydev);
2002
2003         ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
2004                          MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
2005
2006         if (ret)
2007                 return ret;
2008
2009         ret = genphy_soft_reset(phydev);
2010
2011         if (ret)
2012                 return ret;
2013
2014         for (i = 0; i < vsc8531->nleds; i++) {
2015                 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
2016                 if (ret)
2017                         return ret;
2018         }
2019
2020         return ret;
2021
2022 err:
2023         phy_unlock_mdio_bus(phydev);
2024         return ret;
2025 }
2026
2027 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
2028 {
2029         int rc = 0;
2030
2031         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
2032                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2033
2034         return (rc < 0) ? rc : 0;
2035 }
2036
2037 static int vsc85xx_config_intr(struct phy_device *phydev)
2038 {
2039         int rc;
2040
2041         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2042                 vsc8584_config_macsec_intr(phydev);
2043                 vsc8584_config_ts_intr(phydev);
2044
2045                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
2046                                MII_VSC85XX_INT_MASK_MASK);
2047         } else {
2048                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
2049                 if (rc < 0)
2050                         return rc;
2051                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2052         }
2053
2054         return rc;
2055 }
2056
2057 static int vsc85xx_config_aneg(struct phy_device *phydev)
2058 {
2059         int rc;
2060
2061         rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
2062         if (rc < 0)
2063                 return rc;
2064
2065         return genphy_config_aneg(phydev);
2066 }
2067
2068 static int vsc85xx_read_status(struct phy_device *phydev)
2069 {
2070         int rc;
2071
2072         rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
2073         if (rc < 0)
2074                 return rc;
2075
2076         return genphy_read_status(phydev);
2077 }
2078
2079 static int vsc8514_probe(struct phy_device *phydev)
2080 {
2081         struct vsc8531_private *vsc8531;
2082         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2083            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2084            VSC8531_DUPLEX_COLLISION};
2085
2086         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2087         if (!vsc8531)
2088                 return -ENOMEM;
2089
2090         phydev->priv = vsc8531;
2091
2092         vsc8584_get_base_addr(phydev);
2093         devm_phy_package_join(&phydev->mdio.dev, phydev,
2094                               vsc8531->base_addr, 0);
2095
2096         vsc8531->nleds = 4;
2097         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2098         vsc8531->hw_stats = vsc85xx_hw_stats;
2099         vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2100         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2101                                       sizeof(u64), GFP_KERNEL);
2102         if (!vsc8531->stats)
2103                 return -ENOMEM;
2104
2105         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2106 }
2107
2108 static int vsc8574_probe(struct phy_device *phydev)
2109 {
2110         struct vsc8531_private *vsc8531;
2111         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2112            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2113            VSC8531_DUPLEX_COLLISION};
2114
2115         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2116         if (!vsc8531)
2117                 return -ENOMEM;
2118
2119         phydev->priv = vsc8531;
2120
2121         vsc8584_get_base_addr(phydev);
2122         devm_phy_package_join(&phydev->mdio.dev, phydev,
2123                               vsc8531->base_addr, 0);
2124
2125         vsc8531->nleds = 4;
2126         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2127         vsc8531->hw_stats = vsc8584_hw_stats;
2128         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2129         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2130                                       sizeof(u64), GFP_KERNEL);
2131         if (!vsc8531->stats)
2132                 return -ENOMEM;
2133
2134         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2135 }
2136
2137 static int vsc8584_probe(struct phy_device *phydev)
2138 {
2139         struct vsc8531_private *vsc8531;
2140         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2141            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2142            VSC8531_DUPLEX_COLLISION};
2143         int ret;
2144
2145         if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2146                 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2147                 return -ENOTSUPP;
2148         }
2149
2150         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2151         if (!vsc8531)
2152                 return -ENOMEM;
2153
2154         phydev->priv = vsc8531;
2155
2156         vsc8584_get_base_addr(phydev);
2157         devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2158                               sizeof(struct vsc85xx_shared_private));
2159
2160         vsc8531->nleds = 4;
2161         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2162         vsc8531->hw_stats = vsc8584_hw_stats;
2163         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2164         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2165                                       sizeof(u64), GFP_KERNEL);
2166         if (!vsc8531->stats)
2167                 return -ENOMEM;
2168
2169         if (phy_package_probe_once(phydev)) {
2170                 ret = vsc8584_ptp_probe_once(phydev);
2171                 if (ret)
2172                         return ret;
2173         }
2174
2175         ret = vsc8584_ptp_probe(phydev);
2176         if (ret)
2177                 return ret;
2178
2179         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2180 }
2181
2182 static int vsc85xx_probe(struct phy_device *phydev)
2183 {
2184         struct vsc8531_private *vsc8531;
2185         int rate_magic;
2186         u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2187            VSC8531_LINK_100_ACTIVITY};
2188
2189         rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2190         if (rate_magic < 0)
2191                 return rate_magic;
2192
2193         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2194         if (!vsc8531)
2195                 return -ENOMEM;
2196
2197         phydev->priv = vsc8531;
2198
2199         vsc8531->rate_magic = rate_magic;
2200         vsc8531->nleds = 2;
2201         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2202         vsc8531->hw_stats = vsc85xx_hw_stats;
2203         vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2204         vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2205                                       sizeof(u64), GFP_KERNEL);
2206         if (!vsc8531->stats)
2207                 return -ENOMEM;
2208
2209         return vsc85xx_dt_led_modes_get(phydev, default_mode);
2210 }
2211
2212 /* Microsemi VSC85xx PHYs */
2213 static struct phy_driver vsc85xx_driver[] = {
2214 {
2215         .phy_id         = PHY_ID_VSC8502,
2216         .name           = "Microsemi GE VSC8502 SyncE",
2217         .phy_id_mask    = 0xfffffff0,
2218         /* PHY_BASIC_FEATURES */
2219         .soft_reset     = &genphy_soft_reset,
2220         .config_init    = &vsc85xx_config_init,
2221         .config_aneg    = &vsc85xx_config_aneg,
2222         .read_status    = &vsc85xx_read_status,
2223         .ack_interrupt  = &vsc85xx_ack_interrupt,
2224         .config_intr    = &vsc85xx_config_intr,
2225         .suspend        = &genphy_suspend,
2226         .resume         = &genphy_resume,
2227         .probe          = &vsc85xx_probe,
2228         .set_wol        = &vsc85xx_wol_set,
2229         .get_wol        = &vsc85xx_wol_get,
2230         .get_tunable    = &vsc85xx_get_tunable,
2231         .set_tunable    = &vsc85xx_set_tunable,
2232         .read_page      = &vsc85xx_phy_read_page,
2233         .write_page     = &vsc85xx_phy_write_page,
2234         .get_sset_count = &vsc85xx_get_sset_count,
2235         .get_strings    = &vsc85xx_get_strings,
2236         .get_stats      = &vsc85xx_get_stats,
2237 },
2238 {
2239         .phy_id         = PHY_ID_VSC8504,
2240         .name           = "Microsemi GE VSC8504 SyncE",
2241         .phy_id_mask    = 0xfffffff0,
2242         /* PHY_GBIT_FEATURES */
2243         .soft_reset     = &genphy_soft_reset,
2244         .config_init    = &vsc8584_config_init,
2245         .config_aneg    = &vsc85xx_config_aneg,
2246         .aneg_done      = &genphy_aneg_done,
2247         .read_status    = &vsc85xx_read_status,
2248         .ack_interrupt  = &vsc85xx_ack_interrupt,
2249         .config_intr    = &vsc85xx_config_intr,
2250         .did_interrupt  = &vsc8584_did_interrupt,
2251         .suspend        = &genphy_suspend,
2252         .resume         = &genphy_resume,
2253         .probe          = &vsc8574_probe,
2254         .set_wol        = &vsc85xx_wol_set,
2255         .get_wol        = &vsc85xx_wol_get,
2256         .get_tunable    = &vsc85xx_get_tunable,
2257         .set_tunable    = &vsc85xx_set_tunable,
2258         .read_page      = &vsc85xx_phy_read_page,
2259         .write_page     = &vsc85xx_phy_write_page,
2260         .get_sset_count = &vsc85xx_get_sset_count,
2261         .get_strings    = &vsc85xx_get_strings,
2262         .get_stats      = &vsc85xx_get_stats,
2263 },
2264 {
2265         .phy_id         = PHY_ID_VSC8514,
2266         .name           = "Microsemi GE VSC8514 SyncE",
2267         .phy_id_mask    = 0xfffffff0,
2268         .soft_reset     = &genphy_soft_reset,
2269         .config_init    = &vsc8514_config_init,
2270         .config_aneg    = &vsc85xx_config_aneg,
2271         .read_status    = &vsc85xx_read_status,
2272         .ack_interrupt  = &vsc85xx_ack_interrupt,
2273         .config_intr    = &vsc85xx_config_intr,
2274         .suspend        = &genphy_suspend,
2275         .resume         = &genphy_resume,
2276         .probe          = &vsc8514_probe,
2277         .set_wol        = &vsc85xx_wol_set,
2278         .get_wol        = &vsc85xx_wol_get,
2279         .get_tunable    = &vsc85xx_get_tunable,
2280         .set_tunable    = &vsc85xx_set_tunable,
2281         .read_page      = &vsc85xx_phy_read_page,
2282         .write_page     = &vsc85xx_phy_write_page,
2283         .get_sset_count = &vsc85xx_get_sset_count,
2284         .get_strings    = &vsc85xx_get_strings,
2285         .get_stats      = &vsc85xx_get_stats,
2286 },
2287 {
2288         .phy_id         = PHY_ID_VSC8530,
2289         .name           = "Microsemi FE VSC8530",
2290         .phy_id_mask    = 0xfffffff0,
2291         /* PHY_BASIC_FEATURES */
2292         .soft_reset     = &genphy_soft_reset,
2293         .config_init    = &vsc85xx_config_init,
2294         .config_aneg    = &vsc85xx_config_aneg,
2295         .read_status    = &vsc85xx_read_status,
2296         .ack_interrupt  = &vsc85xx_ack_interrupt,
2297         .config_intr    = &vsc85xx_config_intr,
2298         .suspend        = &genphy_suspend,
2299         .resume         = &genphy_resume,
2300         .probe          = &vsc85xx_probe,
2301         .set_wol        = &vsc85xx_wol_set,
2302         .get_wol        = &vsc85xx_wol_get,
2303         .get_tunable    = &vsc85xx_get_tunable,
2304         .set_tunable    = &vsc85xx_set_tunable,
2305         .read_page      = &vsc85xx_phy_read_page,
2306         .write_page     = &vsc85xx_phy_write_page,
2307         .get_sset_count = &vsc85xx_get_sset_count,
2308         .get_strings    = &vsc85xx_get_strings,
2309         .get_stats      = &vsc85xx_get_stats,
2310 },
2311 {
2312         .phy_id         = PHY_ID_VSC8531,
2313         .name           = "Microsemi VSC8531",
2314         .phy_id_mask    = 0xfffffff0,
2315         /* PHY_GBIT_FEATURES */
2316         .soft_reset     = &genphy_soft_reset,
2317         .config_init    = &vsc85xx_config_init,
2318         .config_aneg    = &vsc85xx_config_aneg,
2319         .read_status    = &vsc85xx_read_status,
2320         .ack_interrupt  = &vsc85xx_ack_interrupt,
2321         .config_intr    = &vsc85xx_config_intr,
2322         .suspend        = &genphy_suspend,
2323         .resume         = &genphy_resume,
2324         .probe          = &vsc85xx_probe,
2325         .set_wol        = &vsc85xx_wol_set,
2326         .get_wol        = &vsc85xx_wol_get,
2327         .get_tunable    = &vsc85xx_get_tunable,
2328         .set_tunable    = &vsc85xx_set_tunable,
2329         .read_page      = &vsc85xx_phy_read_page,
2330         .write_page     = &vsc85xx_phy_write_page,
2331         .get_sset_count = &vsc85xx_get_sset_count,
2332         .get_strings    = &vsc85xx_get_strings,
2333         .get_stats      = &vsc85xx_get_stats,
2334 },
2335 {
2336         .phy_id         = PHY_ID_VSC8540,
2337         .name           = "Microsemi FE VSC8540 SyncE",
2338         .phy_id_mask    = 0xfffffff0,
2339         /* PHY_BASIC_FEATURES */
2340         .soft_reset     = &genphy_soft_reset,
2341         .config_init    = &vsc85xx_config_init,
2342         .config_aneg    = &vsc85xx_config_aneg,
2343         .read_status    = &vsc85xx_read_status,
2344         .ack_interrupt  = &vsc85xx_ack_interrupt,
2345         .config_intr    = &vsc85xx_config_intr,
2346         .suspend        = &genphy_suspend,
2347         .resume         = &genphy_resume,
2348         .probe          = &vsc85xx_probe,
2349         .set_wol        = &vsc85xx_wol_set,
2350         .get_wol        = &vsc85xx_wol_get,
2351         .get_tunable    = &vsc85xx_get_tunable,
2352         .set_tunable    = &vsc85xx_set_tunable,
2353         .read_page      = &vsc85xx_phy_read_page,
2354         .write_page     = &vsc85xx_phy_write_page,
2355         .get_sset_count = &vsc85xx_get_sset_count,
2356         .get_strings    = &vsc85xx_get_strings,
2357         .get_stats      = &vsc85xx_get_stats,
2358 },
2359 {
2360         .phy_id         = PHY_ID_VSC8541,
2361         .name           = "Microsemi VSC8541 SyncE",
2362         .phy_id_mask    = 0xfffffff0,
2363         /* PHY_GBIT_FEATURES */
2364         .soft_reset     = &genphy_soft_reset,
2365         .config_init    = &vsc85xx_config_init,
2366         .config_aneg    = &vsc85xx_config_aneg,
2367         .read_status    = &vsc85xx_read_status,
2368         .ack_interrupt  = &vsc85xx_ack_interrupt,
2369         .config_intr    = &vsc85xx_config_intr,
2370         .suspend        = &genphy_suspend,
2371         .resume         = &genphy_resume,
2372         .probe          = &vsc85xx_probe,
2373         .set_wol        = &vsc85xx_wol_set,
2374         .get_wol        = &vsc85xx_wol_get,
2375         .get_tunable    = &vsc85xx_get_tunable,
2376         .set_tunable    = &vsc85xx_set_tunable,
2377         .read_page      = &vsc85xx_phy_read_page,
2378         .write_page     = &vsc85xx_phy_write_page,
2379         .get_sset_count = &vsc85xx_get_sset_count,
2380         .get_strings    = &vsc85xx_get_strings,
2381         .get_stats      = &vsc85xx_get_stats,
2382 },
2383 {
2384         .phy_id         = PHY_ID_VSC8552,
2385         .name           = "Microsemi GE VSC8552 SyncE",
2386         .phy_id_mask    = 0xfffffff0,
2387         /* PHY_GBIT_FEATURES */
2388         .soft_reset     = &genphy_soft_reset,
2389         .config_init    = &vsc8584_config_init,
2390         .config_aneg    = &vsc85xx_config_aneg,
2391         .read_status    = &vsc85xx_read_status,
2392         .ack_interrupt  = &vsc85xx_ack_interrupt,
2393         .config_intr    = &vsc85xx_config_intr,
2394         .did_interrupt  = &vsc8584_did_interrupt,
2395         .suspend        = &genphy_suspend,
2396         .resume         = &genphy_resume,
2397         .probe          = &vsc8574_probe,
2398         .set_wol        = &vsc85xx_wol_set,
2399         .get_wol        = &vsc85xx_wol_get,
2400         .get_tunable    = &vsc85xx_get_tunable,
2401         .set_tunable    = &vsc85xx_set_tunable,
2402         .read_page      = &vsc85xx_phy_read_page,
2403         .write_page     = &vsc85xx_phy_write_page,
2404         .get_sset_count = &vsc85xx_get_sset_count,
2405         .get_strings    = &vsc85xx_get_strings,
2406         .get_stats      = &vsc85xx_get_stats,
2407 },
2408 {
2409         .phy_id         = PHY_ID_VSC856X,
2410         .name           = "Microsemi GE VSC856X SyncE",
2411         .phy_id_mask    = 0xfffffff0,
2412         /* PHY_GBIT_FEATURES */
2413         .soft_reset     = &genphy_soft_reset,
2414         .config_init    = &vsc8584_config_init,
2415         .config_aneg    = &vsc85xx_config_aneg,
2416         .read_status    = &vsc85xx_read_status,
2417         .ack_interrupt  = &vsc85xx_ack_interrupt,
2418         .config_intr    = &vsc85xx_config_intr,
2419         .did_interrupt  = &vsc8584_did_interrupt,
2420         .suspend        = &genphy_suspend,
2421         .resume         = &genphy_resume,
2422         .probe          = &vsc8584_probe,
2423         .get_tunable    = &vsc85xx_get_tunable,
2424         .set_tunable    = &vsc85xx_set_tunable,
2425         .read_page      = &vsc85xx_phy_read_page,
2426         .write_page     = &vsc85xx_phy_write_page,
2427         .get_sset_count = &vsc85xx_get_sset_count,
2428         .get_strings    = &vsc85xx_get_strings,
2429         .get_stats      = &vsc85xx_get_stats,
2430 },
2431 {
2432         .phy_id         = PHY_ID_VSC8572,
2433         .name           = "Microsemi GE VSC8572 SyncE",
2434         .phy_id_mask    = 0xfffffff0,
2435         /* PHY_GBIT_FEATURES */
2436         .soft_reset     = &genphy_soft_reset,
2437         .config_init    = &vsc8584_config_init,
2438         .config_aneg    = &vsc85xx_config_aneg,
2439         .aneg_done      = &genphy_aneg_done,
2440         .read_status    = &vsc85xx_read_status,
2441         .handle_interrupt = &vsc8584_handle_interrupt,
2442         .ack_interrupt  = &vsc85xx_ack_interrupt,
2443         .config_intr    = &vsc85xx_config_intr,
2444         .did_interrupt  = &vsc8584_did_interrupt,
2445         .suspend        = &genphy_suspend,
2446         .resume         = &genphy_resume,
2447         .probe          = &vsc8574_probe,
2448         .set_wol        = &vsc85xx_wol_set,
2449         .get_wol        = &vsc85xx_wol_get,
2450         .get_tunable    = &vsc85xx_get_tunable,
2451         .set_tunable    = &vsc85xx_set_tunable,
2452         .read_page      = &vsc85xx_phy_read_page,
2453         .write_page     = &vsc85xx_phy_write_page,
2454         .get_sset_count = &vsc85xx_get_sset_count,
2455         .get_strings    = &vsc85xx_get_strings,
2456         .get_stats      = &vsc85xx_get_stats,
2457 },
2458 {
2459         .phy_id         = PHY_ID_VSC8574,
2460         .name           = "Microsemi GE VSC8574 SyncE",
2461         .phy_id_mask    = 0xfffffff0,
2462         /* PHY_GBIT_FEATURES */
2463         .soft_reset     = &genphy_soft_reset,
2464         .config_init    = &vsc8584_config_init,
2465         .config_aneg    = &vsc85xx_config_aneg,
2466         .aneg_done      = &genphy_aneg_done,
2467         .read_status    = &vsc85xx_read_status,
2468         .ack_interrupt  = &vsc85xx_ack_interrupt,
2469         .config_intr    = &vsc85xx_config_intr,
2470         .did_interrupt  = &vsc8584_did_interrupt,
2471         .suspend        = &genphy_suspend,
2472         .resume         = &genphy_resume,
2473         .probe          = &vsc8574_probe,
2474         .set_wol        = &vsc85xx_wol_set,
2475         .get_wol        = &vsc85xx_wol_get,
2476         .get_tunable    = &vsc85xx_get_tunable,
2477         .set_tunable    = &vsc85xx_set_tunable,
2478         .read_page      = &vsc85xx_phy_read_page,
2479         .write_page     = &vsc85xx_phy_write_page,
2480         .get_sset_count = &vsc85xx_get_sset_count,
2481         .get_strings    = &vsc85xx_get_strings,
2482         .get_stats      = &vsc85xx_get_stats,
2483 },
2484 {
2485         .phy_id         = PHY_ID_VSC8575,
2486         .name           = "Microsemi GE VSC8575 SyncE",
2487         .phy_id_mask    = 0xfffffff0,
2488         /* PHY_GBIT_FEATURES */
2489         .soft_reset     = &genphy_soft_reset,
2490         .config_init    = &vsc8584_config_init,
2491         .config_aneg    = &vsc85xx_config_aneg,
2492         .aneg_done      = &genphy_aneg_done,
2493         .read_status    = &vsc85xx_read_status,
2494         .handle_interrupt = &vsc8584_handle_interrupt,
2495         .ack_interrupt  = &vsc85xx_ack_interrupt,
2496         .config_intr    = &vsc85xx_config_intr,
2497         .did_interrupt  = &vsc8584_did_interrupt,
2498         .suspend        = &genphy_suspend,
2499         .resume         = &genphy_resume,
2500         .probe          = &vsc8584_probe,
2501         .get_tunable    = &vsc85xx_get_tunable,
2502         .set_tunable    = &vsc85xx_set_tunable,
2503         .read_page      = &vsc85xx_phy_read_page,
2504         .write_page     = &vsc85xx_phy_write_page,
2505         .get_sset_count = &vsc85xx_get_sset_count,
2506         .get_strings    = &vsc85xx_get_strings,
2507         .get_stats      = &vsc85xx_get_stats,
2508 },
2509 {
2510         .phy_id         = PHY_ID_VSC8582,
2511         .name           = "Microsemi GE VSC8582 SyncE",
2512         .phy_id_mask    = 0xfffffff0,
2513         /* PHY_GBIT_FEATURES */
2514         .soft_reset     = &genphy_soft_reset,
2515         .config_init    = &vsc8584_config_init,
2516         .config_aneg    = &vsc85xx_config_aneg,
2517         .aneg_done      = &genphy_aneg_done,
2518         .read_status    = &vsc85xx_read_status,
2519         .handle_interrupt = &vsc8584_handle_interrupt,
2520         .ack_interrupt  = &vsc85xx_ack_interrupt,
2521         .config_intr    = &vsc85xx_config_intr,
2522         .did_interrupt  = &vsc8584_did_interrupt,
2523         .suspend        = &genphy_suspend,
2524         .resume         = &genphy_resume,
2525         .probe          = &vsc8584_probe,
2526         .get_tunable    = &vsc85xx_get_tunable,
2527         .set_tunable    = &vsc85xx_set_tunable,
2528         .read_page      = &vsc85xx_phy_read_page,
2529         .write_page     = &vsc85xx_phy_write_page,
2530         .get_sset_count = &vsc85xx_get_sset_count,
2531         .get_strings    = &vsc85xx_get_strings,
2532         .get_stats      = &vsc85xx_get_stats,
2533 },
2534 {
2535         .phy_id         = PHY_ID_VSC8584,
2536         .name           = "Microsemi GE VSC8584 SyncE",
2537         .phy_id_mask    = 0xfffffff0,
2538         /* PHY_GBIT_FEATURES */
2539         .soft_reset     = &genphy_soft_reset,
2540         .config_init    = &vsc8584_config_init,
2541         .config_aneg    = &vsc85xx_config_aneg,
2542         .aneg_done      = &genphy_aneg_done,
2543         .read_status    = &vsc85xx_read_status,
2544         .handle_interrupt = &vsc8584_handle_interrupt,
2545         .ack_interrupt  = &vsc85xx_ack_interrupt,
2546         .config_intr    = &vsc85xx_config_intr,
2547         .did_interrupt  = &vsc8584_did_interrupt,
2548         .suspend        = &genphy_suspend,
2549         .resume         = &genphy_resume,
2550         .probe          = &vsc8584_probe,
2551         .get_tunable    = &vsc85xx_get_tunable,
2552         .set_tunable    = &vsc85xx_set_tunable,
2553         .read_page      = &vsc85xx_phy_read_page,
2554         .write_page     = &vsc85xx_phy_write_page,
2555         .get_sset_count = &vsc85xx_get_sset_count,
2556         .get_strings    = &vsc85xx_get_strings,
2557         .get_stats      = &vsc85xx_get_stats,
2558         .link_change_notify = &vsc85xx_link_change_notify,
2559 }
2560
2561 };
2562
2563 module_phy_driver(vsc85xx_driver);
2564
2565 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2566         { PHY_ID_VSC8504, 0xfffffff0, },
2567         { PHY_ID_VSC8514, 0xfffffff0, },
2568         { PHY_ID_VSC8530, 0xfffffff0, },
2569         { PHY_ID_VSC8531, 0xfffffff0, },
2570         { PHY_ID_VSC8540, 0xfffffff0, },
2571         { PHY_ID_VSC8541, 0xfffffff0, },
2572         { PHY_ID_VSC8552, 0xfffffff0, },
2573         { PHY_ID_VSC856X, 0xfffffff0, },
2574         { PHY_ID_VSC8572, 0xfffffff0, },
2575         { PHY_ID_VSC8574, 0xfffffff0, },
2576         { PHY_ID_VSC8575, 0xfffffff0, },
2577         { PHY_ID_VSC8582, 0xfffffff0, },
2578         { PHY_ID_VSC8584, 0xfffffff0, },
2579         { }
2580 };
2581
2582 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2583
2584 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2585 MODULE_AUTHOR("Nagaraju Lakkaraju");
2586 MODULE_LICENSE("Dual MIT/GPL");
2587
2588 /*(DEBLOBBED)*/