drivers/net/phy/microchip_t1s.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Microchip 10BASE-T1S PHYs
   4  *
   5  * Support: Microchip Phys:
   6  *  lan8670/1/2 Rev.B1
   7  *  lan8650/1 Rev.B0 Internal PHYs
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/phy.h>
  13
  14 #define PHY_ID_LAN867X_REVB1 0x0007C162
  15 #define PHY_ID_LAN865X_REVB0 0x0007C1B3
  16
  17 #define LAN867X_REG_STS2 0x0019
  18
  19 #define LAN867x_RESET_COMPLETE_STS BIT(11)
  20
  21 #define LAN865X_REG_CFGPARAM_ADDR 0x00D8
  22 #define LAN865X_REG_CFGPARAM_DATA 0x00D9
  23 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA
  24 #define LAN865X_REG_STS2 0x0019
  25
  26 #define LAN865X_CFGPARAM_READ_ENABLE BIT(1)
  27
  28 /* The arrays below are pulled from the following table from AN1699
  29  * Access MMD Address Value Mask
  30  * RMW 0x1F 0x00D0 0x0002 0x0E03
  31  * RMW 0x1F 0x00D1 0x0000 0x0300
  32  * RMW 0x1F 0x0084 0x3380 0xFFC0
  33  * RMW 0x1F 0x0085 0x0006 0x000F
  34  * RMW 0x1F 0x008A 0xC000 0xF800
  35  * RMW 0x1F 0x0087 0x801C 0x801C
  36  * RMW 0x1F 0x0088 0x033F 0x1FFF
  37  * W   0x1F 0x008B 0x0404 ------
  38  * RMW 0x1F 0x0080 0x0600 0x0600
  39  * RMW 0x1F 0x00F1 0x2400 0x7F00
  40  * RMW 0x1F 0x0096 0x2000 0x2000
  41  * W   0x1F 0x0099 0x7F80 ------
  42  */
  43
  44 static const u32 lan867x_revb1_fixup_registers[12] = {
  45         0x00D0, 0x00D1, 0x0084, 0x0085,
  46         0x008A, 0x0087, 0x0088, 0x008B,
  47         0x0080, 0x00F1, 0x0096, 0x0099,
  48 };
  49
  50 static const u16 lan867x_revb1_fixup_values[12] = {
  51         0x0002, 0x0000, 0x3380, 0x0006,
  52         0xC000, 0x801C, 0x033F, 0x0404,
  53         0x0600, 0x2400, 0x2000, 0x7F80,
  54 };
  55
  56 static const u16 lan867x_revb1_fixup_masks[12] = {
  57         0x0E03, 0x0300, 0xFFC0, 0x000F,
  58         0xF800, 0x801C, 0x1FFF, 0xFFFF,
  59         0x0600, 0x7F00, 0x2000, 0xFFFF,
  60 };
  61
  62 /* LAN865x Rev.B0 configuration parameters from AN1760 */
  63 static const u32 lan865x_revb0_fixup_registers[28] = {
  64         0x0091, 0x0081, 0x0043, 0x0044,
  65         0x0045, 0x0053, 0x0054, 0x0055,
  66         0x0040, 0x0050, 0x00D0, 0x00E9,
  67         0x00F5, 0x00F4, 0x00F8, 0x00F9,
  68         0x00B0, 0x00B1, 0x00B2, 0x00B3,
  69         0x00B4, 0x00B5, 0x00B6, 0x00B7,
  70         0x00B8, 0x00B9, 0x00BA, 0x00BB,
  71 };
  72
  73 static const u16 lan865x_revb0_fixup_values[28] = {
  74         0x9660, 0x00C0, 0x00FF, 0xFFFF,
  75         0x0000, 0x00FF, 0xFFFF, 0x0000,
  76         0x0002, 0x0002, 0x5F21, 0x9E50,
  77         0x1CF8, 0xC020, 0x9B00, 0x4E53,
  78         0x0103, 0x0910, 0x1D26, 0x002A,
  79         0x0103, 0x070D, 0x1720, 0x0027,
  80         0x0509, 0x0E13, 0x1C25, 0x002B,
  81 };
  82
  83 static const u16 lan865x_revb0_fixup_cfg_regs[5] = {
  84         0x0084, 0x008A, 0x00AD, 0x00AE, 0x00AF
  85 };
  86
  87 /* Pulled from AN1760 describing 'indirect read'
  88  *
  89  * write_register(0x4, 0x00D8, addr)
  90  * write_register(0x4, 0x00DA, 0x2)
  91  * return (int8)(read_register(0x4, 0x00D9))
  92  *
  93  * 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2
  94  */
  95 static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr)
  96 {
  97         int ret;
  98
  99         ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR,
 100                             addr);
 101         if (ret)
 102                 return ret;
 103
 104         ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL,
 105                             LAN865X_CFGPARAM_READ_ENABLE);
 106         if (ret)
 107                 return ret;
 108
 109         return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA);
 110 }
 111
 112 /* This is pulled straight from AN1760 from 'calculation of offset 1' &
 113  * 'calculation of offset 2'
 114  */
 115 static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[2])
 116 {
 117         const u16 fixup_regs[2] = {0x0004, 0x0008};
 118         int ret;
 119
 120         for (int i = 0; i < ARRAY_SIZE(fixup_regs); i++) {
 121                 ret = lan865x_revb0_indirect_read(phydev, fixup_regs[i]);
 122                 if (ret < 0)
 123                         return ret;
 124                 if (ret & BIT(4))
 125                         offsets[i] = ret | 0xE0;
 126                 else
 127                         offsets[i] = ret;
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int lan865x_read_cfg_params(struct phy_device *phydev, u16 cfg_params[])
 134 {
 135         int ret;
 136
 137         for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {
 138                 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
 139                                    lan865x_revb0_fixup_cfg_regs[i]);
 140                 if (ret < 0)
 141                         return ret;
 142                 cfg_params[i] = (u16)ret;
 143         }
 144
 145         return 0;
 146 }
 147
 148 static int lan865x_write_cfg_params(struct phy_device *phydev, u16 cfg_params[])
 149 {
 150         int ret;
 151
 152         for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) {
 153                 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
 154                                     lan865x_revb0_fixup_cfg_regs[i],
 155                                     cfg_params[i]);
 156                 if (ret)
 157                         return ret;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int lan865x_setup_cfgparam(struct phy_device *phydev)
 164 {
 165         u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)];
 166         u16 cfg_results[5];
 167         s8 offsets[2];
 168         int ret;
 169
 170         ret = lan865x_generate_cfg_offsets(phydev, offsets);
 171         if (ret)
 172                 return ret;
 173
 174         ret = lan865x_read_cfg_params(phydev, cfg_params);
 175         if (ret)
 176                 return ret;
 177
 178         cfg_results[0] = (cfg_params[0] & 0x000F) |
 179                           FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) |
 180                           FIELD_PREP(GENMASK(15, 4), 14 + offsets[0]);
 181         cfg_results[1] = (cfg_params[1] & 0x03FF) |
 182                           FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]);
 183         cfg_results[2] = (cfg_params[2] & 0xC0C0) |
 184                           FIELD_PREP(GENMASK(15, 8), 5 + offsets[0]) |
 185                           (9 + offsets[0]);
 186         cfg_results[3] = (cfg_params[3] & 0xC0C0) |
 187                           FIELD_PREP(GENMASK(15, 8), 9 + offsets[0]) |
 188                           (14 + offsets[0]);
 189         cfg_results[4] = (cfg_params[4] & 0xC0C0) |
 190                           FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) |
 191                           (22 + offsets[0]);
 192
 193         return lan865x_write_cfg_params(phydev, cfg_results);
 194 }
 195
 196 static int lan865x_revb0_config_init(struct phy_device *phydev)
 197 {
 198         int ret;
 199
 200         /* Reference to AN1760
 201          * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.pdf
 202          */
 203         for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) {
 204                 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
 205                                     lan865x_revb0_fixup_registers[i],
 206                                     lan865x_revb0_fixup_values[i]);
 207                 if (ret)
 208                         return ret;
 209         }
 210         /* Function to calculate and write the configuration parameters in the
 211          * 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF registers (from AN1760)
 212          */
 213         return lan865x_setup_cfgparam(phydev);
 214 }
 215
 216 static int lan867x_revb1_config_init(struct phy_device *phydev)
 217 {
 218         int err;
 219
 220         /* The chip completes a reset in 3us, we might get here earlier than
 221          * that, as an added margin we'll conditionally sleep 5us.
 222          */
 223         err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2);
 224         if (err < 0)
 225                 return err;
 226
 227         if (!(err & LAN867x_RESET_COMPLETE_STS)) {
 228                 udelay(5);
 229                 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2);
 230                 if (err < 0)
 231                         return err;
 232                 if (!(err & LAN867x_RESET_COMPLETE_STS)) {
 233                         phydev_err(phydev, "PHY reset failed\n");
 234                         return -ENODEV;
 235                 }
 236         }
 237
 238         /* Reference to AN1699
 239          * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/ProductDocuments/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf
 240          * AN1699 says Read, Modify, Write, but the Write is not required if the
 241          * register already has the required value. So it is safe to use
 242          * phy_modify_mmd here.
 243          */
 244         for (int i = 0; i < ARRAY_SIZE(lan867x_revb1_fixup_registers); i++) {
 245                 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
 246                                      lan867x_revb1_fixup_registers[i],
 247                                      lan867x_revb1_fixup_masks[i],
 248                                      lan867x_revb1_fixup_values[i]);
 249                 if (err)
 250                         return err;
 251         }
 252
 253         return 0;
 254 }
 255
 256 static int lan86xx_read_status(struct phy_device *phydev)
 257 {
 258         /* The phy has some limitations, namely:
 259          *  - always reports link up
 260          *  - only supports 10MBit half duplex
 261          *  - does not support auto negotiate
 262          */
 263         phydev->link = 1;
 264         phydev->duplex = DUPLEX_HALF;
 265         phydev->speed = SPEED_10;
 266         phydev->autoneg = AUTONEG_DISABLE;
 267
 268         return 0;
 269 }
 270
 271 static struct phy_driver microchip_t1s_driver[] = {
 272         {
 273                 PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1),
 274                 .name               = "LAN867X Rev.B1",
 275                 .features           = PHY_BASIC_T1S_P2MP_FEATURES,
 276                 .config_init        = lan867x_revb1_config_init,
 277                 .read_status        = lan86xx_read_status,
 278                 .get_plca_cfg       = genphy_c45_plca_get_cfg,
 279                 .set_plca_cfg       = genphy_c45_plca_set_cfg,
 280                 .get_plca_status    = genphy_c45_plca_get_status,
 281         },
 282         {
 283                 PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0),
 284                 .name               = "LAN865X Rev.B0 Internal Phy",
 285                 .features           = PHY_BASIC_T1S_P2MP_FEATURES,
 286                 .config_init        = lan865x_revb0_config_init,
 287                 .read_status        = lan86xx_read_status,
 288                 .get_plca_cfg       = genphy_c45_plca_get_cfg,
 289                 .set_plca_cfg       = genphy_c45_plca_set_cfg,
 290                 .get_plca_status    = genphy_c45_plca_get_status,
 291         },
 292 };
 293
 294 module_phy_driver(microchip_t1s_driver);
 295
 296 static struct mdio_device_id __maybe_unused tbl[] = {
 297         { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) },
 298         { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) },
 299         { }
 300 };
 301
 302 MODULE_DEVICE_TABLE(mdio, tbl);
 303
 304 MODULE_DESCRIPTION("Microchip 10BASE-T1S PHYs driver");
 305 MODULE_AUTHOR("Ramón Nordin Rodriguez");
 306 MODULE_LICENSE("GPL");