2 * Copyright (C) 2015 Microchip Technology
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mii.h>
20 #include <linux/ethtool.h>
21 #include <linux/phy.h>
22 #include <linux/microchipphy.h>
23 #include <linux/delay.h>
25 #include <dt-bindings/net/microchip-lan78xx.h>
27 #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
28 #define DRIVER_DESC "Microchip LAN88XX PHY driver"
36 static int lan88xx_read_page(struct phy_device *phydev)
38 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
41 static int lan88xx_write_page(struct phy_device *phydev, int page)
43 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
46 static int lan88xx_phy_config_intr(struct phy_device *phydev)
50 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
51 /* unmask all source and clear them before enable */
52 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
53 rc = phy_read(phydev, LAN88XX_INT_STS);
54 rc = phy_write(phydev, LAN88XX_INT_MASK,
55 LAN88XX_INT_MASK_MDINTPIN_EN_ |
56 LAN88XX_INT_MASK_LINK_CHANGE_);
58 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
61 return rc < 0 ? rc : 0;
64 static int lan88xx_phy_ack_interrupt(struct phy_device *phydev)
66 int rc = phy_read(phydev, LAN88XX_INT_STS);
68 return rc < 0 ? rc : 0;
71 static int lan88xx_suspend(struct phy_device *phydev)
73 struct lan88xx_priv *priv = phydev->priv;
75 /* do not power down PHY when WOL is enabled */
77 genphy_suspend(phydev);
82 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
85 int val, save_page, ret = 0;
88 /* Save current page */
89 save_page = phy_save_page(phydev);
91 pr_warn("Failed to get current page\n");
95 /* Switch to TR page */
96 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
98 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
101 pr_warn("Failed to write TR low data\n");
105 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
106 (data & 0x00FF0000) >> 16);
108 pr_warn("Failed to write TR high data\n");
112 /* Config control bits [15:13] of register */
113 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
114 buf |= 0x8000; /* Set [15] to Packet transmit */
116 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
118 pr_warn("Failed to write data in reg\n");
122 usleep_range(1000, 2000);/* Wait for Data to be written */
123 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
125 pr_warn("TR Register[0x%X] configuration failed\n", regaddr);
127 return phy_restore_page(phydev, save_page, ret);
130 static void lan88xx_config_TR_regs(struct phy_device *phydev)
134 /* Get access to Channel 0x1, Node 0xF , Register 0x01.
135 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
136 * MrvlTrFix1000Kp, MasterEnableTR bits.
138 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
140 pr_warn("Failed to Set Register[0x0F82]\n");
142 /* Get access to Channel b'10, Node b'1101, Register 0x06.
143 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
144 * SSTrKp1000Mas bits.
146 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
148 pr_warn("Failed to Set Register[0x168C]\n");
150 /* Get access to Channel b'10, Node b'1111, Register 0x11.
151 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
154 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
156 pr_warn("Failed to Set Register[0x17A2]\n");
158 /* Get access to Channel b'10, Node b'1101, Register 0x10.
159 * Write 24-bit value 0xEEFFDD to register. Setting
160 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
161 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
163 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
165 pr_warn("Failed to Set Register[0x16A0]\n");
167 /* Get access to Channel b'10, Node b'1101, Register 0x13.
168 * Write 24-bit value 0x071448 to register. Setting
169 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
171 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
173 pr_warn("Failed to Set Register[0x16A6]\n");
175 /* Get access to Channel b'10, Node b'1101, Register 0x12.
176 * Write 24-bit value 0x13132F to register. Setting
177 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
179 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
181 pr_warn("Failed to Set Register[0x16A4]\n");
183 /* Get access to Channel b'10, Node b'1101, Register 0x14.
184 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
185 * eee_TrKf_freeze_delay bits.
187 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
189 pr_warn("Failed to Set Register[0x16A8]\n");
191 /* Get access to Channel b'01, Node b'1111, Register 0x34.
192 * Write 24-bit value 0x91B06C to register. Setting
193 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
194 * FastMseSearchUpdGain1000 bits.
196 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
198 pr_warn("Failed to Set Register[0x0FE8]\n");
200 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
201 * Write 24-bit value 0xC0A028 to register. Setting
202 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
203 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
205 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
207 pr_warn("Failed to Set Register[0x0FFC]\n");
209 /* Get access to Channel b'01, Node b'1111, Register 0x35.
210 * Write 24-bit value 0x041600 to register. Setting
211 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
212 * FastMsePhChangeDelay1000 bits.
214 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
216 pr_warn("Failed to Set Register[0x0FEA]\n");
218 /* Get access to Channel b'10, Node b'1101, Register 0x03.
219 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
221 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
223 pr_warn("Failed to Set Register[0x1686]\n");
226 static int lan88xx_probe(struct phy_device *phydev)
228 struct device *dev = &phydev->mdio.dev;
229 struct lan88xx_priv *priv;
233 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
239 len = of_property_read_variable_u32_array(dev->of_node,
240 "microchip,led-modes",
243 ARRAY_SIZE(led_modes));
248 for (i = 0; i < len; i++) {
249 if (led_modes[i] > 15)
251 reg |= led_modes[i] << (i * 4);
253 for (; i < ARRAY_SIZE(led_modes); i++)
254 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
255 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
256 } else if (len == -EOVERFLOW) {
260 /* these values can be used to identify internal PHY */
261 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
262 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
269 static void lan88xx_remove(struct phy_device *phydev)
271 struct device *dev = &phydev->mdio.dev;
272 struct lan88xx_priv *priv = phydev->priv;
275 devm_kfree(dev, priv);
278 static int lan88xx_set_wol(struct phy_device *phydev,
279 struct ethtool_wolinfo *wol)
281 struct lan88xx_priv *priv = phydev->priv;
283 priv->wolopts = wol->wolopts;
288 static void lan88xx_set_mdix(struct phy_device *phydev)
293 switch (phydev->mdix_ctrl) {
295 val = LAN88XX_EXT_MODE_CTRL_MDI_;
298 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
300 case ETH_TP_MDI_AUTO:
301 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
307 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
308 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
309 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
311 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
315 static int lan88xx_config_init(struct phy_device *phydev)
319 genphy_config_init(phydev);
320 /*Zerodetect delay enable */
321 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
322 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
323 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
325 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
328 /* Config DSP registers */
329 lan88xx_config_TR_regs(phydev);
334 static int lan88xx_config_aneg(struct phy_device *phydev)
336 lan88xx_set_mdix(phydev);
338 return genphy_config_aneg(phydev);
341 static struct phy_driver microchip_phy_driver[] = {
343 .phy_id = 0x0007c130,
344 .phy_id_mask = 0xfffffff0,
345 .name = "Microchip LAN88xx",
347 .features = PHY_GBIT_FEATURES,
348 .flags = PHY_HAS_INTERRUPT,
350 .probe = lan88xx_probe,
351 .remove = lan88xx_remove,
353 .config_init = lan88xx_config_init,
354 .config_aneg = lan88xx_config_aneg,
356 .ack_interrupt = lan88xx_phy_ack_interrupt,
357 .config_intr = lan88xx_phy_config_intr,
359 .suspend = lan88xx_suspend,
360 .resume = genphy_resume,
361 .set_wol = lan88xx_set_wol,
362 .read_page = lan88xx_read_page,
363 .write_page = lan88xx_write_page,
366 module_phy_driver(microchip_phy_driver);
368 static struct mdio_device_id __maybe_unused microchip_tbl[] = {
369 { 0x0007c130, 0xfffffff0 },
373 MODULE_DEVICE_TABLE(mdio, microchip_tbl);
375 MODULE_AUTHOR(DRIVER_AUTHOR);
376 MODULE_DESCRIPTION(DRIVER_DESC);
377 MODULE_LICENSE("GPL");