1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/micrel.c
5 * Driver for Micrel PHYs
7 * Author: David J. Choi
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
18 * Switch : ksz8873, ksz886x
22 #include <linux/bitfield.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/phy.h>
26 #include <linux/micrel_phy.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
31 /* Operation Mode Strap Override */
32 #define MII_KSZPHY_OMSO 0x16
33 #define KSZPHY_OMSO_FACTORY_TEST BIT(15)
34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39 /* general Interrupt control/status reg in vendor specific block. */
40 #define MII_KSZPHY_INTCS 0x1B
41 #define KSZPHY_INTCS_JABBER BIT(15)
42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44 #define KSZPHY_INTCS_PARELLEL BIT(12)
45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48 #define KSZPHY_INTCS_LINK_UP BIT(8)
49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
53 #define MII_KSZPHY_CTRL_1 0x1e
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
56 #define MII_KSZPHY_CTRL_2 0x1f
57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58 /* bitmap of PHY register to set interrupt mode */
59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62 /* Write/read to/from extended registers */
63 #define MII_KSZPHY_EXTREG 0x0b
64 #define KSZPHY_EXTREG_WRITE 0x8000
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
69 /* Extended registers */
70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
76 struct kszphy_hw_stat {
82 static struct kszphy_hw_stat kszphy_hw_stats[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
89 u16 interrupt_level_mask;
90 bool has_broadcast_disable;
91 bool has_nand_tree_disable;
92 bool has_rmii_ref_clk_sel;
96 const struct kszphy_type *type;
98 bool rmii_ref_clk_sel;
99 bool rmii_ref_clk_sel_val;
100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
103 static const struct kszphy_type ksz8021_type = {
104 .led_mode_reg = MII_KSZPHY_CTRL_2,
105 .has_broadcast_disable = true,
106 .has_nand_tree_disable = true,
107 .has_rmii_ref_clk_sel = true,
110 static const struct kszphy_type ksz8041_type = {
111 .led_mode_reg = MII_KSZPHY_CTRL_1,
114 static const struct kszphy_type ksz8051_type = {
115 .led_mode_reg = MII_KSZPHY_CTRL_2,
116 .has_nand_tree_disable = true,
119 static const struct kszphy_type ksz8081_type = {
120 .led_mode_reg = MII_KSZPHY_CTRL_2,
121 .has_broadcast_disable = true,
122 .has_nand_tree_disable = true,
123 .has_rmii_ref_clk_sel = true,
126 static const struct kszphy_type ks8737_type = {
127 .interrupt_level_mask = BIT(14),
130 static const struct kszphy_type ksz9021_type = {
131 .interrupt_level_mask = BIT(14),
134 static int kszphy_extended_write(struct phy_device *phydev,
137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
141 static int kszphy_extended_read(struct phy_device *phydev,
144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
148 static int kszphy_ack_interrupt(struct phy_device *phydev)
150 /* bit[7..0] int status, which is a read and clear register. */
153 rc = phy_read(phydev, MII_KSZPHY_INTCS);
155 return (rc < 0) ? rc : 0;
158 static int kszphy_config_intr(struct phy_device *phydev)
160 const struct kszphy_type *type = phydev->drv->driver_data;
164 if (type && type->interrupt_level_mask)
165 mask = type->interrupt_level_mask;
167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
169 /* set the interrupt pin active low */
170 temp = phy_read(phydev, MII_KSZPHY_CTRL);
174 phy_write(phydev, MII_KSZPHY_CTRL, temp);
176 /* enable / disable interrupts */
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
178 temp = KSZPHY_INTCS_ALL;
182 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
194 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
206 case MII_KSZPHY_CTRL_1:
209 case MII_KSZPHY_CTRL_2:
216 temp = phy_read(phydev, reg);
222 temp &= ~(3 << shift);
223 temp |= val << shift;
224 rc = phy_write(phydev, reg, temp);
227 phydev_err(phydev, "failed to set led mode\n");
232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
235 static int kszphy_broadcast_disable(struct phy_device *phydev)
239 ret = phy_read(phydev, MII_KSZPHY_OMSO);
243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
246 phydev_err(phydev, "failed to disable broadcast address\n");
251 static int kszphy_nand_tree_disable(struct phy_device *phydev)
255 ret = phy_read(phydev, MII_KSZPHY_OMSO);
259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
262 ret = phy_write(phydev, MII_KSZPHY_OMSO,
263 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
266 phydev_err(phydev, "failed to disable NAND tree mode\n");
271 /* Some config bits need to be set again on resume, handle them here. */
272 static int kszphy_config_reset(struct phy_device *phydev)
274 struct kszphy_priv *priv = phydev->priv;
277 if (priv->rmii_ref_clk_sel) {
278 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
281 "failed to set rmii reference clock\n");
286 if (priv->type && priv->led_mode >= 0)
287 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
292 static int kszphy_config_init(struct phy_device *phydev)
294 struct kszphy_priv *priv = phydev->priv;
295 const struct kszphy_type *type;
302 if (type && type->has_broadcast_disable)
303 kszphy_broadcast_disable(phydev);
305 if (type && type->has_nand_tree_disable)
306 kszphy_nand_tree_disable(phydev);
308 return kszphy_config_reset(phydev);
311 static int ksz8041_fiber_mode(struct phy_device *phydev)
313 struct device_node *of_node = phydev->mdio.dev.of_node;
315 return of_property_read_bool(of_node, "micrel,fiber-mode");
318 static int ksz8041_config_init(struct phy_device *phydev)
320 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
322 /* Limit supported and advertised modes in fiber mode */
323 if (ksz8041_fiber_mode(phydev)) {
324 phydev->dev_flags |= MICREL_PHY_FXEN;
325 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
326 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
328 linkmode_and(phydev->supported, phydev->supported, mask);
329 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
331 linkmode_and(phydev->advertising, phydev->advertising, mask);
332 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
333 phydev->advertising);
334 phydev->autoneg = AUTONEG_DISABLE;
337 return kszphy_config_init(phydev);
340 static int ksz8041_config_aneg(struct phy_device *phydev)
342 /* Skip auto-negotiation in fiber mode */
343 if (phydev->dev_flags & MICREL_PHY_FXEN) {
344 phydev->speed = SPEED_100;
348 return genphy_config_aneg(phydev);
351 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
356 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
359 ret = phy_read(phydev, MII_BMSR);
363 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
364 * exact PHY ID. However, they can be told apart by the extended
365 * capability registers presence. The KSZ8051 PHY has them while
366 * the switch does not.
375 static int ksz8051_match_phy_device(struct phy_device *phydev)
377 return ksz8051_ksz8795_match_phy_device(phydev, true);
380 static int ksz8081_config_init(struct phy_device *phydev)
382 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
383 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
384 * pull-down is missing, the factory test mode should be cleared by
385 * manually writing a 0.
387 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
389 return kszphy_config_init(phydev);
392 static int ksz8061_config_init(struct phy_device *phydev)
396 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
400 return kszphy_config_init(phydev);
403 static int ksz8795_match_phy_device(struct phy_device *phydev)
405 return ksz8051_ksz8795_match_phy_device(phydev, false);
408 static int ksz9021_load_values_from_of(struct phy_device *phydev,
409 const struct device_node *of_node,
411 const char *field1, const char *field2,
412 const char *field3, const char *field4)
421 if (!of_property_read_u32(of_node, field1, &val1))
424 if (!of_property_read_u32(of_node, field2, &val2))
427 if (!of_property_read_u32(of_node, field3, &val3))
430 if (!of_property_read_u32(of_node, field4, &val4))
437 newval = kszphy_extended_read(phydev, reg);
442 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
445 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
448 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
451 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
453 return kszphy_extended_write(phydev, reg, newval);
456 static int ksz9021_config_init(struct phy_device *phydev)
458 const struct device *dev = &phydev->mdio.dev;
459 const struct device_node *of_node = dev->of_node;
460 const struct device *dev_walker;
462 /* The Micrel driver has a deprecated option to place phy OF
463 * properties in the MAC node. Walk up the tree of devices to
464 * find a device with an OF node.
466 dev_walker = &phydev->mdio.dev;
468 of_node = dev_walker->of_node;
469 dev_walker = dev_walker->parent;
471 } while (!of_node && dev_walker);
474 ksz9021_load_values_from_of(phydev, of_node,
475 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
476 "txen-skew-ps", "txc-skew-ps",
477 "rxdv-skew-ps", "rxc-skew-ps");
478 ksz9021_load_values_from_of(phydev, of_node,
479 MII_KSZPHY_RX_DATA_PAD_SKEW,
480 "rxd0-skew-ps", "rxd1-skew-ps",
481 "rxd2-skew-ps", "rxd3-skew-ps");
482 ksz9021_load_values_from_of(phydev, of_node,
483 MII_KSZPHY_TX_DATA_PAD_SKEW,
484 "txd0-skew-ps", "txd1-skew-ps",
485 "txd2-skew-ps", "txd3-skew-ps");
490 #define KSZ9031_PS_TO_REG 60
492 /* Extended registers */
493 /* MMD Address 0x0 */
494 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
495 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
497 /* MMD Address 0x2 */
498 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
499 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
500 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
502 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
503 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
504 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
505 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
506 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
508 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
509 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
510 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
511 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
512 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
514 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
515 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
516 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
518 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
519 * provide different RGMII options we need to configure delay offset
520 * for each pad relative to build in delay.
522 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
526 #define RX_CLK_ID 0x19
528 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
529 * internal 1.2ns delay.
532 #define RX_CLK_ND 0x0
534 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
536 #define TX_CLK_ID 0x1f
538 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
542 #define TX_CLK_ND 0xf
544 /* MMD Address 0x1C */
545 #define MII_KSZ9031RN_EDPD 0x23
546 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
548 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
549 const struct device_node *of_node,
550 u16 reg, size_t field_sz,
551 const char *field[], u8 numfields,
554 int val[4] = {-1, -2, -3, -4};
561 for (i = 0; i < numfields; i++)
562 if (!of_property_read_u32(of_node, field[i], val + i))
570 if (matches < numfields)
571 newval = phy_read_mmd(phydev, 2, reg);
575 maxval = (field_sz == 4) ? 0xf : 0x1f;
576 for (i = 0; i < numfields; i++)
577 if (val[i] != -(i + 1)) {
579 mask ^= maxval << (field_sz * i);
580 newval = (newval & mask) |
581 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
585 return phy_write_mmd(phydev, 2, reg, newval);
588 /* Center KSZ9031RNX FLP timing at 16ms. */
589 static int ksz9031_center_flp_timing(struct phy_device *phydev)
593 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
598 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
603 return genphy_restart_aneg(phydev);
606 /* Enable energy-detect power-down mode */
607 static int ksz9031_enable_edpd(struct phy_device *phydev)
611 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
614 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
615 reg | MII_KSZ9031RN_EDPD_ENABLE);
618 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
620 u16 rx, tx, rx_clk, tx_clk;
623 switch (phydev->interface) {
624 case PHY_INTERFACE_MODE_RGMII:
630 case PHY_INTERFACE_MODE_RGMII_ID:
636 case PHY_INTERFACE_MODE_RGMII_RXID:
642 case PHY_INTERFACE_MODE_RGMII_TXID:
652 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
653 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
654 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
658 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
659 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
660 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
661 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
662 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
666 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
667 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
668 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
669 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
670 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
674 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
675 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
676 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
679 static int ksz9031_config_init(struct phy_device *phydev)
681 const struct device *dev = &phydev->mdio.dev;
682 const struct device_node *of_node = dev->of_node;
683 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
684 static const char *rx_data_skews[4] = {
685 "rxd0-skew-ps", "rxd1-skew-ps",
686 "rxd2-skew-ps", "rxd3-skew-ps"
688 static const char *tx_data_skews[4] = {
689 "txd0-skew-ps", "txd1-skew-ps",
690 "txd2-skew-ps", "txd3-skew-ps"
692 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
693 const struct device *dev_walker;
696 result = ksz9031_enable_edpd(phydev);
700 /* The Micrel driver has a deprecated option to place phy OF
701 * properties in the MAC node. Walk up the tree of devices to
702 * find a device with an OF node.
704 dev_walker = &phydev->mdio.dev;
706 of_node = dev_walker->of_node;
707 dev_walker = dev_walker->parent;
708 } while (!of_node && dev_walker);
713 if (phy_interface_is_rgmii(phydev)) {
714 result = ksz9031_config_rgmii_delay(phydev);
719 ksz9031_of_load_skew_values(phydev, of_node,
720 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
721 clk_skews, 2, &update);
723 ksz9031_of_load_skew_values(phydev, of_node,
724 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
725 control_skews, 2, &update);
727 ksz9031_of_load_skew_values(phydev, of_node,
728 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
729 rx_data_skews, 4, &update);
731 ksz9031_of_load_skew_values(phydev, of_node,
732 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
733 tx_data_skews, 4, &update);
735 if (update && !phy_interface_is_rgmii(phydev))
737 "*-skew-ps values should be used only with RGMII PHY modes\n");
739 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
740 * When the device links in the 1000BASE-T slave mode only,
741 * the optional 125MHz reference output clock (CLK125_NDO)
742 * has wide duty cycle variation.
744 * The optional CLK125_NDO clock does not meet the RGMII
745 * 45/55 percent (min/max) duty cycle requirement and therefore
746 * cannot be used directly by the MAC side for clocking
747 * applications that have setup/hold time requirements on
748 * rising and falling clock edges.
751 * Force the phy to be the master to receive a stable clock
752 * which meets the duty cycle requirement.
754 if (of_property_read_bool(of_node, "micrel,force-master")) {
755 result = phy_read(phydev, MII_CTRL1000);
757 goto err_force_master;
759 /* enable master mode, config & prefer master */
760 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
761 result = phy_write(phydev, MII_CTRL1000, result);
763 goto err_force_master;
767 return ksz9031_center_flp_timing(phydev);
770 phydev_err(phydev, "failed to force the phy to master mode\n");
774 #define KSZ9131_SKEW_5BIT_MAX 2400
775 #define KSZ9131_SKEW_4BIT_MAX 800
776 #define KSZ9131_OFFSET 700
777 #define KSZ9131_STEP 100
779 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
780 struct device_node *of_node,
781 u16 reg, size_t field_sz,
782 char *field[], u8 numfields)
784 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
785 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
786 int skewval, skewmax = 0;
793 /* psec properties in dts should mean x pico seconds */
795 skewmax = KSZ9131_SKEW_5BIT_MAX;
797 skewmax = KSZ9131_SKEW_4BIT_MAX;
799 for (i = 0; i < numfields; i++)
800 if (!of_property_read_s32(of_node, field[i], &skewval)) {
801 if (skewval < -KSZ9131_OFFSET)
802 skewval = -KSZ9131_OFFSET;
803 else if (skewval > skewmax)
806 val[i] = skewval + KSZ9131_OFFSET;
813 if (matches < numfields)
814 newval = phy_read_mmd(phydev, 2, reg);
818 maxval = (field_sz == 4) ? 0xf : 0x1f;
819 for (i = 0; i < numfields; i++)
820 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
822 mask ^= maxval << (field_sz * i);
823 newval = (newval & mask) |
824 (((val[i] / KSZ9131_STEP) & maxval)
828 return phy_write_mmd(phydev, 2, reg, newval);
831 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
832 #define KSZ9131RN_RXC_DLL_CTRL 76
833 #define KSZ9131RN_TXC_DLL_CTRL 77
834 #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
835 #define KSZ9131RN_DLL_ENABLE_DELAY 0
836 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
838 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
840 u16 rxcdll_val, txcdll_val;
843 switch (phydev->interface) {
844 case PHY_INTERFACE_MODE_RGMII:
845 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
846 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
848 case PHY_INTERFACE_MODE_RGMII_ID:
849 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
850 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
852 case PHY_INTERFACE_MODE_RGMII_RXID:
853 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
854 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
856 case PHY_INTERFACE_MODE_RGMII_TXID:
857 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
858 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
864 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
865 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
870 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
871 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
875 static int ksz9131_config_init(struct phy_device *phydev)
877 const struct device *dev = &phydev->mdio.dev;
878 struct device_node *of_node = dev->of_node;
879 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
880 char *rx_data_skews[4] = {
881 "rxd0-skew-psec", "rxd1-skew-psec",
882 "rxd2-skew-psec", "rxd3-skew-psec"
884 char *tx_data_skews[4] = {
885 "txd0-skew-psec", "txd1-skew-psec",
886 "txd2-skew-psec", "txd3-skew-psec"
888 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
889 const struct device *dev_walker;
892 dev_walker = &phydev->mdio.dev;
894 of_node = dev_walker->of_node;
895 dev_walker = dev_walker->parent;
896 } while (!of_node && dev_walker);
901 if (phy_interface_is_rgmii(phydev)) {
902 ret = ksz9131_config_rgmii_delay(phydev);
907 ret = ksz9131_of_load_skew_values(phydev, of_node,
908 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
913 ret = ksz9131_of_load_skew_values(phydev, of_node,
914 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
919 ret = ksz9131_of_load_skew_values(phydev, of_node,
920 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
925 ret = ksz9131_of_load_skew_values(phydev, of_node,
926 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
934 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
935 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
936 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
937 static int ksz8873mll_read_status(struct phy_device *phydev)
942 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
944 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
946 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
947 phydev->duplex = DUPLEX_HALF;
949 phydev->duplex = DUPLEX_FULL;
951 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
952 phydev->speed = SPEED_10;
954 phydev->speed = SPEED_100;
957 phydev->pause = phydev->asym_pause = 0;
962 static int ksz9031_get_features(struct phy_device *phydev)
966 ret = genphy_read_abilities(phydev);
970 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
971 * Whenever the device's Asymmetric Pause capability is set to 1,
972 * link-up may fail after a link-up to link-down transition.
974 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
977 * Do not enable the Asymmetric Pause capability bit.
979 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
981 /* We force setting the Pause capability as the core will force the
982 * Asymmetric Pause capability to 1 otherwise.
984 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
989 static int ksz9031_read_status(struct phy_device *phydev)
994 err = genphy_read_status(phydev);
998 /* Make sure the PHY is not broken. Read idle error count,
999 * and reset the PHY if it is maxed out.
1001 regval = phy_read(phydev, MII_STAT1000);
1002 if ((regval & 0xFF) == 0xFF) {
1003 phy_init_hw(phydev);
1005 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1006 phydev->drv->config_intr(phydev);
1007 return genphy_config_aneg(phydev);
1013 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1018 static int kszphy_get_sset_count(struct phy_device *phydev)
1020 return ARRAY_SIZE(kszphy_hw_stats);
1023 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1027 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1028 strlcpy(data + i * ETH_GSTRING_LEN,
1029 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1033 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1035 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1036 struct kszphy_priv *priv = phydev->priv;
1040 val = phy_read(phydev, stat.reg);
1044 val = val & ((1 << stat.bits) - 1);
1045 priv->stats[i] += val;
1046 ret = priv->stats[i];
1052 static void kszphy_get_stats(struct phy_device *phydev,
1053 struct ethtool_stats *stats, u64 *data)
1057 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1058 data[i] = kszphy_get_stat(phydev, i);
1061 static int kszphy_suspend(struct phy_device *phydev)
1063 /* Disable PHY Interrupts */
1064 if (phy_interrupt_is_valid(phydev)) {
1065 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1066 if (phydev->drv->config_intr)
1067 phydev->drv->config_intr(phydev);
1070 return genphy_suspend(phydev);
1073 static int kszphy_resume(struct phy_device *phydev)
1077 genphy_resume(phydev);
1079 /* After switching from power-down to normal mode, an internal global
1080 * reset is automatically generated. Wait a minimum of 1 ms before
1081 * read/write access to the PHY registers.
1083 usleep_range(1000, 2000);
1085 ret = kszphy_config_reset(phydev);
1089 /* Enable PHY Interrupts */
1090 if (phy_interrupt_is_valid(phydev)) {
1091 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1092 if (phydev->drv->config_intr)
1093 phydev->drv->config_intr(phydev);
1099 static int kszphy_probe(struct phy_device *phydev)
1101 const struct kszphy_type *type = phydev->drv->driver_data;
1102 const struct device_node *np = phydev->mdio.dev.of_node;
1103 struct kszphy_priv *priv;
1107 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1111 phydev->priv = priv;
1115 if (type && type->led_mode_reg) {
1116 ret = of_property_read_u32(np, "micrel,led-mode",
1119 priv->led_mode = -1;
1121 if (priv->led_mode > 3) {
1122 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1124 priv->led_mode = -1;
1127 priv->led_mode = -1;
1130 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1131 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1132 if (!IS_ERR_OR_NULL(clk)) {
1133 unsigned long rate = clk_get_rate(clk);
1134 bool rmii_ref_clk_sel_25_mhz;
1137 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1138 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1139 "micrel,rmii-reference-clock-select-25-mhz");
1141 if (rate > 24500000 && rate < 25500000) {
1142 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1143 } else if (rate > 49500000 && rate < 50500000) {
1144 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1146 phydev_err(phydev, "Clock rate out of range: %ld\n",
1152 if (ksz8041_fiber_mode(phydev))
1153 phydev->port = PORT_FIBRE;
1155 /* Support legacy board-file configuration */
1156 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1157 priv->rmii_ref_clk_sel = true;
1158 priv->rmii_ref_clk_sel_val = true;
1164 static struct phy_driver ksphy_driver[] = {
1166 .phy_id = PHY_ID_KS8737,
1167 .phy_id_mask = MICREL_PHY_ID_MASK,
1168 .name = "Micrel KS8737",
1169 /* PHY_BASIC_FEATURES */
1170 .driver_data = &ks8737_type,
1171 .config_init = kszphy_config_init,
1172 .ack_interrupt = kszphy_ack_interrupt,
1173 .config_intr = kszphy_config_intr,
1174 .suspend = genphy_suspend,
1175 .resume = genphy_resume,
1177 .phy_id = PHY_ID_KSZ8021,
1178 .phy_id_mask = 0x00ffffff,
1179 .name = "Micrel KSZ8021 or KSZ8031",
1180 /* PHY_BASIC_FEATURES */
1181 .driver_data = &ksz8021_type,
1182 .probe = kszphy_probe,
1183 .config_init = kszphy_config_init,
1184 .ack_interrupt = kszphy_ack_interrupt,
1185 .config_intr = kszphy_config_intr,
1186 .get_sset_count = kszphy_get_sset_count,
1187 .get_strings = kszphy_get_strings,
1188 .get_stats = kszphy_get_stats,
1189 .suspend = genphy_suspend,
1190 .resume = genphy_resume,
1192 .phy_id = PHY_ID_KSZ8031,
1193 .phy_id_mask = 0x00ffffff,
1194 .name = "Micrel KSZ8031",
1195 /* PHY_BASIC_FEATURES */
1196 .driver_data = &ksz8021_type,
1197 .probe = kszphy_probe,
1198 .config_init = kszphy_config_init,
1199 .ack_interrupt = kszphy_ack_interrupt,
1200 .config_intr = kszphy_config_intr,
1201 .get_sset_count = kszphy_get_sset_count,
1202 .get_strings = kszphy_get_strings,
1203 .get_stats = kszphy_get_stats,
1204 .suspend = genphy_suspend,
1205 .resume = genphy_resume,
1207 .phy_id = PHY_ID_KSZ8041,
1208 .phy_id_mask = MICREL_PHY_ID_MASK,
1209 .name = "Micrel KSZ8041",
1210 /* PHY_BASIC_FEATURES */
1211 .driver_data = &ksz8041_type,
1212 .probe = kszphy_probe,
1213 .config_init = ksz8041_config_init,
1214 .config_aneg = ksz8041_config_aneg,
1215 .ack_interrupt = kszphy_ack_interrupt,
1216 .config_intr = kszphy_config_intr,
1217 .get_sset_count = kszphy_get_sset_count,
1218 .get_strings = kszphy_get_strings,
1219 .get_stats = kszphy_get_stats,
1220 /* No suspend/resume callbacks because of errata DS80000700A,
1221 * receiver error following software power down.
1224 .phy_id = PHY_ID_KSZ8041RNLI,
1225 .phy_id_mask = MICREL_PHY_ID_MASK,
1226 .name = "Micrel KSZ8041RNLI",
1227 /* PHY_BASIC_FEATURES */
1228 .driver_data = &ksz8041_type,
1229 .probe = kszphy_probe,
1230 .config_init = kszphy_config_init,
1231 .ack_interrupt = kszphy_ack_interrupt,
1232 .config_intr = kszphy_config_intr,
1233 .get_sset_count = kszphy_get_sset_count,
1234 .get_strings = kszphy_get_strings,
1235 .get_stats = kszphy_get_stats,
1236 .suspend = genphy_suspend,
1237 .resume = genphy_resume,
1239 .name = "Micrel KSZ8051",
1240 /* PHY_BASIC_FEATURES */
1241 .driver_data = &ksz8051_type,
1242 .probe = kszphy_probe,
1243 .config_init = kszphy_config_init,
1244 .ack_interrupt = kszphy_ack_interrupt,
1245 .config_intr = kszphy_config_intr,
1246 .get_sset_count = kszphy_get_sset_count,
1247 .get_strings = kszphy_get_strings,
1248 .get_stats = kszphy_get_stats,
1249 .match_phy_device = ksz8051_match_phy_device,
1250 .suspend = genphy_suspend,
1251 .resume = genphy_resume,
1253 .phy_id = PHY_ID_KSZ8001,
1254 .name = "Micrel KSZ8001 or KS8721",
1255 .phy_id_mask = 0x00fffffc,
1256 /* PHY_BASIC_FEATURES */
1257 .driver_data = &ksz8041_type,
1258 .probe = kszphy_probe,
1259 .config_init = kszphy_config_init,
1260 .ack_interrupt = kszphy_ack_interrupt,
1261 .config_intr = kszphy_config_intr,
1262 .get_sset_count = kszphy_get_sset_count,
1263 .get_strings = kszphy_get_strings,
1264 .get_stats = kszphy_get_stats,
1265 .suspend = genphy_suspend,
1266 .resume = genphy_resume,
1268 .phy_id = PHY_ID_KSZ8081,
1269 .name = "Micrel KSZ8081 or KSZ8091",
1270 .phy_id_mask = MICREL_PHY_ID_MASK,
1271 /* PHY_BASIC_FEATURES */
1272 .driver_data = &ksz8081_type,
1273 .probe = kszphy_probe,
1274 .config_init = ksz8081_config_init,
1275 .ack_interrupt = kszphy_ack_interrupt,
1276 .soft_reset = genphy_soft_reset,
1277 .config_intr = kszphy_config_intr,
1278 .get_sset_count = kszphy_get_sset_count,
1279 .get_strings = kszphy_get_strings,
1280 .get_stats = kszphy_get_stats,
1281 .suspend = kszphy_suspend,
1282 .resume = kszphy_resume,
1284 .phy_id = PHY_ID_KSZ8061,
1285 .name = "Micrel KSZ8061",
1286 .phy_id_mask = MICREL_PHY_ID_MASK,
1287 /* PHY_BASIC_FEATURES */
1288 .config_init = ksz8061_config_init,
1289 .ack_interrupt = kszphy_ack_interrupt,
1290 .config_intr = kszphy_config_intr,
1291 .suspend = genphy_suspend,
1292 .resume = genphy_resume,
1294 .phy_id = PHY_ID_KSZ9021,
1295 .phy_id_mask = 0x000ffffe,
1296 .name = "Micrel KSZ9021 Gigabit PHY",
1297 /* PHY_GBIT_FEATURES */
1298 .driver_data = &ksz9021_type,
1299 .probe = kszphy_probe,
1300 .get_features = ksz9031_get_features,
1301 .config_init = ksz9021_config_init,
1302 .ack_interrupt = kszphy_ack_interrupt,
1303 .config_intr = kszphy_config_intr,
1304 .get_sset_count = kszphy_get_sset_count,
1305 .get_strings = kszphy_get_strings,
1306 .get_stats = kszphy_get_stats,
1307 .suspend = genphy_suspend,
1308 .resume = genphy_resume,
1309 .read_mmd = genphy_read_mmd_unsupported,
1310 .write_mmd = genphy_write_mmd_unsupported,
1312 .phy_id = PHY_ID_KSZ9031,
1313 .phy_id_mask = MICREL_PHY_ID_MASK,
1314 .name = "Micrel KSZ9031 Gigabit PHY",
1315 .driver_data = &ksz9021_type,
1316 .probe = kszphy_probe,
1317 .get_features = ksz9031_get_features,
1318 .config_init = ksz9031_config_init,
1319 .soft_reset = genphy_soft_reset,
1320 .read_status = ksz9031_read_status,
1321 .ack_interrupt = kszphy_ack_interrupt,
1322 .config_intr = kszphy_config_intr,
1323 .get_sset_count = kszphy_get_sset_count,
1324 .get_strings = kszphy_get_strings,
1325 .get_stats = kszphy_get_stats,
1326 .suspend = genphy_suspend,
1327 .resume = kszphy_resume,
1329 .phy_id = PHY_ID_LAN8814,
1330 .phy_id_mask = MICREL_PHY_ID_MASK,
1331 .name = "Microchip INDY Gigabit Quad PHY",
1332 .driver_data = &ksz9021_type,
1333 .probe = kszphy_probe,
1334 .soft_reset = genphy_soft_reset,
1335 .read_status = ksz9031_read_status,
1336 .get_sset_count = kszphy_get_sset_count,
1337 .get_strings = kszphy_get_strings,
1338 .get_stats = kszphy_get_stats,
1339 .suspend = genphy_suspend,
1340 .resume = kszphy_resume,
1342 .phy_id = PHY_ID_KSZ9131,
1343 .phy_id_mask = MICREL_PHY_ID_MASK,
1344 .name = "Microchip KSZ9131 Gigabit PHY",
1345 /* PHY_GBIT_FEATURES */
1346 .driver_data = &ksz9021_type,
1347 .probe = kszphy_probe,
1348 .config_init = ksz9131_config_init,
1349 .read_status = genphy_read_status,
1350 .ack_interrupt = kszphy_ack_interrupt,
1351 .config_intr = kszphy_config_intr,
1352 .get_sset_count = kszphy_get_sset_count,
1353 .get_strings = kszphy_get_strings,
1354 .get_stats = kszphy_get_stats,
1355 .suspend = genphy_suspend,
1356 .resume = kszphy_resume,
1358 .phy_id = PHY_ID_KSZ8873MLL,
1359 .phy_id_mask = MICREL_PHY_ID_MASK,
1360 .name = "Micrel KSZ8873MLL Switch",
1361 /* PHY_BASIC_FEATURES */
1362 .config_init = kszphy_config_init,
1363 .config_aneg = ksz8873mll_config_aneg,
1364 .read_status = ksz8873mll_read_status,
1365 .suspend = genphy_suspend,
1366 .resume = genphy_resume,
1368 .phy_id = PHY_ID_KSZ886X,
1369 .phy_id_mask = MICREL_PHY_ID_MASK,
1370 .name = "Micrel KSZ886X Switch",
1371 /* PHY_BASIC_FEATURES */
1372 .config_init = kszphy_config_init,
1373 .suspend = genphy_suspend,
1374 .resume = genphy_resume,
1376 .name = "Micrel KSZ87XX Switch",
1377 /* PHY_BASIC_FEATURES */
1378 .config_init = kszphy_config_init,
1379 .match_phy_device = ksz8795_match_phy_device,
1380 .suspend = genphy_suspend,
1381 .resume = genphy_resume,
1383 .phy_id = PHY_ID_KSZ9477,
1384 .phy_id_mask = MICREL_PHY_ID_MASK,
1385 .name = "Microchip KSZ9477",
1386 /* PHY_GBIT_FEATURES */
1387 .config_init = kszphy_config_init,
1388 .suspend = genphy_suspend,
1389 .resume = genphy_resume,
1392 module_phy_driver(ksphy_driver);
1394 MODULE_DESCRIPTION("Micrel PHY driver");
1395 MODULE_AUTHOR("David J. Choi");
1396 MODULE_LICENSE("GPL");
1398 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1399 { PHY_ID_KSZ9021, 0x000ffffe },
1400 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1401 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1402 { PHY_ID_KSZ8001, 0x00fffffc },
1403 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1404 { PHY_ID_KSZ8021, 0x00ffffff },
1405 { PHY_ID_KSZ8031, 0x00ffffff },
1406 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1407 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1408 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1409 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1410 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1411 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1412 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
1416 MODULE_DEVICE_TABLE(mdio, micrel_tbl);