2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/phy.h>
28 #include <linux/micrel_phy.h>
30 #include <linux/clk.h>
31 #include <linux/delay.h>
33 /* Operation Mode Strap Override */
34 #define MII_KSZPHY_OMSO 0x16
35 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
36 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
37 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
38 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
40 /* general Interrupt control/status reg in vendor specific block. */
41 #define MII_KSZPHY_INTCS 0x1B
42 #define KSZPHY_INTCS_JABBER BIT(15)
43 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
44 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
45 #define KSZPHY_INTCS_PARELLEL BIT(12)
46 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
47 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
48 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
49 #define KSZPHY_INTCS_LINK_UP BIT(8)
50 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
51 KSZPHY_INTCS_LINK_DOWN)
54 #define MII_KSZPHY_CTRL_1 0x1e
56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
57 #define MII_KSZPHY_CTRL_2 0x1f
58 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
59 /* bitmap of PHY register to set interrupt mode */
60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
61 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
63 /* Write/read to/from extended registers */
64 #define MII_KSZPHY_EXTREG 0x0b
65 #define KSZPHY_EXTREG_WRITE 0x8000
67 #define MII_KSZPHY_EXTREG_WRITE 0x0c
68 #define MII_KSZPHY_EXTREG_READ 0x0d
70 /* Extended registers */
71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
72 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
73 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
77 struct kszphy_hw_stat {
83 static struct kszphy_hw_stat kszphy_hw_stats[] = {
84 { "phy_receive_errors", 21, 16},
85 { "phy_idle_errors", 10, 8 },
90 u16 interrupt_level_mask;
91 bool has_broadcast_disable;
92 bool has_nand_tree_disable;
93 bool has_rmii_ref_clk_sel;
97 const struct kszphy_type *type;
99 bool rmii_ref_clk_sel;
100 bool rmii_ref_clk_sel_val;
101 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
104 static const struct kszphy_type ksz8021_type = {
105 .led_mode_reg = MII_KSZPHY_CTRL_2,
106 .has_broadcast_disable = true,
107 .has_nand_tree_disable = true,
108 .has_rmii_ref_clk_sel = true,
111 static const struct kszphy_type ksz8041_type = {
112 .led_mode_reg = MII_KSZPHY_CTRL_1,
115 static const struct kszphy_type ksz8051_type = {
116 .led_mode_reg = MII_KSZPHY_CTRL_2,
117 .has_nand_tree_disable = true,
120 static const struct kszphy_type ksz8081_type = {
121 .led_mode_reg = MII_KSZPHY_CTRL_2,
122 .has_broadcast_disable = true,
123 .has_nand_tree_disable = true,
124 .has_rmii_ref_clk_sel = true,
127 static const struct kszphy_type ks8737_type = {
128 .interrupt_level_mask = BIT(14),
131 static const struct kszphy_type ksz9021_type = {
132 .interrupt_level_mask = BIT(14),
135 static int kszphy_extended_write(struct phy_device *phydev,
138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
142 static int kszphy_extended_read(struct phy_device *phydev,
145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
146 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
149 static int kszphy_ack_interrupt(struct phy_device *phydev)
151 /* bit[7..0] int status, which is a read and clear register. */
154 rc = phy_read(phydev, MII_KSZPHY_INTCS);
156 return (rc < 0) ? rc : 0;
159 static int kszphy_config_intr(struct phy_device *phydev)
161 const struct kszphy_type *type = phydev->drv->driver_data;
165 if (type && type->interrupt_level_mask)
166 mask = type->interrupt_level_mask;
168 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
170 /* set the interrupt pin active low */
171 temp = phy_read(phydev, MII_KSZPHY_CTRL);
175 phy_write(phydev, MII_KSZPHY_CTRL, temp);
177 /* enable / disable interrupts */
178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
179 temp = KSZPHY_INTCS_ALL;
183 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
190 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
195 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
197 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
207 case MII_KSZPHY_CTRL_1:
210 case MII_KSZPHY_CTRL_2:
217 temp = phy_read(phydev, reg);
223 temp &= ~(3 << shift);
224 temp |= val << shift;
225 rc = phy_write(phydev, reg, temp);
228 phydev_err(phydev, "failed to set led mode\n");
233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
234 * unique (non-broadcast) address on a shared bus.
236 static int kszphy_broadcast_disable(struct phy_device *phydev)
240 ret = phy_read(phydev, MII_KSZPHY_OMSO);
244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
247 phydev_err(phydev, "failed to disable broadcast address\n");
252 static int kszphy_nand_tree_disable(struct phy_device *phydev)
256 ret = phy_read(phydev, MII_KSZPHY_OMSO);
260 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
263 ret = phy_write(phydev, MII_KSZPHY_OMSO,
264 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
267 phydev_err(phydev, "failed to disable NAND tree mode\n");
272 static int kszphy_config_init(struct phy_device *phydev)
274 struct kszphy_priv *priv = phydev->priv;
275 const struct kszphy_type *type;
283 if (type->has_broadcast_disable)
284 kszphy_broadcast_disable(phydev);
286 if (type->has_nand_tree_disable)
287 kszphy_nand_tree_disable(phydev);
289 if (priv->rmii_ref_clk_sel) {
290 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
293 "failed to set rmii reference clock\n");
298 if (priv->led_mode >= 0)
299 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
301 if (phy_interrupt_is_valid(phydev)) {
302 int ctl = phy_read(phydev, MII_BMCR);
307 ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE);
315 static int ksz8041_config_init(struct phy_device *phydev)
317 struct device_node *of_node = phydev->mdio.dev.of_node;
319 /* Limit supported and advertised modes in fiber mode */
320 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
321 phydev->dev_flags |= MICREL_PHY_FXEN;
322 phydev->supported &= SUPPORTED_100baseT_Full |
323 SUPPORTED_100baseT_Half;
324 phydev->supported |= SUPPORTED_FIBRE;
325 phydev->advertising &= ADVERTISED_100baseT_Full |
326 ADVERTISED_100baseT_Half;
327 phydev->advertising |= ADVERTISED_FIBRE;
328 phydev->autoneg = AUTONEG_DISABLE;
331 return kszphy_config_init(phydev);
334 static int ksz8041_config_aneg(struct phy_device *phydev)
336 /* Skip auto-negotiation in fiber mode */
337 if (phydev->dev_flags & MICREL_PHY_FXEN) {
338 phydev->speed = SPEED_100;
342 return genphy_config_aneg(phydev);
345 static int ksz8061_config_init(struct phy_device *phydev)
349 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
353 return kszphy_config_init(phydev);
356 static int ksz9021_load_values_from_of(struct phy_device *phydev,
357 const struct device_node *of_node,
359 const char *field1, const char *field2,
360 const char *field3, const char *field4)
369 if (!of_property_read_u32(of_node, field1, &val1))
372 if (!of_property_read_u32(of_node, field2, &val2))
375 if (!of_property_read_u32(of_node, field3, &val3))
378 if (!of_property_read_u32(of_node, field4, &val4))
385 newval = kszphy_extended_read(phydev, reg);
390 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
393 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
396 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
399 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
401 return kszphy_extended_write(phydev, reg, newval);
404 static int ksz9021_config_init(struct phy_device *phydev)
406 const struct device *dev = &phydev->mdio.dev;
407 const struct device_node *of_node = dev->of_node;
408 const struct device *dev_walker;
410 /* The Micrel driver has a deprecated option to place phy OF
411 * properties in the MAC node. Walk up the tree of devices to
412 * find a device with an OF node.
414 dev_walker = &phydev->mdio.dev;
416 of_node = dev_walker->of_node;
417 dev_walker = dev_walker->parent;
419 } while (!of_node && dev_walker);
422 ksz9021_load_values_from_of(phydev, of_node,
423 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
424 "txen-skew-ps", "txc-skew-ps",
425 "rxdv-skew-ps", "rxc-skew-ps");
426 ksz9021_load_values_from_of(phydev, of_node,
427 MII_KSZPHY_RX_DATA_PAD_SKEW,
428 "rxd0-skew-ps", "rxd1-skew-ps",
429 "rxd2-skew-ps", "rxd3-skew-ps");
430 ksz9021_load_values_from_of(phydev, of_node,
431 MII_KSZPHY_TX_DATA_PAD_SKEW,
432 "txd0-skew-ps", "txd1-skew-ps",
433 "txd2-skew-ps", "txd3-skew-ps");
438 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
439 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
441 #define KSZ9031_PS_TO_REG 60
443 /* Extended registers */
444 /* MMD Address 0x0 */
445 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
446 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
448 /* MMD Address 0x2 */
449 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
450 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
451 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
452 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
454 /* MMD Address 0x1C */
455 #define MII_KSZ9031RN_EDPD 0x23
456 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
458 static int ksz9031_extended_write(struct phy_device *phydev,
459 u8 mode, u32 dev_addr, u32 regnum, u16 val)
461 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
462 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
463 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
464 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
467 static int ksz9031_extended_read(struct phy_device *phydev,
468 u8 mode, u32 dev_addr, u32 regnum)
470 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
471 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
472 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
473 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
476 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
477 const struct device_node *of_node,
478 u16 reg, size_t field_sz,
479 const char *field[], u8 numfields)
481 int val[4] = {-1, -2, -3, -4};
488 for (i = 0; i < numfields; i++)
489 if (!of_property_read_u32(of_node, field[i], val + i))
495 if (matches < numfields)
496 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
500 maxval = (field_sz == 4) ? 0xf : 0x1f;
501 for (i = 0; i < numfields; i++)
502 if (val[i] != -(i + 1)) {
504 mask ^= maxval << (field_sz * i);
505 newval = (newval & mask) |
506 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
510 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
513 static int ksz9031_center_flp_timing(struct phy_device *phydev)
517 /* Center KSZ9031RNX FLP timing at 16ms. */
518 result = ksz9031_extended_write(phydev, OP_DATA, 0,
519 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
520 result = ksz9031_extended_write(phydev, OP_DATA, 0,
521 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
526 return genphy_restart_aneg(phydev);
529 /* Enable energy-detect power-down mode */
530 static int ksz9031_enable_edpd(struct phy_device *phydev)
534 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
537 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
538 reg | MII_KSZ9031RN_EDPD_ENABLE);
541 static int ksz9031_config_init(struct phy_device *phydev)
543 const struct device *dev = &phydev->mdio.dev;
544 const struct device_node *of_node = dev->of_node;
545 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
546 static const char *rx_data_skews[4] = {
547 "rxd0-skew-ps", "rxd1-skew-ps",
548 "rxd2-skew-ps", "rxd3-skew-ps"
550 static const char *tx_data_skews[4] = {
551 "txd0-skew-ps", "txd1-skew-ps",
552 "txd2-skew-ps", "txd3-skew-ps"
554 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
555 const struct device *dev_walker;
558 result = ksz9031_enable_edpd(phydev);
562 /* The Micrel driver has a deprecated option to place phy OF
563 * properties in the MAC node. Walk up the tree of devices to
564 * find a device with an OF node.
566 dev_walker = &phydev->mdio.dev;
568 of_node = dev_walker->of_node;
569 dev_walker = dev_walker->parent;
570 } while (!of_node && dev_walker);
573 ksz9031_of_load_skew_values(phydev, of_node,
574 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
577 ksz9031_of_load_skew_values(phydev, of_node,
578 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
581 ksz9031_of_load_skew_values(phydev, of_node,
582 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
585 ksz9031_of_load_skew_values(phydev, of_node,
586 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
590 return ksz9031_center_flp_timing(phydev);
593 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
594 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
595 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
596 static int ksz8873mll_read_status(struct phy_device *phydev)
601 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
603 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
605 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
606 phydev->duplex = DUPLEX_HALF;
608 phydev->duplex = DUPLEX_FULL;
610 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
611 phydev->speed = SPEED_10;
613 phydev->speed = SPEED_100;
616 phydev->pause = phydev->asym_pause = 0;
621 static int ksz9031_read_status(struct phy_device *phydev)
626 err = genphy_read_status(phydev);
630 /* Make sure the PHY is not broken. Read idle error count,
631 * and reset the PHY if it is maxed out.
633 regval = phy_read(phydev, MII_STAT1000);
634 if ((regval & 0xFF) == 0xFF) {
637 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
638 phydev->drv->config_intr(phydev);
639 return genphy_config_aneg(phydev);
645 static int ksz8873mll_config_aneg(struct phy_device *phydev)
650 /* This routine returns -1 as an indication to the caller that the
651 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
652 * MMD extended PHY registers.
655 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
661 /* This routine does nothing since the Micrel ksz9021 does not support
662 * standard IEEE MMD extended PHY registers.
665 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
670 static int kszphy_get_sset_count(struct phy_device *phydev)
672 return ARRAY_SIZE(kszphy_hw_stats);
675 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
679 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
680 strlcpy(data + i * ETH_GSTRING_LEN,
681 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
686 #define UINT64_MAX (u64)(~((u64)0))
688 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
690 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
691 struct kszphy_priv *priv = phydev->priv;
695 val = phy_read(phydev, stat.reg);
699 val = val & ((1 << stat.bits) - 1);
700 priv->stats[i] += val;
701 ret = priv->stats[i];
707 static void kszphy_get_stats(struct phy_device *phydev,
708 struct ethtool_stats *stats, u64 *data)
712 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
713 data[i] = kszphy_get_stat(phydev, i);
716 static int kszphy_suspend(struct phy_device *phydev)
718 /* Disable PHY Interrupts */
719 if (phy_interrupt_is_valid(phydev)) {
720 phydev->interrupts = PHY_INTERRUPT_DISABLED;
721 if (phydev->drv->config_intr)
722 phydev->drv->config_intr(phydev);
725 return genphy_suspend(phydev);
728 static int kszphy_resume(struct phy_device *phydev)
730 genphy_resume(phydev);
732 /* After switching from power-down to normal mode, an internal global
733 * reset is automatically generated. Wait a minimum of 1 ms before
734 * read/write access to the PHY registers.
736 usleep_range(1000, 2000);
738 /* Enable PHY Interrupts */
739 if (phy_interrupt_is_valid(phydev)) {
740 phydev->interrupts = PHY_INTERRUPT_ENABLED;
741 if (phydev->drv->config_intr)
742 phydev->drv->config_intr(phydev);
748 static int kszphy_probe(struct phy_device *phydev)
750 const struct kszphy_type *type = phydev->drv->driver_data;
751 const struct device_node *np = phydev->mdio.dev.of_node;
752 struct kszphy_priv *priv;
756 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
764 if (type->led_mode_reg) {
765 ret = of_property_read_u32(np, "micrel,led-mode",
770 if (priv->led_mode > 3) {
771 phydev_err(phydev, "invalid led mode: 0x%02x\n",
779 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
780 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
781 if (!IS_ERR_OR_NULL(clk)) {
782 unsigned long rate = clk_get_rate(clk);
783 bool rmii_ref_clk_sel_25_mhz;
785 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
786 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
787 "micrel,rmii-reference-clock-select-25-mhz");
789 if (rate > 24500000 && rate < 25500000) {
790 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
791 } else if (rate > 49500000 && rate < 50500000) {
792 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
794 phydev_err(phydev, "Clock rate out of range: %ld\n",
800 /* Support legacy board-file configuration */
801 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
802 priv->rmii_ref_clk_sel = true;
803 priv->rmii_ref_clk_sel_val = true;
809 static struct phy_driver ksphy_driver[] = {
811 .phy_id = PHY_ID_KS8737,
812 .phy_id_mask = MICREL_PHY_ID_MASK,
813 .name = "Micrel KS8737",
814 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
815 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
816 .driver_data = &ks8737_type,
817 .config_init = kszphy_config_init,
818 .config_aneg = genphy_config_aneg,
819 .read_status = genphy_read_status,
820 .ack_interrupt = kszphy_ack_interrupt,
821 .config_intr = kszphy_config_intr,
822 .suspend = genphy_suspend,
823 .resume = genphy_resume,
825 .phy_id = PHY_ID_KSZ8021,
826 .phy_id_mask = 0x00ffffff,
827 .name = "Micrel KSZ8021 or KSZ8031",
828 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
829 SUPPORTED_Asym_Pause),
830 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
831 .driver_data = &ksz8021_type,
832 .probe = kszphy_probe,
833 .config_init = kszphy_config_init,
834 .config_aneg = genphy_config_aneg,
835 .read_status = genphy_read_status,
836 .ack_interrupt = kszphy_ack_interrupt,
837 .config_intr = kszphy_config_intr,
838 .get_sset_count = kszphy_get_sset_count,
839 .get_strings = kszphy_get_strings,
840 .get_stats = kszphy_get_stats,
841 .suspend = genphy_suspend,
842 .resume = genphy_resume,
844 .phy_id = PHY_ID_KSZ8031,
845 .phy_id_mask = 0x00ffffff,
846 .name = "Micrel KSZ8031",
847 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
848 SUPPORTED_Asym_Pause),
849 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
850 .driver_data = &ksz8021_type,
851 .probe = kszphy_probe,
852 .config_init = kszphy_config_init,
853 .config_aneg = genphy_config_aneg,
854 .read_status = genphy_read_status,
855 .ack_interrupt = kszphy_ack_interrupt,
856 .config_intr = kszphy_config_intr,
857 .get_sset_count = kszphy_get_sset_count,
858 .get_strings = kszphy_get_strings,
859 .get_stats = kszphy_get_stats,
860 .suspend = genphy_suspend,
861 .resume = genphy_resume,
863 .phy_id = PHY_ID_KSZ8041,
864 .phy_id_mask = MICREL_PHY_ID_MASK,
865 .name = "Micrel KSZ8041",
866 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
867 | SUPPORTED_Asym_Pause),
868 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
869 .driver_data = &ksz8041_type,
870 .probe = kszphy_probe,
871 .config_init = ksz8041_config_init,
872 .config_aneg = ksz8041_config_aneg,
873 .read_status = genphy_read_status,
874 .ack_interrupt = kszphy_ack_interrupt,
875 .config_intr = kszphy_config_intr,
876 .get_sset_count = kszphy_get_sset_count,
877 .get_strings = kszphy_get_strings,
878 .get_stats = kszphy_get_stats,
879 /* No suspend/resume callbacks because of errata DS80000700A,
880 * receiver error following software power down.
883 .phy_id = PHY_ID_KSZ8041RNLI,
884 .phy_id_mask = MICREL_PHY_ID_MASK,
885 .name = "Micrel KSZ8041RNLI",
886 .features = PHY_BASIC_FEATURES |
887 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
888 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
889 .driver_data = &ksz8041_type,
890 .probe = kszphy_probe,
891 .config_init = kszphy_config_init,
892 .config_aneg = genphy_config_aneg,
893 .read_status = genphy_read_status,
894 .ack_interrupt = kszphy_ack_interrupt,
895 .config_intr = kszphy_config_intr,
896 .get_sset_count = kszphy_get_sset_count,
897 .get_strings = kszphy_get_strings,
898 .get_stats = kszphy_get_stats,
899 .suspend = genphy_suspend,
900 .resume = genphy_resume,
902 .phy_id = PHY_ID_KSZ8051,
903 .phy_id_mask = MICREL_PHY_ID_MASK,
904 .name = "Micrel KSZ8051",
905 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
906 | SUPPORTED_Asym_Pause),
907 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
908 .driver_data = &ksz8051_type,
909 .probe = kszphy_probe,
910 .config_init = kszphy_config_init,
911 .config_aneg = genphy_config_aneg,
912 .read_status = genphy_read_status,
913 .ack_interrupt = kszphy_ack_interrupt,
914 .config_intr = kszphy_config_intr,
915 .get_sset_count = kszphy_get_sset_count,
916 .get_strings = kszphy_get_strings,
917 .get_stats = kszphy_get_stats,
918 .suspend = genphy_suspend,
919 .resume = genphy_resume,
921 .phy_id = PHY_ID_KSZ8001,
922 .name = "Micrel KSZ8001 or KS8721",
923 .phy_id_mask = 0x00fffffc,
924 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
925 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
926 .driver_data = &ksz8041_type,
927 .probe = kszphy_probe,
928 .config_init = kszphy_config_init,
929 .config_aneg = genphy_config_aneg,
930 .read_status = genphy_read_status,
931 .ack_interrupt = kszphy_ack_interrupt,
932 .config_intr = kszphy_config_intr,
933 .get_sset_count = kszphy_get_sset_count,
934 .get_strings = kszphy_get_strings,
935 .get_stats = kszphy_get_stats,
936 .suspend = genphy_suspend,
937 .resume = genphy_resume,
939 .phy_id = PHY_ID_KSZ8081,
940 .name = "Micrel KSZ8081 or KSZ8091",
941 .phy_id_mask = MICREL_PHY_ID_MASK,
942 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
943 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
944 .driver_data = &ksz8081_type,
945 .probe = kszphy_probe,
946 .config_init = kszphy_config_init,
947 .config_aneg = genphy_config_aneg,
948 .read_status = genphy_read_status,
949 .ack_interrupt = kszphy_ack_interrupt,
950 .config_intr = kszphy_config_intr,
951 .get_sset_count = kszphy_get_sset_count,
952 .get_strings = kszphy_get_strings,
953 .get_stats = kszphy_get_stats,
954 .suspend = kszphy_suspend,
955 .resume = kszphy_resume,
957 .phy_id = PHY_ID_KSZ8061,
958 .name = "Micrel KSZ8061",
959 .phy_id_mask = MICREL_PHY_ID_MASK,
960 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
961 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
962 .config_init = ksz8061_config_init,
963 .config_aneg = genphy_config_aneg,
964 .read_status = genphy_read_status,
965 .ack_interrupt = kszphy_ack_interrupt,
966 .config_intr = kszphy_config_intr,
967 .suspend = genphy_suspend,
968 .resume = genphy_resume,
970 .phy_id = PHY_ID_KSZ9021,
971 .phy_id_mask = 0x000ffffe,
972 .name = "Micrel KSZ9021 Gigabit PHY",
973 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
974 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
975 .driver_data = &ksz9021_type,
976 .probe = kszphy_probe,
977 .config_init = ksz9021_config_init,
978 .config_aneg = genphy_config_aneg,
979 .read_status = genphy_read_status,
980 .ack_interrupt = kszphy_ack_interrupt,
981 .config_intr = kszphy_config_intr,
982 .get_sset_count = kszphy_get_sset_count,
983 .get_strings = kszphy_get_strings,
984 .get_stats = kszphy_get_stats,
985 .suspend = genphy_suspend,
986 .resume = genphy_resume,
987 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
988 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
990 .phy_id = PHY_ID_KSZ9031,
991 .phy_id_mask = MICREL_PHY_ID_MASK,
992 .name = "Micrel KSZ9031 Gigabit PHY",
993 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
994 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
995 .driver_data = &ksz9021_type,
996 .probe = kszphy_probe,
997 .config_init = ksz9031_config_init,
998 .config_aneg = genphy_config_aneg,
999 .read_status = ksz9031_read_status,
1000 .ack_interrupt = kszphy_ack_interrupt,
1001 .config_intr = kszphy_config_intr,
1002 .get_sset_count = kszphy_get_sset_count,
1003 .get_strings = kszphy_get_strings,
1004 .get_stats = kszphy_get_stats,
1005 .suspend = genphy_suspend,
1006 .resume = kszphy_resume,
1008 .phy_id = PHY_ID_KSZ8873MLL,
1009 .phy_id_mask = MICREL_PHY_ID_MASK,
1010 .name = "Micrel KSZ8873MLL Switch",
1011 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
1012 .flags = PHY_HAS_MAGICANEG,
1013 .config_init = kszphy_config_init,
1014 .config_aneg = ksz8873mll_config_aneg,
1015 .read_status = ksz8873mll_read_status,
1016 .suspend = genphy_suspend,
1017 .resume = genphy_resume,
1019 .phy_id = PHY_ID_KSZ886X,
1020 .phy_id_mask = MICREL_PHY_ID_MASK,
1021 .name = "Micrel KSZ886X Switch",
1022 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
1023 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1024 .config_init = kszphy_config_init,
1025 .config_aneg = genphy_config_aneg,
1026 .read_status = genphy_read_status,
1027 .suspend = genphy_suspend,
1028 .resume = genphy_resume,
1030 .phy_id = PHY_ID_KSZ8795,
1031 .phy_id_mask = MICREL_PHY_ID_MASK,
1032 .name = "Micrel KSZ8795",
1033 .features = PHY_BASIC_FEATURES,
1034 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1035 .config_init = kszphy_config_init,
1036 .config_aneg = ksz8873mll_config_aneg,
1037 .read_status = ksz8873mll_read_status,
1038 .suspend = genphy_suspend,
1039 .resume = genphy_resume,
1042 module_phy_driver(ksphy_driver);
1044 MODULE_DESCRIPTION("Micrel PHY driver");
1045 MODULE_AUTHOR("David J. Choi");
1046 MODULE_LICENSE("GPL");
1048 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1049 { PHY_ID_KSZ9021, 0x000ffffe },
1050 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1051 { PHY_ID_KSZ8001, 0x00fffffc },
1052 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1053 { PHY_ID_KSZ8021, 0x00ffffff },
1054 { PHY_ID_KSZ8031, 0x00ffffff },
1055 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1056 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1057 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1058 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1059 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1060 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1064 MODULE_DEVICE_TABLE(mdio, micrel_tbl);