drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  *                       ksz9477
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/phy.h>
  29 #include <linux/micrel_phy.h>
  30 #include <linux/of.h>
  31 #include <linux/clk.h>
  32 #include <linux/delay.h>
  33
  34 /* Operation Mode Strap Override */
  35 #define MII_KSZPHY_OMSO                         0x16
  36 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  37 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  38 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  39 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  40
  41 /* general Interrupt control/status reg in vendor specific block. */
  42 #define MII_KSZPHY_INTCS                        0x1B
  43 #define KSZPHY_INTCS_JABBER                     BIT(15)
  44 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  45 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  46 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  47 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  48 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  49 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  50 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  51 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  52                                                 KSZPHY_INTCS_LINK_DOWN)
  53
  54 /* PHY Control 1 */
  55 #define MII_KSZPHY_CTRL_1                       0x1e
  56
  57 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  58 #define MII_KSZPHY_CTRL_2                       0x1f
  59 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  60 /* bitmap of PHY register to set interrupt mode */
  61 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  62 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  63
  64 /* Write/read to/from extended registers */
  65 #define MII_KSZPHY_EXTREG                       0x0b
  66 #define KSZPHY_EXTREG_WRITE                     0x8000
  67
  68 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  69 #define MII_KSZPHY_EXTREG_READ                  0x0d
  70
  71 /* Extended registers */
  72 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  73 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  74 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  75
  76 #define PS_TO_REG                               200
  77
  78 struct kszphy_hw_stat {
  79         const char *string;
  80         u8 reg;
  81         u8 bits;
  82 };
  83
  84 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  85         { "phy_receive_errors", 21, 16},
  86         { "phy_idle_errors", 10, 8 },
  87 };
  88
  89 struct kszphy_type {
  90         u32 led_mode_reg;
  91         u16 interrupt_level_mask;
  92         bool has_broadcast_disable;
  93         bool has_nand_tree_disable;
  94         bool has_rmii_ref_clk_sel;
  95 };
  96
  97 struct kszphy_priv {
  98         const struct kszphy_type *type;
  99         int led_mode;
 100         bool rmii_ref_clk_sel;
 101         bool rmii_ref_clk_sel_val;
 102         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 103 };
 104
 105 static const struct kszphy_type ksz8021_type = {
 106         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 107         .has_broadcast_disable  = true,
 108         .has_nand_tree_disable  = true,
 109         .has_rmii_ref_clk_sel   = true,
 110 };
 111
 112 static const struct kszphy_type ksz8041_type = {
 113         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 114 };
 115
 116 static const struct kszphy_type ksz8051_type = {
 117         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 118         .has_nand_tree_disable  = true,
 119 };
 120
 121 static const struct kszphy_type ksz8081_type = {
 122         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 123         .has_broadcast_disable  = true,
 124         .has_nand_tree_disable  = true,
 125         .has_rmii_ref_clk_sel   = true,
 126 };
 127
 128 static const struct kszphy_type ks8737_type = {
 129         .interrupt_level_mask   = BIT(14),
 130 };
 131
 132 static const struct kszphy_type ksz9021_type = {
 133         .interrupt_level_mask   = BIT(14),
 134 };
 135
 136 static int kszphy_extended_write(struct phy_device *phydev,
 137                                 u32 regnum, u16 val)
 138 {
 139         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 140         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 141 }
 142
 143 static int kszphy_extended_read(struct phy_device *phydev,
 144                                 u32 regnum)
 145 {
 146         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 147         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 148 }
 149
 150 static int kszphy_ack_interrupt(struct phy_device *phydev)
 151 {
 152         /* bit[7..0] int status, which is a read and clear register. */
 153         int rc;
 154
 155         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 156
 157         return (rc < 0) ? rc : 0;
 158 }
 159
 160 static int kszphy_config_intr(struct phy_device *phydev)
 161 {
 162         const struct kszphy_type *type = phydev->drv->driver_data;
 163         int temp;
 164         u16 mask;
 165
 166         if (type && type->interrupt_level_mask)
 167                 mask = type->interrupt_level_mask;
 168         else
 169                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 170
 171         /* set the interrupt pin active low */
 172         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 173         if (temp < 0)
 174                 return temp;
 175         temp &= ~mask;
 176         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 177
 178         /* enable / disable interrupts */
 179         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 180                 temp = KSZPHY_INTCS_ALL;
 181         else
 182                 temp = 0;
 183
 184         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 185 }
 186
 187 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 188 {
 189         int ctrl;
 190
 191         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 192         if (ctrl < 0)
 193                 return ctrl;
 194
 195         if (val)
 196                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 197         else
 198                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 199
 200         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 201 }
 202
 203 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 204 {
 205         int rc, temp, shift;
 206
 207         switch (reg) {
 208         case MII_KSZPHY_CTRL_1:
 209                 shift = 14;
 210                 break;
 211         case MII_KSZPHY_CTRL_2:
 212                 shift = 4;
 213                 break;
 214         default:
 215                 return -EINVAL;
 216         }
 217
 218         temp = phy_read(phydev, reg);
 219         if (temp < 0) {
 220                 rc = temp;
 221                 goto out;
 222         }
 223
 224         temp &= ~(3 << shift);
 225         temp |= val << shift;
 226         rc = phy_write(phydev, reg, temp);
 227 out:
 228         if (rc < 0)
 229                 phydev_err(phydev, "failed to set led mode\n");
 230
 231         return rc;
 232 }
 233
 234 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 235  * unique (non-broadcast) address on a shared bus.
 236  */
 237 static int kszphy_broadcast_disable(struct phy_device *phydev)
 238 {
 239         int ret;
 240
 241         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 242         if (ret < 0)
 243                 goto out;
 244
 245         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 246 out:
 247         if (ret)
 248                 phydev_err(phydev, "failed to disable broadcast address\n");
 249
 250         return ret;
 251 }
 252
 253 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 254 {
 255         int ret;
 256
 257         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 258         if (ret < 0)
 259                 goto out;
 260
 261         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 262                 return 0;
 263
 264         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 265                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 266 out:
 267         if (ret)
 268                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 269
 270         return ret;
 271 }
 272
 273 /* Some config bits need to be set again on resume, handle them here. */
 274 static int kszphy_config_reset(struct phy_device *phydev)
 275 {
 276         struct kszphy_priv *priv = phydev->priv;
 277         int ret;
 278
 279         if (priv->rmii_ref_clk_sel) {
 280                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 281                 if (ret) {
 282                         phydev_err(phydev,
 283                                    "failed to set rmii reference clock\n");
 284                         return ret;
 285                 }
 286         }
 287
 288         if (priv->type && priv->led_mode >= 0)
 289                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 290
 291         return 0;
 292 }
 293
 294 static int kszphy_config_init(struct phy_device *phydev)
 295 {
 296         struct kszphy_priv *priv = phydev->priv;
 297         const struct kszphy_type *type;
 298
 299         if (!priv)
 300                 return 0;
 301
 302         type = priv->type;
 303
 304         if (type && type->has_broadcast_disable)
 305                 kszphy_broadcast_disable(phydev);
 306
 307         if (type && type->has_nand_tree_disable)
 308                 kszphy_nand_tree_disable(phydev);
 309
 310         return kszphy_config_reset(phydev);
 311 }
 312
 313 static int ksz8041_config_init(struct phy_device *phydev)
 314 {
 315         struct device_node *of_node = phydev->mdio.dev.of_node;
 316
 317         /* Limit supported and advertised modes in fiber mode */
 318         if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
 319                 phydev->dev_flags |= MICREL_PHY_FXEN;
 320                 phydev->supported &= SUPPORTED_100baseT_Full |
 321                                      SUPPORTED_100baseT_Half;
 322                 phydev->supported |= SUPPORTED_FIBRE;
 323                 phydev->advertising &= ADVERTISED_100baseT_Full |
 324                                        ADVERTISED_100baseT_Half;
 325                 phydev->advertising |= ADVERTISED_FIBRE;
 326                 phydev->autoneg = AUTONEG_DISABLE;
 327         }
 328
 329         return kszphy_config_init(phydev);
 330 }
 331
 332 static int ksz8041_config_aneg(struct phy_device *phydev)
 333 {
 334         /* Skip auto-negotiation in fiber mode */
 335         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 336                 phydev->speed = SPEED_100;
 337                 return 0;
 338         }
 339
 340         return genphy_config_aneg(phydev);
 341 }
 342
 343 static int ksz8061_config_init(struct phy_device *phydev)
 344 {
 345         int ret;
 346
 347         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 348         if (ret)
 349                 return ret;
 350
 351         return kszphy_config_init(phydev);
 352 }
 353
 354 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 355                                        const struct device_node *of_node,
 356                                        u16 reg,
 357                                        const char *field1, const char *field2,
 358                                        const char *field3, const char *field4)
 359 {
 360         int val1 = -1;
 361         int val2 = -2;
 362         int val3 = -3;
 363         int val4 = -4;
 364         int newval;
 365         int matches = 0;
 366
 367         if (!of_property_read_u32(of_node, field1, &val1))
 368                 matches++;
 369
 370         if (!of_property_read_u32(of_node, field2, &val2))
 371                 matches++;
 372
 373         if (!of_property_read_u32(of_node, field3, &val3))
 374                 matches++;
 375
 376         if (!of_property_read_u32(of_node, field4, &val4))
 377                 matches++;
 378
 379         if (!matches)
 380                 return 0;
 381
 382         if (matches < 4)
 383                 newval = kszphy_extended_read(phydev, reg);
 384         else
 385                 newval = 0;
 386
 387         if (val1 != -1)
 388                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 389
 390         if (val2 != -2)
 391                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 392
 393         if (val3 != -3)
 394                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 395
 396         if (val4 != -4)
 397                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 398
 399         return kszphy_extended_write(phydev, reg, newval);
 400 }
 401
 402 static int ksz9021_config_init(struct phy_device *phydev)
 403 {
 404         const struct device *dev = &phydev->mdio.dev;
 405         const struct device_node *of_node = dev->of_node;
 406         const struct device *dev_walker;
 407
 408         /* The Micrel driver has a deprecated option to place phy OF
 409          * properties in the MAC node. Walk up the tree of devices to
 410          * find a device with an OF node.
 411          */
 412         dev_walker = &phydev->mdio.dev;
 413         do {
 414                 of_node = dev_walker->of_node;
 415                 dev_walker = dev_walker->parent;
 416
 417         } while (!of_node && dev_walker);
 418
 419         if (of_node) {
 420                 ksz9021_load_values_from_of(phydev, of_node,
 421                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 422                                     "txen-skew-ps", "txc-skew-ps",
 423                                     "rxdv-skew-ps", "rxc-skew-ps");
 424                 ksz9021_load_values_from_of(phydev, of_node,
 425                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 426                                     "rxd0-skew-ps", "rxd1-skew-ps",
 427                                     "rxd2-skew-ps", "rxd3-skew-ps");
 428                 ksz9021_load_values_from_of(phydev, of_node,
 429                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 430                                     "txd0-skew-ps", "txd1-skew-ps",
 431                                     "txd2-skew-ps", "txd3-skew-ps");
 432         }
 433         return 0;
 434 }
 435
 436 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 437 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 438 #define OP_DATA                         1
 439 #define KSZ9031_PS_TO_REG               60
 440
 441 /* Extended registers */
 442 /* MMD Address 0x0 */
 443 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 444 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 445
 446 /* MMD Address 0x2 */
 447 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 448 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 449 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 450 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 451
 452 /* MMD Address 0x1C */
 453 #define MII_KSZ9031RN_EDPD              0x23
 454 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 455
 456 static int ksz9031_extended_write(struct phy_device *phydev,
 457                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 458 {
 459         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 460         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 461         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 462         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 463 }
 464
 465 static int ksz9031_extended_read(struct phy_device *phydev,
 466                                  u8 mode, u32 dev_addr, u32 regnum)
 467 {
 468         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 469         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 470         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 471         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 472 }
 473
 474 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 475                                        const struct device_node *of_node,
 476                                        u16 reg, size_t field_sz,
 477                                        const char *field[], u8 numfields)
 478 {
 479         int val[4] = {-1, -2, -3, -4};
 480         int matches = 0;
 481         u16 mask;
 482         u16 maxval;
 483         u16 newval;
 484         int i;
 485
 486         for (i = 0; i < numfields; i++)
 487                 if (!of_property_read_u32(of_node, field[i], val + i))
 488                         matches++;
 489
 490         if (!matches)
 491                 return 0;
 492
 493         if (matches < numfields)
 494                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 495         else
 496                 newval = 0;
 497
 498         maxval = (field_sz == 4) ? 0xf : 0x1f;
 499         for (i = 0; i < numfields; i++)
 500                 if (val[i] != -(i + 1)) {
 501                         mask = 0xffff;
 502                         mask ^= maxval << (field_sz * i);
 503                         newval = (newval & mask) |
 504                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 505                                         << (field_sz * i));
 506                 }
 507
 508         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 509 }
 510
 511 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 512 {
 513         int result;
 514
 515         /* Center KSZ9031RNX FLP timing at 16ms. */
 516         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 517                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 518         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 519                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 520
 521         if (result)
 522                 return result;
 523
 524         return genphy_restart_aneg(phydev);
 525 }
 526
 527 /* Enable energy-detect power-down mode */
 528 static int ksz9031_enable_edpd(struct phy_device *phydev)
 529 {
 530         int reg;
 531
 532         reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
 533         if (reg < 0)
 534                 return reg;
 535         return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
 536                                       reg | MII_KSZ9031RN_EDPD_ENABLE);
 537 }
 538
 539 static int ksz9031_config_init(struct phy_device *phydev)
 540 {
 541         const struct device *dev = &phydev->mdio.dev;
 542         const struct device_node *of_node = dev->of_node;
 543         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 544         static const char *rx_data_skews[4] = {
 545                 "rxd0-skew-ps", "rxd1-skew-ps",
 546                 "rxd2-skew-ps", "rxd3-skew-ps"
 547         };
 548         static const char *tx_data_skews[4] = {
 549                 "txd0-skew-ps", "txd1-skew-ps",
 550                 "txd2-skew-ps", "txd3-skew-ps"
 551         };
 552         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 553         const struct device *dev_walker;
 554         int result;
 555
 556         result = ksz9031_enable_edpd(phydev);
 557         if (result < 0)
 558                 return result;
 559
 560         /* The Micrel driver has a deprecated option to place phy OF
 561          * properties in the MAC node. Walk up the tree of devices to
 562          * find a device with an OF node.
 563          */
 564         dev_walker = &phydev->mdio.dev;
 565         do {
 566                 of_node = dev_walker->of_node;
 567                 dev_walker = dev_walker->parent;
 568         } while (!of_node && dev_walker);
 569
 570         if (of_node) {
 571                 ksz9031_of_load_skew_values(phydev, of_node,
 572                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 573                                 clk_skews, 2);
 574
 575                 ksz9031_of_load_skew_values(phydev, of_node,
 576                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 577                                 control_skews, 2);
 578
 579                 ksz9031_of_load_skew_values(phydev, of_node,
 580                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 581                                 rx_data_skews, 4);
 582
 583                 ksz9031_of_load_skew_values(phydev, of_node,
 584                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 585                                 tx_data_skews, 4);
 586         }
 587
 588         return ksz9031_center_flp_timing(phydev);
 589 }
 590
 591 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 592 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 593 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 594 static int ksz8873mll_read_status(struct phy_device *phydev)
 595 {
 596         int regval;
 597
 598         /* dummy read */
 599         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 600
 601         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 602
 603         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 604                 phydev->duplex = DUPLEX_HALF;
 605         else
 606                 phydev->duplex = DUPLEX_FULL;
 607
 608         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 609                 phydev->speed = SPEED_10;
 610         else
 611                 phydev->speed = SPEED_100;
 612
 613         phydev->link = 1;
 614         phydev->pause = phydev->asym_pause = 0;
 615
 616         return 0;
 617 }
 618
 619 static int ksz9031_read_status(struct phy_device *phydev)
 620 {
 621         int err;
 622         int regval;
 623
 624         err = genphy_read_status(phydev);
 625         if (err)
 626                 return err;
 627
 628         /* Make sure the PHY is not broken. Read idle error count,
 629          * and reset the PHY if it is maxed out.
 630          */
 631         regval = phy_read(phydev, MII_STAT1000);
 632         if ((regval & 0xFF) == 0xFF) {
 633                 phy_init_hw(phydev);
 634                 phydev->link = 0;
 635                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
 636                         phydev->drv->config_intr(phydev);
 637                 return genphy_config_aneg(phydev);
 638         }
 639
 640         return 0;
 641 }
 642
 643 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 644 {
 645         return 0;
 646 }
 647
 648 /* This routine returns -1 as an indication to the caller that the
 649  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
 650  * MMD extended PHY registers.
 651  */
 652 static int
 653 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum)
 654 {
 655         return -1;
 656 }
 657
 658 /* This routine does nothing since the Micrel ksz9021 does not support
 659  * standard IEEE MMD extended PHY registers.
 660  */
 661 static int
 662 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val)
 663 {
 664         return -1;
 665 }
 666
 667 static int kszphy_get_sset_count(struct phy_device *phydev)
 668 {
 669         return ARRAY_SIZE(kszphy_hw_stats);
 670 }
 671
 672 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 673 {
 674         int i;
 675
 676         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 677                 strlcpy(data + i * ETH_GSTRING_LEN,
 678                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 679         }
 680 }
 681
 682 #ifndef UINT64_MAX
 683 #define UINT64_MAX              (u64)(~((u64)0))
 684 #endif
 685 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 686 {
 687         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 688         struct kszphy_priv *priv = phydev->priv;
 689         int val;
 690         u64 ret;
 691
 692         val = phy_read(phydev, stat.reg);
 693         if (val < 0) {
 694                 ret = UINT64_MAX;
 695         } else {
 696                 val = val & ((1 << stat.bits) - 1);
 697                 priv->stats[i] += val;
 698                 ret = priv->stats[i];
 699         }
 700
 701         return ret;
 702 }
 703
 704 static void kszphy_get_stats(struct phy_device *phydev,
 705                              struct ethtool_stats *stats, u64 *data)
 706 {
 707         int i;
 708
 709         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 710                 data[i] = kszphy_get_stat(phydev, i);
 711 }
 712
 713 static int kszphy_suspend(struct phy_device *phydev)
 714 {
 715         /* Disable PHY Interrupts */
 716         if (phy_interrupt_is_valid(phydev)) {
 717                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
 718                 if (phydev->drv->config_intr)
 719                         phydev->drv->config_intr(phydev);
 720         }
 721
 722         return genphy_suspend(phydev);
 723 }
 724
 725 static int kszphy_resume(struct phy_device *phydev)
 726 {
 727         int ret;
 728
 729         genphy_resume(phydev);
 730
 731         /* After switching from power-down to normal mode, an internal global
 732          * reset is automatically generated. Wait a minimum of 1 ms before
 733          * read/write access to the PHY registers.
 734          */
 735         usleep_range(1000, 2000);
 736
 737         ret = kszphy_config_reset(phydev);
 738         if (ret)
 739                 return ret;
 740
 741         /* Enable PHY Interrupts */
 742         if (phy_interrupt_is_valid(phydev)) {
 743                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
 744                 if (phydev->drv->config_intr)
 745                         phydev->drv->config_intr(phydev);
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int kszphy_probe(struct phy_device *phydev)
 752 {
 753         const struct kszphy_type *type = phydev->drv->driver_data;
 754         const struct device_node *np = phydev->mdio.dev.of_node;
 755         struct kszphy_priv *priv;
 756         struct clk *clk;
 757         int ret;
 758
 759         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 760         if (!priv)
 761                 return -ENOMEM;
 762
 763         phydev->priv = priv;
 764
 765         priv->type = type;
 766
 767         if (type && type->led_mode_reg) {
 768                 ret = of_property_read_u32(np, "micrel,led-mode",
 769                                 &priv->led_mode);
 770                 if (ret)
 771                         priv->led_mode = -1;
 772
 773                 if (priv->led_mode > 3) {
 774                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 775                                    priv->led_mode);
 776                         priv->led_mode = -1;
 777                 }
 778         } else {
 779                 priv->led_mode = -1;
 780         }
 781
 782         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 783         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 784         if (!IS_ERR_OR_NULL(clk)) {
 785                 unsigned long rate = clk_get_rate(clk);
 786                 bool rmii_ref_clk_sel_25_mhz;
 787
 788                 if (type)
 789                         priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 790                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 791                                 "micrel,rmii-reference-clock-select-25-mhz");
 792
 793                 if (rate > 24500000 && rate < 25500000) {
 794                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 795                 } else if (rate > 49500000 && rate < 50500000) {
 796                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 797                 } else {
 798                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 799                                    rate);
 800                         return -EINVAL;
 801                 }
 802         }
 803
 804         /* Support legacy board-file configuration */
 805         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 806                 priv->rmii_ref_clk_sel = true;
 807                 priv->rmii_ref_clk_sel_val = true;
 808         }
 809
 810         return 0;
 811 }
 812
 813 static struct phy_driver ksphy_driver[] = {
 814 {
 815         .phy_id         = PHY_ID_KS8737,
 816         .phy_id_mask    = MICREL_PHY_ID_MASK,
 817         .name           = "Micrel KS8737",
 818         .features       = PHY_BASIC_FEATURES,
 819         .flags          = PHY_HAS_INTERRUPT,
 820         .driver_data    = &ks8737_type,
 821         .config_init    = kszphy_config_init,
 822         .config_aneg    = genphy_config_aneg,
 823         .read_status    = genphy_read_status,
 824         .ack_interrupt  = kszphy_ack_interrupt,
 825         .config_intr    = kszphy_config_intr,
 826         .suspend        = genphy_suspend,
 827         .resume         = genphy_resume,
 828 }, {
 829         .phy_id         = PHY_ID_KSZ8021,
 830         .phy_id_mask    = 0x00ffffff,
 831         .name           = "Micrel KSZ8021 or KSZ8031",
 832         .features       = PHY_BASIC_FEATURES,
 833         .flags          = PHY_HAS_INTERRUPT,
 834         .driver_data    = &ksz8021_type,
 835         .probe          = kszphy_probe,
 836         .config_init    = kszphy_config_init,
 837         .config_aneg    = genphy_config_aneg,
 838         .read_status    = genphy_read_status,
 839         .ack_interrupt  = kszphy_ack_interrupt,
 840         .config_intr    = kszphy_config_intr,
 841         .get_sset_count = kszphy_get_sset_count,
 842         .get_strings    = kszphy_get_strings,
 843         .get_stats      = kszphy_get_stats,
 844         .suspend        = genphy_suspend,
 845         .resume         = genphy_resume,
 846 }, {
 847         .phy_id         = PHY_ID_KSZ8031,
 848         .phy_id_mask    = 0x00ffffff,
 849         .name           = "Micrel KSZ8031",
 850         .features       = PHY_BASIC_FEATURES,
 851         .flags          = PHY_HAS_INTERRUPT,
 852         .driver_data    = &ksz8021_type,
 853         .probe          = kszphy_probe,
 854         .config_init    = kszphy_config_init,
 855         .config_aneg    = genphy_config_aneg,
 856         .read_status    = genphy_read_status,
 857         .ack_interrupt  = kszphy_ack_interrupt,
 858         .config_intr    = kszphy_config_intr,
 859         .get_sset_count = kszphy_get_sset_count,
 860         .get_strings    = kszphy_get_strings,
 861         .get_stats      = kszphy_get_stats,
 862         .suspend        = genphy_suspend,
 863         .resume         = genphy_resume,
 864 }, {
 865         .phy_id         = PHY_ID_KSZ8041,
 866         .phy_id_mask    = MICREL_PHY_ID_MASK,
 867         .name           = "Micrel KSZ8041",
 868         .features       = PHY_BASIC_FEATURES,
 869         .flags          = PHY_HAS_INTERRUPT,
 870         .driver_data    = &ksz8041_type,
 871         .probe          = kszphy_probe,
 872         .config_init    = ksz8041_config_init,
 873         .config_aneg    = ksz8041_config_aneg,
 874         .read_status    = genphy_read_status,
 875         .ack_interrupt  = kszphy_ack_interrupt,
 876         .config_intr    = kszphy_config_intr,
 877         .get_sset_count = kszphy_get_sset_count,
 878         .get_strings    = kszphy_get_strings,
 879         .get_stats      = kszphy_get_stats,
 880         /* No suspend/resume callbacks because of errata DS80000700A,
 881          * receiver error following software power down.
 882          */
 883 }, {
 884         .phy_id         = PHY_ID_KSZ8041RNLI,
 885         .phy_id_mask    = MICREL_PHY_ID_MASK,
 886         .name           = "Micrel KSZ8041RNLI",
 887         .features       = PHY_BASIC_FEATURES,
 888         .flags          = PHY_HAS_INTERRUPT,
 889         .driver_data    = &ksz8041_type,
 890         .probe          = kszphy_probe,
 891         .config_init    = kszphy_config_init,
 892         .config_aneg    = genphy_config_aneg,
 893         .read_status    = genphy_read_status,
 894         .ack_interrupt  = kszphy_ack_interrupt,
 895         .config_intr    = kszphy_config_intr,
 896         .get_sset_count = kszphy_get_sset_count,
 897         .get_strings    = kszphy_get_strings,
 898         .get_stats      = kszphy_get_stats,
 899         .suspend        = genphy_suspend,
 900         .resume         = genphy_resume,
 901 }, {
 902         .phy_id         = PHY_ID_KSZ8051,
 903         .phy_id_mask    = MICREL_PHY_ID_MASK,
 904         .name           = "Micrel KSZ8051",
 905         .features       = PHY_BASIC_FEATURES,
 906         .flags          = PHY_HAS_INTERRUPT,
 907         .driver_data    = &ksz8051_type,
 908         .probe          = kszphy_probe,
 909         .config_init    = kszphy_config_init,
 910         .config_aneg    = genphy_config_aneg,
 911         .read_status    = genphy_read_status,
 912         .ack_interrupt  = kszphy_ack_interrupt,
 913         .config_intr    = kszphy_config_intr,
 914         .get_sset_count = kszphy_get_sset_count,
 915         .get_strings    = kszphy_get_strings,
 916         .get_stats      = kszphy_get_stats,
 917         .suspend        = genphy_suspend,
 918         .resume         = genphy_resume,
 919 }, {
 920         .phy_id         = PHY_ID_KSZ8001,
 921         .name           = "Micrel KSZ8001 or KS8721",
 922         .phy_id_mask    = 0x00fffffc,
 923         .features       = PHY_BASIC_FEATURES,
 924         .flags          = PHY_HAS_INTERRUPT,
 925         .driver_data    = &ksz8041_type,
 926         .probe          = kszphy_probe,
 927         .config_init    = kszphy_config_init,
 928         .config_aneg    = genphy_config_aneg,
 929         .read_status    = genphy_read_status,
 930         .ack_interrupt  = kszphy_ack_interrupt,
 931         .config_intr    = kszphy_config_intr,
 932         .get_sset_count = kszphy_get_sset_count,
 933         .get_strings    = kszphy_get_strings,
 934         .get_stats      = kszphy_get_stats,
 935         .suspend        = genphy_suspend,
 936         .resume         = genphy_resume,
 937 }, {
 938         .phy_id         = PHY_ID_KSZ8081,
 939         .name           = "Micrel KSZ8081 or KSZ8091",
 940         .phy_id_mask    = MICREL_PHY_ID_MASK,
 941         .features       = PHY_BASIC_FEATURES,
 942         .flags          = PHY_HAS_INTERRUPT,
 943         .driver_data    = &ksz8081_type,
 944         .probe          = kszphy_probe,
 945         .config_init    = kszphy_config_init,
 946         .config_aneg    = genphy_config_aneg,
 947         .read_status    = genphy_read_status,
 948         .ack_interrupt  = kszphy_ack_interrupt,
 949         .config_intr    = kszphy_config_intr,
 950         .get_sset_count = kszphy_get_sset_count,
 951         .get_strings    = kszphy_get_strings,
 952         .get_stats      = kszphy_get_stats,
 953         .suspend        = kszphy_suspend,
 954         .resume         = kszphy_resume,
 955 }, {
 956         .phy_id         = PHY_ID_KSZ8061,
 957         .name           = "Micrel KSZ8061",
 958         .phy_id_mask    = MICREL_PHY_ID_MASK,
 959         .features       = PHY_BASIC_FEATURES,
 960         .flags          = PHY_HAS_INTERRUPT,
 961         .config_init    = ksz8061_config_init,
 962         .config_aneg    = genphy_config_aneg,
 963         .read_status    = genphy_read_status,
 964         .ack_interrupt  = kszphy_ack_interrupt,
 965         .config_intr    = kszphy_config_intr,
 966         .suspend        = genphy_suspend,
 967         .resume         = genphy_resume,
 968 }, {
 969         .phy_id         = PHY_ID_KSZ9021,
 970         .phy_id_mask    = 0x000ffffe,
 971         .name           = "Micrel KSZ9021 Gigabit PHY",
 972         .features       = PHY_GBIT_FEATURES,
 973         .flags          = PHY_HAS_INTERRUPT,
 974         .driver_data    = &ksz9021_type,
 975         .probe          = kszphy_probe,
 976         .config_init    = ksz9021_config_init,
 977         .config_aneg    = genphy_config_aneg,
 978         .read_status    = genphy_read_status,
 979         .ack_interrupt  = kszphy_ack_interrupt,
 980         .config_intr    = kszphy_config_intr,
 981         .get_sset_count = kszphy_get_sset_count,
 982         .get_strings    = kszphy_get_strings,
 983         .get_stats      = kszphy_get_stats,
 984         .suspend        = genphy_suspend,
 985         .resume         = genphy_resume,
 986         .read_mmd       = ksz9021_rd_mmd_phyreg,
 987         .write_mmd      = ksz9021_wr_mmd_phyreg,
 988 }, {
 989         .phy_id         = PHY_ID_KSZ9031,
 990         .phy_id_mask    = MICREL_PHY_ID_MASK,
 991         .name           = "Micrel KSZ9031 Gigabit PHY",
 992         .features       = PHY_GBIT_FEATURES,
 993         .flags          = PHY_HAS_INTERRUPT,
 994         .driver_data    = &ksz9021_type,
 995         .probe          = kszphy_probe,
 996         .config_init    = ksz9031_config_init,
 997         .config_aneg    = genphy_config_aneg,
 998         .read_status    = ksz9031_read_status,
 999         .ack_interrupt  = kszphy_ack_interrupt,
1000         .config_intr    = kszphy_config_intr,
1001         .get_sset_count = kszphy_get_sset_count,
1002         .get_strings    = kszphy_get_strings,
1003         .get_stats      = kszphy_get_stats,
1004         .suspend        = genphy_suspend,
1005         .resume         = kszphy_resume,
1006 }, {
1007         .phy_id         = PHY_ID_KSZ8873MLL,
1008         .phy_id_mask    = MICREL_PHY_ID_MASK,
1009         .name           = "Micrel KSZ8873MLL Switch",
1010         .config_init    = kszphy_config_init,
1011         .config_aneg    = ksz8873mll_config_aneg,
1012         .read_status    = ksz8873mll_read_status,
1013         .suspend        = genphy_suspend,
1014         .resume         = genphy_resume,
1015 }, {
1016         .phy_id         = PHY_ID_KSZ886X,
1017         .phy_id_mask    = MICREL_PHY_ID_MASK,
1018         .name           = "Micrel KSZ886X Switch",
1019         .features       = PHY_BASIC_FEATURES,
1020         .flags          = PHY_HAS_INTERRUPT,
1021         .config_init    = kszphy_config_init,
1022         .config_aneg    = genphy_config_aneg,
1023         .read_status    = genphy_read_status,
1024         .suspend        = genphy_suspend,
1025         .resume         = genphy_resume,
1026 }, {
1027         .phy_id         = PHY_ID_KSZ8795,
1028         .phy_id_mask    = MICREL_PHY_ID_MASK,
1029         .name           = "Micrel KSZ8795",
1030         .features       = PHY_BASIC_FEATURES,
1031         .flags          = PHY_HAS_INTERRUPT,
1032         .config_init    = kszphy_config_init,
1033         .config_aneg    = ksz8873mll_config_aneg,
1034         .read_status    = ksz8873mll_read_status,
1035         .suspend        = genphy_suspend,
1036         .resume         = genphy_resume,
1037 }, {
1038         .phy_id         = PHY_ID_KSZ9477,
1039         .phy_id_mask    = MICREL_PHY_ID_MASK,
1040         .name           = "Microchip KSZ9477",
1041         .features       = PHY_GBIT_FEATURES,
1042         .config_init    = kszphy_config_init,
1043         .config_aneg    = genphy_config_aneg,
1044         .read_status    = genphy_read_status,
1045         .suspend        = genphy_suspend,
1046         .resume         = genphy_resume,
1047 } };
1048
1049 module_phy_driver(ksphy_driver);
1050
1051 MODULE_DESCRIPTION("Micrel PHY driver");
1052 MODULE_AUTHOR("David J. Choi");
1053 MODULE_LICENSE("GPL");
1054
1055 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1056         { PHY_ID_KSZ9021, 0x000ffffe },
1057         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1058         { PHY_ID_KSZ8001, 0x00fffffc },
1059         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1060         { PHY_ID_KSZ8021, 0x00ffffff },
1061         { PHY_ID_KSZ8031, 0x00ffffff },
1062         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1063         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1064         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1065         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1066         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1067         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1068         { }
1069 };
1070
1071 MODULE_DEVICE_TABLE(mdio, micrel_tbl);