2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/phy.h>
29 #include <linux/micrel_phy.h>
31 #include <linux/clk.h>
32 #include <linux/delay.h>
34 /* Operation Mode Strap Override */
35 #define MII_KSZPHY_OMSO 0x16
36 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
37 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
38 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
39 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
41 /* general Interrupt control/status reg in vendor specific block. */
42 #define MII_KSZPHY_INTCS 0x1B
43 #define KSZPHY_INTCS_JABBER BIT(15)
44 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
45 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
46 #define KSZPHY_INTCS_PARELLEL BIT(12)
47 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
48 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
49 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
50 #define KSZPHY_INTCS_LINK_UP BIT(8)
51 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
52 KSZPHY_INTCS_LINK_DOWN)
55 #define MII_KSZPHY_CTRL_1 0x1e
57 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
58 #define MII_KSZPHY_CTRL_2 0x1f
59 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
60 /* bitmap of PHY register to set interrupt mode */
61 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
62 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
64 /* Write/read to/from extended registers */
65 #define MII_KSZPHY_EXTREG 0x0b
66 #define KSZPHY_EXTREG_WRITE 0x8000
68 #define MII_KSZPHY_EXTREG_WRITE 0x0c
69 #define MII_KSZPHY_EXTREG_READ 0x0d
71 /* Extended registers */
72 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
73 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
74 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
78 struct kszphy_hw_stat {
84 static struct kszphy_hw_stat kszphy_hw_stats[] = {
85 { "phy_receive_errors", 21, 16},
86 { "phy_idle_errors", 10, 8 },
91 u16 interrupt_level_mask;
92 bool has_broadcast_disable;
93 bool has_nand_tree_disable;
94 bool has_rmii_ref_clk_sel;
98 const struct kszphy_type *type;
100 bool rmii_ref_clk_sel;
101 bool rmii_ref_clk_sel_val;
102 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
105 static const struct kszphy_type ksz8021_type = {
106 .led_mode_reg = MII_KSZPHY_CTRL_2,
107 .has_broadcast_disable = true,
108 .has_nand_tree_disable = true,
109 .has_rmii_ref_clk_sel = true,
112 static const struct kszphy_type ksz8041_type = {
113 .led_mode_reg = MII_KSZPHY_CTRL_1,
116 static const struct kszphy_type ksz8051_type = {
117 .led_mode_reg = MII_KSZPHY_CTRL_2,
118 .has_nand_tree_disable = true,
121 static const struct kszphy_type ksz8081_type = {
122 .led_mode_reg = MII_KSZPHY_CTRL_2,
123 .has_broadcast_disable = true,
124 .has_nand_tree_disable = true,
125 .has_rmii_ref_clk_sel = true,
128 static const struct kszphy_type ks8737_type = {
129 .interrupt_level_mask = BIT(14),
132 static const struct kszphy_type ksz9021_type = {
133 .interrupt_level_mask = BIT(14),
136 static int kszphy_extended_write(struct phy_device *phydev,
139 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
140 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
143 static int kszphy_extended_read(struct phy_device *phydev,
146 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
147 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
150 static int kszphy_ack_interrupt(struct phy_device *phydev)
152 /* bit[7..0] int status, which is a read and clear register. */
155 rc = phy_read(phydev, MII_KSZPHY_INTCS);
157 return (rc < 0) ? rc : 0;
160 static int kszphy_config_intr(struct phy_device *phydev)
162 const struct kszphy_type *type = phydev->drv->driver_data;
166 if (type && type->interrupt_level_mask)
167 mask = type->interrupt_level_mask;
169 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
171 /* set the interrupt pin active low */
172 temp = phy_read(phydev, MII_KSZPHY_CTRL);
176 phy_write(phydev, MII_KSZPHY_CTRL, temp);
178 /* enable / disable interrupts */
179 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
180 temp = KSZPHY_INTCS_ALL;
184 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
187 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
191 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
196 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
198 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
200 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
203 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
208 case MII_KSZPHY_CTRL_1:
211 case MII_KSZPHY_CTRL_2:
218 temp = phy_read(phydev, reg);
224 temp &= ~(3 << shift);
225 temp |= val << shift;
226 rc = phy_write(phydev, reg, temp);
229 phydev_err(phydev, "failed to set led mode\n");
234 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
235 * unique (non-broadcast) address on a shared bus.
237 static int kszphy_broadcast_disable(struct phy_device *phydev)
241 ret = phy_read(phydev, MII_KSZPHY_OMSO);
245 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
248 phydev_err(phydev, "failed to disable broadcast address\n");
253 static int kszphy_nand_tree_disable(struct phy_device *phydev)
257 ret = phy_read(phydev, MII_KSZPHY_OMSO);
261 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
264 ret = phy_write(phydev, MII_KSZPHY_OMSO,
265 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
268 phydev_err(phydev, "failed to disable NAND tree mode\n");
273 /* Some config bits need to be set again on resume, handle them here. */
274 static int kszphy_config_reset(struct phy_device *phydev)
276 struct kszphy_priv *priv = phydev->priv;
279 if (priv->rmii_ref_clk_sel) {
280 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
283 "failed to set rmii reference clock\n");
288 if (priv->led_mode >= 0)
289 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
294 static int kszphy_config_init(struct phy_device *phydev)
296 struct kszphy_priv *priv = phydev->priv;
297 const struct kszphy_type *type;
304 if (type->has_broadcast_disable)
305 kszphy_broadcast_disable(phydev);
307 if (type->has_nand_tree_disable)
308 kszphy_nand_tree_disable(phydev);
310 return kszphy_config_reset(phydev);
313 static int ksz8041_config_init(struct phy_device *phydev)
315 struct device_node *of_node = phydev->mdio.dev.of_node;
317 /* Limit supported and advertised modes in fiber mode */
318 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
319 phydev->dev_flags |= MICREL_PHY_FXEN;
320 phydev->supported &= SUPPORTED_100baseT_Full |
321 SUPPORTED_100baseT_Half;
322 phydev->supported |= SUPPORTED_FIBRE;
323 phydev->advertising &= ADVERTISED_100baseT_Full |
324 ADVERTISED_100baseT_Half;
325 phydev->advertising |= ADVERTISED_FIBRE;
326 phydev->autoneg = AUTONEG_DISABLE;
329 return kszphy_config_init(phydev);
332 static int ksz8041_config_aneg(struct phy_device *phydev)
334 /* Skip auto-negotiation in fiber mode */
335 if (phydev->dev_flags & MICREL_PHY_FXEN) {
336 phydev->speed = SPEED_100;
340 return genphy_config_aneg(phydev);
343 static int ksz8061_config_init(struct phy_device *phydev)
347 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
351 return kszphy_config_init(phydev);
354 static int ksz9021_load_values_from_of(struct phy_device *phydev,
355 const struct device_node *of_node,
357 const char *field1, const char *field2,
358 const char *field3, const char *field4)
367 if (!of_property_read_u32(of_node, field1, &val1))
370 if (!of_property_read_u32(of_node, field2, &val2))
373 if (!of_property_read_u32(of_node, field3, &val3))
376 if (!of_property_read_u32(of_node, field4, &val4))
383 newval = kszphy_extended_read(phydev, reg);
388 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
391 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
394 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
397 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
399 return kszphy_extended_write(phydev, reg, newval);
402 static int ksz9021_config_init(struct phy_device *phydev)
404 const struct device *dev = &phydev->mdio.dev;
405 const struct device_node *of_node = dev->of_node;
406 const struct device *dev_walker;
408 /* The Micrel driver has a deprecated option to place phy OF
409 * properties in the MAC node. Walk up the tree of devices to
410 * find a device with an OF node.
412 dev_walker = &phydev->mdio.dev;
414 of_node = dev_walker->of_node;
415 dev_walker = dev_walker->parent;
417 } while (!of_node && dev_walker);
420 ksz9021_load_values_from_of(phydev, of_node,
421 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
422 "txen-skew-ps", "txc-skew-ps",
423 "rxdv-skew-ps", "rxc-skew-ps");
424 ksz9021_load_values_from_of(phydev, of_node,
425 MII_KSZPHY_RX_DATA_PAD_SKEW,
426 "rxd0-skew-ps", "rxd1-skew-ps",
427 "rxd2-skew-ps", "rxd3-skew-ps");
428 ksz9021_load_values_from_of(phydev, of_node,
429 MII_KSZPHY_TX_DATA_PAD_SKEW,
430 "txd0-skew-ps", "txd1-skew-ps",
431 "txd2-skew-ps", "txd3-skew-ps");
436 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
437 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
439 #define KSZ9031_PS_TO_REG 60
441 /* Extended registers */
442 /* MMD Address 0x0 */
443 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
444 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
446 /* MMD Address 0x2 */
447 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
448 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
449 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
450 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
452 /* MMD Address 0x1C */
453 #define MII_KSZ9031RN_EDPD 0x23
454 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
456 static int ksz9031_extended_write(struct phy_device *phydev,
457 u8 mode, u32 dev_addr, u32 regnum, u16 val)
459 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
460 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
461 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
462 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
465 static int ksz9031_extended_read(struct phy_device *phydev,
466 u8 mode, u32 dev_addr, u32 regnum)
468 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
469 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
470 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
471 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
474 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
475 const struct device_node *of_node,
476 u16 reg, size_t field_sz,
477 const char *field[], u8 numfields)
479 int val[4] = {-1, -2, -3, -4};
486 for (i = 0; i < numfields; i++)
487 if (!of_property_read_u32(of_node, field[i], val + i))
493 if (matches < numfields)
494 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
498 maxval = (field_sz == 4) ? 0xf : 0x1f;
499 for (i = 0; i < numfields; i++)
500 if (val[i] != -(i + 1)) {
502 mask ^= maxval << (field_sz * i);
503 newval = (newval & mask) |
504 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
508 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
511 /* Center KSZ9031RNX FLP timing at 16ms. */
512 static int ksz9031_center_flp_timing(struct phy_device *phydev)
516 result = ksz9031_extended_write(phydev, OP_DATA, 0,
517 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
521 result = ksz9031_extended_write(phydev, OP_DATA, 0,
522 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
526 return genphy_restart_aneg(phydev);
529 /* Enable energy-detect power-down mode */
530 static int ksz9031_enable_edpd(struct phy_device *phydev)
534 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
537 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
538 reg | MII_KSZ9031RN_EDPD_ENABLE);
541 static int ksz9031_config_init(struct phy_device *phydev)
543 const struct device *dev = &phydev->mdio.dev;
544 const struct device_node *of_node = dev->of_node;
545 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
546 static const char *rx_data_skews[4] = {
547 "rxd0-skew-ps", "rxd1-skew-ps",
548 "rxd2-skew-ps", "rxd3-skew-ps"
550 static const char *tx_data_skews[4] = {
551 "txd0-skew-ps", "txd1-skew-ps",
552 "txd2-skew-ps", "txd3-skew-ps"
554 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
555 const struct device *dev_walker;
558 result = ksz9031_enable_edpd(phydev);
562 /* The Micrel driver has a deprecated option to place phy OF
563 * properties in the MAC node. Walk up the tree of devices to
564 * find a device with an OF node.
566 dev_walker = &phydev->mdio.dev;
568 of_node = dev_walker->of_node;
569 dev_walker = dev_walker->parent;
570 } while (!of_node && dev_walker);
573 ksz9031_of_load_skew_values(phydev, of_node,
574 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
577 ksz9031_of_load_skew_values(phydev, of_node,
578 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
581 ksz9031_of_load_skew_values(phydev, of_node,
582 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
585 ksz9031_of_load_skew_values(phydev, of_node,
586 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
589 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
590 * When the device links in the 1000BASE-T slave mode only,
591 * the optional 125MHz reference output clock (CLK125_NDO)
592 * has wide duty cycle variation.
594 * The optional CLK125_NDO clock does not meet the RGMII
595 * 45/55 percent (min/max) duty cycle requirement and therefore
596 * cannot be used directly by the MAC side for clocking
597 * applications that have setup/hold time requirements on
598 * rising and falling clock edges.
601 * Force the phy to be the master to receive a stable clock
602 * which meets the duty cycle requirement.
604 if (of_property_read_bool(of_node, "micrel,force-master")) {
605 result = phy_read(phydev, MII_CTRL1000);
607 goto err_force_master;
609 /* enable master mode, config & prefer master */
610 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
611 result = phy_write(phydev, MII_CTRL1000, result);
613 goto err_force_master;
617 return ksz9031_center_flp_timing(phydev);
620 phydev_err(phydev, "failed to force the phy to master mode\n");
624 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
625 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
626 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
627 static int ksz8873mll_read_status(struct phy_device *phydev)
632 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
634 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
636 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
637 phydev->duplex = DUPLEX_HALF;
639 phydev->duplex = DUPLEX_FULL;
641 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
642 phydev->speed = SPEED_10;
644 phydev->speed = SPEED_100;
647 phydev->pause = phydev->asym_pause = 0;
652 static int ksz9031_read_status(struct phy_device *phydev)
657 err = genphy_read_status(phydev);
661 /* Make sure the PHY is not broken. Read idle error count,
662 * and reset the PHY if it is maxed out.
664 regval = phy_read(phydev, MII_STAT1000);
665 if ((regval & 0xFF) == 0xFF) {
668 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
669 phydev->drv->config_intr(phydev);
670 return genphy_config_aneg(phydev);
676 static int ksz8873mll_config_aneg(struct phy_device *phydev)
681 static int kszphy_get_sset_count(struct phy_device *phydev)
683 return ARRAY_SIZE(kszphy_hw_stats);
686 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
690 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
691 strlcpy(data + i * ETH_GSTRING_LEN,
692 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
696 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
698 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
699 struct kszphy_priv *priv = phydev->priv;
703 val = phy_read(phydev, stat.reg);
707 val = val & ((1 << stat.bits) - 1);
708 priv->stats[i] += val;
709 ret = priv->stats[i];
715 static void kszphy_get_stats(struct phy_device *phydev,
716 struct ethtool_stats *stats, u64 *data)
720 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
721 data[i] = kszphy_get_stat(phydev, i);
724 static int kszphy_suspend(struct phy_device *phydev)
726 /* Disable PHY Interrupts */
727 if (phy_interrupt_is_valid(phydev)) {
728 phydev->interrupts = PHY_INTERRUPT_DISABLED;
729 if (phydev->drv->config_intr)
730 phydev->drv->config_intr(phydev);
733 return genphy_suspend(phydev);
736 static int kszphy_resume(struct phy_device *phydev)
740 genphy_resume(phydev);
742 /* After switching from power-down to normal mode, an internal global
743 * reset is automatically generated. Wait a minimum of 1 ms before
744 * read/write access to the PHY registers.
746 usleep_range(1000, 2000);
748 ret = kszphy_config_reset(phydev);
752 /* Enable PHY Interrupts */
753 if (phy_interrupt_is_valid(phydev)) {
754 phydev->interrupts = PHY_INTERRUPT_ENABLED;
755 if (phydev->drv->config_intr)
756 phydev->drv->config_intr(phydev);
762 static int kszphy_probe(struct phy_device *phydev)
764 const struct kszphy_type *type = phydev->drv->driver_data;
765 const struct device_node *np = phydev->mdio.dev.of_node;
766 struct kszphy_priv *priv;
770 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
778 if (type->led_mode_reg) {
779 ret = of_property_read_u32(np, "micrel,led-mode",
784 if (priv->led_mode > 3) {
785 phydev_err(phydev, "invalid led mode: 0x%02x\n",
793 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
794 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
795 if (!IS_ERR_OR_NULL(clk)) {
796 unsigned long rate = clk_get_rate(clk);
797 bool rmii_ref_clk_sel_25_mhz;
799 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
800 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
801 "micrel,rmii-reference-clock-select-25-mhz");
803 if (rate > 24500000 && rate < 25500000) {
804 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
805 } else if (rate > 49500000 && rate < 50500000) {
806 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
808 phydev_err(phydev, "Clock rate out of range: %ld\n",
814 /* Support legacy board-file configuration */
815 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
816 priv->rmii_ref_clk_sel = true;
817 priv->rmii_ref_clk_sel_val = true;
823 static struct phy_driver ksphy_driver[] = {
825 .phy_id = PHY_ID_KS8737,
826 .phy_id_mask = MICREL_PHY_ID_MASK,
827 .name = "Micrel KS8737",
828 .features = PHY_BASIC_FEATURES,
829 .flags = PHY_HAS_INTERRUPT,
830 .driver_data = &ks8737_type,
831 .config_init = kszphy_config_init,
832 .ack_interrupt = kszphy_ack_interrupt,
833 .config_intr = kszphy_config_intr,
834 .suspend = genphy_suspend,
835 .resume = genphy_resume,
837 .phy_id = PHY_ID_KSZ8021,
838 .phy_id_mask = 0x00ffffff,
839 .name = "Micrel KSZ8021 or KSZ8031",
840 .features = PHY_BASIC_FEATURES,
841 .flags = PHY_HAS_INTERRUPT,
842 .driver_data = &ksz8021_type,
843 .probe = kszphy_probe,
844 .config_init = kszphy_config_init,
845 .ack_interrupt = kszphy_ack_interrupt,
846 .config_intr = kszphy_config_intr,
847 .get_sset_count = kszphy_get_sset_count,
848 .get_strings = kszphy_get_strings,
849 .get_stats = kszphy_get_stats,
850 .suspend = genphy_suspend,
851 .resume = genphy_resume,
853 .phy_id = PHY_ID_KSZ8031,
854 .phy_id_mask = 0x00ffffff,
855 .name = "Micrel KSZ8031",
856 .features = PHY_BASIC_FEATURES,
857 .flags = PHY_HAS_INTERRUPT,
858 .driver_data = &ksz8021_type,
859 .probe = kszphy_probe,
860 .config_init = kszphy_config_init,
861 .ack_interrupt = kszphy_ack_interrupt,
862 .config_intr = kszphy_config_intr,
863 .get_sset_count = kszphy_get_sset_count,
864 .get_strings = kszphy_get_strings,
865 .get_stats = kszphy_get_stats,
866 .suspend = genphy_suspend,
867 .resume = genphy_resume,
869 .phy_id = PHY_ID_KSZ8041,
870 .phy_id_mask = MICREL_PHY_ID_MASK,
871 .name = "Micrel KSZ8041",
872 .features = PHY_BASIC_FEATURES,
873 .flags = PHY_HAS_INTERRUPT,
874 .driver_data = &ksz8041_type,
875 .probe = kszphy_probe,
876 .config_init = ksz8041_config_init,
877 .config_aneg = ksz8041_config_aneg,
878 .ack_interrupt = kszphy_ack_interrupt,
879 .config_intr = kszphy_config_intr,
880 .get_sset_count = kszphy_get_sset_count,
881 .get_strings = kszphy_get_strings,
882 .get_stats = kszphy_get_stats,
883 /* No suspend/resume callbacks because of errata DS80000700A,
884 * receiver error following software power down.
887 .phy_id = PHY_ID_KSZ8041RNLI,
888 .phy_id_mask = MICREL_PHY_ID_MASK,
889 .name = "Micrel KSZ8041RNLI",
890 .features = PHY_BASIC_FEATURES,
891 .flags = PHY_HAS_INTERRUPT,
892 .driver_data = &ksz8041_type,
893 .probe = kszphy_probe,
894 .config_init = kszphy_config_init,
895 .ack_interrupt = kszphy_ack_interrupt,
896 .config_intr = kszphy_config_intr,
897 .get_sset_count = kszphy_get_sset_count,
898 .get_strings = kszphy_get_strings,
899 .get_stats = kszphy_get_stats,
900 .suspend = genphy_suspend,
901 .resume = genphy_resume,
903 .phy_id = PHY_ID_KSZ8051,
904 .phy_id_mask = MICREL_PHY_ID_MASK,
905 .name = "Micrel KSZ8051",
906 .features = PHY_BASIC_FEATURES,
907 .flags = PHY_HAS_INTERRUPT,
908 .driver_data = &ksz8051_type,
909 .probe = kszphy_probe,
910 .config_init = kszphy_config_init,
911 .ack_interrupt = kszphy_ack_interrupt,
912 .config_intr = kszphy_config_intr,
913 .get_sset_count = kszphy_get_sset_count,
914 .get_strings = kszphy_get_strings,
915 .get_stats = kszphy_get_stats,
916 .suspend = genphy_suspend,
917 .resume = genphy_resume,
919 .phy_id = PHY_ID_KSZ8001,
920 .name = "Micrel KSZ8001 or KS8721",
921 .phy_id_mask = 0x00fffffc,
922 .features = PHY_BASIC_FEATURES,
923 .flags = PHY_HAS_INTERRUPT,
924 .driver_data = &ksz8041_type,
925 .probe = kszphy_probe,
926 .config_init = kszphy_config_init,
927 .ack_interrupt = kszphy_ack_interrupt,
928 .config_intr = kszphy_config_intr,
929 .get_sset_count = kszphy_get_sset_count,
930 .get_strings = kszphy_get_strings,
931 .get_stats = kszphy_get_stats,
932 .suspend = genphy_suspend,
933 .resume = genphy_resume,
935 .phy_id = PHY_ID_KSZ8081,
936 .name = "Micrel KSZ8081 or KSZ8091",
937 .phy_id_mask = MICREL_PHY_ID_MASK,
938 .features = PHY_BASIC_FEATURES,
939 .flags = PHY_HAS_INTERRUPT,
940 .driver_data = &ksz8081_type,
941 .probe = kszphy_probe,
942 .config_init = kszphy_config_init,
943 .ack_interrupt = kszphy_ack_interrupt,
944 .config_intr = kszphy_config_intr,
945 .get_sset_count = kszphy_get_sset_count,
946 .get_strings = kszphy_get_strings,
947 .get_stats = kszphy_get_stats,
948 .suspend = kszphy_suspend,
949 .resume = kszphy_resume,
951 .phy_id = PHY_ID_KSZ8061,
952 .name = "Micrel KSZ8061",
953 .phy_id_mask = MICREL_PHY_ID_MASK,
954 .features = PHY_BASIC_FEATURES,
955 .flags = PHY_HAS_INTERRUPT,
956 .config_init = ksz8061_config_init,
957 .ack_interrupt = kszphy_ack_interrupt,
958 .config_intr = kszphy_config_intr,
959 .suspend = genphy_suspend,
960 .resume = genphy_resume,
962 .phy_id = PHY_ID_KSZ9021,
963 .phy_id_mask = 0x000ffffe,
964 .name = "Micrel KSZ9021 Gigabit PHY",
965 .features = PHY_GBIT_FEATURES,
966 .flags = PHY_HAS_INTERRUPT,
967 .driver_data = &ksz9021_type,
968 .probe = kszphy_probe,
969 .config_init = ksz9021_config_init,
970 .ack_interrupt = kszphy_ack_interrupt,
971 .config_intr = kszphy_config_intr,
972 .get_sset_count = kszphy_get_sset_count,
973 .get_strings = kszphy_get_strings,
974 .get_stats = kszphy_get_stats,
975 .suspend = genphy_suspend,
976 .resume = genphy_resume,
977 .read_mmd = genphy_read_mmd_unsupported,
978 .write_mmd = genphy_write_mmd_unsupported,
980 .phy_id = PHY_ID_KSZ9031,
981 .phy_id_mask = MICREL_PHY_ID_MASK,
982 .name = "Micrel KSZ9031 Gigabit PHY",
983 .features = PHY_GBIT_FEATURES,
984 .flags = PHY_HAS_INTERRUPT,
985 .driver_data = &ksz9021_type,
986 .probe = kszphy_probe,
987 .config_init = ksz9031_config_init,
988 .soft_reset = genphy_soft_reset,
989 .read_status = ksz9031_read_status,
990 .ack_interrupt = kszphy_ack_interrupt,
991 .config_intr = kszphy_config_intr,
992 .get_sset_count = kszphy_get_sset_count,
993 .get_strings = kszphy_get_strings,
994 .get_stats = kszphy_get_stats,
995 .suspend = genphy_suspend,
996 .resume = kszphy_resume,
998 .phy_id = PHY_ID_KSZ8873MLL,
999 .phy_id_mask = MICREL_PHY_ID_MASK,
1000 .name = "Micrel KSZ8873MLL Switch",
1001 .config_init = kszphy_config_init,
1002 .config_aneg = ksz8873mll_config_aneg,
1003 .read_status = ksz8873mll_read_status,
1004 .suspend = genphy_suspend,
1005 .resume = genphy_resume,
1007 .phy_id = PHY_ID_KSZ886X,
1008 .phy_id_mask = MICREL_PHY_ID_MASK,
1009 .name = "Micrel KSZ886X Switch",
1010 .features = PHY_BASIC_FEATURES,
1011 .flags = PHY_HAS_INTERRUPT,
1012 .config_init = kszphy_config_init,
1013 .suspend = genphy_suspend,
1014 .resume = genphy_resume,
1016 .phy_id = PHY_ID_KSZ8795,
1017 .phy_id_mask = MICREL_PHY_ID_MASK,
1018 .name = "Micrel KSZ8795",
1019 .features = PHY_BASIC_FEATURES,
1020 .flags = PHY_HAS_INTERRUPT,
1021 .config_init = kszphy_config_init,
1022 .config_aneg = ksz8873mll_config_aneg,
1023 .read_status = ksz8873mll_read_status,
1024 .suspend = genphy_suspend,
1025 .resume = genphy_resume,
1027 .phy_id = PHY_ID_KSZ9477,
1028 .phy_id_mask = MICREL_PHY_ID_MASK,
1029 .name = "Microchip KSZ9477",
1030 .features = PHY_GBIT_FEATURES,
1031 .config_init = kszphy_config_init,
1032 .suspend = genphy_suspend,
1033 .resume = genphy_resume,
1036 module_phy_driver(ksphy_driver);
1038 MODULE_DESCRIPTION("Micrel PHY driver");
1039 MODULE_AUTHOR("David J. Choi");
1040 MODULE_LICENSE("GPL");
1042 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1043 { PHY_ID_KSZ9021, 0x000ffffe },
1044 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1045 { PHY_ID_KSZ8001, 0x00fffffc },
1046 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1047 { PHY_ID_KSZ8021, 0x00ffffff },
1048 { PHY_ID_KSZ8031, 0x00ffffff },
1049 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1050 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1051 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1052 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1053 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1054 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1058 MODULE_DEVICE_TABLE(mdio, micrel_tbl);