1 /* Applied Micro X-Gene SoC MDIO Driver
3 * Copyright (c) 2016, Applied Micro Circuits Corporation
4 * Author: Iyappan Subramanian <isubramanian@apm.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/acpi.h>
21 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/efi.h>
24 #include <linux/if_vlan.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_net.h>
29 #include <linux/of_mdio.h>
30 #include <linux/prefetch.h>
31 #include <linux/phy.h>
33 #include "mdio-xgene.h"
35 static bool xgene_mdio_status;
37 static u32 xgene_enet_rd_mac(void __iomem *base_addr, u32 rd_addr)
39 void __iomem *addr, *rd, *cmd, *cmd_done;
40 u32 done, rd_data = BUSY_MASK;
43 addr = base_addr + MAC_ADDR_REG_OFFSET;
44 rd = base_addr + MAC_READ_REG_OFFSET;
45 cmd = base_addr + MAC_COMMAND_REG_OFFSET;
46 cmd_done = base_addr + MAC_COMMAND_DONE_REG_OFFSET;
48 iowrite32(rd_addr, addr);
49 iowrite32(XGENE_ENET_RD_CMD, cmd);
52 done = ioread32(cmd_done);
61 rd_data = ioread32(rd);
67 static void xgene_enet_wr_mac(void __iomem *base_addr, u32 wr_addr, u32 wr_data)
69 void __iomem *addr, *wr, *cmd, *cmd_done;
73 addr = base_addr + MAC_ADDR_REG_OFFSET;
74 wr = base_addr + MAC_WRITE_REG_OFFSET;
75 cmd = base_addr + MAC_COMMAND_REG_OFFSET;
76 cmd_done = base_addr + MAC_COMMAND_DONE_REG_OFFSET;
78 iowrite32(wr_addr, addr);
79 iowrite32(wr_data, wr);
80 iowrite32(XGENE_ENET_WR_CMD, cmd);
83 done = ioread32(cmd_done);
90 pr_err("MCX mac write failed, addr: 0x%04x\n", wr_addr);
95 int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg)
97 void __iomem *addr = (void __iomem *)bus->priv;
101 data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
102 xgene_enet_wr_mac(addr, MII_MGMT_ADDRESS_ADDR, data);
103 xgene_enet_wr_mac(addr, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
106 done = xgene_enet_rd_mac(addr, MII_MGMT_INDICATORS_ADDR);
107 } while ((done & BUSY_MASK) && wait--);
109 if (done & BUSY_MASK) {
110 dev_err(&bus->dev, "MII_MGMT read failed\n");
114 data = xgene_enet_rd_mac(addr, MII_MGMT_STATUS_ADDR);
115 xgene_enet_wr_mac(addr, MII_MGMT_COMMAND_ADDR, 0);
119 EXPORT_SYMBOL(xgene_mdio_rgmii_read);
121 int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data)
123 void __iomem *addr = (void __iomem *)bus->priv;
127 val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
128 xgene_enet_wr_mac(addr, MII_MGMT_ADDRESS_ADDR, val);
130 xgene_enet_wr_mac(addr, MII_MGMT_CONTROL_ADDR, data);
133 done = xgene_enet_rd_mac(addr, MII_MGMT_INDICATORS_ADDR);
134 } while ((done & BUSY_MASK) && wait--);
136 if (done & BUSY_MASK) {
137 dev_err(&bus->dev, "MII_MGMT write failed\n");
143 EXPORT_SYMBOL(xgene_mdio_rgmii_write);
145 static u32 xgene_menet_rd_diag_csr(struct xgene_mdio_pdata *pdata, u32 offset)
147 return ioread32(pdata->diag_csr_addr + offset);
150 static void xgene_menet_wr_diag_csr(struct xgene_mdio_pdata *pdata,
153 iowrite32(val, pdata->diag_csr_addr + offset);
156 static int xgene_enet_ecc_init(struct xgene_mdio_pdata *pdata)
161 xgene_menet_wr_diag_csr(pdata, MENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
163 usleep_range(100, 110);
164 data = xgene_menet_rd_diag_csr(pdata, MENET_BLOCK_MEM_RDY_ADDR);
165 } while ((data != 0xffffffff) && wait--);
167 if (data != 0xffffffff) {
168 dev_err(pdata->dev, "Failed to release memory from shutdown\n");
175 static void xgene_gmac_reset(struct xgene_mdio_pdata *pdata)
177 xgene_enet_wr_mac(pdata->mac_csr_addr, MAC_CONFIG_1_ADDR, SOFT_RESET);
178 xgene_enet_wr_mac(pdata->mac_csr_addr, MAC_CONFIG_1_ADDR, 0);
181 static int xgene_mdio_reset(struct xgene_mdio_pdata *pdata)
185 if (pdata->dev->of_node) {
186 clk_prepare_enable(pdata->clk);
188 clk_disable_unprepare(pdata->clk);
190 clk_prepare_enable(pdata->clk);
194 acpi_evaluate_object(ACPI_HANDLE(pdata->dev),
199 ret = xgene_enet_ecc_init(pdata);
201 if (pdata->dev->of_node)
202 clk_disable_unprepare(pdata->clk);
205 xgene_gmac_reset(pdata);
210 static void xgene_enet_rd_mdio_csr(void __iomem *base_addr,
211 u32 offset, u32 *val)
213 void __iomem *addr = base_addr + offset;
215 *val = ioread32(addr);
218 static void xgene_enet_wr_mdio_csr(void __iomem *base_addr,
221 void __iomem *addr = base_addr + offset;
223 iowrite32(val, addr);
226 static int xgene_xfi_mdio_write(struct mii_bus *bus, int phy_id,
229 void __iomem *addr = (void __iomem *)bus->priv;
233 val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) |
234 SET_VAL(HSTMIIMWRDAT, data);
235 xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val);
237 val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_WRITE);
238 xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val);
242 xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status);
243 } while ((status & BUSY_MASK) && timeout--);
245 xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0);
250 static int xgene_xfi_mdio_read(struct mii_bus *bus, int phy_id, int reg)
252 void __iomem *addr = (void __iomem *)bus->priv;
253 u32 data, status, val;
256 val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg);
257 xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val);
259 val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_READ);
260 xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val);
264 xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status);
265 } while ((status & BUSY_MASK) && timeout--);
267 if (status & BUSY_MASK) {
268 pr_err("XGENET_MII_MGMT write failed\n");
272 xgene_enet_rd_mdio_csr(addr, MIIMRD_FIELD_ADDR, &data);
273 xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0);
278 struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr)
280 struct phy_device *phy_dev;
282 phy_dev = get_phy_device(bus, phy_addr, false);
283 if (!phy_dev || IS_ERR(phy_dev))
286 if (phy_device_register(phy_dev))
287 phy_device_free(phy_dev);
291 EXPORT_SYMBOL(xgene_enet_phy_register);
294 static acpi_status acpi_register_phy(acpi_handle handle, u32 lvl,
295 void *context, void **ret)
297 struct mii_bus *mdio = context;
298 struct acpi_device *adev;
299 struct phy_device *phy_dev;
300 const union acpi_object *obj;
303 if (acpi_bus_get_device(handle, &adev))
306 if (acpi_dev_get_property(adev, "phy-channel", ACPI_TYPE_INTEGER, &obj))
308 phy_addr = obj->integer.value;
310 phy_dev = xgene_enet_phy_register(mdio, phy_addr);
311 adev->driver_data = phy_dev;
317 static const struct of_device_id xgene_mdio_of_match[] = {
319 .compatible = "apm,xgene-mdio-rgmii",
320 .data = (void *)XGENE_MDIO_RGMII
323 .compatible = "apm,xgene-mdio-xfi",
324 .data = (void *)XGENE_MDIO_XFI
328 MODULE_DEVICE_TABLE(of, xgene_mdio_of_match);
331 static const struct acpi_device_id xgene_mdio_acpi_match[] = {
332 { "APMC0D65", XGENE_MDIO_RGMII },
333 { "APMC0D66", XGENE_MDIO_XFI },
337 MODULE_DEVICE_TABLE(acpi, xgene_mdio_acpi_match);
341 static int xgene_mdio_probe(struct platform_device *pdev)
343 struct device *dev = &pdev->dev;
344 struct mii_bus *mdio_bus;
345 const struct of_device_id *of_id;
346 struct resource *res;
347 struct xgene_mdio_pdata *pdata;
348 void __iomem *csr_base;
349 int mdio_id = 0, ret = 0;
351 of_id = of_match_device(xgene_mdio_of_match, &pdev->dev);
353 mdio_id = (enum xgene_mdio_id)of_id->data;
356 const struct acpi_device_id *acpi_id;
358 acpi_id = acpi_match_device(xgene_mdio_acpi_match, &pdev->dev);
360 mdio_id = (enum xgene_mdio_id)acpi_id->driver_data;
367 pdata = devm_kzalloc(dev, sizeof(struct xgene_mdio_pdata), GFP_KERNEL);
370 pdata->mdio_id = mdio_id;
373 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
374 csr_base = devm_ioremap_resource(dev, res);
375 if (IS_ERR(csr_base))
376 return PTR_ERR(csr_base);
377 pdata->mac_csr_addr = csr_base;
378 pdata->mdio_csr_addr = csr_base + BLOCK_XG_MDIO_CSR_OFFSET;
379 pdata->diag_csr_addr = csr_base + BLOCK_DIAG_CSR_OFFSET;
382 pdata->clk = devm_clk_get(dev, NULL);
383 if (IS_ERR(pdata->clk)) {
384 dev_err(dev, "Unable to retrieve clk\n");
385 return PTR_ERR(pdata->clk);
389 ret = xgene_mdio_reset(pdata);
393 mdio_bus = mdiobus_alloc();
399 mdio_bus->name = "APM X-Gene MDIO bus";
401 if (mdio_id == XGENE_MDIO_RGMII) {
402 mdio_bus->read = xgene_mdio_rgmii_read;
403 mdio_bus->write = xgene_mdio_rgmii_write;
404 mdio_bus->priv = (void __force *)pdata->mac_csr_addr;
405 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s",
408 mdio_bus->read = xgene_xfi_mdio_read;
409 mdio_bus->write = xgene_xfi_mdio_write;
410 mdio_bus->priv = (void __force *)pdata->mdio_csr_addr;
411 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s",
415 mdio_bus->parent = dev;
416 platform_set_drvdata(pdev, pdata);
419 ret = of_mdiobus_register(mdio_bus, dev->of_node);
422 /* Mask out all PHYs from auto probing. */
423 mdio_bus->phy_mask = ~0;
424 ret = mdiobus_register(mdio_bus);
428 acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_HANDLE(dev), 1,
429 acpi_register_phy, NULL, mdio_bus, NULL);
436 pdata->mdio_bus = mdio_bus;
437 xgene_mdio_status = true;
442 mdiobus_free(mdio_bus);
446 clk_disable_unprepare(pdata->clk);
451 static int xgene_mdio_remove(struct platform_device *pdev)
453 struct xgene_mdio_pdata *pdata = platform_get_drvdata(pdev);
454 struct mii_bus *mdio_bus = pdata->mdio_bus;
455 struct device *dev = &pdev->dev;
457 mdiobus_unregister(mdio_bus);
458 mdiobus_free(mdio_bus);
461 clk_disable_unprepare(pdata->clk);
466 static struct platform_driver xgene_mdio_driver = {
468 .name = "xgene-mdio",
469 .of_match_table = of_match_ptr(xgene_mdio_of_match),
470 .acpi_match_table = ACPI_PTR(xgene_mdio_acpi_match),
472 .probe = xgene_mdio_probe,
473 .remove = xgene_mdio_remove,
476 module_platform_driver(xgene_mdio_driver);
478 MODULE_DESCRIPTION("APM X-Gene SoC MDIO driver");
479 MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
480 MODULE_LICENSE("GPL");