2 * Marvell 10G 88x3310 PHY driver
4 * Based upon the ID registers, this PHY appears to be a mixture of IPs
5 * from two different companies.
7 * There appears to be several different data paths through the PHY which
8 * are automatically managed by the PHY. The following has been determined
9 * via observation and experimentation:
11 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
12 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
13 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 * If both the fiber and copper ports are connected, the first to gain
16 * link takes priority and the other port is completely locked out.
18 #include <linux/phy.h>
19 #include <linux/marvell_phy.h>
23 MV_PMA_BOOT_FATAL = BIT(0),
25 MV_PCS_BASE_T = 0x0000,
26 MV_PCS_BASE_R = 0x1000,
27 MV_PCS_1000BASEX = 0x2000,
29 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
30 * registers appear to set themselves to the 0x800X when AN is
31 * restarted, but status registers appear readable from either.
33 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
34 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
36 /* This register appears to reflect the copper status */
37 MV_AN_RESULT = 0xa016,
38 MV_AN_RESULT_SPD_10 = BIT(12),
39 MV_AN_RESULT_SPD_100 = BIT(13),
40 MV_AN_RESULT_SPD_1000 = BIT(14),
41 MV_AN_RESULT_SPD_10000 = BIT(15),
44 static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
49 old = phy_read_mmd(phydev, devad, reg);
53 val = (old & ~mask) | (bits & mask);
57 ret = phy_write_mmd(phydev, devad, reg, val);
59 return ret < 0 ? ret : 1;
62 static int mv3310_probe(struct phy_device *phydev)
64 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
67 if (!phydev->is_c45 ||
68 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
71 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
75 if (ret & MV_PMA_BOOT_FATAL) {
76 dev_warn(&phydev->mdio.dev,
77 "PHY failed to boot firmware, status=%04x\n", ret);
85 * Resetting the MV88X3310 causes it to become non-responsive. Avoid
86 * setting the reset bit(s).
88 static int mv3310_soft_reset(struct phy_device *phydev)
93 static int mv3310_config_init(struct phy_device *phydev)
95 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
99 /* Check that the PHY interface type is compatible */
100 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
101 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
102 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
103 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
104 phydev->interface != PHY_INTERFACE_MODE_10GKR)
107 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
108 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
110 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
111 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
115 if (val & MDIO_AN_STAT1_ABLE)
116 __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
119 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
123 /* Ethtool does not support the WAN mode bits */
124 if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR |
125 MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 |
126 MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW |
127 MDIO_PMA_STAT2_10GBEW))
128 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
129 if (val & MDIO_PMA_STAT2_10GBSR)
130 __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
131 if (val & MDIO_PMA_STAT2_10GBLR)
132 __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
133 if (val & MDIO_PMA_STAT2_10GBER)
134 __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
136 if (val & MDIO_PMA_STAT2_EXTABLE) {
137 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
141 if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT |
142 MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT))
143 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
144 if (val & MDIO_PMA_EXTABLE_10GBLRM)
145 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
146 if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR |
147 MDIO_PMA_EXTABLE_1000BKX))
148 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported);
149 if (val & MDIO_PMA_EXTABLE_10GBLRM)
150 __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
152 if (val & MDIO_PMA_EXTABLE_10GBT)
153 __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
155 if (val & MDIO_PMA_EXTABLE_10GBKX4)
156 __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
158 if (val & MDIO_PMA_EXTABLE_10GBKR)
159 __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
161 if (val & MDIO_PMA_EXTABLE_1000BT)
162 __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
164 if (val & MDIO_PMA_EXTABLE_1000BKX)
165 __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
167 if (val & MDIO_PMA_EXTABLE_100BTX)
168 __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
170 if (val & MDIO_PMA_EXTABLE_10BT)
171 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
175 if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
176 dev_warn(&phydev->mdio.dev,
177 "PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
178 __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
180 phydev->supported &= mask;
181 phydev->advertising &= phydev->supported;
186 static int mv3310_config_aneg(struct phy_device *phydev)
188 bool changed = false;
192 if (phydev->autoneg == AUTONEG_DISABLE) {
193 ret = genphy_c45_pma_setup_forced(phydev);
197 return genphy_c45_an_disable_aneg(phydev);
200 phydev->advertising &= phydev->supported;
201 advertising = phydev->advertising;
203 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
204 ADVERTISE_ALL | ADVERTISE_100BASE4 |
205 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
206 ethtool_adv_to_mii_adv_t(advertising));
212 ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
213 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
214 ethtool_adv_to_mii_ctrl1000_t(advertising));
220 /* 10G control register */
221 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
222 MDIO_AN_10GBT_CTRL_ADV10G,
223 advertising & ADVERTISED_10000baseT_Full ?
224 MDIO_AN_10GBT_CTRL_ADV10G : 0);
231 ret = genphy_c45_restart_aneg(phydev);
236 static int mv3310_aneg_done(struct phy_device *phydev)
240 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
244 if (val & MDIO_STAT1_LSTATUS)
247 return genphy_c45_aneg_done(phydev);
250 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
251 static int mv3310_read_10gbr_status(struct phy_device *phydev)
254 phydev->speed = SPEED_10000;
255 phydev->duplex = DUPLEX_FULL;
257 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
258 phydev->interface = PHY_INTERFACE_MODE_10GKR;
263 static int mv3310_read_status(struct phy_device *phydev)
265 u32 mmd_mask = phydev->c45_ids.devices_in_package;
268 /* The vendor devads do not report link status. Avoid the PHYXS
269 * instance as there are three, and its status depends on the MAC
270 * being appropriately configured for the negotiated speed.
272 mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) |
273 BIT(MDIO_MMD_PHYXS));
275 phydev->speed = SPEED_UNKNOWN;
276 phydev->duplex = DUPLEX_UNKNOWN;
277 phydev->lp_advertising = 0;
280 phydev->asym_pause = 0;
282 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
286 if (val & MDIO_STAT1_LSTATUS)
287 return mv3310_read_10gbr_status(phydev);
289 val = genphy_c45_read_link(phydev, mmd_mask);
293 phydev->link = val > 0 ? 1 : 0;
295 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
299 if (val & MDIO_AN_STAT1_COMPLETE) {
300 val = genphy_c45_read_lpa(phydev);
304 /* Read the link partner's 1G advertisment */
305 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
309 phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);
311 if (phydev->autoneg == AUTONEG_ENABLE) {
312 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_RESULT);
316 if (val & MV_AN_RESULT_SPD_10000)
317 phydev->speed = SPEED_10000;
318 else if (val & MV_AN_RESULT_SPD_1000)
319 phydev->speed = SPEED_1000;
320 else if (val & MV_AN_RESULT_SPD_100)
321 phydev->speed = SPEED_100;
322 else if (val & MV_AN_RESULT_SPD_10)
323 phydev->speed = SPEED_10;
325 phydev->duplex = DUPLEX_FULL;
329 if (phydev->autoneg != AUTONEG_ENABLE) {
330 val = genphy_c45_read_pma(phydev);
335 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
336 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
337 /* The PHY automatically switches its serdes interface (and
338 * active PHYXS instance) between Cisco SGMII and 10GBase-KR
339 * modes according to the speed. Florian suggests setting
340 * phydev->interface to communicate this to the MAC. Only do
341 * this if we are already in either SGMII or 10GBase-KR mode.
343 if (phydev->speed == SPEED_10000)
344 phydev->interface = PHY_INTERFACE_MODE_10GKR;
345 else if (phydev->speed >= SPEED_10 &&
346 phydev->speed < SPEED_10000)
347 phydev->interface = PHY_INTERFACE_MODE_SGMII;
353 static struct phy_driver mv3310_drivers[] = {
355 .phy_id = 0x002b09aa,
356 .phy_id_mask = MARVELL_PHY_ID_MASK,
358 .features = SUPPORTED_10baseT_Full |
359 SUPPORTED_100baseT_Full |
360 SUPPORTED_1000baseT_Full |
364 SUPPORTED_10000baseT_Full |
366 .probe = mv3310_probe,
367 .soft_reset = mv3310_soft_reset,
368 .config_init = mv3310_config_init,
369 .config_aneg = mv3310_config_aneg,
370 .aneg_done = mv3310_aneg_done,
371 .read_status = mv3310_read_status,
375 module_phy_driver(mv3310_drivers);
377 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
378 { 0x002b09aa, MARVELL_PHY_ID_MASK },
381 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
382 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
383 MODULE_LICENSE("GPL");