2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
30 #include <linux/module.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/phy.h>
34 #include <linux/marvell_phy.h>
39 #include <linux/uaccess.h>
41 #define MII_MARVELL_PHY_PAGE 22
43 #define MII_M1011_IEVENT 0x13
44 #define MII_M1011_IEVENT_CLEAR 0x0000
46 #define MII_M1011_IMASK 0x12
47 #define MII_M1011_IMASK_INIT 0x6400
48 #define MII_M1011_IMASK_CLEAR 0x0000
50 #define MII_M1011_PHY_SCR 0x10
51 #define MII_M1011_PHY_SCR_MDI 0x0000
52 #define MII_M1011_PHY_SCR_MDI_X 0x0020
53 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
55 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
56 #define MII_M1145_PHY_EXT_SR 0x1b
57 #define MII_M1145_PHY_EXT_CR 0x14
58 #define MII_M1145_RGMII_RX_DELAY 0x0080
59 #define MII_M1145_RGMII_TX_DELAY 0x0002
60 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61 #define MII_M1145_HWCFG_MODE_MASK 0xf
62 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
64 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65 #define MII_M1145_HWCFG_MODE_MASK 0xf
66 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_RX_DELAY 0x80
73 #define MII_M1111_TX_DELAY 0x2
74 #define MII_M1111_PHY_EXT_SR 0x1b
76 #define MII_M1111_HWCFG_MODE_MASK 0xf
77 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
79 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
80 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
81 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
84 #define MII_M1111_COPPER 0
85 #define MII_M1111_FIBER 1
87 #define MII_88E1121_PHY_MSCR_PAGE 2
88 #define MII_88E1121_PHY_MSCR_REG 21
89 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
93 #define MII_88E1318S_PHY_MSCR1_REG 16
94 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
96 /* Copper Specific Interrupt Enable Register */
97 #define MII_88E1318S_PHY_CSIER 0x12
98 /* WOL Event Interrupt Enable */
99 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
101 /* LED Timer Control Register */
102 #define MII_88E1318S_PHY_LED_PAGE 0x03
103 #define MII_88E1318S_PHY_LED_TCR 0x12
104 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
108 /* Magic Packet MAC address registers */
109 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
113 #define MII_88E1318S_PHY_WOL_PAGE 0x11
114 #define MII_88E1318S_PHY_WOL_CTRL 0x10
115 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
118 #define MII_88E1121_PHY_LED_CTRL 16
119 #define MII_88E1121_PHY_LED_PAGE 3
120 #define MII_88E1121_PHY_LED_DEF 0x0030
122 #define MII_M1011_PHY_STATUS 0x11
123 #define MII_M1011_PHY_STATUS_1000 0x8000
124 #define MII_M1011_PHY_STATUS_100 0x4000
125 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128 #define MII_M1011_PHY_STATUS_LINK 0x0400
130 #define MII_M1116R_CONTROL_REG_MAC 21
132 #define MII_88E3016_PHY_SPEC_CTRL 0x10
133 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
136 #define MII_88E1510_GEN_CTRL_REG_1 0x14
137 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
141 #define LPA_FIBER_1000HALF 0x40
142 #define LPA_FIBER_1000FULL 0x20
144 #define LPA_PAUSE_FIBER 0x180
145 #define LPA_PAUSE_ASYM_FIBER 0x100
147 #define ADVERTISE_FIBER_1000HALF 0x40
148 #define ADVERTISE_FIBER_1000FULL 0x20
150 #define ADVERTISE_PAUSE_FIBER 0x180
151 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100
153 #define REGISTER_LINK_STATUS 0x400
154 #define NB_FIBER_STATS 1
156 MODULE_DESCRIPTION("Marvell PHY driver");
157 MODULE_AUTHOR("Andy Fleming");
158 MODULE_LICENSE("GPL");
160 struct marvell_hw_stat {
167 static struct marvell_hw_stat marvell_hw_stats[] = {
168 { "phy_receive_errors_copper", 0, 21, 16},
169 { "phy_idle_errors", 0, 10, 8 },
170 { "phy_receive_errors_fiber", 1, 21, 16},
173 struct marvell_priv {
174 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
177 static int marvell_ack_interrupt(struct phy_device *phydev)
181 /* Clear the interrupts by reading the reg */
182 err = phy_read(phydev, MII_M1011_IEVENT);
190 static int marvell_config_intr(struct phy_device *phydev)
194 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
195 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
197 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
202 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
208 /* get the current settings */
209 reg = phy_read(phydev, MII_M1011_PHY_SCR);
214 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
217 val |= MII_M1011_PHY_SCR_MDI;
220 val |= MII_M1011_PHY_SCR_MDI_X;
222 case ETH_TP_MDI_AUTO:
223 case ETH_TP_MDI_INVALID:
225 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
230 /* Set the new polarity value in the register */
231 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
239 static int marvell_config_aneg(struct phy_device *phydev)
243 err = marvell_set_polarity(phydev, phydev->mdix);
247 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
248 MII_M1111_PHY_LED_DIRECT);
252 err = genphy_config_aneg(phydev);
256 if (phydev->autoneg != AUTONEG_ENABLE) {
260 * A write to speed/duplex bits (that is performed by
261 * genphy_config_aneg() call above) must be followed by
262 * a software reset. Otherwise, the write has no effect.
264 bmcr = phy_read(phydev, MII_BMCR);
268 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
276 static int m88e1101_config_aneg(struct phy_device *phydev)
280 /* This Marvell PHY has an errata which requires
281 * that certain registers get written in order
282 * to restart autonegotiation
284 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
289 err = phy_write(phydev, 0x1d, 0x1f);
293 err = phy_write(phydev, 0x1e, 0x200c);
297 err = phy_write(phydev, 0x1d, 0x5);
301 err = phy_write(phydev, 0x1e, 0);
305 err = phy_write(phydev, 0x1e, 0x100);
309 return marvell_config_aneg(phydev);
312 static int m88e1111_config_aneg(struct phy_device *phydev)
316 /* The Marvell PHY has an errata which requires
317 * that certain registers get written in order
318 * to restart autonegotiation
320 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
322 err = marvell_set_polarity(phydev, phydev->mdix);
326 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
327 MII_M1111_PHY_LED_DIRECT);
331 err = genphy_config_aneg(phydev);
335 if (phydev->autoneg != AUTONEG_ENABLE) {
338 /* A write to speed/duplex bits (that is performed by
339 * genphy_config_aneg() call above) must be followed by
340 * a software reset. Otherwise, the write has no effect.
342 bmcr = phy_read(phydev, MII_BMCR);
346 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
354 #ifdef CONFIG_OF_MDIO
356 * Set and/or override some configuration registers based on the
357 * marvell,reg-init property stored in the of_node for the phydev.
359 * marvell,reg-init = <reg-page reg mask value>,...;
361 * There may be one or more sets of <reg-page reg mask value>:
363 * reg-page: which register bank to use.
365 * mask: if non-zero, ANDed with existing register value.
366 * value: ORed with the masked value and written to the regiser.
369 static int marvell_of_reg_init(struct phy_device *phydev)
372 int len, i, saved_page, current_page, page_changed, ret;
374 if (!phydev->mdio.dev.of_node)
377 paddr = of_get_property(phydev->mdio.dev.of_node,
378 "marvell,reg-init", &len);
379 if (!paddr || len < (4 * sizeof(*paddr)))
382 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
386 current_page = saved_page;
389 len /= sizeof(*paddr);
390 for (i = 0; i < len - 3; i += 4) {
391 u16 reg_page = be32_to_cpup(paddr + i);
392 u16 reg = be32_to_cpup(paddr + i + 1);
393 u16 mask = be32_to_cpup(paddr + i + 2);
394 u16 val_bits = be32_to_cpup(paddr + i + 3);
397 if (reg_page != current_page) {
398 current_page = reg_page;
400 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
407 val = phy_read(phydev, reg);
416 ret = phy_write(phydev, reg, val);
423 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
430 static int marvell_of_reg_init(struct phy_device *phydev)
434 #endif /* CONFIG_OF_MDIO */
436 static int m88e1121_config_aneg(struct phy_device *phydev)
438 int err, oldpage, mscr;
440 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
442 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
443 MII_88E1121_PHY_MSCR_PAGE);
447 if (phy_interface_is_rgmii(phydev)) {
449 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
450 MII_88E1121_PHY_MSCR_DELAY_MASK;
452 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
453 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
454 MII_88E1121_PHY_MSCR_TX_DELAY);
455 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
456 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
457 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
458 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
460 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
465 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
467 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
471 err = phy_write(phydev, MII_M1011_PHY_SCR,
472 MII_M1011_PHY_SCR_AUTO_CROSS);
476 return genphy_config_aneg(phydev);
479 static int m88e1318_config_aneg(struct phy_device *phydev)
481 int err, oldpage, mscr;
483 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
485 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
486 MII_88E1121_PHY_MSCR_PAGE);
490 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
491 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
493 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
497 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
501 return m88e1121_config_aneg(phydev);
505 * ethtool_adv_to_fiber_adv_t
506 * @ethadv: the ethtool advertisement settings
508 * A small helper function that translates ethtool advertisement
509 * settings to phy autonegotiation advertisements for the
510 * MII_ADV register for fiber link.
512 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
516 if (ethadv & ADVERTISED_1000baseT_Half)
517 result |= ADVERTISE_FIBER_1000HALF;
518 if (ethadv & ADVERTISED_1000baseT_Full)
519 result |= ADVERTISE_FIBER_1000FULL;
521 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
522 result |= LPA_PAUSE_ASYM_FIBER;
523 else if (ethadv & ADVERTISE_PAUSE_CAP)
524 result |= (ADVERTISE_PAUSE_FIBER
525 & (~ADVERTISE_PAUSE_ASYM_FIBER));
531 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
532 * @phydev: target phy_device struct
534 * Description: If auto-negotiation is enabled, we configure the
535 * advertising, and then restart auto-negotiation. If it is not
536 * enabled, then we write the BMCR. Adapted for fiber link in
537 * some Marvell's devices.
539 static int marvell_config_aneg_fiber(struct phy_device *phydev)
546 if (phydev->autoneg != AUTONEG_ENABLE)
547 return genphy_setup_forced(phydev);
549 /* Only allow advertising what this PHY supports */
550 phydev->advertising &= phydev->supported;
551 advertise = phydev->advertising;
553 /* Setup fiber advertisement */
554 adv = phy_read(phydev, MII_ADVERTISE);
559 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
561 adv |= ethtool_adv_to_fiber_adv_t(advertise);
564 err = phy_write(phydev, MII_ADVERTISE, adv);
572 /* Advertisement hasn't changed, but maybe aneg was never on to
573 * begin with? Or maybe phy was isolated?
575 int ctl = phy_read(phydev, MII_BMCR);
580 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
581 changed = 1; /* do restart aneg */
584 /* Only restart aneg if we are advertising something different
585 * than we were before.
588 changed = genphy_restart_aneg(phydev);
593 static int m88e1510_config_aneg(struct phy_device *phydev)
597 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
601 /* Configure the copper link first */
602 err = m88e1318_config_aneg(phydev);
606 /* Then the fiber link */
607 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
611 err = marvell_config_aneg_fiber(phydev);
615 return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
618 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
622 static int marvell_config_init(struct phy_device *phydev)
624 /* Set registers from marvell,reg-init DT property */
625 return marvell_of_reg_init(phydev);
628 static int m88e1116r_config_init(struct phy_device *phydev)
633 temp = phy_read(phydev, MII_BMCR);
635 err = phy_write(phydev, MII_BMCR, temp);
641 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
645 temp = phy_read(phydev, MII_M1011_PHY_SCR);
646 temp |= (7 << 12); /* max number of gigabit attempts */
647 temp |= (1 << 11); /* enable downshift */
648 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
649 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
653 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
656 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
659 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
662 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
666 temp = phy_read(phydev, MII_BMCR);
668 err = phy_write(phydev, MII_BMCR, temp);
674 return marvell_config_init(phydev);
677 static int m88e3016_config_init(struct phy_device *phydev)
681 /* Enable Scrambler and Auto-Crossover */
682 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
686 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
687 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
689 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
693 return marvell_config_init(phydev);
696 static int m88e1111_config_init(struct phy_device *phydev)
701 if (phy_interface_is_rgmii(phydev)) {
703 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
707 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
708 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
709 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
710 temp &= ~MII_M1111_TX_DELAY;
711 temp |= MII_M1111_RX_DELAY;
712 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
713 temp &= ~MII_M1111_RX_DELAY;
714 temp |= MII_M1111_TX_DELAY;
717 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
721 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
725 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
727 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
728 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
730 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
732 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
737 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
738 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
742 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
743 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
744 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
746 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
750 /* make sure copper is selected */
751 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
755 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
761 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
762 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
765 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
766 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
770 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
773 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
774 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
775 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
780 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
784 temp = phy_read(phydev, MII_BMCR);
785 while (temp & BMCR_RESET);
787 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
790 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
791 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
792 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
797 err = marvell_of_reg_init(phydev);
801 return phy_write(phydev, MII_BMCR, BMCR_RESET);
804 static int m88e1121_config_init(struct phy_device *phydev)
808 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
810 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
814 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
815 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
816 MII_88E1121_PHY_LED_DEF);
820 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
822 /* Set marvell,reg-init configuration from device tree */
823 return marvell_config_init(phydev);
826 static int m88e1510_config_init(struct phy_device *phydev)
831 /* SGMII-to-Copper mode initialization */
832 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
834 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
838 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
839 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
840 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
841 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
842 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
846 /* PHY reset is necessary after changing MODE[2:0] */
847 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
848 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
852 /* Reset page selection */
853 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
858 return m88e1121_config_init(phydev);
861 static int m88e1118_config_aneg(struct phy_device *phydev)
865 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
869 err = phy_write(phydev, MII_M1011_PHY_SCR,
870 MII_M1011_PHY_SCR_AUTO_CROSS);
874 err = genphy_config_aneg(phydev);
878 static int m88e1118_config_init(struct phy_device *phydev)
883 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
887 /* Enable 1000 Mbit */
888 err = phy_write(phydev, 0x15, 0x1070);
893 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
897 /* Adjust LED Control */
898 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
899 err = phy_write(phydev, 0x10, 0x1100);
901 err = phy_write(phydev, 0x10, 0x021e);
905 err = marvell_of_reg_init(phydev);
910 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
914 return phy_write(phydev, MII_BMCR, BMCR_RESET);
917 static int m88e1149_config_init(struct phy_device *phydev)
922 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
926 /* Enable 1000 Mbit */
927 err = phy_write(phydev, 0x15, 0x1048);
931 err = marvell_of_reg_init(phydev);
936 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
940 return phy_write(phydev, MII_BMCR, BMCR_RESET);
943 static int m88e1145_config_init(struct phy_device *phydev)
948 /* Take care of errata E0 & E1 */
949 err = phy_write(phydev, 0x1d, 0x001b);
953 err = phy_write(phydev, 0x1e, 0x418f);
957 err = phy_write(phydev, 0x1d, 0x0016);
961 err = phy_write(phydev, 0x1e, 0xa2da);
965 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
966 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
970 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
972 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
976 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
977 err = phy_write(phydev, 0x1d, 0x0012);
981 temp = phy_read(phydev, 0x1e);
986 temp |= 2 << 9; /* 36 ohm */
987 temp |= 2 << 6; /* 39 ohm */
989 err = phy_write(phydev, 0x1e, temp);
993 err = phy_write(phydev, 0x1d, 0x3);
997 err = phy_write(phydev, 0x1e, 0x8000);
1003 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1004 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
1008 temp &= ~MII_M1145_HWCFG_MODE_MASK;
1009 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1010 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1012 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1017 err = marvell_of_reg_init(phydev);
1025 * fiber_lpa_to_ethtool_lpa_t
1026 * @lpa: value of the MII_LPA register for fiber link
1028 * A small helper function that translates MII_LPA
1029 * bits to ethtool LP advertisement settings.
1031 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1035 if (lpa & LPA_FIBER_1000HALF)
1036 result |= ADVERTISED_1000baseT_Half;
1037 if (lpa & LPA_FIBER_1000FULL)
1038 result |= ADVERTISED_1000baseT_Full;
1044 * marvell_update_link - update link status in real time in @phydev
1045 * @phydev: target phy_device struct
1047 * Description: Update the value in phydev->link to reflect the
1048 * current link value.
1050 static int marvell_update_link(struct phy_device *phydev, int fiber)
1054 /* Use the generic register for copper link, or specific
1055 * register for fiber case */
1057 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1061 if ((status & REGISTER_LINK_STATUS) == 0)
1066 return genphy_update_link(phydev);
1072 /* marvell_read_status_page
1075 * Check the link, then figure out the current state
1076 * by comparing what we advertise with what the link partner
1077 * advertises. Start by checking the gigabit possibilities,
1078 * then move on to 10/100.
1080 static int marvell_read_status_page(struct phy_device *phydev, int page)
1089 /* Detect and update the link, but return if there
1091 if (page == MII_M1111_FIBER)
1096 err = marvell_update_link(phydev, fiber);
1100 if (AUTONEG_ENABLE == phydev->autoneg) {
1101 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1105 lpa = phy_read(phydev, MII_LPA);
1109 lpagb = phy_read(phydev, MII_STAT1000);
1113 adv = phy_read(phydev, MII_ADVERTISE);
1117 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1118 phydev->duplex = DUPLEX_FULL;
1120 phydev->duplex = DUPLEX_HALF;
1122 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1123 phydev->pause = phydev->asym_pause = 0;
1126 case MII_M1011_PHY_STATUS_1000:
1127 phydev->speed = SPEED_1000;
1130 case MII_M1011_PHY_STATUS_100:
1131 phydev->speed = SPEED_100;
1135 phydev->speed = SPEED_10;
1140 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
1141 mii_lpa_to_ethtool_lpa_t(lpa);
1143 if (phydev->duplex == DUPLEX_FULL) {
1144 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1145 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1148 /* The fiber link is only 1000M capable */
1149 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1151 if (phydev->duplex == DUPLEX_FULL) {
1152 if (!(lpa & LPA_PAUSE_FIBER)) {
1154 phydev->asym_pause = 0;
1155 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1157 phydev->asym_pause = 1;
1160 phydev->asym_pause = 0;
1165 int bmcr = phy_read(phydev, MII_BMCR);
1170 if (bmcr & BMCR_FULLDPLX)
1171 phydev->duplex = DUPLEX_FULL;
1173 phydev->duplex = DUPLEX_HALF;
1175 if (bmcr & BMCR_SPEED1000)
1176 phydev->speed = SPEED_1000;
1177 else if (bmcr & BMCR_SPEED100)
1178 phydev->speed = SPEED_100;
1180 phydev->speed = SPEED_10;
1182 phydev->pause = phydev->asym_pause = 0;
1183 phydev->lp_advertising = 0;
1189 /* marvell_read_status
1191 * Some Marvell's phys have two modes: fiber and copper.
1192 * Both need status checked.
1194 * First, check the fiber link and status.
1195 * If the fiber link is down, check the copper link and status which
1196 * will be the default value if both link are down.
1198 static int marvell_read_status(struct phy_device *phydev)
1202 /* Check the fiber mode first */
1203 if (phydev->supported & SUPPORTED_FIBRE &&
1204 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1205 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1209 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1213 /* If the fiber link is up, it is the selected and used link.
1214 * In this case, we need to stay in the fiber page.
1215 * Please to be careful about that, avoid to restore Copper page
1216 * in other functions which could break the behaviour
1217 * for some fiber phy like 88E1512.
1222 /* If fiber link is down, check and save copper mode state */
1223 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1228 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1231 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1237 * Some Marvell's phys have two modes: fiber and copper.
1238 * Both need to be suspended
1240 static int marvell_suspend(struct phy_device *phydev)
1244 /* Suspend the fiber mode first */
1245 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1246 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1250 /* With the page set, use the generic suspend */
1251 err = genphy_suspend(phydev);
1255 /* Then, the copper link */
1256 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1261 /* With the page set, use the generic suspend */
1262 return genphy_suspend(phydev);
1265 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1271 * Some Marvell's phys have two modes: fiber and copper.
1272 * Both need to be resumed
1274 static int marvell_resume(struct phy_device *phydev)
1278 /* Resume the fiber mode first */
1279 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1280 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1284 /* With the page set, use the generic resume */
1285 err = genphy_resume(phydev);
1289 /* Then, the copper link */
1290 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1295 /* With the page set, use the generic resume */
1296 return genphy_resume(phydev);
1299 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1303 static int marvell_aneg_done(struct phy_device *phydev)
1305 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1306 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1309 static int m88e1121_did_interrupt(struct phy_device *phydev)
1313 imask = phy_read(phydev, MII_M1011_IEVENT);
1315 if (imask & MII_M1011_IMASK_INIT)
1321 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1323 wol->supported = WAKE_MAGIC;
1326 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
1327 MII_88E1318S_PHY_WOL_PAGE) < 0)
1330 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1331 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1332 wol->wolopts |= WAKE_MAGIC;
1334 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
1338 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1340 int err, oldpage, temp;
1342 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1344 if (wol->wolopts & WAKE_MAGIC) {
1345 /* Explicitly switch to page 0x00, just to be sure */
1346 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
1350 /* Enable the WOL interrupt */
1351 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1352 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1353 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1357 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1358 MII_88E1318S_PHY_LED_PAGE);
1362 /* Setup LED[2] as interrupt pin (active low) */
1363 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1364 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1365 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1366 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1367 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1371 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1372 MII_88E1318S_PHY_WOL_PAGE);
1376 /* Store the device address for the magic packet */
1377 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1378 ((phydev->attached_dev->dev_addr[5] << 8) |
1379 phydev->attached_dev->dev_addr[4]));
1382 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1383 ((phydev->attached_dev->dev_addr[3] << 8) |
1384 phydev->attached_dev->dev_addr[2]));
1387 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1388 ((phydev->attached_dev->dev_addr[1] << 8) |
1389 phydev->attached_dev->dev_addr[0]));
1393 /* Clear WOL status and enable magic packet matching */
1394 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1395 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1396 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1397 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1401 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1402 MII_88E1318S_PHY_WOL_PAGE);
1406 /* Clear WOL status and disable magic packet matching */
1407 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1408 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1409 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1410 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1415 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1422 static int marvell_get_sset_count(struct phy_device *phydev)
1424 if (phydev->supported & SUPPORTED_FIBRE)
1425 return ARRAY_SIZE(marvell_hw_stats);
1427 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1430 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1432 int count = marvell_get_sset_count(phydev);
1435 for (i = 0; i < count; i++) {
1436 memcpy(data + i * ETH_GSTRING_LEN,
1437 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1442 #define UINT64_MAX (u64)(~((u64)0))
1444 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1446 struct marvell_hw_stat stat = marvell_hw_stats[i];
1447 struct marvell_priv *priv = phydev->priv;
1448 int err, oldpage, val;
1451 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1452 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1457 val = phy_read(phydev, stat.reg);
1461 val = val & ((1 << stat.bits) - 1);
1462 priv->stats[i] += val;
1463 ret = priv->stats[i];
1466 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1471 static void marvell_get_stats(struct phy_device *phydev,
1472 struct ethtool_stats *stats, u64 *data)
1474 int count = marvell_get_sset_count(phydev);
1477 for (i = 0; i < count; i++)
1478 data[i] = marvell_get_stat(phydev, i);
1481 static int marvell_probe(struct phy_device *phydev)
1483 struct marvell_priv *priv;
1485 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1489 phydev->priv = priv;
1494 static struct phy_driver marvell_drivers[] = {
1496 .phy_id = MARVELL_PHY_ID_88E1101,
1497 .phy_id_mask = MARVELL_PHY_ID_MASK,
1498 .name = "Marvell 88E1101",
1499 .features = PHY_GBIT_FEATURES,
1500 .probe = marvell_probe,
1501 .flags = PHY_HAS_INTERRUPT,
1502 .config_init = &marvell_config_init,
1503 .config_aneg = &m88e1101_config_aneg,
1504 .read_status = &genphy_read_status,
1505 .ack_interrupt = &marvell_ack_interrupt,
1506 .config_intr = &marvell_config_intr,
1507 .resume = &genphy_resume,
1508 .suspend = &genphy_suspend,
1509 .get_sset_count = marvell_get_sset_count,
1510 .get_strings = marvell_get_strings,
1511 .get_stats = marvell_get_stats,
1514 .phy_id = MARVELL_PHY_ID_88E1112,
1515 .phy_id_mask = MARVELL_PHY_ID_MASK,
1516 .name = "Marvell 88E1112",
1517 .features = PHY_GBIT_FEATURES,
1518 .flags = PHY_HAS_INTERRUPT,
1519 .probe = marvell_probe,
1520 .config_init = &m88e1111_config_init,
1521 .config_aneg = &marvell_config_aneg,
1522 .read_status = &genphy_read_status,
1523 .ack_interrupt = &marvell_ack_interrupt,
1524 .config_intr = &marvell_config_intr,
1525 .resume = &genphy_resume,
1526 .suspend = &genphy_suspend,
1527 .get_sset_count = marvell_get_sset_count,
1528 .get_strings = marvell_get_strings,
1529 .get_stats = marvell_get_stats,
1532 .phy_id = MARVELL_PHY_ID_88E1111,
1533 .phy_id_mask = MARVELL_PHY_ID_MASK,
1534 .name = "Marvell 88E1111",
1535 .features = PHY_GBIT_FEATURES,
1536 .flags = PHY_HAS_INTERRUPT,
1537 .probe = marvell_probe,
1538 .config_init = &m88e1111_config_init,
1539 .config_aneg = &m88e1111_config_aneg,
1540 .read_status = &marvell_read_status,
1541 .ack_interrupt = &marvell_ack_interrupt,
1542 .config_intr = &marvell_config_intr,
1543 .resume = &genphy_resume,
1544 .suspend = &genphy_suspend,
1545 .get_sset_count = marvell_get_sset_count,
1546 .get_strings = marvell_get_strings,
1547 .get_stats = marvell_get_stats,
1550 .phy_id = MARVELL_PHY_ID_88E1118,
1551 .phy_id_mask = MARVELL_PHY_ID_MASK,
1552 .name = "Marvell 88E1118",
1553 .features = PHY_GBIT_FEATURES,
1554 .flags = PHY_HAS_INTERRUPT,
1555 .probe = marvell_probe,
1556 .config_init = &m88e1118_config_init,
1557 .config_aneg = &m88e1118_config_aneg,
1558 .read_status = &genphy_read_status,
1559 .ack_interrupt = &marvell_ack_interrupt,
1560 .config_intr = &marvell_config_intr,
1561 .resume = &genphy_resume,
1562 .suspend = &genphy_suspend,
1563 .get_sset_count = marvell_get_sset_count,
1564 .get_strings = marvell_get_strings,
1565 .get_stats = marvell_get_stats,
1568 .phy_id = MARVELL_PHY_ID_88E1121R,
1569 .phy_id_mask = MARVELL_PHY_ID_MASK,
1570 .name = "Marvell 88E1121R",
1571 .features = PHY_GBIT_FEATURES,
1572 .flags = PHY_HAS_INTERRUPT,
1573 .probe = marvell_probe,
1574 .config_init = &m88e1121_config_init,
1575 .config_aneg = &m88e1121_config_aneg,
1576 .read_status = &marvell_read_status,
1577 .ack_interrupt = &marvell_ack_interrupt,
1578 .config_intr = &marvell_config_intr,
1579 .did_interrupt = &m88e1121_did_interrupt,
1580 .resume = &genphy_resume,
1581 .suspend = &genphy_suspend,
1582 .get_sset_count = marvell_get_sset_count,
1583 .get_strings = marvell_get_strings,
1584 .get_stats = marvell_get_stats,
1587 .phy_id = MARVELL_PHY_ID_88E1318S,
1588 .phy_id_mask = MARVELL_PHY_ID_MASK,
1589 .name = "Marvell 88E1318S",
1590 .features = PHY_GBIT_FEATURES,
1591 .flags = PHY_HAS_INTERRUPT,
1592 .probe = marvell_probe,
1593 .config_init = &m88e1121_config_init,
1594 .config_aneg = &m88e1318_config_aneg,
1595 .read_status = &marvell_read_status,
1596 .ack_interrupt = &marvell_ack_interrupt,
1597 .config_intr = &marvell_config_intr,
1598 .did_interrupt = &m88e1121_did_interrupt,
1599 .get_wol = &m88e1318_get_wol,
1600 .set_wol = &m88e1318_set_wol,
1601 .resume = &genphy_resume,
1602 .suspend = &genphy_suspend,
1603 .get_sset_count = marvell_get_sset_count,
1604 .get_strings = marvell_get_strings,
1605 .get_stats = marvell_get_stats,
1608 .phy_id = MARVELL_PHY_ID_88E1145,
1609 .phy_id_mask = MARVELL_PHY_ID_MASK,
1610 .name = "Marvell 88E1145",
1611 .features = PHY_GBIT_FEATURES,
1612 .flags = PHY_HAS_INTERRUPT,
1613 .probe = marvell_probe,
1614 .config_init = &m88e1145_config_init,
1615 .config_aneg = &m88e1101_config_aneg,
1616 .read_status = &genphy_read_status,
1617 .ack_interrupt = &marvell_ack_interrupt,
1618 .config_intr = &marvell_config_intr,
1619 .resume = &genphy_resume,
1620 .suspend = &genphy_suspend,
1621 .get_sset_count = marvell_get_sset_count,
1622 .get_strings = marvell_get_strings,
1623 .get_stats = marvell_get_stats,
1626 .phy_id = MARVELL_PHY_ID_88E1149R,
1627 .phy_id_mask = MARVELL_PHY_ID_MASK,
1628 .name = "Marvell 88E1149R",
1629 .features = PHY_GBIT_FEATURES,
1630 .flags = PHY_HAS_INTERRUPT,
1631 .probe = marvell_probe,
1632 .config_init = &m88e1149_config_init,
1633 .config_aneg = &m88e1118_config_aneg,
1634 .read_status = &genphy_read_status,
1635 .ack_interrupt = &marvell_ack_interrupt,
1636 .config_intr = &marvell_config_intr,
1637 .resume = &genphy_resume,
1638 .suspend = &genphy_suspend,
1639 .get_sset_count = marvell_get_sset_count,
1640 .get_strings = marvell_get_strings,
1641 .get_stats = marvell_get_stats,
1644 .phy_id = MARVELL_PHY_ID_88E1240,
1645 .phy_id_mask = MARVELL_PHY_ID_MASK,
1646 .name = "Marvell 88E1240",
1647 .features = PHY_GBIT_FEATURES,
1648 .flags = PHY_HAS_INTERRUPT,
1649 .probe = marvell_probe,
1650 .config_init = &m88e1111_config_init,
1651 .config_aneg = &marvell_config_aneg,
1652 .read_status = &genphy_read_status,
1653 .ack_interrupt = &marvell_ack_interrupt,
1654 .config_intr = &marvell_config_intr,
1655 .resume = &genphy_resume,
1656 .suspend = &genphy_suspend,
1657 .get_sset_count = marvell_get_sset_count,
1658 .get_strings = marvell_get_strings,
1659 .get_stats = marvell_get_stats,
1662 .phy_id = MARVELL_PHY_ID_88E1116R,
1663 .phy_id_mask = MARVELL_PHY_ID_MASK,
1664 .name = "Marvell 88E1116R",
1665 .features = PHY_GBIT_FEATURES,
1666 .flags = PHY_HAS_INTERRUPT,
1667 .probe = marvell_probe,
1668 .config_init = &m88e1116r_config_init,
1669 .config_aneg = &genphy_config_aneg,
1670 .read_status = &genphy_read_status,
1671 .ack_interrupt = &marvell_ack_interrupt,
1672 .config_intr = &marvell_config_intr,
1673 .resume = &genphy_resume,
1674 .suspend = &genphy_suspend,
1675 .get_sset_count = marvell_get_sset_count,
1676 .get_strings = marvell_get_strings,
1677 .get_stats = marvell_get_stats,
1680 .phy_id = MARVELL_PHY_ID_88E1510,
1681 .phy_id_mask = MARVELL_PHY_ID_MASK,
1682 .name = "Marvell 88E1510",
1683 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
1684 .flags = PHY_HAS_INTERRUPT,
1685 .probe = marvell_probe,
1686 .config_init = &m88e1510_config_init,
1687 .config_aneg = &m88e1510_config_aneg,
1688 .read_status = &marvell_read_status,
1689 .ack_interrupt = &marvell_ack_interrupt,
1690 .config_intr = &marvell_config_intr,
1691 .did_interrupt = &m88e1121_did_interrupt,
1692 .resume = &marvell_resume,
1693 .suspend = &marvell_suspend,
1694 .get_sset_count = marvell_get_sset_count,
1695 .get_strings = marvell_get_strings,
1696 .get_stats = marvell_get_stats,
1699 .phy_id = MARVELL_PHY_ID_88E1540,
1700 .phy_id_mask = MARVELL_PHY_ID_MASK,
1701 .name = "Marvell 88E1540",
1702 .features = PHY_GBIT_FEATURES,
1703 .flags = PHY_HAS_INTERRUPT,
1704 .probe = marvell_probe,
1705 .config_init = &marvell_config_init,
1706 .config_aneg = &m88e1510_config_aneg,
1707 .read_status = &marvell_read_status,
1708 .ack_interrupt = &marvell_ack_interrupt,
1709 .config_intr = &marvell_config_intr,
1710 .did_interrupt = &m88e1121_did_interrupt,
1711 .resume = &genphy_resume,
1712 .suspend = &genphy_suspend,
1713 .get_sset_count = marvell_get_sset_count,
1714 .get_strings = marvell_get_strings,
1715 .get_stats = marvell_get_stats,
1718 .phy_id = MARVELL_PHY_ID_88E3016,
1719 .phy_id_mask = MARVELL_PHY_ID_MASK,
1720 .name = "Marvell 88E3016",
1721 .features = PHY_BASIC_FEATURES,
1722 .flags = PHY_HAS_INTERRUPT,
1723 .probe = marvell_probe,
1724 .config_aneg = &genphy_config_aneg,
1725 .config_init = &m88e3016_config_init,
1726 .aneg_done = &marvell_aneg_done,
1727 .read_status = &marvell_read_status,
1728 .ack_interrupt = &marvell_ack_interrupt,
1729 .config_intr = &marvell_config_intr,
1730 .did_interrupt = &m88e1121_did_interrupt,
1731 .resume = &genphy_resume,
1732 .suspend = &genphy_suspend,
1733 .get_sset_count = marvell_get_sset_count,
1734 .get_strings = marvell_get_strings,
1735 .get_stats = marvell_get_stats,
1739 module_phy_driver(marvell_drivers);
1741 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1742 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1743 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1744 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1745 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1746 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1747 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1748 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1749 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1750 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1751 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1752 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1753 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
1754 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1758 MODULE_DEVICE_TABLE(mdio, marvell_tbl);