1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/marvell.c
5 * Driver for Marvell PHYs
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/errno.h>
17 #include <linux/unistd.h>
18 #include <linux/hwmon.h>
19 #include <linux/interrupt.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/spinlock.h>
27 #include <linux/module.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/ethtool_netlink.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/bitfield.h>
38 #include <linux/uaccess.h>
40 #define MII_MARVELL_PHY_PAGE 22
41 #define MII_MARVELL_COPPER_PAGE 0x00
42 #define MII_MARVELL_FIBER_PAGE 0x01
43 #define MII_MARVELL_MSCR_PAGE 0x02
44 #define MII_MARVELL_LED_PAGE 0x03
45 #define MII_MARVELL_VCT5_PAGE 0x05
46 #define MII_MARVELL_MISC_TEST_PAGE 0x06
47 #define MII_MARVELL_VCT7_PAGE 0x07
48 #define MII_MARVELL_WOL_PAGE 0x11
50 #define MII_M1011_IEVENT 0x13
51 #define MII_M1011_IEVENT_CLEAR 0x0000
53 #define MII_M1011_IMASK 0x12
54 #define MII_M1011_IMASK_INIT 0x6400
55 #define MII_M1011_IMASK_CLEAR 0x0000
57 #define MII_M1011_PHY_SCR 0x10
58 #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
59 #define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
60 #define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
61 #define MII_M1011_PHY_SCR_MDI (0x0 << 5)
62 #define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
63 #define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
65 #define MII_M1011_PHY_SSR 0x11
66 #define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
73 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
74 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
75 #define MII_M1111_RGMII_RX_DELAY BIT(7)
76 #define MII_M1111_RGMII_TX_DELAY BIT(1)
77 #define MII_M1111_PHY_EXT_SR 0x1b
79 #define MII_M1111_HWCFG_MODE_MASK 0xf
80 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
81 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
82 #define MII_M1111_HWCFG_MODE_RTBI 0x7
83 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
84 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
85 #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
86 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
88 #define MII_88E1121_PHY_MSCR_REG 21
89 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
93 #define MII_88E1121_MISC_TEST 0x1a
94 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
95 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
96 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
97 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
98 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
99 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
101 #define MII_88E1510_TEMP_SENSOR 0x1b
102 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
104 #define MII_88E1540_COPPER_CTRL3 0x1a
105 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
106 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
107 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
108 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
109 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
110 #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
112 #define MII_88E6390_MISC_TEST 0x1b
113 #define MII_88E6390_MISC_TEST_SAMPLE_1S 0
114 #define MII_88E6390_MISC_TEST_SAMPLE_10MS BIT(14)
115 #define MII_88E6390_MISC_TEST_SAMPLE_DISABLE BIT(15)
116 #define MII_88E6390_MISC_TEST_SAMPLE_ENABLE 0
117 #define MII_88E6390_MISC_TEST_SAMPLE_MASK (0x3 << 14)
119 #define MII_88E6390_TEMP_SENSOR 0x1c
120 #define MII_88E6390_TEMP_SENSOR_MASK 0xff
121 #define MII_88E6390_TEMP_SENSOR_SAMPLES 10
123 #define MII_88E1318S_PHY_MSCR1_REG 16
124 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
126 /* Copper Specific Interrupt Enable Register */
127 #define MII_88E1318S_PHY_CSIER 0x12
128 /* WOL Event Interrupt Enable */
129 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
131 /* LED Timer Control Register */
132 #define MII_88E1318S_PHY_LED_TCR 0x12
133 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
134 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
135 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
137 /* Magic Packet MAC address registers */
138 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
139 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
140 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
142 #define MII_88E1318S_PHY_WOL_CTRL 0x10
143 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
144 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
146 #define MII_PHY_LED_CTRL 16
147 #define MII_88E1121_PHY_LED_DEF 0x0030
148 #define MII_88E1510_PHY_LED_DEF 0x1177
149 #define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
151 #define MII_M1011_PHY_STATUS 0x11
152 #define MII_M1011_PHY_STATUS_1000 0x8000
153 #define MII_M1011_PHY_STATUS_100 0x4000
154 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
155 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
156 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
157 #define MII_M1011_PHY_STATUS_LINK 0x0400
159 #define MII_88E3016_PHY_SPEC_CTRL 0x10
160 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
161 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
163 #define MII_88E1510_GEN_CTRL_REG_1 0x14
164 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
165 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
166 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
168 #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
169 #define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
170 #define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
171 #define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
172 #define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
173 #define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
174 #define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
176 #define MII_VCT5_CTRL 0x17
177 #define MII_VCT5_CTRL_ENABLE BIT(15)
178 #define MII_VCT5_CTRL_COMPLETE BIT(14)
179 #define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
180 #define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
181 #define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
182 #define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
183 #define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
184 #define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
185 #define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
186 #define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
187 #define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
188 #define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
189 #define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
190 #define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
191 #define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
192 #define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
193 #define MII_VCT5_CTRL_SAMPLES_SHIFT 8
194 #define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
195 #define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
196 #define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
197 #define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
198 #define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
200 #define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
201 #define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
202 #define MII_VCT5_TX_PULSE_CTRL 0x1c
203 #define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
204 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
205 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
206 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
207 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
208 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
209 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
210 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
211 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
212 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
213 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
214 #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
215 #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
217 /* For TDR measurements less than 11 meters, a short pulse should be
220 #define TDR_SHORT_CABLE_LENGTH 11
222 #define MII_VCT7_PAIR_0_DISTANCE 0x10
223 #define MII_VCT7_PAIR_1_DISTANCE 0x11
224 #define MII_VCT7_PAIR_2_DISTANCE 0x12
225 #define MII_VCT7_PAIR_3_DISTANCE 0x13
227 #define MII_VCT7_RESULTS 0x14
228 #define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
229 #define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
230 #define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
231 #define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
232 #define MII_VCT7_RESULTS_PAIR3_SHIFT 12
233 #define MII_VCT7_RESULTS_PAIR2_SHIFT 8
234 #define MII_VCT7_RESULTS_PAIR1_SHIFT 4
235 #define MII_VCT7_RESULTS_PAIR0_SHIFT 0
236 #define MII_VCT7_RESULTS_INVALID 0
237 #define MII_VCT7_RESULTS_OK 1
238 #define MII_VCT7_RESULTS_OPEN 2
239 #define MII_VCT7_RESULTS_SAME_SHORT 3
240 #define MII_VCT7_RESULTS_CROSS_SHORT 4
241 #define MII_VCT7_RESULTS_BUSY 9
243 #define MII_VCT7_CTRL 0x15
244 #define MII_VCT7_CTRL_RUN_NOW BIT(15)
245 #define MII_VCT7_CTRL_RUN_ANEG BIT(14)
246 #define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
247 #define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
248 #define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
249 #define MII_VCT7_CTRL_METERS BIT(10)
250 #define MII_VCT7_CTRL_CENTIMETERS 0
252 #define LPA_PAUSE_FIBER 0x180
253 #define LPA_PAUSE_ASYM_FIBER 0x100
255 #define NB_FIBER_STATS 1
257 MODULE_DESCRIPTION("Marvell PHY driver");
258 MODULE_AUTHOR("Andy Fleming");
259 MODULE_LICENSE("GPL");
261 struct marvell_hw_stat {
268 static struct marvell_hw_stat marvell_hw_stats[] = {
269 { "phy_receive_errors_copper", 0, 21, 16},
270 { "phy_idle_errors", 0, 10, 8 },
271 { "phy_receive_errors_fiber", 1, 21, 16},
274 struct marvell_priv {
275 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
277 struct device *hwmon_dev;
285 static int marvell_read_page(struct phy_device *phydev)
287 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
290 static int marvell_write_page(struct phy_device *phydev, int page)
292 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
295 static int marvell_set_page(struct phy_device *phydev, int page)
297 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
300 static int marvell_ack_interrupt(struct phy_device *phydev)
304 /* Clear the interrupts by reading the reg */
305 err = phy_read(phydev, MII_M1011_IEVENT);
313 static int marvell_config_intr(struct phy_device *phydev)
317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
318 err = phy_write(phydev, MII_M1011_IMASK,
319 MII_M1011_IMASK_INIT);
321 err = phy_write(phydev, MII_M1011_IMASK,
322 MII_M1011_IMASK_CLEAR);
327 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
333 /* get the current settings */
334 reg = phy_read(phydev, MII_M1011_PHY_SCR);
339 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
342 val |= MII_M1011_PHY_SCR_MDI;
345 val |= MII_M1011_PHY_SCR_MDI_X;
347 case ETH_TP_MDI_AUTO:
348 case ETH_TP_MDI_INVALID:
350 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
355 /* Set the new polarity value in the register */
356 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
364 static int marvell_config_aneg(struct phy_device *phydev)
369 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
375 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
376 MII_M1111_PHY_LED_DIRECT);
380 err = genphy_config_aneg(phydev);
384 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
385 /* A write to speed/duplex bits (that is performed by
386 * genphy_config_aneg() call above) must be followed by
387 * a software reset. Otherwise, the write has no effect.
389 err = genphy_soft_reset(phydev);
397 static int m88e1101_config_aneg(struct phy_device *phydev)
401 /* This Marvell PHY has an errata which requires
402 * that certain registers get written in order
403 * to restart autonegotiation
405 err = genphy_soft_reset(phydev);
409 err = phy_write(phydev, 0x1d, 0x1f);
413 err = phy_write(phydev, 0x1e, 0x200c);
417 err = phy_write(phydev, 0x1d, 0x5);
421 err = phy_write(phydev, 0x1e, 0);
425 err = phy_write(phydev, 0x1e, 0x100);
429 return marvell_config_aneg(phydev);
432 #if IS_ENABLED(CONFIG_OF_MDIO)
433 /* Set and/or override some configuration registers based on the
434 * marvell,reg-init property stored in the of_node for the phydev.
436 * marvell,reg-init = <reg-page reg mask value>,...;
438 * There may be one or more sets of <reg-page reg mask value>:
440 * reg-page: which register bank to use.
442 * mask: if non-zero, ANDed with existing register value.
443 * value: ORed with the masked value and written to the regiser.
446 static int marvell_of_reg_init(struct phy_device *phydev)
449 int len, i, saved_page, current_page, ret = 0;
451 if (!phydev->mdio.dev.of_node)
454 paddr = of_get_property(phydev->mdio.dev.of_node,
455 "marvell,reg-init", &len);
456 if (!paddr || len < (4 * sizeof(*paddr)))
459 saved_page = phy_save_page(phydev);
462 current_page = saved_page;
464 len /= sizeof(*paddr);
465 for (i = 0; i < len - 3; i += 4) {
466 u16 page = be32_to_cpup(paddr + i);
467 u16 reg = be32_to_cpup(paddr + i + 1);
468 u16 mask = be32_to_cpup(paddr + i + 2);
469 u16 val_bits = be32_to_cpup(paddr + i + 3);
472 if (page != current_page) {
474 ret = marvell_write_page(phydev, page);
481 val = __phy_read(phydev, reg);
490 ret = __phy_write(phydev, reg, val);
495 return phy_restore_page(phydev, saved_page, ret);
498 static int marvell_of_reg_init(struct phy_device *phydev)
502 #endif /* CONFIG_OF_MDIO */
504 static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
508 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
509 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
510 MII_88E1121_PHY_MSCR_TX_DELAY;
511 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
512 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
513 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
514 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
518 return phy_modify_paged_changed(phydev, MII_MARVELL_MSCR_PAGE,
519 MII_88E1121_PHY_MSCR_REG,
520 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
523 static int m88e1121_config_aneg(struct phy_device *phydev)
528 if (phy_interface_is_rgmii(phydev)) {
529 err = m88e1121_config_aneg_rgmii_delays(phydev);
536 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
542 err = genphy_config_aneg(phydev);
546 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
547 /* A software reset is used to ensure a "commit" of the
550 err = genphy_soft_reset(phydev);
558 static int m88e1318_config_aneg(struct phy_device *phydev)
562 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
563 MII_88E1318S_PHY_MSCR1_REG,
564 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
568 return m88e1121_config_aneg(phydev);
572 * linkmode_adv_to_fiber_adv_t
573 * @advertise: the linkmode advertisement settings
575 * A small helper function that translates linkmode advertisement
576 * settings to phy autonegotiation advertisements for the MII_ADV
577 * register for fiber link.
579 static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
583 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
584 result |= ADVERTISE_1000XHALF;
585 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
586 result |= ADVERTISE_1000XFULL;
588 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
589 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
590 result |= ADVERTISE_1000XPSE_ASYM;
591 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
592 result |= ADVERTISE_1000XPAUSE;
598 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
599 * @phydev: target phy_device struct
601 * Description: If auto-negotiation is enabled, we configure the
602 * advertising, and then restart auto-negotiation. If it is not
603 * enabled, then we write the BMCR. Adapted for fiber link in
604 * some Marvell's devices.
606 static int marvell_config_aneg_fiber(struct phy_device *phydev)
612 if (phydev->autoneg != AUTONEG_ENABLE)
613 return genphy_setup_forced(phydev);
615 /* Only allow advertising what this PHY supports */
616 linkmode_and(phydev->advertising, phydev->advertising,
619 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
621 /* Setup fiber advertisement */
622 err = phy_modify_changed(phydev, MII_ADVERTISE,
623 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
624 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
631 return genphy_check_and_restart_aneg(phydev, changed);
634 static int m88e1510_config_aneg(struct phy_device *phydev)
638 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
642 /* Configure the copper link first */
643 err = m88e1318_config_aneg(phydev);
647 /* Do not touch the fiber page if we're in copper->sgmii mode */
648 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
651 /* Then the fiber link */
652 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
656 err = marvell_config_aneg_fiber(phydev);
660 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
663 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
667 static void marvell_config_led(struct phy_device *phydev)
672 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
673 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
674 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
675 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
676 def_config = MII_88E1121_PHY_LED_DEF;
678 /* Default PHY LED config:
679 * LED[0] .. 1000Mbps Link
680 * LED[1] .. 100Mbps Link
681 * LED[2] .. Blink, Activity
683 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
684 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
685 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
687 def_config = MII_88E1510_PHY_LED_DEF;
693 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
696 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
699 static int marvell_config_init(struct phy_device *phydev)
701 /* Set defalut LED */
702 marvell_config_led(phydev);
704 /* Set registers from marvell,reg-init DT property */
705 return marvell_of_reg_init(phydev);
708 static int m88e3016_config_init(struct phy_device *phydev)
712 /* Enable Scrambler and Auto-Crossover */
713 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
714 MII_88E3016_DISABLE_SCRAMBLER,
715 MII_88E3016_AUTO_MDIX_CROSSOVER);
719 return marvell_config_init(phydev);
722 static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
724 int fibre_copper_auto)
726 if (fibre_copper_auto)
727 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
729 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
730 MII_M1111_HWCFG_MODE_MASK |
731 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
732 MII_M1111_HWCFG_FIBER_COPPER_RES,
736 static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
740 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
741 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
742 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
743 delay = MII_M1111_RGMII_RX_DELAY;
744 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
745 delay = MII_M1111_RGMII_TX_DELAY;
750 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
751 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
755 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
760 err = m88e1111_config_init_rgmii_delays(phydev);
764 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
768 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
770 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
771 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
773 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
775 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
778 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
782 err = m88e1111_config_init_hwcfg_mode(
784 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
785 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
789 /* make sure copper is selected */
790 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
793 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
797 err = m88e1111_config_init_rgmii_delays(phydev);
801 err = m88e1111_config_init_hwcfg_mode(
803 MII_M1111_HWCFG_MODE_RTBI,
804 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
809 err = genphy_soft_reset(phydev);
813 return m88e1111_config_init_hwcfg_mode(
815 MII_M1111_HWCFG_MODE_RTBI,
816 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
819 static int m88e1111_config_init(struct phy_device *phydev)
823 if (phy_interface_is_rgmii(phydev)) {
824 err = m88e1111_config_init_rgmii(phydev);
829 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
830 err = m88e1111_config_init_sgmii(phydev);
835 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
836 err = m88e1111_config_init_rtbi(phydev);
841 err = marvell_of_reg_init(phydev);
845 return genphy_soft_reset(phydev);
848 static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
850 int val, cnt, enable;
852 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
856 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
857 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
859 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
864 static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
868 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
872 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
873 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
875 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
876 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
878 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
879 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
880 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
887 return genphy_soft_reset(phydev);
890 static int m88e1111_get_tunable(struct phy_device *phydev,
891 struct ethtool_tunable *tuna, void *data)
894 case ETHTOOL_PHY_DOWNSHIFT:
895 return m88e1111_get_downshift(phydev, data);
901 static int m88e1111_set_tunable(struct phy_device *phydev,
902 struct ethtool_tunable *tuna, const void *data)
905 case ETHTOOL_PHY_DOWNSHIFT:
906 return m88e1111_set_downshift(phydev, *(const u8 *)data);
912 static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
914 int val, cnt, enable;
916 val = phy_read(phydev, MII_M1011_PHY_SCR);
920 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
921 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
923 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
928 static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
932 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
936 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
937 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
939 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
940 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
942 err = phy_modify(phydev, MII_M1011_PHY_SCR,
943 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
944 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
951 return genphy_soft_reset(phydev);
954 static int m88e1011_get_tunable(struct phy_device *phydev,
955 struct ethtool_tunable *tuna, void *data)
958 case ETHTOOL_PHY_DOWNSHIFT:
959 return m88e1011_get_downshift(phydev, data);
965 static int m88e1011_set_tunable(struct phy_device *phydev,
966 struct ethtool_tunable *tuna, const void *data)
969 case ETHTOOL_PHY_DOWNSHIFT:
970 return m88e1011_set_downshift(phydev, *(const u8 *)data);
976 static int m88e1116r_config_init(struct phy_device *phydev)
980 err = genphy_soft_reset(phydev);
986 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
990 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
994 err = m88e1011_set_downshift(phydev, 8);
998 if (phy_interface_is_rgmii(phydev)) {
999 err = m88e1121_config_aneg_rgmii_delays(phydev);
1004 err = genphy_soft_reset(phydev);
1008 return marvell_config_init(phydev);
1011 static int m88e1318_config_init(struct phy_device *phydev)
1013 if (phy_interrupt_is_valid(phydev)) {
1014 int err = phy_modify_paged(
1015 phydev, MII_MARVELL_LED_PAGE,
1016 MII_88E1318S_PHY_LED_TCR,
1017 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1018 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1019 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1024 return marvell_config_init(phydev);
1027 static int m88e1510_config_init(struct phy_device *phydev)
1031 /* SGMII-to-Copper mode initialization */
1032 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1033 /* Select page 18 */
1034 err = marvell_set_page(phydev, 18);
1038 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1039 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1040 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1041 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1045 /* PHY reset is necessary after changing MODE[2:0] */
1046 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, 0,
1047 MII_88E1510_GEN_CTRL_REG_1_RESET);
1051 /* Reset page selection */
1052 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1057 return m88e1318_config_init(phydev);
1060 static int m88e1118_config_aneg(struct phy_device *phydev)
1064 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1068 err = genphy_config_aneg(phydev);
1072 return genphy_soft_reset(phydev);
1075 static int m88e1118_config_init(struct phy_device *phydev)
1079 /* Change address */
1080 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1084 /* Enable 1000 Mbit */
1085 err = phy_write(phydev, 0x15, 0x1070);
1089 /* Change address */
1090 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
1094 if (phy_interface_is_rgmii(phydev)) {
1095 err = m88e1121_config_aneg_rgmii_delays(phydev);
1100 /* Adjust LED Control */
1101 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1102 err = phy_write(phydev, 0x10, 0x1100);
1104 err = phy_write(phydev, 0x10, 0x021e);
1108 err = marvell_of_reg_init(phydev);
1113 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1117 return genphy_soft_reset(phydev);
1120 static int m88e1149_config_init(struct phy_device *phydev)
1124 /* Change address */
1125 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1129 /* Enable 1000 Mbit */
1130 err = phy_write(phydev, 0x15, 0x1048);
1134 err = marvell_of_reg_init(phydev);
1139 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1143 return genphy_soft_reset(phydev);
1146 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1150 err = m88e1111_config_init_rgmii_delays(phydev);
1154 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1155 err = phy_write(phydev, 0x1d, 0x0012);
1159 err = phy_modify(phydev, 0x1e, 0x0fc0,
1160 2 << 9 | /* 36 ohm */
1161 2 << 6); /* 39 ohm */
1165 err = phy_write(phydev, 0x1d, 0x3);
1169 err = phy_write(phydev, 0x1e, 0x8000);
1174 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1176 return m88e1111_config_init_hwcfg_mode(
1177 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1178 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1181 static int m88e1145_config_init(struct phy_device *phydev)
1185 /* Take care of errata E0 & E1 */
1186 err = phy_write(phydev, 0x1d, 0x001b);
1190 err = phy_write(phydev, 0x1e, 0x418f);
1194 err = phy_write(phydev, 0x1d, 0x0016);
1198 err = phy_write(phydev, 0x1e, 0xa2da);
1202 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1203 err = m88e1145_config_init_rgmii(phydev);
1208 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1209 err = m88e1145_config_init_sgmii(phydev);
1214 err = marvell_of_reg_init(phydev);
1221 static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1225 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1229 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1230 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1234 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1237 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1240 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1243 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1246 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1256 static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1258 struct ethtool_eee eee;
1261 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1262 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1263 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1265 /* According to the Marvell data sheet EEE must be disabled for
1266 * Fast Link Down detection to work properly
1268 ret = phy_ethtool_get_eee(phydev, &eee);
1269 if (!ret && eee.eee_enabled) {
1270 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1275 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1276 else if (*msecs <= 15)
1277 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1278 else if (*msecs <= 30)
1279 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1281 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1283 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1285 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1286 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1290 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1291 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1294 static int m88e1540_get_tunable(struct phy_device *phydev,
1295 struct ethtool_tunable *tuna, void *data)
1298 case ETHTOOL_PHY_FAST_LINK_DOWN:
1299 return m88e1540_get_fld(phydev, data);
1300 case ETHTOOL_PHY_DOWNSHIFT:
1301 return m88e1011_get_downshift(phydev, data);
1307 static int m88e1540_set_tunable(struct phy_device *phydev,
1308 struct ethtool_tunable *tuna, const void *data)
1311 case ETHTOOL_PHY_FAST_LINK_DOWN:
1312 return m88e1540_set_fld(phydev, data);
1313 case ETHTOOL_PHY_DOWNSHIFT:
1314 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1320 /* The VOD can be out of specification on link up. Poke an
1321 * undocumented register, in an undocumented page, with a magic value
1324 static int m88e6390_errata(struct phy_device *phydev)
1328 err = phy_write(phydev, MII_BMCR,
1329 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1333 usleep_range(300, 400);
1335 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1339 return genphy_soft_reset(phydev);
1342 static int m88e6390_config_aneg(struct phy_device *phydev)
1346 err = m88e6390_errata(phydev);
1350 return m88e1510_config_aneg(phydev);
1354 * fiber_lpa_mod_linkmode_lpa_t
1355 * @advertising: the linkmode advertisement settings
1356 * @lpa: value of the MII_LPA register for fiber link
1358 * A small helper function that translates MII_LPA bits to linkmode LP
1359 * advertisement settings. Other bits in advertising are left
1362 static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1364 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1365 advertising, lpa & LPA_1000XHALF);
1367 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1368 advertising, lpa & LPA_1000XFULL);
1371 static int marvell_read_status_page_an(struct phy_device *phydev,
1372 int fiber, int status)
1377 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1382 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1383 phydev->duplex = DUPLEX_FULL;
1385 phydev->duplex = DUPLEX_HALF;
1387 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1388 case MII_M1011_PHY_STATUS_1000:
1389 phydev->speed = SPEED_1000;
1392 case MII_M1011_PHY_STATUS_100:
1393 phydev->speed = SPEED_100;
1397 phydev->speed = SPEED_10;
1402 err = genphy_read_lpa(phydev);
1406 phy_resolve_aneg_pause(phydev);
1408 lpa = phy_read(phydev, MII_LPA);
1412 /* The fiber link is only 1000M capable */
1413 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1415 if (phydev->duplex == DUPLEX_FULL) {
1416 if (!(lpa & LPA_PAUSE_FIBER)) {
1418 phydev->asym_pause = 0;
1419 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1421 phydev->asym_pause = 1;
1424 phydev->asym_pause = 0;
1432 /* marvell_read_status_page
1435 * Check the link, then figure out the current state
1436 * by comparing what we advertise with what the link partner
1437 * advertises. Start by checking the gigabit possibilities,
1438 * then move on to 10/100.
1440 static int marvell_read_status_page(struct phy_device *phydev, int page)
1446 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1450 /* Use the generic register for copper link status,
1451 * and the PHY status register for fiber link status.
1453 if (page == MII_MARVELL_FIBER_PAGE) {
1454 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1456 err = genphy_update_link(phydev);
1461 if (page == MII_MARVELL_FIBER_PAGE)
1466 linkmode_zero(phydev->lp_advertising);
1468 phydev->asym_pause = 0;
1469 phydev->speed = SPEED_UNKNOWN;
1470 phydev->duplex = DUPLEX_UNKNOWN;
1471 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1473 if (phydev->autoneg == AUTONEG_ENABLE)
1474 err = marvell_read_status_page_an(phydev, fiber, status);
1476 err = genphy_read_status_fixed(phydev);
1481 /* marvell_read_status
1483 * Some Marvell's phys have two modes: fiber and copper.
1484 * Both need status checked.
1486 * First, check the fiber link and status.
1487 * If the fiber link is down, check the copper link and status which
1488 * will be the default value if both link are down.
1490 static int marvell_read_status(struct phy_device *phydev)
1494 /* Check the fiber mode first */
1495 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1496 phydev->supported) &&
1497 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1498 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1502 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1506 /* If the fiber link is up, it is the selected and
1507 * used link. In this case, we need to stay in the
1508 * fiber page. Please to be careful about that, avoid
1509 * to restore Copper page in other functions which
1510 * could break the behaviour for some fiber phy like
1516 /* If fiber link is down, check and save copper mode state */
1517 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1522 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1525 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1531 * Some Marvell's phys have two modes: fiber and copper.
1532 * Both need to be suspended
1534 static int marvell_suspend(struct phy_device *phydev)
1538 /* Suspend the fiber mode first */
1539 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1540 phydev->supported)) {
1541 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1545 /* With the page set, use the generic suspend */
1546 err = genphy_suspend(phydev);
1550 /* Then, the copper link */
1551 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1556 /* With the page set, use the generic suspend */
1557 return genphy_suspend(phydev);
1560 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1566 * Some Marvell's phys have two modes: fiber and copper.
1567 * Both need to be resumed
1569 static int marvell_resume(struct phy_device *phydev)
1573 /* Resume the fiber mode first */
1574 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1575 phydev->supported)) {
1576 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1580 /* With the page set, use the generic resume */
1581 err = genphy_resume(phydev);
1585 /* Then, the copper link */
1586 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1591 /* With the page set, use the generic resume */
1592 return genphy_resume(phydev);
1595 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1599 static int marvell_aneg_done(struct phy_device *phydev)
1601 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1603 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1606 static int m88e1121_did_interrupt(struct phy_device *phydev)
1610 imask = phy_read(phydev, MII_M1011_IEVENT);
1612 if (imask & MII_M1011_IMASK_INIT)
1618 static void m88e1318_get_wol(struct phy_device *phydev,
1619 struct ethtool_wolinfo *wol)
1623 wol->supported = WAKE_MAGIC;
1626 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1627 MII_88E1318S_PHY_WOL_CTRL);
1628 if (ret >= 0 && ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1629 wol->wolopts |= WAKE_MAGIC;
1632 static int m88e1318_set_wol(struct phy_device *phydev,
1633 struct ethtool_wolinfo *wol)
1635 int err = 0, oldpage;
1637 oldpage = phy_save_page(phydev);
1641 if (wol->wolopts & WAKE_MAGIC) {
1642 /* Explicitly switch to page 0x00, just to be sure */
1643 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1647 /* If WOL event happened once, the LED[2] interrupt pin
1648 * will not be cleared unless we reading the interrupt status
1649 * register. If interrupts are in use, the normal interrupt
1650 * handling will clear the WOL event. Clear the WOL event
1651 * before enabling it if !phy_interrupt_is_valid()
1653 if (!phy_interrupt_is_valid(phydev))
1654 __phy_read(phydev, MII_M1011_IEVENT);
1656 /* Enable the WOL interrupt */
1657 err = __phy_modify(phydev, MII_88E1318S_PHY_CSIER, 0,
1658 MII_88E1318S_PHY_CSIER_WOL_EIE);
1662 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1666 /* Setup LED[2] as interrupt pin (active low) */
1667 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1668 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1669 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1670 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1674 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1678 /* Store the device address for the magic packet */
1679 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1680 ((phydev->attached_dev->dev_addr[5] << 8) |
1681 phydev->attached_dev->dev_addr[4]));
1684 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1685 ((phydev->attached_dev->dev_addr[3] << 8) |
1686 phydev->attached_dev->dev_addr[2]));
1689 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1690 ((phydev->attached_dev->dev_addr[1] << 8) |
1691 phydev->attached_dev->dev_addr[0]));
1695 /* Clear WOL status and enable magic packet matching */
1696 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1697 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1698 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1702 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1706 /* Clear WOL status and disable magic packet matching */
1707 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1708 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1709 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1715 return phy_restore_page(phydev, oldpage, err);
1718 static int marvell_get_sset_count(struct phy_device *phydev)
1720 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1722 return ARRAY_SIZE(marvell_hw_stats);
1724 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1727 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1729 int count = marvell_get_sset_count(phydev);
1732 for (i = 0; i < count; i++) {
1733 strlcpy(data + i * ETH_GSTRING_LEN,
1734 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1738 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1740 struct marvell_hw_stat stat = marvell_hw_stats[i];
1741 struct marvell_priv *priv = phydev->priv;
1745 val = phy_read_paged(phydev, stat.page, stat.reg);
1749 val = val & ((1 << stat.bits) - 1);
1750 priv->stats[i] += val;
1751 ret = priv->stats[i];
1757 static void marvell_get_stats(struct phy_device *phydev,
1758 struct ethtool_stats *stats, u64 *data)
1760 int count = marvell_get_sset_count(phydev);
1763 for (i = 0; i < count; i++)
1764 data[i] = marvell_get_stat(phydev, i);
1767 static int marvell_vct5_wait_complete(struct phy_device *phydev)
1772 for (i = 0; i < 32; i++) {
1773 val = __phy_read(phydev, MII_VCT5_CTRL);
1777 if (val & MII_VCT5_CTRL_COMPLETE)
1781 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
1785 static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
1791 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
1792 val = __phy_read(phydev, reg);
1797 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
1798 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
1800 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
1801 amplitude = -amplitude;
1803 return 1000 * amplitude / 128;
1806 static u32 marvell_vct5_distance2cm(int distance)
1808 return distance * 805 / 10;
1811 static u32 marvell_vct5_cm2distance(int cm)
1813 return cm * 10 / 805;
1816 static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
1817 int distance, int pair)
1824 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
1829 reg = MII_VCT5_CTRL_ENABLE |
1830 MII_VCT5_CTRL_TX_SAME_CHANNEL |
1831 MII_VCT5_CTRL_SAMPLES_DEFAULT |
1832 MII_VCT5_CTRL_SAMPLE_POINT |
1833 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
1834 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
1838 err = marvell_vct5_wait_complete(phydev);
1842 for (i = 0; i < 4; i++) {
1843 if (pair != PHY_PAIR_ALL && i != pair)
1846 mV = marvell_vct5_amplitude(phydev, i);
1847 ethnl_cable_test_amplitude(phydev, i, mV);
1853 static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
1855 struct marvell_priv *priv = phydev->priv;
1862 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
1863 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
1865 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1867 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1868 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1869 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1871 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1872 MII_VCT5_TX_PULSE_CTRL, reg);
1876 /* Reading the TDR data is very MDIO heavy. We need to optimize
1877 * access to keep the time to a minimum. So lock the bus once,
1878 * and don't release it until complete. We can then avoid having
1879 * to change the page for every access, greatly speeding things
1882 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
1886 for (distance = priv->first;
1887 distance <= priv->last;
1888 distance += priv->step) {
1889 err = marvell_vct5_amplitude_distance(phydev, distance,
1894 if (distance > TDR_SHORT_CABLE_LENGTH &&
1895 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
1896 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1897 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1898 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1899 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1900 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
1907 return phy_restore_page(phydev, page, err);
1910 static int marvell_cable_test_start_common(struct phy_device *phydev)
1912 int bmcr, bmsr, ret;
1914 /* If auto-negotiation is enabled, but not complete, the cable
1915 * test never completes. So disable auto-neg.
1917 bmcr = phy_read(phydev, MII_BMCR);
1921 bmsr = phy_read(phydev, MII_BMSR);
1926 if (bmcr & BMCR_ANENABLE) {
1927 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1930 ret = genphy_soft_reset(phydev);
1935 /* If the link is up, allow it some time to go down */
1936 if (bmsr & BMSR_LSTATUS)
1942 static int marvell_vct7_cable_test_start(struct phy_device *phydev)
1944 struct marvell_priv *priv = phydev->priv;
1947 ret = marvell_cable_test_start_common(phydev);
1951 priv->cable_test_tdr = false;
1953 /* Reset the VCT5 API control to defaults, otherwise
1954 * VCT7 does not work correctly.
1956 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1958 MII_VCT5_CTRL_TX_SAME_CHANNEL |
1959 MII_VCT5_CTRL_SAMPLES_DEFAULT |
1960 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
1961 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
1965 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1966 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
1970 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
1972 MII_VCT7_CTRL_RUN_NOW |
1973 MII_VCT7_CTRL_CENTIMETERS);
1976 static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
1977 const struct phy_tdr_config *cfg)
1979 struct marvell_priv *priv = phydev->priv;
1982 priv->cable_test_tdr = true;
1983 priv->first = marvell_vct5_cm2distance(cfg->first);
1984 priv->last = marvell_vct5_cm2distance(cfg->last);
1985 priv->step = marvell_vct5_cm2distance(cfg->step);
1986 priv->pair = cfg->pair;
1988 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
1991 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
1995 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2000 ret = marvell_cable_test_start_common(phydev);
2004 ret = ethnl_cable_test_pulse(phydev, 1000);
2008 return ethnl_cable_test_step(phydev,
2009 marvell_vct5_distance2cm(priv->first),
2010 marvell_vct5_distance2cm(priv->last),
2011 marvell_vct5_distance2cm(priv->step));
2014 static int marvell_vct7_distance_to_length(int distance, bool meter)
2022 static bool marvell_vct7_distance_valid(int result)
2025 case MII_VCT7_RESULTS_OPEN:
2026 case MII_VCT7_RESULTS_SAME_SHORT:
2027 case MII_VCT7_RESULTS_CROSS_SHORT:
2033 static int marvell_vct7_report_length(struct phy_device *phydev,
2034 int pair, bool meter)
2039 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2040 MII_VCT7_PAIR_0_DISTANCE + pair);
2044 length = marvell_vct7_distance_to_length(ret, meter);
2046 ethnl_cable_test_fault_length(phydev, pair, length);
2051 static int marvell_vct7_cable_test_report_trans(int result)
2054 case MII_VCT7_RESULTS_OK:
2055 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2056 case MII_VCT7_RESULTS_OPEN:
2057 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2058 case MII_VCT7_RESULTS_SAME_SHORT:
2059 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2060 case MII_VCT7_RESULTS_CROSS_SHORT:
2061 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2063 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2067 static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2069 int pair0, pair1, pair2, pair3;
2073 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2078 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2079 MII_VCT7_RESULTS_PAIR3_SHIFT;
2080 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2081 MII_VCT7_RESULTS_PAIR2_SHIFT;
2082 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2083 MII_VCT7_RESULTS_PAIR1_SHIFT;
2084 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2085 MII_VCT7_RESULTS_PAIR0_SHIFT;
2087 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2088 marvell_vct7_cable_test_report_trans(pair0));
2089 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2090 marvell_vct7_cable_test_report_trans(pair1));
2091 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2092 marvell_vct7_cable_test_report_trans(pair2));
2093 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2094 marvell_vct7_cable_test_report_trans(pair3));
2096 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2100 meter = ret & MII_VCT7_CTRL_METERS;
2102 if (marvell_vct7_distance_valid(pair0))
2103 marvell_vct7_report_length(phydev, 0, meter);
2104 if (marvell_vct7_distance_valid(pair1))
2105 marvell_vct7_report_length(phydev, 1, meter);
2106 if (marvell_vct7_distance_valid(pair2))
2107 marvell_vct7_report_length(phydev, 2, meter);
2108 if (marvell_vct7_distance_valid(pair3))
2109 marvell_vct7_report_length(phydev, 3, meter);
2114 static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2117 struct marvell_priv *priv = phydev->priv;
2120 if (priv->cable_test_tdr) {
2121 ret = marvell_vct5_amplitude_graph(phydev);
2128 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2134 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2137 return marvell_vct7_cable_test_report(phydev);
2144 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2152 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2156 /* Enable temperature sensor */
2157 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2161 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2162 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2166 /* Wait for temperature to stabilize */
2167 usleep_range(10000, 12000);
2169 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2175 /* Disable temperature sensor */
2176 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2177 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2181 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2184 return phy_restore_page(phydev, oldpage, ret);
2187 static int m88e1121_hwmon_read(struct device *dev,
2188 enum hwmon_sensor_types type,
2189 u32 attr, int channel, long *temp)
2191 struct phy_device *phydev = dev_get_drvdata(dev);
2195 case hwmon_temp_input:
2196 err = m88e1121_get_temp(phydev, temp);
2205 static umode_t m88e1121_hwmon_is_visible(const void *data,
2206 enum hwmon_sensor_types type,
2207 u32 attr, int channel)
2209 if (type != hwmon_temp)
2213 case hwmon_temp_input:
2220 static u32 m88e1121_hwmon_chip_config[] = {
2221 HWMON_C_REGISTER_TZ,
2225 static const struct hwmon_channel_info m88e1121_hwmon_chip = {
2227 .config = m88e1121_hwmon_chip_config,
2230 static u32 m88e1121_hwmon_temp_config[] = {
2235 static const struct hwmon_channel_info m88e1121_hwmon_temp = {
2237 .config = m88e1121_hwmon_temp_config,
2240 static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
2241 &m88e1121_hwmon_chip,
2242 &m88e1121_hwmon_temp,
2246 static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
2247 .is_visible = m88e1121_hwmon_is_visible,
2248 .read = m88e1121_hwmon_read,
2251 static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
2252 .ops = &m88e1121_hwmon_hwmon_ops,
2253 .info = m88e1121_hwmon_info,
2256 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2262 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2263 MII_88E1510_TEMP_SENSOR);
2267 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2272 static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2278 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2279 MII_88E1121_MISC_TEST);
2283 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2284 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2291 static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2294 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2296 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2297 MII_88E1121_MISC_TEST,
2298 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2299 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2302 static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2308 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2309 MII_88E1121_MISC_TEST);
2313 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2318 static int m88e1510_hwmon_read(struct device *dev,
2319 enum hwmon_sensor_types type,
2320 u32 attr, int channel, long *temp)
2322 struct phy_device *phydev = dev_get_drvdata(dev);
2326 case hwmon_temp_input:
2327 err = m88e1510_get_temp(phydev, temp);
2329 case hwmon_temp_crit:
2330 err = m88e1510_get_temp_critical(phydev, temp);
2332 case hwmon_temp_max_alarm:
2333 err = m88e1510_get_temp_alarm(phydev, temp);
2342 static int m88e1510_hwmon_write(struct device *dev,
2343 enum hwmon_sensor_types type,
2344 u32 attr, int channel, long temp)
2346 struct phy_device *phydev = dev_get_drvdata(dev);
2350 case hwmon_temp_crit:
2351 err = m88e1510_set_temp_critical(phydev, temp);
2359 static umode_t m88e1510_hwmon_is_visible(const void *data,
2360 enum hwmon_sensor_types type,
2361 u32 attr, int channel)
2363 if (type != hwmon_temp)
2367 case hwmon_temp_input:
2368 case hwmon_temp_max_alarm:
2370 case hwmon_temp_crit:
2377 static u32 m88e1510_hwmon_temp_config[] = {
2378 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2382 static const struct hwmon_channel_info m88e1510_hwmon_temp = {
2384 .config = m88e1510_hwmon_temp_config,
2387 static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
2388 &m88e1121_hwmon_chip,
2389 &m88e1510_hwmon_temp,
2393 static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
2394 .is_visible = m88e1510_hwmon_is_visible,
2395 .read = m88e1510_hwmon_read,
2396 .write = m88e1510_hwmon_write,
2399 static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
2400 .ops = &m88e1510_hwmon_hwmon_ops,
2401 .info = m88e1510_hwmon_info,
2404 static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2413 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2417 /* Enable temperature sensor */
2418 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2422 ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
2423 ret |= MII_88E6390_MISC_TEST_SAMPLE_ENABLE |
2424 MII_88E6390_MISC_TEST_SAMPLE_1S;
2426 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2430 /* Wait for temperature to stabilize */
2431 usleep_range(10000, 12000);
2433 /* Reading the temperature sense has an errata. You need to read
2434 * a number of times and take an average.
2436 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2437 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2440 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2443 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2444 *temp = (sum - 75) * 1000;
2446 /* Disable temperature sensor */
2447 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2451 ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
2452 ret |= MII_88E6390_MISC_TEST_SAMPLE_DISABLE;
2454 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2457 phy_restore_page(phydev, oldpage, ret);
2462 static int m88e6390_hwmon_read(struct device *dev,
2463 enum hwmon_sensor_types type,
2464 u32 attr, int channel, long *temp)
2466 struct phy_device *phydev = dev_get_drvdata(dev);
2470 case hwmon_temp_input:
2471 err = m88e6390_get_temp(phydev, temp);
2480 static umode_t m88e6390_hwmon_is_visible(const void *data,
2481 enum hwmon_sensor_types type,
2482 u32 attr, int channel)
2484 if (type != hwmon_temp)
2488 case hwmon_temp_input:
2495 static u32 m88e6390_hwmon_temp_config[] = {
2500 static const struct hwmon_channel_info m88e6390_hwmon_temp = {
2502 .config = m88e6390_hwmon_temp_config,
2505 static const struct hwmon_channel_info *m88e6390_hwmon_info[] = {
2506 &m88e1121_hwmon_chip,
2507 &m88e6390_hwmon_temp,
2511 static const struct hwmon_ops m88e6390_hwmon_hwmon_ops = {
2512 .is_visible = m88e6390_hwmon_is_visible,
2513 .read = m88e6390_hwmon_read,
2516 static const struct hwmon_chip_info m88e6390_hwmon_chip_info = {
2517 .ops = &m88e6390_hwmon_hwmon_ops,
2518 .info = m88e6390_hwmon_info,
2521 static int marvell_hwmon_name(struct phy_device *phydev)
2523 struct marvell_priv *priv = phydev->priv;
2524 struct device *dev = &phydev->mdio.dev;
2525 const char *devname = dev_name(dev);
2526 size_t len = strlen(devname);
2529 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2530 if (!priv->hwmon_name)
2533 for (i = j = 0; i < len && devname[i]; i++) {
2534 if (isalnum(devname[i]))
2535 priv->hwmon_name[j++] = devname[i];
2541 static int marvell_hwmon_probe(struct phy_device *phydev,
2542 const struct hwmon_chip_info *chip)
2544 struct marvell_priv *priv = phydev->priv;
2545 struct device *dev = &phydev->mdio.dev;
2548 err = marvell_hwmon_name(phydev);
2552 priv->hwmon_dev = devm_hwmon_device_register_with_info(
2553 dev, priv->hwmon_name, phydev, chip, NULL);
2555 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
2558 static int m88e1121_hwmon_probe(struct phy_device *phydev)
2560 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
2563 static int m88e1510_hwmon_probe(struct phy_device *phydev)
2565 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
2568 static int m88e6390_hwmon_probe(struct phy_device *phydev)
2570 return marvell_hwmon_probe(phydev, &m88e6390_hwmon_chip_info);
2573 static int m88e1121_hwmon_probe(struct phy_device *phydev)
2578 static int m88e1510_hwmon_probe(struct phy_device *phydev)
2583 static int m88e6390_hwmon_probe(struct phy_device *phydev)
2589 static int marvell_probe(struct phy_device *phydev)
2591 struct marvell_priv *priv;
2593 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2597 phydev->priv = priv;
2602 static int m88e1121_probe(struct phy_device *phydev)
2606 err = marvell_probe(phydev);
2610 return m88e1121_hwmon_probe(phydev);
2613 static int m88e1510_probe(struct phy_device *phydev)
2617 err = marvell_probe(phydev);
2621 return m88e1510_hwmon_probe(phydev);
2624 static int m88e6390_probe(struct phy_device *phydev)
2628 err = marvell_probe(phydev);
2632 return m88e6390_hwmon_probe(phydev);
2635 static struct phy_driver marvell_drivers[] = {
2637 .phy_id = MARVELL_PHY_ID_88E1101,
2638 .phy_id_mask = MARVELL_PHY_ID_MASK,
2639 .name = "Marvell 88E1101",
2640 /* PHY_GBIT_FEATURES */
2641 .probe = marvell_probe,
2642 .config_init = marvell_config_init,
2643 .config_aneg = m88e1101_config_aneg,
2644 .ack_interrupt = marvell_ack_interrupt,
2645 .config_intr = marvell_config_intr,
2646 .resume = genphy_resume,
2647 .suspend = genphy_suspend,
2648 .read_page = marvell_read_page,
2649 .write_page = marvell_write_page,
2650 .get_sset_count = marvell_get_sset_count,
2651 .get_strings = marvell_get_strings,
2652 .get_stats = marvell_get_stats,
2655 .phy_id = MARVELL_PHY_ID_88E1112,
2656 .phy_id_mask = MARVELL_PHY_ID_MASK,
2657 .name = "Marvell 88E1112",
2658 /* PHY_GBIT_FEATURES */
2659 .probe = marvell_probe,
2660 .config_init = m88e1111_config_init,
2661 .config_aneg = marvell_config_aneg,
2662 .ack_interrupt = marvell_ack_interrupt,
2663 .config_intr = marvell_config_intr,
2664 .resume = genphy_resume,
2665 .suspend = genphy_suspend,
2666 .read_page = marvell_read_page,
2667 .write_page = marvell_write_page,
2668 .get_sset_count = marvell_get_sset_count,
2669 .get_strings = marvell_get_strings,
2670 .get_stats = marvell_get_stats,
2671 .get_tunable = m88e1011_get_tunable,
2672 .set_tunable = m88e1011_set_tunable,
2675 .phy_id = MARVELL_PHY_ID_88E1111,
2676 .phy_id_mask = MARVELL_PHY_ID_MASK,
2677 .name = "Marvell 88E1111",
2678 /* PHY_GBIT_FEATURES */
2679 .probe = marvell_probe,
2680 .config_init = m88e1111_config_init,
2681 .config_aneg = marvell_config_aneg,
2682 .read_status = marvell_read_status,
2683 .ack_interrupt = marvell_ack_interrupt,
2684 .config_intr = marvell_config_intr,
2685 .resume = genphy_resume,
2686 .suspend = genphy_suspend,
2687 .read_page = marvell_read_page,
2688 .write_page = marvell_write_page,
2689 .get_sset_count = marvell_get_sset_count,
2690 .get_strings = marvell_get_strings,
2691 .get_stats = marvell_get_stats,
2692 .get_tunable = m88e1111_get_tunable,
2693 .set_tunable = m88e1111_set_tunable,
2696 .phy_id = MARVELL_PHY_ID_88E1118,
2697 .phy_id_mask = MARVELL_PHY_ID_MASK,
2698 .name = "Marvell 88E1118",
2699 /* PHY_GBIT_FEATURES */
2700 .probe = marvell_probe,
2701 .config_init = m88e1118_config_init,
2702 .config_aneg = m88e1118_config_aneg,
2703 .ack_interrupt = marvell_ack_interrupt,
2704 .config_intr = marvell_config_intr,
2705 .resume = genphy_resume,
2706 .suspend = genphy_suspend,
2707 .read_page = marvell_read_page,
2708 .write_page = marvell_write_page,
2709 .get_sset_count = marvell_get_sset_count,
2710 .get_strings = marvell_get_strings,
2711 .get_stats = marvell_get_stats,
2714 .phy_id = MARVELL_PHY_ID_88E1121R,
2715 .phy_id_mask = MARVELL_PHY_ID_MASK,
2716 .name = "Marvell 88E1121R",
2717 /* PHY_GBIT_FEATURES */
2718 .probe = m88e1121_probe,
2719 .config_init = marvell_config_init,
2720 .config_aneg = m88e1121_config_aneg,
2721 .read_status = marvell_read_status,
2722 .ack_interrupt = marvell_ack_interrupt,
2723 .config_intr = marvell_config_intr,
2724 .did_interrupt = m88e1121_did_interrupt,
2725 .resume = genphy_resume,
2726 .suspend = genphy_suspend,
2727 .read_page = marvell_read_page,
2728 .write_page = marvell_write_page,
2729 .get_sset_count = marvell_get_sset_count,
2730 .get_strings = marvell_get_strings,
2731 .get_stats = marvell_get_stats,
2732 .get_tunable = m88e1011_get_tunable,
2733 .set_tunable = m88e1011_set_tunable,
2736 .phy_id = MARVELL_PHY_ID_88E1318S,
2737 .phy_id_mask = MARVELL_PHY_ID_MASK,
2738 .name = "Marvell 88E1318S",
2739 /* PHY_GBIT_FEATURES */
2740 .probe = marvell_probe,
2741 .config_init = m88e1318_config_init,
2742 .config_aneg = m88e1318_config_aneg,
2743 .read_status = marvell_read_status,
2744 .ack_interrupt = marvell_ack_interrupt,
2745 .config_intr = marvell_config_intr,
2746 .did_interrupt = m88e1121_did_interrupt,
2747 .get_wol = m88e1318_get_wol,
2748 .set_wol = m88e1318_set_wol,
2749 .resume = genphy_resume,
2750 .suspend = genphy_suspend,
2751 .read_page = marvell_read_page,
2752 .write_page = marvell_write_page,
2753 .get_sset_count = marvell_get_sset_count,
2754 .get_strings = marvell_get_strings,
2755 .get_stats = marvell_get_stats,
2758 .phy_id = MARVELL_PHY_ID_88E1145,
2759 .phy_id_mask = MARVELL_PHY_ID_MASK,
2760 .name = "Marvell 88E1145",
2761 /* PHY_GBIT_FEATURES */
2762 .probe = marvell_probe,
2763 .config_init = m88e1145_config_init,
2764 .config_aneg = m88e1101_config_aneg,
2765 .read_status = genphy_read_status,
2766 .ack_interrupt = marvell_ack_interrupt,
2767 .config_intr = marvell_config_intr,
2768 .resume = genphy_resume,
2769 .suspend = genphy_suspend,
2770 .read_page = marvell_read_page,
2771 .write_page = marvell_write_page,
2772 .get_sset_count = marvell_get_sset_count,
2773 .get_strings = marvell_get_strings,
2774 .get_stats = marvell_get_stats,
2775 .get_tunable = m88e1111_get_tunable,
2776 .set_tunable = m88e1111_set_tunable,
2779 .phy_id = MARVELL_PHY_ID_88E1149R,
2780 .phy_id_mask = MARVELL_PHY_ID_MASK,
2781 .name = "Marvell 88E1149R",
2782 /* PHY_GBIT_FEATURES */
2783 .probe = marvell_probe,
2784 .config_init = m88e1149_config_init,
2785 .config_aneg = m88e1118_config_aneg,
2786 .ack_interrupt = marvell_ack_interrupt,
2787 .config_intr = marvell_config_intr,
2788 .resume = genphy_resume,
2789 .suspend = genphy_suspend,
2790 .read_page = marvell_read_page,
2791 .write_page = marvell_write_page,
2792 .get_sset_count = marvell_get_sset_count,
2793 .get_strings = marvell_get_strings,
2794 .get_stats = marvell_get_stats,
2797 .phy_id = MARVELL_PHY_ID_88E1240,
2798 .phy_id_mask = MARVELL_PHY_ID_MASK,
2799 .name = "Marvell 88E1240",
2800 /* PHY_GBIT_FEATURES */
2801 .probe = marvell_probe,
2802 .config_init = m88e1111_config_init,
2803 .config_aneg = marvell_config_aneg,
2804 .ack_interrupt = marvell_ack_interrupt,
2805 .config_intr = marvell_config_intr,
2806 .resume = genphy_resume,
2807 .suspend = genphy_suspend,
2808 .read_page = marvell_read_page,
2809 .write_page = marvell_write_page,
2810 .get_sset_count = marvell_get_sset_count,
2811 .get_strings = marvell_get_strings,
2812 .get_stats = marvell_get_stats,
2815 .phy_id = MARVELL_PHY_ID_88E1116R,
2816 .phy_id_mask = MARVELL_PHY_ID_MASK,
2817 .name = "Marvell 88E1116R",
2818 /* PHY_GBIT_FEATURES */
2819 .probe = marvell_probe,
2820 .config_init = m88e1116r_config_init,
2821 .ack_interrupt = marvell_ack_interrupt,
2822 .config_intr = marvell_config_intr,
2823 .resume = genphy_resume,
2824 .suspend = genphy_suspend,
2825 .read_page = marvell_read_page,
2826 .write_page = marvell_write_page,
2827 .get_sset_count = marvell_get_sset_count,
2828 .get_strings = marvell_get_strings,
2829 .get_stats = marvell_get_stats,
2830 .get_tunable = m88e1011_get_tunable,
2831 .set_tunable = m88e1011_set_tunable,
2834 .phy_id = MARVELL_PHY_ID_88E1510,
2835 .phy_id_mask = MARVELL_PHY_ID_MASK,
2836 .name = "Marvell 88E1510",
2837 .features = PHY_GBIT_FIBRE_FEATURES,
2838 .flags = PHY_POLL_CABLE_TEST,
2839 .probe = m88e1510_probe,
2840 .config_init = m88e1510_config_init,
2841 .config_aneg = m88e1510_config_aneg,
2842 .read_status = marvell_read_status,
2843 .ack_interrupt = marvell_ack_interrupt,
2844 .config_intr = marvell_config_intr,
2845 .did_interrupt = m88e1121_did_interrupt,
2846 .get_wol = m88e1318_get_wol,
2847 .set_wol = m88e1318_set_wol,
2848 .resume = marvell_resume,
2849 .suspend = marvell_suspend,
2850 .read_page = marvell_read_page,
2851 .write_page = marvell_write_page,
2852 .get_sset_count = marvell_get_sset_count,
2853 .get_strings = marvell_get_strings,
2854 .get_stats = marvell_get_stats,
2855 .set_loopback = genphy_loopback,
2856 .get_tunable = m88e1011_get_tunable,
2857 .set_tunable = m88e1011_set_tunable,
2858 .cable_test_start = marvell_vct7_cable_test_start,
2859 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2860 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2863 .phy_id = MARVELL_PHY_ID_88E1540,
2864 .phy_id_mask = MARVELL_PHY_ID_MASK,
2865 .name = "Marvell 88E1540",
2866 /* PHY_GBIT_FEATURES */
2867 .flags = PHY_POLL_CABLE_TEST,
2868 .probe = m88e1510_probe,
2869 .config_init = marvell_config_init,
2870 .config_aneg = m88e1510_config_aneg,
2871 .read_status = marvell_read_status,
2872 .ack_interrupt = marvell_ack_interrupt,
2873 .config_intr = marvell_config_intr,
2874 .did_interrupt = m88e1121_did_interrupt,
2875 .resume = genphy_resume,
2876 .suspend = genphy_suspend,
2877 .read_page = marvell_read_page,
2878 .write_page = marvell_write_page,
2879 .get_sset_count = marvell_get_sset_count,
2880 .get_strings = marvell_get_strings,
2881 .get_stats = marvell_get_stats,
2882 .get_tunable = m88e1540_get_tunable,
2883 .set_tunable = m88e1540_set_tunable,
2884 .cable_test_start = marvell_vct7_cable_test_start,
2885 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2886 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2889 .phy_id = MARVELL_PHY_ID_88E1545,
2890 .phy_id_mask = MARVELL_PHY_ID_MASK,
2891 .name = "Marvell 88E1545",
2892 .probe = m88e1510_probe,
2893 /* PHY_GBIT_FEATURES */
2894 .flags = PHY_POLL_CABLE_TEST,
2895 .config_init = marvell_config_init,
2896 .config_aneg = m88e1510_config_aneg,
2897 .read_status = marvell_read_status,
2898 .ack_interrupt = marvell_ack_interrupt,
2899 .config_intr = marvell_config_intr,
2900 .did_interrupt = m88e1121_did_interrupt,
2901 .resume = genphy_resume,
2902 .suspend = genphy_suspend,
2903 .read_page = marvell_read_page,
2904 .write_page = marvell_write_page,
2905 .get_sset_count = marvell_get_sset_count,
2906 .get_strings = marvell_get_strings,
2907 .get_stats = marvell_get_stats,
2908 .get_tunable = m88e1540_get_tunable,
2909 .set_tunable = m88e1540_set_tunable,
2910 .cable_test_start = marvell_vct7_cable_test_start,
2911 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2912 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2915 .phy_id = MARVELL_PHY_ID_88E3016,
2916 .phy_id_mask = MARVELL_PHY_ID_MASK,
2917 .name = "Marvell 88E3016",
2918 /* PHY_BASIC_FEATURES */
2919 .probe = marvell_probe,
2920 .config_init = m88e3016_config_init,
2921 .aneg_done = marvell_aneg_done,
2922 .read_status = marvell_read_status,
2923 .ack_interrupt = marvell_ack_interrupt,
2924 .config_intr = marvell_config_intr,
2925 .did_interrupt = m88e1121_did_interrupt,
2926 .resume = genphy_resume,
2927 .suspend = genphy_suspend,
2928 .read_page = marvell_read_page,
2929 .write_page = marvell_write_page,
2930 .get_sset_count = marvell_get_sset_count,
2931 .get_strings = marvell_get_strings,
2932 .get_stats = marvell_get_stats,
2935 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
2936 .phy_id_mask = MARVELL_PHY_ID_MASK,
2937 .name = "Marvell 88E6341 Family",
2938 /* PHY_GBIT_FEATURES */
2939 .flags = PHY_POLL_CABLE_TEST,
2940 .probe = m88e1510_probe,
2941 .config_init = marvell_config_init,
2942 .config_aneg = m88e6390_config_aneg,
2943 .read_status = marvell_read_status,
2944 .ack_interrupt = marvell_ack_interrupt,
2945 .config_intr = marvell_config_intr,
2946 .did_interrupt = m88e1121_did_interrupt,
2947 .resume = genphy_resume,
2948 .suspend = genphy_suspend,
2949 .read_page = marvell_read_page,
2950 .write_page = marvell_write_page,
2951 .get_sset_count = marvell_get_sset_count,
2952 .get_strings = marvell_get_strings,
2953 .get_stats = marvell_get_stats,
2954 .get_tunable = m88e1540_get_tunable,
2955 .set_tunable = m88e1540_set_tunable,
2956 .cable_test_start = marvell_vct7_cable_test_start,
2957 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2958 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2961 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
2962 .phy_id_mask = MARVELL_PHY_ID_MASK,
2963 .name = "Marvell 88E6390 Family",
2964 /* PHY_GBIT_FEATURES */
2965 .flags = PHY_POLL_CABLE_TEST,
2966 .probe = m88e6390_probe,
2967 .config_init = marvell_config_init,
2968 .config_aneg = m88e6390_config_aneg,
2969 .read_status = marvell_read_status,
2970 .ack_interrupt = marvell_ack_interrupt,
2971 .config_intr = marvell_config_intr,
2972 .did_interrupt = m88e1121_did_interrupt,
2973 .resume = genphy_resume,
2974 .suspend = genphy_suspend,
2975 .read_page = marvell_read_page,
2976 .write_page = marvell_write_page,
2977 .get_sset_count = marvell_get_sset_count,
2978 .get_strings = marvell_get_strings,
2979 .get_stats = marvell_get_stats,
2980 .get_tunable = m88e1540_get_tunable,
2981 .set_tunable = m88e1540_set_tunable,
2982 .cable_test_start = marvell_vct7_cable_test_start,
2983 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2984 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2987 .phy_id = MARVELL_PHY_ID_88E1340S,
2988 .phy_id_mask = MARVELL_PHY_ID_MASK,
2989 .name = "Marvell 88E1340S",
2990 .probe = m88e1510_probe,
2991 /* PHY_GBIT_FEATURES */
2992 .config_init = marvell_config_init,
2993 .config_aneg = m88e1510_config_aneg,
2994 .read_status = marvell_read_status,
2995 .ack_interrupt = marvell_ack_interrupt,
2996 .config_intr = marvell_config_intr,
2997 .did_interrupt = m88e1121_did_interrupt,
2998 .resume = genphy_resume,
2999 .suspend = genphy_suspend,
3000 .read_page = marvell_read_page,
3001 .write_page = marvell_write_page,
3002 .get_sset_count = marvell_get_sset_count,
3003 .get_strings = marvell_get_strings,
3004 .get_stats = marvell_get_stats,
3005 .get_tunable = m88e1540_get_tunable,
3006 .set_tunable = m88e1540_set_tunable,
3009 .phy_id = MARVELL_PHY_ID_88E1548P,
3010 .phy_id_mask = MARVELL_PHY_ID_MASK,
3011 .name = "Marvell 88E1548P",
3012 .probe = m88e1510_probe,
3013 .features = PHY_GBIT_FIBRE_FEATURES,
3014 .config_init = marvell_config_init,
3015 .config_aneg = m88e1510_config_aneg,
3016 .read_status = marvell_read_status,
3017 .ack_interrupt = marvell_ack_interrupt,
3018 .config_intr = marvell_config_intr,
3019 .did_interrupt = m88e1121_did_interrupt,
3020 .resume = genphy_resume,
3021 .suspend = genphy_suspend,
3022 .read_page = marvell_read_page,
3023 .write_page = marvell_write_page,
3024 .get_sset_count = marvell_get_sset_count,
3025 .get_strings = marvell_get_strings,
3026 .get_stats = marvell_get_stats,
3027 .get_tunable = m88e1540_get_tunable,
3028 .set_tunable = m88e1540_set_tunable,
3032 module_phy_driver(marvell_drivers);
3034 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3035 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3036 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3037 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3038 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3039 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3040 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3041 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3042 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3043 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3044 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3045 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3046 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3047 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3048 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3049 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3050 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
3051 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3052 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3056 MODULE_DEVICE_TABLE(mdio, marvell_tbl);