drivers/net/phy/marvell.c

   1 /*
   2  * drivers/net/phy/marvell.c
   3  *
   4  * Driver for Marvell PHYs
   5  *
   6  * Author: Andy Fleming
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  *
  10  * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/string.h>
  20 #include <linux/errno.h>
  21 #include <linux/unistd.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mii.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/phy.h>
  34 #include <linux/marvell_phy.h>
  35 #include <linux/of.h>
  36
  37 #include <linux/io.h>
  38 #include <asm/irq.h>
  39 #include <linux/uaccess.h>
  40
  41 #define MII_MARVELL_PHY_PAGE            22
  42
  43 #define MII_M1011_IEVENT                0x13
  44 #define MII_M1011_IEVENT_CLEAR          0x0000
  45
  46 #define MII_M1011_IMASK                 0x12
  47 #define MII_M1011_IMASK_INIT            0x6400
  48 #define MII_M1011_IMASK_CLEAR           0x0000
  49
  50 #define MII_M1011_PHY_SCR               0x10
  51 #define MII_M1011_PHY_SCR_MDI           0x0000
  52 #define MII_M1011_PHY_SCR_MDI_X         0x0020
  53 #define MII_M1011_PHY_SCR_AUTO_CROSS    0x0060
  54
  55 #define MII_M1145_PHY_EXT_ADDR_PAGE     0x16
  56 #define MII_M1145_PHY_EXT_SR            0x1b
  57 #define MII_M1145_PHY_EXT_CR            0x14
  58 #define MII_M1145_RGMII_RX_DELAY        0x0080
  59 #define MII_M1145_RGMII_TX_DELAY        0x0002
  60 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK       0x4
  61 #define MII_M1145_HWCFG_MODE_MASK               0xf
  62 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO       0x8000
  63
  64 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK       0x4
  65 #define MII_M1145_HWCFG_MODE_MASK               0xf
  66 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO       0x8000
  67
  68 #define MII_M1111_PHY_LED_CONTROL       0x18
  69 #define MII_M1111_PHY_LED_DIRECT        0x4100
  70 #define MII_M1111_PHY_LED_COMBINE       0x411c
  71 #define MII_M1111_PHY_EXT_CR            0x14
  72 #define MII_M1111_RX_DELAY              0x80
  73 #define MII_M1111_TX_DELAY              0x2
  74 #define MII_M1111_PHY_EXT_SR            0x1b
  75
  76 #define MII_M1111_HWCFG_MODE_MASK               0xf
  77 #define MII_M1111_HWCFG_MODE_COPPER_RGMII       0xb
  78 #define MII_M1111_HWCFG_MODE_FIBER_RGMII        0x3
  79 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK       0x4
  80 #define MII_M1111_HWCFG_MODE_COPPER_RTBI        0x9
  81 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO       0x8000
  82 #define MII_M1111_HWCFG_FIBER_COPPER_RES        0x2000
  83
  84 #define MII_M1111_COPPER                0
  85 #define MII_M1111_FIBER                 1
  86
  87 #define MII_88E1121_PHY_MSCR_PAGE       2
  88 #define MII_88E1121_PHY_MSCR_REG        21
  89 #define MII_88E1121_PHY_MSCR_RX_DELAY   BIT(5)
  90 #define MII_88E1121_PHY_MSCR_TX_DELAY   BIT(4)
  91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
  92
  93 #define MII_88E1318S_PHY_MSCR1_REG      16
  94 #define MII_88E1318S_PHY_MSCR1_PAD_ODD  BIT(6)
  95
  96 /* Copper Specific Interrupt Enable Register */
  97 #define MII_88E1318S_PHY_CSIER                              0x12
  98 /* WOL Event Interrupt Enable */
  99 #define MII_88E1318S_PHY_CSIER_WOL_EIE                      BIT(7)
 100
 101 /* LED Timer Control Register */
 102 #define MII_88E1318S_PHY_LED_PAGE                           0x03
 103 #define MII_88E1318S_PHY_LED_TCR                            0x12
 104 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT                  BIT(15)
 105 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE                BIT(7)
 106 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW             BIT(11)
 107
 108 /* Magic Packet MAC address registers */
 109 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2                 0x17
 110 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1                 0x18
 111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0                 0x19
 112
 113 #define MII_88E1318S_PHY_WOL_PAGE                           0x11
 114 #define MII_88E1318S_PHY_WOL_CTRL                           0x10
 115 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS          BIT(12)
 116 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
 117
 118 #define MII_88E1121_PHY_LED_CTRL        16
 119 #define MII_88E1121_PHY_LED_PAGE        3
 120 #define MII_88E1121_PHY_LED_DEF         0x0030
 121
 122 #define MII_M1011_PHY_STATUS            0x11
 123 #define MII_M1011_PHY_STATUS_1000       0x8000
 124 #define MII_M1011_PHY_STATUS_100        0x4000
 125 #define MII_M1011_PHY_STATUS_SPD_MASK   0xc000
 126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
 127 #define MII_M1011_PHY_STATUS_RESOLVED   0x0800
 128 #define MII_M1011_PHY_STATUS_LINK       0x0400
 129
 130 #define MII_M1116R_CONTROL_REG_MAC      21
 131
 132 #define MII_88E3016_PHY_SPEC_CTRL       0x10
 133 #define MII_88E3016_DISABLE_SCRAMBLER   0x0200
 134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
 135
 136 MODULE_DESCRIPTION("Marvell PHY driver");
 137 MODULE_AUTHOR("Andy Fleming");
 138 MODULE_LICENSE("GPL");
 139
 140 static int marvell_ack_interrupt(struct phy_device *phydev)
 141 {
 142         int err;
 143
 144         /* Clear the interrupts by reading the reg */
 145         err = phy_read(phydev, MII_M1011_IEVENT);
 146
 147         if (err < 0)
 148                 return err;
 149
 150         return 0;
 151 }
 152
 153 static int marvell_config_intr(struct phy_device *phydev)
 154 {
 155         int err;
 156
 157         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 158                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 159         else
 160                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
 161
 162         return err;
 163 }
 164
 165 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
 166 {
 167         int reg;
 168         int err;
 169         int val;
 170
 171         /* get the current settings */
 172         reg = phy_read(phydev, MII_M1011_PHY_SCR);
 173         if (reg < 0)
 174                 return reg;
 175
 176         val = reg;
 177         val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
 178         switch (polarity) {
 179         case ETH_TP_MDI:
 180                 val |= MII_M1011_PHY_SCR_MDI;
 181                 break;
 182         case ETH_TP_MDI_X:
 183                 val |= MII_M1011_PHY_SCR_MDI_X;
 184                 break;
 185         case ETH_TP_MDI_AUTO:
 186         case ETH_TP_MDI_INVALID:
 187         default:
 188                 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
 189                 break;
 190         }
 191
 192         if (val != reg) {
 193                 /* Set the new polarity value in the register */
 194                 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
 195                 if (err)
 196                         return err;
 197         }
 198
 199         return 0;
 200 }
 201
 202 static int marvell_config_aneg(struct phy_device *phydev)
 203 {
 204         int err;
 205
 206         err = marvell_set_polarity(phydev, phydev->mdix);
 207         if (err < 0)
 208                 return err;
 209
 210         err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
 211                         MII_M1111_PHY_LED_DIRECT);
 212         if (err < 0)
 213                 return err;
 214
 215         err = genphy_config_aneg(phydev);
 216         if (err < 0)
 217                 return err;
 218
 219         if (phydev->autoneg != AUTONEG_ENABLE) {
 220                 int bmcr;
 221
 222                 /*
 223                  * A write to speed/duplex bits (that is performed by
 224                  * genphy_config_aneg() call above) must be followed by
 225                  * a software reset. Otherwise, the write has no effect.
 226                  */
 227                 bmcr = phy_read(phydev, MII_BMCR);
 228                 if (bmcr < 0)
 229                         return bmcr;
 230
 231                 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
 232                 if (err < 0)
 233                         return err;
 234         }
 235
 236         return 0;
 237 }
 238
 239 static int m88e1101_config_aneg(struct phy_device *phydev)
 240 {
 241         int err;
 242
 243         /* This Marvell PHY has an errata which requires
 244          * that certain registers get written in order
 245          * to restart autonegotiation
 246          */
 247         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 248
 249         if (err < 0)
 250                 return err;
 251
 252         err = phy_write(phydev, 0x1d, 0x1f);
 253         if (err < 0)
 254                 return err;
 255
 256         err = phy_write(phydev, 0x1e, 0x200c);
 257         if (err < 0)
 258                 return err;
 259
 260         err = phy_write(phydev, 0x1d, 0x5);
 261         if (err < 0)
 262                 return err;
 263
 264         err = phy_write(phydev, 0x1e, 0);
 265         if (err < 0)
 266                 return err;
 267
 268         err = phy_write(phydev, 0x1e, 0x100);
 269         if (err < 0)
 270                 return err;
 271
 272         return marvell_config_aneg(phydev);
 273 }
 274
 275 #ifdef CONFIG_OF_MDIO
 276 /*
 277  * Set and/or override some configuration registers based on the
 278  * marvell,reg-init property stored in the of_node for the phydev.
 279  *
 280  * marvell,reg-init = <reg-page reg mask value>,...;
 281  *
 282  * There may be one or more sets of <reg-page reg mask value>:
 283  *
 284  * reg-page: which register bank to use.
 285  * reg: the register.
 286  * mask: if non-zero, ANDed with existing register value.
 287  * value: ORed with the masked value and written to the regiser.
 288  *
 289  */
 290 static int marvell_of_reg_init(struct phy_device *phydev)
 291 {
 292         const __be32 *paddr;
 293         int len, i, saved_page, current_page, page_changed, ret;
 294
 295         if (!phydev->dev.of_node)
 296                 return 0;
 297
 298         paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
 299         if (!paddr || len < (4 * sizeof(*paddr)))
 300                 return 0;
 301
 302         saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 303         if (saved_page < 0)
 304                 return saved_page;
 305         page_changed = 0;
 306         current_page = saved_page;
 307
 308         ret = 0;
 309         len /= sizeof(*paddr);
 310         for (i = 0; i < len - 3; i += 4) {
 311                 u16 reg_page = be32_to_cpup(paddr + i);
 312                 u16 reg = be32_to_cpup(paddr + i + 1);
 313                 u16 mask = be32_to_cpup(paddr + i + 2);
 314                 u16 val_bits = be32_to_cpup(paddr + i + 3);
 315                 int val;
 316
 317                 if (reg_page != current_page) {
 318                         current_page = reg_page;
 319                         page_changed = 1;
 320                         ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
 321                         if (ret < 0)
 322                                 goto err;
 323                 }
 324
 325                 val = 0;
 326                 if (mask) {
 327                         val = phy_read(phydev, reg);
 328                         if (val < 0) {
 329                                 ret = val;
 330                                 goto err;
 331                         }
 332                         val &= mask;
 333                 }
 334                 val |= val_bits;
 335
 336                 ret = phy_write(phydev, reg, val);
 337                 if (ret < 0)
 338                         goto err;
 339
 340         }
 341 err:
 342         if (page_changed) {
 343                 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
 344                 if (ret == 0)
 345                         ret = i;
 346         }
 347         return ret;
 348 }
 349 #else
 350 static int marvell_of_reg_init(struct phy_device *phydev)
 351 {
 352         return 0;
 353 }
 354 #endif /* CONFIG_OF_MDIO */
 355
 356 static int m88e1121_config_aneg(struct phy_device *phydev)
 357 {
 358         int err, oldpage, mscr;
 359
 360         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 361
 362         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 363                         MII_88E1121_PHY_MSCR_PAGE);
 364         if (err < 0)
 365                 return err;
 366
 367         if (phy_interface_is_rgmii(phydev)) {
 368
 369                 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
 370                         MII_88E1121_PHY_MSCR_DELAY_MASK;
 371
 372                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 373                         mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
 374                                  MII_88E1121_PHY_MSCR_TX_DELAY);
 375                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 376                         mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
 377                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 378                         mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
 379
 380                 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
 381                 if (err < 0)
 382                         return err;
 383         }
 384
 385         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 386
 387         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 388         if (err < 0)
 389                 return err;
 390
 391         err = phy_write(phydev, MII_M1011_PHY_SCR,
 392                         MII_M1011_PHY_SCR_AUTO_CROSS);
 393         if (err < 0)
 394                 return err;
 395
 396         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 397
 398         phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
 399         phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
 400         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 401
 402         err = genphy_config_aneg(phydev);
 403
 404         return err;
 405 }
 406
 407 static int m88e1318_config_aneg(struct phy_device *phydev)
 408 {
 409         int err, oldpage, mscr;
 410
 411         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 412
 413         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 414                         MII_88E1121_PHY_MSCR_PAGE);
 415         if (err < 0)
 416                 return err;
 417
 418         mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
 419         mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
 420
 421         err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
 422         if (err < 0)
 423                 return err;
 424
 425         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 426         if (err < 0)
 427                 return err;
 428
 429         return m88e1121_config_aneg(phydev);
 430 }
 431
 432 static int m88e1510_config_aneg(struct phy_device *phydev)
 433 {
 434         int err;
 435
 436         err = m88e1318_config_aneg(phydev);
 437         if (err < 0)
 438                 return err;
 439
 440         return marvell_of_reg_init(phydev);
 441 }
 442
 443 static int m88e1116r_config_init(struct phy_device *phydev)
 444 {
 445         int temp;
 446         int err;
 447
 448         temp = phy_read(phydev, MII_BMCR);
 449         temp |= BMCR_RESET;
 450         err = phy_write(phydev, MII_BMCR, temp);
 451         if (err < 0)
 452                 return err;
 453
 454         mdelay(500);
 455
 456         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 457         if (err < 0)
 458                 return err;
 459
 460         temp = phy_read(phydev, MII_M1011_PHY_SCR);
 461         temp |= (7 << 12);      /* max number of gigabit attempts */
 462         temp |= (1 << 11);      /* enable downshift */
 463         temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
 464         err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
 465         if (err < 0)
 466                 return err;
 467
 468         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
 469         if (err < 0)
 470                 return err;
 471         temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
 472         temp |= (1 << 5);
 473         temp |= (1 << 4);
 474         err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
 475         if (err < 0)
 476                 return err;
 477         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 478         if (err < 0)
 479                 return err;
 480
 481         temp = phy_read(phydev, MII_BMCR);
 482         temp |= BMCR_RESET;
 483         err = phy_write(phydev, MII_BMCR, temp);
 484         if (err < 0)
 485                 return err;
 486
 487         mdelay(500);
 488
 489         return 0;
 490 }
 491
 492 static int m88e3016_config_init(struct phy_device *phydev)
 493 {
 494         int reg;
 495
 496         /* Enable Scrambler and Auto-Crossover */
 497         reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
 498         if (reg < 0)
 499                 return reg;
 500
 501         reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
 502         reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
 503
 504         reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
 505         if (reg < 0)
 506                 return reg;
 507
 508         return 0;
 509 }
 510
 511 static int m88e1111_config_init(struct phy_device *phydev)
 512 {
 513         int err;
 514         int temp;
 515
 516         if (phy_interface_is_rgmii(phydev)) {
 517
 518                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 519                 if (temp < 0)
 520                         return temp;
 521
 522                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 523                         temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 524                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 525                         temp &= ~MII_M1111_TX_DELAY;
 526                         temp |= MII_M1111_RX_DELAY;
 527                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 528                         temp &= ~MII_M1111_RX_DELAY;
 529                         temp |= MII_M1111_TX_DELAY;
 530                 }
 531
 532                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 533                 if (err < 0)
 534                         return err;
 535
 536                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 537                 if (temp < 0)
 538                         return temp;
 539
 540                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 541
 542                 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
 543                         temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
 544                 else
 545                         temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
 546
 547                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 548                 if (err < 0)
 549                         return err;
 550         }
 551
 552         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 553                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 554                 if (temp < 0)
 555                         return temp;
 556
 557                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 558                 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
 559                 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 560
 561                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 562                 if (err < 0)
 563                         return err;
 564
 565                 /* make sure copper is selected */
 566                 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
 567                 if (err < 0)
 568                         return err;
 569
 570                 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
 571                                 err & (~0xff));
 572                 if (err < 0)
 573                         return err;
 574         }
 575
 576         if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
 577                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 578                 if (temp < 0)
 579                         return temp;
 580                 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 581                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 582                 if (err < 0)
 583                         return err;
 584
 585                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 586                 if (temp < 0)
 587                         return temp;
 588                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 589                 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 590                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 591                 if (err < 0)
 592                         return err;
 593
 594                 /* soft reset */
 595                 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 596                 if (err < 0)
 597                         return err;
 598                 do
 599                         temp = phy_read(phydev, MII_BMCR);
 600                 while (temp & BMCR_RESET);
 601
 602                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 603                 if (temp < 0)
 604                         return temp;
 605                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 606                 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 607                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 608                 if (err < 0)
 609                         return err;
 610         }
 611
 612         err = marvell_of_reg_init(phydev);
 613         if (err < 0)
 614                 return err;
 615
 616         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 617 }
 618
 619 static int m88e1118_config_aneg(struct phy_device *phydev)
 620 {
 621         int err;
 622
 623         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 624         if (err < 0)
 625                 return err;
 626
 627         err = phy_write(phydev, MII_M1011_PHY_SCR,
 628                         MII_M1011_PHY_SCR_AUTO_CROSS);
 629         if (err < 0)
 630                 return err;
 631
 632         err = genphy_config_aneg(phydev);
 633         return 0;
 634 }
 635
 636 static int m88e1118_config_init(struct phy_device *phydev)
 637 {
 638         int err;
 639
 640         /* Change address */
 641         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 642         if (err < 0)
 643                 return err;
 644
 645         /* Enable 1000 Mbit */
 646         err = phy_write(phydev, 0x15, 0x1070);
 647         if (err < 0)
 648                 return err;
 649
 650         /* Change address */
 651         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
 652         if (err < 0)
 653                 return err;
 654
 655         /* Adjust LED Control */
 656         if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
 657                 err = phy_write(phydev, 0x10, 0x1100);
 658         else
 659                 err = phy_write(phydev, 0x10, 0x021e);
 660         if (err < 0)
 661                 return err;
 662
 663         err = marvell_of_reg_init(phydev);
 664         if (err < 0)
 665                 return err;
 666
 667         /* Reset address */
 668         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 669         if (err < 0)
 670                 return err;
 671
 672         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 673 }
 674
 675 static int m88e1149_config_init(struct phy_device *phydev)
 676 {
 677         int err;
 678
 679         /* Change address */
 680         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 681         if (err < 0)
 682                 return err;
 683
 684         /* Enable 1000 Mbit */
 685         err = phy_write(phydev, 0x15, 0x1048);
 686         if (err < 0)
 687                 return err;
 688
 689         err = marvell_of_reg_init(phydev);
 690         if (err < 0)
 691                 return err;
 692
 693         /* Reset address */
 694         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 695         if (err < 0)
 696                 return err;
 697
 698         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 699 }
 700
 701 static int m88e1145_config_init(struct phy_device *phydev)
 702 {
 703         int err;
 704         int temp;
 705
 706         /* Take care of errata E0 & E1 */
 707         err = phy_write(phydev, 0x1d, 0x001b);
 708         if (err < 0)
 709                 return err;
 710
 711         err = phy_write(phydev, 0x1e, 0x418f);
 712         if (err < 0)
 713                 return err;
 714
 715         err = phy_write(phydev, 0x1d, 0x0016);
 716         if (err < 0)
 717                 return err;
 718
 719         err = phy_write(phydev, 0x1e, 0xa2da);
 720         if (err < 0)
 721                 return err;
 722
 723         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 724                 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
 725                 if (temp < 0)
 726                         return temp;
 727
 728                 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
 729
 730                 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
 731                 if (err < 0)
 732                         return err;
 733
 734                 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
 735                         err = phy_write(phydev, 0x1d, 0x0012);
 736                         if (err < 0)
 737                                 return err;
 738
 739                         temp = phy_read(phydev, 0x1e);
 740                         if (temp < 0)
 741                                 return temp;
 742
 743                         temp &= 0xf03f;
 744                         temp |= 2 << 9; /* 36 ohm */
 745                         temp |= 2 << 6; /* 39 ohm */
 746
 747                         err = phy_write(phydev, 0x1e, temp);
 748                         if (err < 0)
 749                                 return err;
 750
 751                         err = phy_write(phydev, 0x1d, 0x3);
 752                         if (err < 0)
 753                                 return err;
 754
 755                         err = phy_write(phydev, 0x1e, 0x8000);
 756                         if (err < 0)
 757                                 return err;
 758                 }
 759         }
 760
 761         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 762                 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
 763                 if (temp < 0)
 764                         return temp;
 765
 766                 temp &= ~MII_M1145_HWCFG_MODE_MASK;
 767                 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
 768                 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
 769
 770                 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
 771                 if (err < 0)
 772                         return err;
 773         }
 774
 775         err = marvell_of_reg_init(phydev);
 776         if (err < 0)
 777                 return err;
 778
 779         return 0;
 780 }
 781
 782 /* marvell_read_status
 783  *
 784  * Generic status code does not detect Fiber correctly!
 785  * Description:
 786  *   Check the link, then figure out the current state
 787  *   by comparing what we advertise with what the link partner
 788  *   advertises.  Start by checking the gigabit possibilities,
 789  *   then move on to 10/100.
 790  */
 791 static int marvell_read_status(struct phy_device *phydev)
 792 {
 793         int adv;
 794         int err;
 795         int lpa;
 796         int lpagb;
 797         int status = 0;
 798
 799         /* Update the link, but return if there
 800          * was an error */
 801         err = genphy_update_link(phydev);
 802         if (err)
 803                 return err;
 804
 805         if (AUTONEG_ENABLE == phydev->autoneg) {
 806                 status = phy_read(phydev, MII_M1011_PHY_STATUS);
 807                 if (status < 0)
 808                         return status;
 809
 810                 lpa = phy_read(phydev, MII_LPA);
 811                 if (lpa < 0)
 812                         return lpa;
 813
 814                 lpagb = phy_read(phydev, MII_STAT1000);
 815                 if (lpagb < 0)
 816                         return lpagb;
 817
 818                 adv = phy_read(phydev, MII_ADVERTISE);
 819                 if (adv < 0)
 820                         return adv;
 821
 822                 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
 823                                          mii_lpa_to_ethtool_lpa_t(lpa);
 824
 825                 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
 826                         phydev->duplex = DUPLEX_FULL;
 827                 else
 828                         phydev->duplex = DUPLEX_HALF;
 829
 830                 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
 831                 phydev->pause = phydev->asym_pause = 0;
 832
 833                 switch (status) {
 834                 case MII_M1011_PHY_STATUS_1000:
 835                         phydev->speed = SPEED_1000;
 836                         break;
 837
 838                 case MII_M1011_PHY_STATUS_100:
 839                         phydev->speed = SPEED_100;
 840                         break;
 841
 842                 default:
 843                         phydev->speed = SPEED_10;
 844                         break;
 845                 }
 846
 847                 if (phydev->duplex == DUPLEX_FULL) {
 848                         phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
 849                         phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
 850                 }
 851         } else {
 852                 int bmcr = phy_read(phydev, MII_BMCR);
 853
 854                 if (bmcr < 0)
 855                         return bmcr;
 856
 857                 if (bmcr & BMCR_FULLDPLX)
 858                         phydev->duplex = DUPLEX_FULL;
 859                 else
 860                         phydev->duplex = DUPLEX_HALF;
 861
 862                 if (bmcr & BMCR_SPEED1000)
 863                         phydev->speed = SPEED_1000;
 864                 else if (bmcr & BMCR_SPEED100)
 865                         phydev->speed = SPEED_100;
 866                 else
 867                         phydev->speed = SPEED_10;
 868
 869                 phydev->pause = phydev->asym_pause = 0;
 870                 phydev->lp_advertising = 0;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int marvell_aneg_done(struct phy_device *phydev)
 877 {
 878         int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
 879         return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
 880 }
 881
 882 static int m88e1121_did_interrupt(struct phy_device *phydev)
 883 {
 884         int imask;
 885
 886         imask = phy_read(phydev, MII_M1011_IEVENT);
 887
 888         if (imask & MII_M1011_IMASK_INIT)
 889                 return 1;
 890
 891         return 0;
 892 }
 893
 894 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 895 {
 896         wol->supported = WAKE_MAGIC;
 897         wol->wolopts = 0;
 898
 899         if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
 900                       MII_88E1318S_PHY_WOL_PAGE) < 0)
 901                 return;
 902
 903         if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
 904             MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
 905                 wol->wolopts |= WAKE_MAGIC;
 906
 907         if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
 908                 return;
 909 }
 910
 911 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 912 {
 913         int err, oldpage, temp;
 914
 915         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 916
 917         if (wol->wolopts & WAKE_MAGIC) {
 918                 /* Explicitly switch to page 0x00, just to be sure */
 919                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
 920                 if (err < 0)
 921                         return err;
 922
 923                 /* Enable the WOL interrupt */
 924                 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
 925                 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
 926                 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
 927                 if (err < 0)
 928                         return err;
 929
 930                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 931                                 MII_88E1318S_PHY_LED_PAGE);
 932                 if (err < 0)
 933                         return err;
 934
 935                 /* Setup LED[2] as interrupt pin (active low) */
 936                 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
 937                 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
 938                 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
 939                 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
 940                 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
 941                 if (err < 0)
 942                         return err;
 943
 944                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 945                                 MII_88E1318S_PHY_WOL_PAGE);
 946                 if (err < 0)
 947                         return err;
 948
 949                 /* Store the device address for the magic packet */
 950                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
 951                                 ((phydev->attached_dev->dev_addr[5] << 8) |
 952                                  phydev->attached_dev->dev_addr[4]));
 953                 if (err < 0)
 954                         return err;
 955                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
 956                                 ((phydev->attached_dev->dev_addr[3] << 8) |
 957                                  phydev->attached_dev->dev_addr[2]));
 958                 if (err < 0)
 959                         return err;
 960                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
 961                                 ((phydev->attached_dev->dev_addr[1] << 8) |
 962                                  phydev->attached_dev->dev_addr[0]));
 963                 if (err < 0)
 964                         return err;
 965
 966                 /* Clear WOL status and enable magic packet matching */
 967                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 968                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 969                 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 970                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 971                 if (err < 0)
 972                         return err;
 973         } else {
 974                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 975                                 MII_88E1318S_PHY_WOL_PAGE);
 976                 if (err < 0)
 977                         return err;
 978
 979                 /* Clear WOL status and disable magic packet matching */
 980                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 981                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 982                 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 983                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 984                 if (err < 0)
 985                         return err;
 986         }
 987
 988         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 989         if (err < 0)
 990                 return err;
 991
 992         return 0;
 993 }
 994
 995 static struct phy_driver marvell_drivers[] = {
 996         {
 997                 .phy_id = MARVELL_PHY_ID_88E1101,
 998                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 999                 .name = "Marvell 88E1101",
1000                 .features = PHY_GBIT_FEATURES,
1001                 .flags = PHY_HAS_INTERRUPT,
1002                 .config_aneg = &m88e1101_config_aneg,
1003                 .read_status = &genphy_read_status,
1004                 .ack_interrupt = &marvell_ack_interrupt,
1005                 .config_intr = &marvell_config_intr,
1006                 .resume = &genphy_resume,
1007                 .suspend = &genphy_suspend,
1008                 .driver = { .owner = THIS_MODULE },
1009         },
1010         {
1011                 .phy_id = MARVELL_PHY_ID_88E1112,
1012                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1013                 .name = "Marvell 88E1112",
1014                 .features = PHY_GBIT_FEATURES,
1015                 .flags = PHY_HAS_INTERRUPT,
1016                 .config_init = &m88e1111_config_init,
1017                 .config_aneg = &marvell_config_aneg,
1018                 .read_status = &genphy_read_status,
1019                 .ack_interrupt = &marvell_ack_interrupt,
1020                 .config_intr = &marvell_config_intr,
1021                 .resume = &genphy_resume,
1022                 .suspend = &genphy_suspend,
1023                 .driver = { .owner = THIS_MODULE },
1024         },
1025         {
1026                 .phy_id = MARVELL_PHY_ID_88E1111,
1027                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1028                 .name = "Marvell 88E1111",
1029                 .features = PHY_GBIT_FEATURES,
1030                 .flags = PHY_HAS_INTERRUPT,
1031                 .config_init = &m88e1111_config_init,
1032                 .config_aneg = &marvell_config_aneg,
1033                 .read_status = &marvell_read_status,
1034                 .ack_interrupt = &marvell_ack_interrupt,
1035                 .config_intr = &marvell_config_intr,
1036                 .resume = &genphy_resume,
1037                 .suspend = &genphy_suspend,
1038                 .driver = { .owner = THIS_MODULE },
1039         },
1040         {
1041                 .phy_id = MARVELL_PHY_ID_88E1118,
1042                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1043                 .name = "Marvell 88E1118",
1044                 .features = PHY_GBIT_FEATURES,
1045                 .flags = PHY_HAS_INTERRUPT,
1046                 .config_init = &m88e1118_config_init,
1047                 .config_aneg = &m88e1118_config_aneg,
1048                 .read_status = &genphy_read_status,
1049                 .ack_interrupt = &marvell_ack_interrupt,
1050                 .config_intr = &marvell_config_intr,
1051                 .resume = &genphy_resume,
1052                 .suspend = &genphy_suspend,
1053                 .driver = {.owner = THIS_MODULE,},
1054         },
1055         {
1056                 .phy_id = MARVELL_PHY_ID_88E1121R,
1057                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1058                 .name = "Marvell 88E1121R",
1059                 .features = PHY_GBIT_FEATURES,
1060                 .flags = PHY_HAS_INTERRUPT,
1061                 .config_aneg = &m88e1121_config_aneg,
1062                 .read_status = &marvell_read_status,
1063                 .ack_interrupt = &marvell_ack_interrupt,
1064                 .config_intr = &marvell_config_intr,
1065                 .did_interrupt = &m88e1121_did_interrupt,
1066                 .resume = &genphy_resume,
1067                 .suspend = &genphy_suspend,
1068                 .driver = { .owner = THIS_MODULE },
1069         },
1070         {
1071                 .phy_id = MARVELL_PHY_ID_88E1318S,
1072                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1073                 .name = "Marvell 88E1318S",
1074                 .features = PHY_GBIT_FEATURES,
1075                 .flags = PHY_HAS_INTERRUPT,
1076                 .config_aneg = &m88e1318_config_aneg,
1077                 .read_status = &marvell_read_status,
1078                 .ack_interrupt = &marvell_ack_interrupt,
1079                 .config_intr = &marvell_config_intr,
1080                 .did_interrupt = &m88e1121_did_interrupt,
1081                 .get_wol = &m88e1318_get_wol,
1082                 .set_wol = &m88e1318_set_wol,
1083                 .resume = &genphy_resume,
1084                 .suspend = &genphy_suspend,
1085                 .driver = { .owner = THIS_MODULE },
1086         },
1087         {
1088                 .phy_id = MARVELL_PHY_ID_88E1145,
1089                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1090                 .name = "Marvell 88E1145",
1091                 .features = PHY_GBIT_FEATURES,
1092                 .flags = PHY_HAS_INTERRUPT,
1093                 .config_init = &m88e1145_config_init,
1094                 .config_aneg = &m88e1101_config_aneg,
1095                 .read_status = &genphy_read_status,
1096                 .ack_interrupt = &marvell_ack_interrupt,
1097                 .config_intr = &marvell_config_intr,
1098                 .resume = &genphy_resume,
1099                 .suspend = &genphy_suspend,
1100                 .driver = { .owner = THIS_MODULE },
1101         },
1102         {
1103                 .phy_id = MARVELL_PHY_ID_88E1149R,
1104                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1105                 .name = "Marvell 88E1149R",
1106                 .features = PHY_GBIT_FEATURES,
1107                 .flags = PHY_HAS_INTERRUPT,
1108                 .config_init = &m88e1149_config_init,
1109                 .config_aneg = &m88e1118_config_aneg,
1110                 .read_status = &genphy_read_status,
1111                 .ack_interrupt = &marvell_ack_interrupt,
1112                 .config_intr = &marvell_config_intr,
1113                 .resume = &genphy_resume,
1114                 .suspend = &genphy_suspend,
1115                 .driver = { .owner = THIS_MODULE },
1116         },
1117         {
1118                 .phy_id = MARVELL_PHY_ID_88E1240,
1119                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1120                 .name = "Marvell 88E1240",
1121                 .features = PHY_GBIT_FEATURES,
1122                 .flags = PHY_HAS_INTERRUPT,
1123                 .config_init = &m88e1111_config_init,
1124                 .config_aneg = &marvell_config_aneg,
1125                 .read_status = &genphy_read_status,
1126                 .ack_interrupt = &marvell_ack_interrupt,
1127                 .config_intr = &marvell_config_intr,
1128                 .resume = &genphy_resume,
1129                 .suspend = &genphy_suspend,
1130                 .driver = { .owner = THIS_MODULE },
1131         },
1132         {
1133                 .phy_id = MARVELL_PHY_ID_88E1116R,
1134                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1135                 .name = "Marvell 88E1116R",
1136                 .features = PHY_GBIT_FEATURES,
1137                 .flags = PHY_HAS_INTERRUPT,
1138                 .config_init = &m88e1116r_config_init,
1139                 .config_aneg = &genphy_config_aneg,
1140                 .read_status = &genphy_read_status,
1141                 .ack_interrupt = &marvell_ack_interrupt,
1142                 .config_intr = &marvell_config_intr,
1143                 .resume = &genphy_resume,
1144                 .suspend = &genphy_suspend,
1145                 .driver = { .owner = THIS_MODULE },
1146         },
1147         {
1148                 .phy_id = MARVELL_PHY_ID_88E1510,
1149                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1150                 .name = "Marvell 88E1510",
1151                 .features = PHY_GBIT_FEATURES,
1152                 .flags = PHY_HAS_INTERRUPT,
1153                 .config_aneg = &m88e1510_config_aneg,
1154                 .read_status = &marvell_read_status,
1155                 .ack_interrupt = &marvell_ack_interrupt,
1156                 .config_intr = &marvell_config_intr,
1157                 .did_interrupt = &m88e1121_did_interrupt,
1158                 .resume = &genphy_resume,
1159                 .suspend = &genphy_suspend,
1160                 .driver = { .owner = THIS_MODULE },
1161         },
1162         {
1163                 .phy_id = MARVELL_PHY_ID_88E1540,
1164                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1165                 .name = "Marvell 88E1540",
1166                 .features = PHY_GBIT_FEATURES,
1167                 .flags = PHY_HAS_INTERRUPT,
1168                 .config_aneg = &m88e1510_config_aneg,
1169                 .read_status = &marvell_read_status,
1170                 .ack_interrupt = &marvell_ack_interrupt,
1171                 .config_intr = &marvell_config_intr,
1172                 .did_interrupt = &m88e1121_did_interrupt,
1173                 .resume = &genphy_resume,
1174                 .suspend = &genphy_suspend,
1175                 .driver = { .owner = THIS_MODULE },
1176         },
1177         {
1178                 .phy_id = MARVELL_PHY_ID_88E3016,
1179                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1180                 .name = "Marvell 88E3016",
1181                 .features = PHY_BASIC_FEATURES,
1182                 .flags = PHY_HAS_INTERRUPT,
1183                 .config_aneg = &genphy_config_aneg,
1184                 .config_init = &m88e3016_config_init,
1185                 .aneg_done = &marvell_aneg_done,
1186                 .read_status = &marvell_read_status,
1187                 .ack_interrupt = &marvell_ack_interrupt,
1188                 .config_intr = &marvell_config_intr,
1189                 .did_interrupt = &m88e1121_did_interrupt,
1190                 .resume = &genphy_resume,
1191                 .suspend = &genphy_suspend,
1192                 .driver = { .owner = THIS_MODULE },
1193         },
1194 };
1195
1196 module_phy_driver(marvell_drivers);
1197
1198 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1199         { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1200         { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1201         { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1202         { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1203         { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1204         { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1205         { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1206         { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1207         { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1208         { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1209         { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1210         { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
1211         { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1212         { }
1213 };
1214
1215 MODULE_DEVICE_TABLE(mdio, marvell_tbl);