1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for ICPlus PHYs
5 * Copyright (c) 2007 Freescale Semiconductor, Inc.
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/errno.h>
10 #include <linux/unistd.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/skbuff.h>
17 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/mii.h>
21 #include <linux/ethtool.h>
22 #include <linux/phy.h>
23 #include <linux/property.h>
27 #include <linux/uaccess.h>
29 MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
30 MODULE_AUTHOR("Michael Barkowski");
31 MODULE_LICENSE("GPL");
33 /* IP101A/G - IP1001 */
34 #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
35 #define IP1001_RXPHASE_SEL BIT(0) /* Add delay on RX_CLK */
36 #define IP1001_TXPHASE_SEL BIT(1) /* Add delay on TX_CLK */
37 #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
38 #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
39 #define IP101A_G_APS_ON BIT(1) /* IP101A/G APS Mode bit */
40 #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
41 #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */
42 #define IP101A_G_IRQ_ALL_MASK BIT(11) /* IRQ's inactive */
43 #define IP101A_G_IRQ_SPEED_CHANGE BIT(2)
44 #define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1)
45 #define IP101A_G_IRQ_LINK_CHANGE BIT(0)
47 #define IP101G_DIGITAL_IO_SPEC_CTRL 0x1d
48 #define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2)
50 /* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin
51 * (pin number 21). The hardware default is RXER (receive error) mode. But it
52 * can be configured to interrupt mode manually.
54 enum ip101gr_sel_intr32 {
55 IP101GR_SEL_INTR32_KEEP,
56 IP101GR_SEL_INTR32_INTR,
57 IP101GR_SEL_INTR32_RXER,
60 struct ip101a_g_phy_priv {
61 enum ip101gr_sel_intr32 sel_intr32;
64 static int ip175c_config_init(struct phy_device *phydev)
67 static int full_reset_performed;
69 if (full_reset_performed == 0) {
72 err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c);
76 /* ensure no bus delays overlap reset period */
77 err = mdiobus_read(phydev->mdio.bus, 30, 0);
79 /* data sheet specifies reset period is 2 msec */
82 /* enable IP175C mode */
83 err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c);
87 /* Set MII0 speed and duplex (in PHY mode) */
88 err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420);
92 /* reset switch ports */
93 for (i = 0; i < 5; i++) {
94 err = mdiobus_write(phydev->mdio.bus, i,
95 MII_BMCR, BMCR_RESET);
100 for (i = 0; i < 5; i++)
101 err = mdiobus_read(phydev->mdio.bus, i, MII_BMCR);
105 full_reset_performed = 1;
108 if (phydev->mdio.addr != 4) {
109 phydev->state = PHY_RUNNING;
110 phydev->speed = SPEED_100;
111 phydev->duplex = DUPLEX_FULL;
113 netif_carrier_on(phydev->attached_dev);
119 static int ip1xx_reset(struct phy_device *phydev)
123 /* Software Reset PHY */
124 bmcr = phy_read(phydev, MII_BMCR);
128 bmcr = phy_write(phydev, MII_BMCR, bmcr);
133 bmcr = phy_read(phydev, MII_BMCR);
136 } while (bmcr & BMCR_RESET);
141 static int ip1001_config_init(struct phy_device *phydev)
145 c = ip1xx_reset(phydev);
149 /* Enable Auto Power Saving mode */
150 c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
154 c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
158 if (phy_interface_is_rgmii(phydev)) {
160 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
164 c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
166 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
167 c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
168 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
169 c |= IP1001_RXPHASE_SEL;
170 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
171 c |= IP1001_TXPHASE_SEL;
173 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
181 static int ip175c_read_status(struct phy_device *phydev)
183 if (phydev->mdio.addr == 4) /* WAN port */
184 genphy_read_status(phydev);
186 /* Don't need to read status for switch ports */
187 phydev->irq = PHY_IGNORE_INTERRUPT;
192 static int ip175c_config_aneg(struct phy_device *phydev)
194 if (phydev->mdio.addr == 4) /* WAN port */
195 genphy_config_aneg(phydev);
200 static int ip101a_g_probe(struct phy_device *phydev)
202 struct device *dev = &phydev->mdio.dev;
203 struct ip101a_g_phy_priv *priv;
205 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
209 /* Both functions (RX error and interrupt status) are sharing the same
210 * pin on the 32-pin IP101GR, so this is an exclusive choice.
212 if (device_property_read_bool(dev, "icplus,select-rx-error") &&
213 device_property_read_bool(dev, "icplus,select-interrupt")) {
215 "RXER and INTR mode cannot be selected together\n");
219 if (device_property_read_bool(dev, "icplus,select-rx-error"))
220 priv->sel_intr32 = IP101GR_SEL_INTR32_RXER;
221 else if (device_property_read_bool(dev, "icplus,select-interrupt"))
222 priv->sel_intr32 = IP101GR_SEL_INTR32_INTR;
224 priv->sel_intr32 = IP101GR_SEL_INTR32_KEEP;
231 static int ip101a_g_config_init(struct phy_device *phydev)
233 struct ip101a_g_phy_priv *priv = phydev->priv;
236 c = ip1xx_reset(phydev);
240 /* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */
241 switch (priv->sel_intr32) {
242 case IP101GR_SEL_INTR32_RXER:
243 err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
244 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0);
249 case IP101GR_SEL_INTR32_INTR:
250 err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
251 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32,
252 IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32);
258 /* Don't touch IP101G_DIGITAL_IO_SPEC_CTRL because it's not
259 * documented on IP101A and it's not clear whether this would
261 * For the 32-pin IP101GR we simply keep the SEL_INTR32
262 * configuration as set by the bootloader when not configured
263 * to one of the special functions.
268 /* Enable Auto Power Saving mode */
269 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
270 c |= IP101A_G_APS_ON;
272 return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
275 static int ip101a_g_config_intr(struct phy_device *phydev)
279 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
280 /* INTR pin used: Speed/link/duplex will cause an interrupt */
281 val = IP101A_G_IRQ_PIN_USED;
283 val = IP101A_G_IRQ_ALL_MASK;
285 return phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val);
288 static int ip101a_g_did_interrupt(struct phy_device *phydev)
290 int val = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
295 return val & (IP101A_G_IRQ_SPEED_CHANGE |
296 IP101A_G_IRQ_DUPLEX_CHANGE |
297 IP101A_G_IRQ_LINK_CHANGE);
300 static int ip101a_g_ack_interrupt(struct phy_device *phydev)
302 int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
309 static struct phy_driver icplus_driver[] = {
311 .phy_id = 0x02430d80,
312 .name = "ICPlus IP175C",
313 .phy_id_mask = 0x0ffffff0,
314 /* PHY_BASIC_FEATURES */
315 .config_init = &ip175c_config_init,
316 .config_aneg = &ip175c_config_aneg,
317 .read_status = &ip175c_read_status,
318 .suspend = genphy_suspend,
319 .resume = genphy_resume,
321 .phy_id = 0x02430d90,
322 .name = "ICPlus IP1001",
323 .phy_id_mask = 0x0ffffff0,
324 /* PHY_GBIT_FEATURES */
325 .config_init = &ip1001_config_init,
326 .suspend = genphy_suspend,
327 .resume = genphy_resume,
329 .phy_id = 0x02430c54,
330 .name = "ICPlus IP101A/G",
331 .phy_id_mask = 0x0ffffff0,
332 /* PHY_BASIC_FEATURES */
333 .probe = ip101a_g_probe,
334 .config_intr = ip101a_g_config_intr,
335 .did_interrupt = ip101a_g_did_interrupt,
336 .ack_interrupt = ip101a_g_ack_interrupt,
337 .config_init = &ip101a_g_config_init,
338 .suspend = genphy_suspend,
339 .resume = genphy_resume,
342 module_phy_driver(icplus_driver);
344 static struct mdio_device_id __maybe_unused icplus_tbl[] = {
345 { 0x02430d80, 0x0ffffff0 },
346 { 0x02430d90, 0x0ffffff0 },
347 { 0x02430c54, 0x0ffffff0 },
351 MODULE_DEVICE_TABLE(mdio, icplus_tbl);