2 * Driver for the Texas Instruments DP83867 PHY
4 * Copyright (C) 2015 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/ethtool.h>
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/module.h>
21 #include <linux/phy.h>
23 #include <dt-bindings/net/ti-dp83867.h>
25 #define DP83867_PHY_ID 0x2000a231
26 #define DP83867_DEVADDR 0x1f
28 #define MII_DP83867_PHYCTRL 0x10
29 #define MII_DP83867_MICR 0x12
30 #define MII_DP83867_ISR 0x13
31 #define DP83867_CTRL 0x1f
32 #define DP83867_CFG3 0x1e
34 /* Extended Registers */
35 #define DP83867_RGMIICTL 0x0032
36 #define DP83867_STRAP_STS1 0x006E
37 #define DP83867_RGMIIDCTL 0x0086
39 #define DP83867_SW_RESET BIT(15)
40 #define DP83867_SW_RESTART BIT(14)
42 /* MICR Interrupt bits */
43 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
44 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
45 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
46 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
47 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
48 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
49 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
50 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
51 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
52 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
53 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
54 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
57 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
58 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
61 #define DP83867_STRAP_STS1_RESERVED BIT(11)
64 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
65 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
66 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
69 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
71 struct dp83867_private {
77 static int dp83867_ack_interrupt(struct phy_device *phydev)
79 int err = phy_read(phydev, MII_DP83867_ISR);
87 static int dp83867_config_intr(struct phy_device *phydev)
91 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
92 micr_status = phy_read(phydev, MII_DP83867_MICR);
97 (MII_DP83867_MICR_AN_ERR_INT_EN |
98 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
99 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
100 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
101 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
102 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
104 return phy_write(phydev, MII_DP83867_MICR, micr_status);
108 return phy_write(phydev, MII_DP83867_MICR, micr_status);
111 #ifdef CONFIG_OF_MDIO
112 static int dp83867_of_init(struct phy_device *phydev)
114 struct dp83867_private *dp83867 = phydev->priv;
115 struct device *dev = &phydev->mdio.dev;
116 struct device_node *of_node = dev->of_node;
122 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
123 &dp83867->rx_id_delay);
125 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
126 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
129 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
130 &dp83867->tx_id_delay);
132 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
133 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
136 return of_property_read_u32(of_node, "ti,fifo-depth",
137 &dp83867->fifo_depth);
140 static int dp83867_of_init(struct phy_device *phydev)
144 #endif /* CONFIG_OF_MDIO */
146 static int dp83867_config_init(struct phy_device *phydev)
148 struct dp83867_private *dp83867;
153 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
158 phydev->priv = dp83867;
159 ret = dp83867_of_init(phydev);
163 dp83867 = (struct dp83867_private *)phydev->priv;
166 if (phy_interface_is_rgmii(phydev)) {
167 val = phy_read(phydev, MII_DP83867_PHYCTRL);
170 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
171 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
173 /* The code below checks if "port mirroring" N/A MODE4 has been
174 * enabled during power on bootstrap.
176 * Such N/A mode enabled by mistake can put PHY IC in some
177 * internal testing mode and disable RGMII transmission.
179 * In this particular case one needs to check STRAP_STS1
180 * register's bit 11 (marked as RESERVED).
183 bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
185 if (bs & DP83867_STRAP_STS1_RESERVED)
186 val &= ~DP83867_PHYCR_RESERVED_MASK;
188 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
193 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
194 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
195 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
198 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
199 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
201 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
202 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
204 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
205 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
207 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
208 DP83867_DEVADDR, val);
210 delay = (dp83867->rx_id_delay |
211 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
213 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
214 DP83867_DEVADDR, delay);
217 /* Enable Interrupt output INT_OE in CFG3 register */
218 if (phy_interrupt_is_valid(phydev)) {
219 val = phy_read(phydev, DP83867_CFG3);
221 phy_write(phydev, DP83867_CFG3, val);
227 static int dp83867_phy_reset(struct phy_device *phydev)
231 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
235 return dp83867_config_init(phydev);
238 static struct phy_driver dp83867_driver[] = {
240 .phy_id = DP83867_PHY_ID,
241 .phy_id_mask = 0xfffffff0,
242 .name = "TI DP83867",
243 .features = PHY_GBIT_FEATURES,
244 .flags = PHY_HAS_INTERRUPT,
246 .config_init = dp83867_config_init,
247 .soft_reset = dp83867_phy_reset,
250 .ack_interrupt = dp83867_ack_interrupt,
251 .config_intr = dp83867_config_intr,
253 .config_aneg = genphy_config_aneg,
254 .read_status = genphy_read_status,
255 .suspend = genphy_suspend,
256 .resume = genphy_resume,
259 module_phy_driver(dp83867_driver);
261 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
262 { DP83867_PHY_ID, 0xfffffff0 },
266 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
268 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
269 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
270 MODULE_LICENSE("GPL");