drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  */
   6
   7 #include <linux/ethtool.h>
   8 #include <linux/kernel.h>
   9 #include <linux/mii.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/delay.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/bitfield.h>
  17
  18 #include <dt-bindings/net/ti-dp83867.h>
  19
  20 #define DP83867_PHY_ID          0x2000a231
  21 #define DP83867_DEVADDR         0x1f
  22
  23 #define MII_DP83867_PHYCTRL     0x10
  24 #define MII_DP83867_PHYSTS      0x11
  25 #define MII_DP83867_MICR        0x12
  26 #define MII_DP83867_ISR         0x13
  27 #define DP83867_CFG2            0x14
  28 #define DP83867_CFG3            0x1e
  29 #define DP83867_CTRL            0x1f
  30
  31 /* Extended Registers */
  32 #define DP83867_FLD_THR_CFG     0x002e
  33 #define DP83867_CFG4            0x0031
  34 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  35 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  36 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  37 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  38 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  39
  40 #define DP83867_RGMIICTL        0x0032
  41 #define DP83867_STRAP_STS1      0x006E
  42 #define DP83867_STRAP_STS2      0x006f
  43 #define DP83867_RGMIIDCTL       0x0086
  44 #define DP83867_RXFCFG          0x0134
  45 #define DP83867_RXFPMD1 0x0136
  46 #define DP83867_RXFPMD2 0x0137
  47 #define DP83867_RXFPMD3 0x0138
  48 #define DP83867_RXFSOP1 0x0139
  49 #define DP83867_RXFSOP2 0x013A
  50 #define DP83867_RXFSOP3 0x013B
  51 #define DP83867_IO_MUX_CFG      0x0170
  52 #define DP83867_SGMIICTL        0x00D3
  53 #define DP83867_10M_SGMII_CFG   0x016F
  54 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  55
  56 #define DP83867_SW_RESET        BIT(15)
  57 #define DP83867_SW_RESTART      BIT(14)
  58
  59 /* MICR Interrupt bits */
  60 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  61 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  62 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  63 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  64 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  65 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  66 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  67 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  68 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  69 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  70 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  71 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  72
  73 /* RGMIICTL bits */
  74 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  75 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  76
  77 /* SGMIICTL bits */
  78 #define DP83867_SGMII_TYPE              BIT(14)
  79
  80 /* RXFCFG bits*/
  81 #define DP83867_WOL_MAGIC_EN            BIT(0)
  82 #define DP83867_WOL_BCAST_EN            BIT(2)
  83 #define DP83867_WOL_UCAST_EN            BIT(4)
  84 #define DP83867_WOL_SEC_EN              BIT(5)
  85 #define DP83867_WOL_ENH_MAC             BIT(7)
  86
  87 /* STRAP_STS1 bits */
  88 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  89
  90 /* STRAP_STS2 bits */
  91 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  93 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  95 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  96 #define DP83867_STRAP_STS2_STRAP_FLD            BIT(10)
  97
  98 /* PHY CTRL bits */
  99 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT       14
 100 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT       12
 101 #define DP83867_PHYCR_FIFO_DEPTH_MAX            0x03
 102 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK        GENMASK(15, 14)
 103 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK        GENMASK(13, 12)
 104 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
 105 #define DP83867_PHYCR_FORCE_LINK_GOOD           BIT(10)
 106
 107 /* RGMIIDCTL bits */
 108 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
 109 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
 110 #define DP83867_RGMII_TX_CLK_DELAY_INV  (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
 111 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
 112 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT        0
 113 #define DP83867_RGMII_RX_CLK_DELAY_INV  (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
 114
 115 /* IO_MUX_CFG bits */
 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
 117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
 118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 119 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 120 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
 121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 122
 123 /* PHY STS bits */
 124 #define DP83867_PHYSTS_1000                     BIT(15)
 125 #define DP83867_PHYSTS_100                      BIT(14)
 126 #define DP83867_PHYSTS_DUPLEX                   BIT(13)
 127 #define DP83867_PHYSTS_LINK                     BIT(10)
 128
 129 /* CFG2 bits */
 130 #define DP83867_DOWNSHIFT_EN            (BIT(8) | BIT(9))
 131 #define DP83867_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
 132 #define DP83867_DOWNSHIFT_1_COUNT_VAL   0
 133 #define DP83867_DOWNSHIFT_2_COUNT_VAL   1
 134 #define DP83867_DOWNSHIFT_4_COUNT_VAL   2
 135 #define DP83867_DOWNSHIFT_8_COUNT_VAL   3
 136 #define DP83867_DOWNSHIFT_1_COUNT       1
 137 #define DP83867_DOWNSHIFT_2_COUNT       2
 138 #define DP83867_DOWNSHIFT_4_COUNT       4
 139 #define DP83867_DOWNSHIFT_8_COUNT       8
 140 #define DP83867_SGMII_AUTONEG_EN        BIT(7)
 141
 142 /* CFG3 bits */
 143 #define DP83867_CFG3_INT_OE                     BIT(7)
 144 #define DP83867_CFG3_ROBUST_AUTO_MDIX           BIT(9)
 145
 146 /* CFG4 bits */
 147 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
 148
 149 /* FLD_THR_CFG */
 150 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK        0x7
 151
 152 enum {
 153         DP83867_PORT_MIRROING_KEEP,
 154         DP83867_PORT_MIRROING_EN,
 155         DP83867_PORT_MIRROING_DIS,
 156 };
 157
 158 struct dp83867_private {
 159         u32 rx_id_delay;
 160         u32 tx_id_delay;
 161         u32 tx_fifo_depth;
 162         u32 rx_fifo_depth;
 163         int io_impedance;
 164         int port_mirroring;
 165         bool rxctrl_strap_quirk;
 166         bool set_clk_output;
 167         u32 clk_output_sel;
 168         bool sgmii_ref_clk_en;
 169 };
 170
 171 static int dp83867_ack_interrupt(struct phy_device *phydev)
 172 {
 173         int err = phy_read(phydev, MII_DP83867_ISR);
 174
 175         if (err < 0)
 176                 return err;
 177
 178         return 0;
 179 }
 180
 181 static int dp83867_set_wol(struct phy_device *phydev,
 182                            struct ethtool_wolinfo *wol)
 183 {
 184         struct net_device *ndev = phydev->attached_dev;
 185         u16 val_rxcfg, val_micr;
 186         u8 *mac;
 187
 188         val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 189         val_micr = phy_read(phydev, MII_DP83867_MICR);
 190
 191         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
 192                             WAKE_BCAST)) {
 193                 val_rxcfg |= DP83867_WOL_ENH_MAC;
 194                 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
 195
 196                 if (wol->wolopts & WAKE_MAGIC) {
 197                         mac = (u8 *)ndev->dev_addr;
 198
 199                         if (!is_valid_ether_addr(mac))
 200                                 return -EINVAL;
 201
 202                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
 203                                       (mac[1] << 8 | mac[0]));
 204                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
 205                                       (mac[3] << 8 | mac[2]));
 206                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
 207                                       (mac[5] << 8 | mac[4]));
 208
 209                         val_rxcfg |= DP83867_WOL_MAGIC_EN;
 210                 } else {
 211                         val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
 212                 }
 213
 214                 if (wol->wolopts & WAKE_MAGICSECURE) {
 215                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 216                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 217                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
 218                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 219                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
 220                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 221
 222                         val_rxcfg |= DP83867_WOL_SEC_EN;
 223                 } else {
 224                         val_rxcfg &= ~DP83867_WOL_SEC_EN;
 225                 }
 226
 227                 if (wol->wolopts & WAKE_UCAST)
 228                         val_rxcfg |= DP83867_WOL_UCAST_EN;
 229                 else
 230                         val_rxcfg &= ~DP83867_WOL_UCAST_EN;
 231
 232                 if (wol->wolopts & WAKE_BCAST)
 233                         val_rxcfg |= DP83867_WOL_BCAST_EN;
 234                 else
 235                         val_rxcfg &= ~DP83867_WOL_BCAST_EN;
 236         } else {
 237                 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
 238                 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
 239         }
 240
 241         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
 242         phy_write(phydev, MII_DP83867_MICR, val_micr);
 243
 244         return 0;
 245 }
 246
 247 static void dp83867_get_wol(struct phy_device *phydev,
 248                             struct ethtool_wolinfo *wol)
 249 {
 250         u16 value, sopass_val;
 251
 252         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
 253                         WAKE_MAGICSECURE);
 254         wol->wolopts = 0;
 255
 256         value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 257
 258         if (value & DP83867_WOL_UCAST_EN)
 259                 wol->wolopts |= WAKE_UCAST;
 260
 261         if (value & DP83867_WOL_BCAST_EN)
 262                 wol->wolopts |= WAKE_BCAST;
 263
 264         if (value & DP83867_WOL_MAGIC_EN)
 265                 wol->wolopts |= WAKE_MAGIC;
 266
 267         if (value & DP83867_WOL_SEC_EN) {
 268                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 269                                           DP83867_RXFSOP1);
 270                 wol->sopass[0] = (sopass_val & 0xff);
 271                 wol->sopass[1] = (sopass_val >> 8);
 272
 273                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 274                                           DP83867_RXFSOP2);
 275                 wol->sopass[2] = (sopass_val & 0xff);
 276                 wol->sopass[3] = (sopass_val >> 8);
 277
 278                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 279                                           DP83867_RXFSOP3);
 280                 wol->sopass[4] = (sopass_val & 0xff);
 281                 wol->sopass[5] = (sopass_val >> 8);
 282
 283                 wol->wolopts |= WAKE_MAGICSECURE;
 284         }
 285
 286         if (!(value & DP83867_WOL_ENH_MAC))
 287                 wol->wolopts = 0;
 288 }
 289
 290 static int dp83867_config_intr(struct phy_device *phydev)
 291 {
 292         int micr_status, err;
 293
 294         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 295                 err = dp83867_ack_interrupt(phydev);
 296                 if (err)
 297                         return err;
 298
 299                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 300                 if (micr_status < 0)
 301                         return micr_status;
 302
 303                 micr_status |=
 304                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 305                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 306                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 307                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 308                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 309                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 310
 311                 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
 312         } else {
 313                 micr_status = 0x0;
 314                 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
 315                 if (err)
 316                         return err;
 317
 318                 err = dp83867_ack_interrupt(phydev);
 319         }
 320
 321         return err;
 322 }
 323
 324 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
 325 {
 326         int irq_status, irq_enabled;
 327
 328         irq_status = phy_read(phydev, MII_DP83867_ISR);
 329         if (irq_status < 0) {
 330                 phy_error(phydev);
 331                 return IRQ_NONE;
 332         }
 333
 334         irq_enabled = phy_read(phydev, MII_DP83867_MICR);
 335         if (irq_enabled < 0) {
 336                 phy_error(phydev);
 337                 return IRQ_NONE;
 338         }
 339
 340         if (!(irq_status & irq_enabled))
 341                 return IRQ_NONE;
 342
 343         phy_trigger_machine(phydev);
 344
 345         return IRQ_HANDLED;
 346 }
 347
 348 static int dp83867_read_status(struct phy_device *phydev)
 349 {
 350         int status = phy_read(phydev, MII_DP83867_PHYSTS);
 351         int ret;
 352
 353         ret = genphy_read_status(phydev);
 354         if (ret)
 355                 return ret;
 356
 357         if (status < 0)
 358                 return status;
 359
 360         if (status & DP83867_PHYSTS_DUPLEX)
 361                 phydev->duplex = DUPLEX_FULL;
 362         else
 363                 phydev->duplex = DUPLEX_HALF;
 364
 365         if (status & DP83867_PHYSTS_1000)
 366                 phydev->speed = SPEED_1000;
 367         else if (status & DP83867_PHYSTS_100)
 368                 phydev->speed = SPEED_100;
 369         else
 370                 phydev->speed = SPEED_10;
 371
 372         return 0;
 373 }
 374
 375 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
 376 {
 377         int val, cnt, enable, count;
 378
 379         val = phy_read(phydev, DP83867_CFG2);
 380         if (val < 0)
 381                 return val;
 382
 383         enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
 384         cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
 385
 386         switch (cnt) {
 387         case DP83867_DOWNSHIFT_1_COUNT_VAL:
 388                 count = DP83867_DOWNSHIFT_1_COUNT;
 389                 break;
 390         case DP83867_DOWNSHIFT_2_COUNT_VAL:
 391                 count = DP83867_DOWNSHIFT_2_COUNT;
 392                 break;
 393         case DP83867_DOWNSHIFT_4_COUNT_VAL:
 394                 count = DP83867_DOWNSHIFT_4_COUNT;
 395                 break;
 396         case DP83867_DOWNSHIFT_8_COUNT_VAL:
 397                 count = DP83867_DOWNSHIFT_8_COUNT;
 398                 break;
 399         default:
 400                 return -EINVAL;
 401         }
 402
 403         *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
 404
 405         return 0;
 406 }
 407
 408 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
 409 {
 410         int val, count;
 411
 412         if (cnt > DP83867_DOWNSHIFT_8_COUNT)
 413                 return -E2BIG;
 414
 415         if (!cnt)
 416                 return phy_clear_bits(phydev, DP83867_CFG2,
 417                                       DP83867_DOWNSHIFT_EN);
 418
 419         switch (cnt) {
 420         case DP83867_DOWNSHIFT_1_COUNT:
 421                 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
 422                 break;
 423         case DP83867_DOWNSHIFT_2_COUNT:
 424                 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
 425                 break;
 426         case DP83867_DOWNSHIFT_4_COUNT:
 427                 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
 428                 break;
 429         case DP83867_DOWNSHIFT_8_COUNT:
 430                 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
 431                 break;
 432         default:
 433                 phydev_err(phydev,
 434                            "Downshift count must be 1, 2, 4 or 8\n");
 435                 return -EINVAL;
 436         }
 437
 438         val = DP83867_DOWNSHIFT_EN;
 439         val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
 440
 441         return phy_modify(phydev, DP83867_CFG2,
 442                           DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
 443                           val);
 444 }
 445
 446 static int dp83867_get_tunable(struct phy_device *phydev,
 447                                struct ethtool_tunable *tuna, void *data)
 448 {
 449         switch (tuna->id) {
 450         case ETHTOOL_PHY_DOWNSHIFT:
 451                 return dp83867_get_downshift(phydev, data);
 452         default:
 453                 return -EOPNOTSUPP;
 454         }
 455 }
 456
 457 static int dp83867_set_tunable(struct phy_device *phydev,
 458                                struct ethtool_tunable *tuna, const void *data)
 459 {
 460         switch (tuna->id) {
 461         case ETHTOOL_PHY_DOWNSHIFT:
 462                 return dp83867_set_downshift(phydev, *(const u8 *)data);
 463         default:
 464                 return -EOPNOTSUPP;
 465         }
 466 }
 467
 468 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 469 {
 470         struct dp83867_private *dp83867 =
 471                 (struct dp83867_private *)phydev->priv;
 472
 473         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 474                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 475                                  DP83867_CFG4_PORT_MIRROR_EN);
 476         else
 477                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 478                                    DP83867_CFG4_PORT_MIRROR_EN);
 479         return 0;
 480 }
 481
 482 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
 483 {
 484         struct dp83867_private *dp83867 = phydev->priv;
 485
 486         /* Existing behavior was to use default pin strapping delay in rgmii
 487          * mode, but rgmii should have meant no delay.  Warn existing users.
 488          */
 489         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 490                 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 491                                              DP83867_STRAP_STS2);
 492                 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 493                                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 494                 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 495                                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 496
 497                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 498                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 499                         phydev_warn(phydev,
 500                                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 501                                     "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
 502                                     txskew, rxskew);
 503         }
 504
 505         /* RX delay *must* be specified if internal delay of RX is used. */
 506         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 507              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
 508              dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
 509                 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
 510                 return -EINVAL;
 511         }
 512
 513         /* TX delay *must* be specified if internal delay of TX is used. */
 514         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 515              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
 516              dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
 517                 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
 518                 return -EINVAL;
 519         }
 520
 521         return 0;
 522 }
 523
 524 #if IS_ENABLED(CONFIG_OF_MDIO)
 525 static int dp83867_of_init(struct phy_device *phydev)
 526 {
 527         struct dp83867_private *dp83867 = phydev->priv;
 528         struct device *dev = &phydev->mdio.dev;
 529         struct device_node *of_node = dev->of_node;
 530         int ret;
 531
 532         if (!of_node)
 533                 return -ENODEV;
 534
 535         /* Optional configuration */
 536         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 537                                    &dp83867->clk_output_sel);
 538         /* If not set, keep default */
 539         if (!ret) {
 540                 dp83867->set_clk_output = true;
 541                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 542                  * DP83867_CLK_O_SEL_OFF.
 543                  */
 544                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 545                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 546                         phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
 547                                    dp83867->clk_output_sel);
 548                         return -EINVAL;
 549                 }
 550         }
 551
 552         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 553                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 554         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 555                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 556         else
 557                 dp83867->io_impedance = -1; /* leave at default */
 558
 559         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 560                                                             "ti,dp83867-rxctrl-strap-quirk");
 561
 562         dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
 563                                                           "ti,sgmii-ref-clock-output-enable");
 564
 565         dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
 566         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 567                                    &dp83867->rx_id_delay);
 568         if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 569                 phydev_err(phydev,
 570                            "ti,rx-internal-delay value of %u out of range\n",
 571                            dp83867->rx_id_delay);
 572                 return -EINVAL;
 573         }
 574
 575         dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
 576         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 577                                    &dp83867->tx_id_delay);
 578         if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 579                 phydev_err(phydev,
 580                            "ti,tx-internal-delay value of %u out of range\n",
 581                            dp83867->tx_id_delay);
 582                 return -EINVAL;
 583         }
 584
 585         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 586                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 587
 588         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 589                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 590
 591         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 592                                    &dp83867->tx_fifo_depth);
 593         if (ret) {
 594                 ret = of_property_read_u32(of_node, "tx-fifo-depth",
 595                                            &dp83867->tx_fifo_depth);
 596                 if (ret)
 597                         dp83867->tx_fifo_depth =
 598                                         DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 599         }
 600
 601         if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 602                 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
 603                            dp83867->tx_fifo_depth);
 604                 return -EINVAL;
 605         }
 606
 607         ret = of_property_read_u32(of_node, "rx-fifo-depth",
 608                                    &dp83867->rx_fifo_depth);
 609         if (ret)
 610                 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 611
 612         if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 613                 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
 614                            dp83867->rx_fifo_depth);
 615                 return -EINVAL;
 616         }
 617
 618         return 0;
 619 }
 620 #else
 621 static int dp83867_of_init(struct phy_device *phydev)
 622 {
 623         return 0;
 624 }
 625 #endif /* CONFIG_OF_MDIO */
 626
 627 static int dp83867_probe(struct phy_device *phydev)
 628 {
 629         struct dp83867_private *dp83867;
 630
 631         dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 632                                GFP_KERNEL);
 633         if (!dp83867)
 634                 return -ENOMEM;
 635
 636         phydev->priv = dp83867;
 637
 638         return dp83867_of_init(phydev);
 639 }
 640
 641 static int dp83867_config_init(struct phy_device *phydev)
 642 {
 643         struct dp83867_private *dp83867 = phydev->priv;
 644         int ret, val, bs;
 645         u16 delay;
 646
 647         /* Force speed optimization for the PHY even if it strapped */
 648         ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
 649                          DP83867_DOWNSHIFT_EN);
 650         if (ret)
 651                 return ret;
 652
 653         ret = dp83867_verify_rgmii_cfg(phydev);
 654         if (ret)
 655                 return ret;
 656
 657         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 658         if (dp83867->rxctrl_strap_quirk)
 659                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 660                                    BIT(7));
 661
 662         bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
 663         if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
 664                 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
 665                  * be set to 0x2. This may causes the PHY link to be unstable -
 666                  * the default value 0x1 need to be restored.
 667                  */
 668                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 669                                      DP83867_FLD_THR_CFG,
 670                                      DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
 671                                      0x1);
 672                 if (ret)
 673                         return ret;
 674         }
 675
 676         if (phy_interface_is_rgmii(phydev) ||
 677             phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 678                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 679                 if (val < 0)
 680                         return val;
 681
 682                 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
 683                 val |= (dp83867->tx_fifo_depth <<
 684                         DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
 685
 686                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 687                         val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
 688                         val |= (dp83867->rx_fifo_depth <<
 689                                 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
 690                 }
 691
 692                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 693                 if (ret)
 694                         return ret;
 695         }
 696
 697         if (phy_interface_is_rgmii(phydev)) {
 698                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 699                 if (val < 0)
 700                         return val;
 701
 702                 /* The code below checks if "port mirroring" N/A MODE4 has been
 703                  * enabled during power on bootstrap.
 704                  *
 705                  * Such N/A mode enabled by mistake can put PHY IC in some
 706                  * internal testing mode and disable RGMII transmission.
 707                  *
 708                  * In this particular case one needs to check STRAP_STS1
 709                  * register's bit 11 (marked as RESERVED).
 710                  */
 711
 712                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 713                 if (bs & DP83867_STRAP_STS1_RESERVED)
 714                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 715
 716                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 717                 if (ret)
 718                         return ret;
 719
 720                 /* If rgmii mode with no internal delay is selected, we do NOT use
 721                  * aligned mode as one might expect.  Instead we use the PHY's default
 722                  * based on pin strapping.  And the "mode 0" default is to *use*
 723                  * internal delay with a value of 7 (2.00 ns).
 724                  *
 725                  * Set up RGMII delays
 726                  */
 727                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 728
 729                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 730                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 731                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 732
 733                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 734                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 735
 736                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 737                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 738
 739                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 740
 741                 delay = 0;
 742                 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
 743                         delay |= dp83867->rx_id_delay;
 744                 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
 745                         delay |= dp83867->tx_id_delay <<
 746                                  DP83867_RGMII_TX_CLK_DELAY_SHIFT;
 747
 748                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 749                               delay);
 750         }
 751
 752         /* If specified, set io impedance */
 753         if (dp83867->io_impedance >= 0)
 754                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 755                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 756                                dp83867->io_impedance);
 757
 758         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 759                 /* For support SPEED_10 in SGMII mode
 760                  * DP83867_10M_SGMII_RATE_ADAPT bit
 761                  * has to be cleared by software. That
 762                  * does not affect SPEED_100 and
 763                  * SPEED_1000.
 764                  */
 765                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 766                                      DP83867_10M_SGMII_CFG,
 767                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 768                                      0);
 769                 if (ret)
 770                         return ret;
 771
 772                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 773                  * are 01). That is not enough to finalize autoneg on some
 774                  * devices. Increase this timer duration to maximum 16ms.
 775                  */
 776                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 777                                      DP83867_CFG4,
 778                                      DP83867_CFG4_SGMII_ANEG_MASK,
 779                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 780
 781                 if (ret)
 782                         return ret;
 783
 784                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
 785                 /* SGMII type is set to 4-wire mode by default.
 786                  * If we place appropriate property in dts (see above)
 787                  * switch on 6-wire mode.
 788                  */
 789                 if (dp83867->sgmii_ref_clk_en)
 790                         val |= DP83867_SGMII_TYPE;
 791                 else
 792                         val &= ~DP83867_SGMII_TYPE;
 793                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
 794         }
 795
 796         val = phy_read(phydev, DP83867_CFG3);
 797         /* Enable Interrupt output INT_OE in CFG3 register */
 798         if (phy_interrupt_is_valid(phydev))
 799                 val |= DP83867_CFG3_INT_OE;
 800
 801         val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
 802         phy_write(phydev, DP83867_CFG3, val);
 803
 804         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 805                 dp83867_config_port_mirroring(phydev);
 806
 807         /* Clock output selection if muxing property is set */
 808         if (dp83867->set_clk_output) {
 809                 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 810
 811                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 812                         val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 813                 } else {
 814                         mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 815                         val = dp83867->clk_output_sel <<
 816                               DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 817                 }
 818
 819                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 820                                mask, val);
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int dp83867_phy_reset(struct phy_device *phydev)
 827 {
 828         int err;
 829
 830         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
 831         if (err < 0)
 832                 return err;
 833
 834         usleep_range(10, 20);
 835
 836         return phy_modify(phydev, MII_DP83867_PHYCTRL,
 837                          DP83867_PHYCR_FORCE_LINK_GOOD, 0);
 838 }
 839
 840 static void dp83867_link_change_notify(struct phy_device *phydev)
 841 {
 842         /* There is a limitation in DP83867 PHY device where SGMII AN is
 843          * only triggered once after the device is booted up. Even after the
 844          * PHY TPI is down and up again, SGMII AN is not triggered and
 845          * hence no new in-band message from PHY to MAC side SGMII.
 846          * This could cause an issue during power up, when PHY is up prior
 847          * to MAC. At this condition, once MAC side SGMII is up, MAC side
 848          * SGMII wouldn`t receive new in-band message from TI PHY with
 849          * correct link status, speed and duplex info.
 850          * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
 851          * whenever there is a link change.
 852          */
 853         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 854                 int val = 0;
 855
 856                 val = phy_clear_bits(phydev, DP83867_CFG2,
 857                                      DP83867_SGMII_AUTONEG_EN);
 858                 if (val < 0)
 859                         return;
 860
 861                 phy_set_bits(phydev, DP83867_CFG2,
 862                              DP83867_SGMII_AUTONEG_EN);
 863         }
 864 }
 865
 866 static struct phy_driver dp83867_driver[] = {
 867         {
 868                 .phy_id         = DP83867_PHY_ID,
 869                 .phy_id_mask    = 0xfffffff0,
 870                 .name           = "TI DP83867",
 871                 /* PHY_GBIT_FEATURES */
 872
 873                 .probe          = dp83867_probe,
 874                 .config_init    = dp83867_config_init,
 875                 .soft_reset     = dp83867_phy_reset,
 876
 877                 .read_status    = dp83867_read_status,
 878                 .get_tunable    = dp83867_get_tunable,
 879                 .set_tunable    = dp83867_set_tunable,
 880
 881                 .get_wol        = dp83867_get_wol,
 882                 .set_wol        = dp83867_set_wol,
 883
 884                 /* IRQ related */
 885                 .config_intr    = dp83867_config_intr,
 886                 .handle_interrupt = dp83867_handle_interrupt,
 887
 888                 .suspend        = genphy_suspend,
 889                 .resume         = genphy_resume,
 890
 891                 .link_change_notify = dp83867_link_change_notify,
 892         },
 893 };
 894 module_phy_driver(dp83867_driver);
 895
 896 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 897         { DP83867_PHY_ID, 0xfffffff0 },
 898         { }
 899 };
 900
 901 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 902
 903 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 904 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 905 MODULE_LICENSE("GPL v2");