drivers/net/phy/dp83867.c

   1 /*
   2  * Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/ethtool.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mii.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/phy.h>
  22
  23 #include <dt-bindings/net/ti-dp83867.h>
  24
  25 #define DP83867_PHY_ID          0x2000a231
  26 #define DP83867_DEVADDR         0x1f
  27
  28 #define MII_DP83867_PHYCTRL     0x10
  29 #define MII_DP83867_MICR        0x12
  30 #define MII_DP83867_ISR         0x13
  31 #define DP83867_CTRL            0x1f
  32 #define DP83867_CFG3            0x1e
  33
  34 /* Extended Registers */
  35 #define DP83867_CFG4            0x0031
  36 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  37 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  38 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  39 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  40 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  41
  42 #define DP83867_RGMIICTL        0x0032
  43 #define DP83867_STRAP_STS1      0x006E
  44 #define DP83867_RGMIIDCTL       0x0086
  45 #define DP83867_IO_MUX_CFG      0x0170
  46 #define DP83867_10M_SGMII_CFG   0x016F
  47 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  48
  49 #define DP83867_SW_RESET        BIT(15)
  50 #define DP83867_SW_RESTART      BIT(14)
  51
  52 /* MICR Interrupt bits */
  53 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  54 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  55 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  56 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  57 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  58 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  59 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  60 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  61 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  62 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  63 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  64 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  65
  66 /* RGMIICTL bits */
  67 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  68 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  69
  70 /* STRAP_STS1 bits */
  71 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  72
  73 /* PHY CTRL bits */
  74 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  75 #define DP83867_PHYCR_FIFO_DEPTH_MASK           (3 << 14)
  76 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
  77
  78 /* RGMIIDCTL bits */
  79 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  80
  81 /* IO_MUX_CFG bits */
  82 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  83
  84 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  85 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  86 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
  87 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  88
  89 /* CFG3 bits */
  90 #define DP83867_CFG3_INT_OE                     BIT(7)
  91 #define DP83867_CFG3_ROBUST_AUTO_MDIX           BIT(9)
  92
  93 /* CFG4 bits */
  94 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
  95
  96 enum {
  97         DP83867_PORT_MIRROING_KEEP,
  98         DP83867_PORT_MIRROING_EN,
  99         DP83867_PORT_MIRROING_DIS,
 100 };
 101
 102 struct dp83867_private {
 103         int rx_id_delay;
 104         int tx_id_delay;
 105         int fifo_depth;
 106         int io_impedance;
 107         int port_mirroring;
 108         bool rxctrl_strap_quirk;
 109         int clk_output_sel;
 110 };
 111
 112 static int dp83867_ack_interrupt(struct phy_device *phydev)
 113 {
 114         int err = phy_read(phydev, MII_DP83867_ISR);
 115
 116         if (err < 0)
 117                 return err;
 118
 119         return 0;
 120 }
 121
 122 static int dp83867_config_intr(struct phy_device *phydev)
 123 {
 124         int micr_status;
 125
 126         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 127                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 128                 if (micr_status < 0)
 129                         return micr_status;
 130
 131                 micr_status |=
 132                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 133                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 134                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 135                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 136                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 137                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 138
 139                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 140         }
 141
 142         micr_status = 0x0;
 143         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 144 }
 145
 146 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 147 {
 148         struct dp83867_private *dp83867 =
 149                 (struct dp83867_private *)phydev->priv;
 150         u16 val;
 151
 152         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 153
 154         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 155                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 156         else
 157                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 158
 159         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 160
 161         return 0;
 162 }
 163
 164 #ifdef CONFIG_OF_MDIO
 165 static int dp83867_of_init(struct phy_device *phydev)
 166 {
 167         struct dp83867_private *dp83867 = phydev->priv;
 168         struct device *dev = &phydev->mdio.dev;
 169         struct device_node *of_node = dev->of_node;
 170         int ret;
 171
 172         if (!of_node)
 173                 return -ENODEV;
 174
 175         dp83867->io_impedance = -EINVAL;
 176
 177         /* Optional configuration */
 178         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 179                                    &dp83867->clk_output_sel);
 180         if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
 181                 /* Keep the default value if ti,clk-output-sel is not set
 182                  * or too high
 183                  */
 184                 dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
 185
 186         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 187                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 188         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 189                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 190
 191         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 192                                         "ti,dp83867-rxctrl-strap-quirk");
 193
 194         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 195                                    &dp83867->rx_id_delay);
 196         if (ret &&
 197             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 198              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 199                 return ret;
 200
 201         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 202                                    &dp83867->tx_id_delay);
 203         if (ret &&
 204             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 205              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 206                 return ret;
 207
 208         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 209                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 210
 211         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 212                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 213
 214         return of_property_read_u32(of_node, "ti,fifo-depth",
 215                                    &dp83867->fifo_depth);
 216 }
 217 #else
 218 static int dp83867_of_init(struct phy_device *phydev)
 219 {
 220         return 0;
 221 }
 222 #endif /* CONFIG_OF_MDIO */
 223
 224 static int dp83867_config_init(struct phy_device *phydev)
 225 {
 226         struct dp83867_private *dp83867;
 227         int ret, val, bs;
 228         u16 delay;
 229
 230         if (!phydev->priv) {
 231                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 232                                        GFP_KERNEL);
 233                 if (!dp83867)
 234                         return -ENOMEM;
 235
 236                 phydev->priv = dp83867;
 237                 ret = dp83867_of_init(phydev);
 238                 if (ret)
 239                         return ret;
 240         } else {
 241                 dp83867 = (struct dp83867_private *)phydev->priv;
 242         }
 243
 244         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 245         if (dp83867->rxctrl_strap_quirk) {
 246                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 247                 val &= ~BIT(7);
 248                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 249         }
 250
 251         if (phy_interface_is_rgmii(phydev)) {
 252                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 253                 if (val < 0)
 254                         return val;
 255                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 256                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 257
 258                 /* The code below checks if "port mirroring" N/A MODE4 has been
 259                  * enabled during power on bootstrap.
 260                  *
 261                  * Such N/A mode enabled by mistake can put PHY IC in some
 262                  * internal testing mode and disable RGMII transmission.
 263                  *
 264                  * In this particular case one needs to check STRAP_STS1
 265                  * register's bit 11 (marked as RESERVED).
 266                  */
 267
 268                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 269                 if (bs & DP83867_STRAP_STS1_RESERVED)
 270                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 271
 272                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 273                 if (ret)
 274                         return ret;
 275
 276                 /* Set up RGMII delays */
 277                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 278
 279                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 280                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 281
 282                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 283                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 284
 285                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 286                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 287
 288                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 289
 290                 delay = (dp83867->rx_id_delay |
 291                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 292
 293                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 294                               delay);
 295
 296                 if (dp83867->io_impedance >= 0) {
 297                         val = phy_read_mmd(phydev, DP83867_DEVADDR,
 298                                            DP83867_IO_MUX_CFG);
 299
 300                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 301                         val |= dp83867->io_impedance &
 302                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 303
 304                         phy_write_mmd(phydev, DP83867_DEVADDR,
 305                                       DP83867_IO_MUX_CFG, val);
 306                 }
 307         }
 308
 309         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 310                 /* For support SPEED_10 in SGMII mode
 311                  * DP83867_10M_SGMII_RATE_ADAPT bit
 312                  * has to be cleared by software. That
 313                  * does not affect SPEED_100 and
 314                  * SPEED_1000.
 315                  */
 316                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 317                                    DP83867_10M_SGMII_CFG);
 318                 val &= ~DP83867_10M_SGMII_RATE_ADAPT_MASK;
 319                 ret = phy_write_mmd(phydev, DP83867_DEVADDR,
 320                                     DP83867_10M_SGMII_CFG, val);
 321
 322                 if (ret)
 323                         return ret;
 324
 325                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 326                  * are 01). That is not enough to finalize autoneg on some
 327                  * devices. Increase this timer duration to maximum 16ms.
 328                  */
 329                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 330                 val &= ~DP83867_CFG4_SGMII_ANEG_MASK;
 331                 val |= DP83867_CFG4_SGMII_ANEG_TIMER_16MS;
 332                 ret = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 333
 334                 if (ret)
 335                         return ret;
 336         }
 337
 338         val = phy_read(phydev, DP83867_CFG3);
 339         /* Enable Interrupt output INT_OE in CFG3 register */
 340         if (phy_interrupt_is_valid(phydev))
 341                 val |= DP83867_CFG3_INT_OE;
 342
 343         val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
 344         phy_write(phydev, DP83867_CFG3, val);
 345
 346         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 347                 dp83867_config_port_mirroring(phydev);
 348
 349         /* Clock output selection if muxing property is set */
 350         if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
 351                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
 352                 val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 353                 val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 354                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
 355         }
 356
 357         return 0;
 358 }
 359
 360 static int dp83867_phy_reset(struct phy_device *phydev)
 361 {
 362         int err;
 363
 364         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 365         if (err < 0)
 366                 return err;
 367
 368         return dp83867_config_init(phydev);
 369 }
 370
 371 static struct phy_driver dp83867_driver[] = {
 372         {
 373                 .phy_id         = DP83867_PHY_ID,
 374                 .phy_id_mask    = 0xfffffff0,
 375                 .name           = "TI DP83867",
 376                 .features       = PHY_GBIT_FEATURES,
 377                 .flags          = PHY_HAS_INTERRUPT,
 378
 379                 .config_init    = dp83867_config_init,
 380                 .soft_reset     = dp83867_phy_reset,
 381
 382                 /* IRQ related */
 383                 .ack_interrupt  = dp83867_ack_interrupt,
 384                 .config_intr    = dp83867_config_intr,
 385
 386                 .suspend        = genphy_suspend,
 387                 .resume         = genphy_resume,
 388         },
 389 };
 390 module_phy_driver(dp83867_driver);
 391
 392 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 393         { DP83867_PHY_ID, 0xfffffff0 },
 394         { }
 395 };
 396
 397 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 398
 399 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 400 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 401 MODULE_LICENSE("GPL");