2 * Driver for the Texas Instruments DP83867 PHY
4 * Copyright (C) 2015 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/ethtool.h>
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/module.h>
21 #include <linux/phy.h>
23 #include <dt-bindings/net/ti-dp83867.h>
25 #define DP83867_PHY_ID 0x2000a231
26 #define DP83867_DEVADDR 0x1f
28 #define MII_DP83867_PHYCTRL 0x10
29 #define MII_DP83867_MICR 0x12
30 #define MII_DP83867_ISR 0x13
31 #define DP83867_CTRL 0x1f
32 #define DP83867_CFG3 0x1e
34 /* Extended Registers */
35 #define DP83867_CFG4 0x0031
36 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
37 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
38 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
39 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
40 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
42 #define DP83867_RGMIICTL 0x0032
43 #define DP83867_STRAP_STS1 0x006E
44 #define DP83867_RGMIIDCTL 0x0086
45 #define DP83867_IO_MUX_CFG 0x0170
46 #define DP83867_10M_SGMII_CFG 0x016F
47 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
49 #define DP83867_SW_RESET BIT(15)
50 #define DP83867_SW_RESTART BIT(14)
52 /* MICR Interrupt bits */
53 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
54 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
55 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
56 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
57 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
58 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
59 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
60 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
61 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
62 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
63 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
64 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
67 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
68 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
71 #define DP83867_STRAP_STS1_RESERVED BIT(11)
74 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
75 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
76 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
79 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
82 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
84 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
85 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
88 #define DP83867_CFG3_INT_OE BIT(7)
89 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
92 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
95 DP83867_PORT_MIRROING_KEEP,
96 DP83867_PORT_MIRROING_EN,
97 DP83867_PORT_MIRROING_DIS,
100 struct dp83867_private {
106 bool rxctrl_strap_quirk;
109 static int dp83867_ack_interrupt(struct phy_device *phydev)
111 int err = phy_read(phydev, MII_DP83867_ISR);
119 static int dp83867_config_intr(struct phy_device *phydev)
123 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
124 micr_status = phy_read(phydev, MII_DP83867_MICR);
129 (MII_DP83867_MICR_AN_ERR_INT_EN |
130 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
131 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
132 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
133 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
134 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
136 return phy_write(phydev, MII_DP83867_MICR, micr_status);
140 return phy_write(phydev, MII_DP83867_MICR, micr_status);
143 static int dp83867_config_port_mirroring(struct phy_device *phydev)
145 struct dp83867_private *dp83867 =
146 (struct dp83867_private *)phydev->priv;
149 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
151 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
152 val |= DP83867_CFG4_PORT_MIRROR_EN;
154 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
156 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
161 #ifdef CONFIG_OF_MDIO
162 static int dp83867_of_init(struct phy_device *phydev)
164 struct dp83867_private *dp83867 = phydev->priv;
165 struct device *dev = &phydev->mdio.dev;
166 struct device_node *of_node = dev->of_node;
172 dp83867->io_impedance = -EINVAL;
174 /* Optional configuration */
175 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
176 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
177 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
178 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
180 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
181 "ti,dp83867-rxctrl-strap-quirk");
183 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
184 &dp83867->rx_id_delay);
186 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
187 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
190 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
191 &dp83867->tx_id_delay);
193 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
194 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
197 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
198 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
200 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
201 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
203 return of_property_read_u32(of_node, "ti,fifo-depth",
204 &dp83867->fifo_depth);
207 static int dp83867_of_init(struct phy_device *phydev)
211 #endif /* CONFIG_OF_MDIO */
213 static int dp83867_config_init(struct phy_device *phydev)
215 struct dp83867_private *dp83867;
220 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
225 phydev->priv = dp83867;
226 ret = dp83867_of_init(phydev);
230 dp83867 = (struct dp83867_private *)phydev->priv;
233 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
234 if (dp83867->rxctrl_strap_quirk) {
235 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
237 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
240 if (phy_interface_is_rgmii(phydev)) {
241 val = phy_read(phydev, MII_DP83867_PHYCTRL);
244 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
245 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
247 /* The code below checks if "port mirroring" N/A MODE4 has been
248 * enabled during power on bootstrap.
250 * Such N/A mode enabled by mistake can put PHY IC in some
251 * internal testing mode and disable RGMII transmission.
253 * In this particular case one needs to check STRAP_STS1
254 * register's bit 11 (marked as RESERVED).
257 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
258 if (bs & DP83867_STRAP_STS1_RESERVED)
259 val &= ~DP83867_PHYCR_RESERVED_MASK;
261 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
265 /* Set up RGMII delays */
266 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
268 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
269 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
271 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
272 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
274 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
275 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
277 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
279 delay = (dp83867->rx_id_delay |
280 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
282 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
285 if (dp83867->io_impedance >= 0) {
286 val = phy_read_mmd(phydev, DP83867_DEVADDR,
289 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
290 val |= dp83867->io_impedance &
291 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
293 phy_write_mmd(phydev, DP83867_DEVADDR,
294 DP83867_IO_MUX_CFG, val);
298 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
299 /* For support SPEED_10 in SGMII mode
300 * DP83867_10M_SGMII_RATE_ADAPT bit
301 * has to be cleared by software. That
302 * does not affect SPEED_100 and
305 val = phy_read_mmd(phydev, DP83867_DEVADDR,
306 DP83867_10M_SGMII_CFG);
307 val &= ~DP83867_10M_SGMII_RATE_ADAPT_MASK;
308 ret = phy_write_mmd(phydev, DP83867_DEVADDR,
309 DP83867_10M_SGMII_CFG, val);
314 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
315 * are 01). That is not enough to finalize autoneg on some
316 * devices. Increase this timer duration to maximum 16ms.
318 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
319 val &= ~DP83867_CFG4_SGMII_ANEG_MASK;
320 val |= DP83867_CFG4_SGMII_ANEG_TIMER_16MS;
321 ret = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
327 val = phy_read(phydev, DP83867_CFG3);
328 /* Enable Interrupt output INT_OE in CFG3 register */
329 if (phy_interrupt_is_valid(phydev))
330 val |= DP83867_CFG3_INT_OE;
332 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
333 phy_write(phydev, DP83867_CFG3, val);
335 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
336 dp83867_config_port_mirroring(phydev);
341 static int dp83867_phy_reset(struct phy_device *phydev)
345 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
349 return dp83867_config_init(phydev);
352 static struct phy_driver dp83867_driver[] = {
354 .phy_id = DP83867_PHY_ID,
355 .phy_id_mask = 0xfffffff0,
356 .name = "TI DP83867",
357 .features = PHY_GBIT_FEATURES,
358 .flags = PHY_HAS_INTERRUPT,
360 .config_init = dp83867_config_init,
361 .soft_reset = dp83867_phy_reset,
364 .ack_interrupt = dp83867_ack_interrupt,
365 .config_intr = dp83867_config_intr,
367 .config_aneg = genphy_config_aneg,
368 .read_status = genphy_read_status,
369 .suspend = genphy_suspend,
370 .resume = genphy_resume,
373 module_phy_driver(dp83867_driver);
375 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
376 { DP83867_PHY_ID, 0xfffffff0 },
380 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
382 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
383 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
384 MODULE_LICENSE("GPL");