drivers/net/phy/dp83822.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
   3  *
   4  * Copyright (C) 2017 Texas Instruments Inc.
   5  */
   6
   7 #include <linux/ethtool.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/netdevice.h>
  15
  16 #define DP83822_PHY_ID          0x2000a240
  17 #define DP83825S_PHY_ID         0x2000a140
  18 #define DP83825I_PHY_ID         0x2000a150
  19 #define DP83825CM_PHY_ID        0x2000a160
  20 #define DP83825CS_PHY_ID        0x2000a170
  21 #define DP83826C_PHY_ID         0x2000a130
  22 #define DP83826NC_PHY_ID        0x2000a110
  23
  24 #define DP83822_DEVADDR         0x1f
  25
  26 #define MII_DP83822_CTRL_2      0x0a
  27 #define MII_DP83822_PHYSTS      0x10
  28 #define MII_DP83822_PHYSCR      0x11
  29 #define MII_DP83822_MISR1       0x12
  30 #define MII_DP83822_MISR2       0x13
  31 #define MII_DP83822_FCSCR       0x14
  32 #define MII_DP83822_RCSR        0x17
  33 #define MII_DP83822_RESET_CTRL  0x1f
  34 #define MII_DP83822_GENCFG      0x465
  35 #define MII_DP83822_SOR1        0x467
  36
  37 /* GENCFG */
  38 #define DP83822_SIG_DET_LOW     BIT(0)
  39
  40 /* Control Register 2 bits */
  41 #define DP83822_FX_ENABLE       BIT(14)
  42
  43 #define DP83822_HW_RESET        BIT(15)
  44 #define DP83822_SW_RESET        BIT(14)
  45
  46 /* PHY STS bits */
  47 #define DP83822_PHYSTS_DUPLEX                   BIT(2)
  48 #define DP83822_PHYSTS_10                       BIT(1)
  49 #define DP83822_PHYSTS_LINK                     BIT(0)
  50
  51 /* PHYSCR Register Fields */
  52 #define DP83822_PHYSCR_INT_OE           BIT(0) /* Interrupt Output Enable */
  53 #define DP83822_PHYSCR_INTEN            BIT(1) /* Interrupt Enable */
  54
  55 /* MISR1 bits */
  56 #define DP83822_RX_ERR_HF_INT_EN        BIT(0)
  57 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
  58 #define DP83822_ANEG_COMPLETE_INT_EN    BIT(2)
  59 #define DP83822_DUP_MODE_CHANGE_INT_EN  BIT(3)
  60 #define DP83822_SPEED_CHANGED_INT_EN    BIT(4)
  61 #define DP83822_LINK_STAT_INT_EN        BIT(5)
  62 #define DP83822_ENERGY_DET_INT_EN       BIT(6)
  63 #define DP83822_LINK_QUAL_INT_EN        BIT(7)
  64
  65 /* MISR2 bits */
  66 #define DP83822_JABBER_DET_INT_EN       BIT(0)
  67 #define DP83822_WOL_PKT_INT_EN          BIT(1)
  68 #define DP83822_SLEEP_MODE_INT_EN       BIT(2)
  69 #define DP83822_MDI_XOVER_INT_EN        BIT(3)
  70 #define DP83822_LB_FIFO_INT_EN          BIT(4)
  71 #define DP83822_PAGE_RX_INT_EN          BIT(5)
  72 #define DP83822_ANEG_ERR_INT_EN         BIT(6)
  73 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
  74
  75 /* INT_STAT1 bits */
  76 #define DP83822_WOL_INT_EN      BIT(4)
  77 #define DP83822_WOL_INT_STAT    BIT(12)
  78
  79 #define MII_DP83822_RXSOP1      0x04a5
  80 #define MII_DP83822_RXSOP2      0x04a6
  81 #define MII_DP83822_RXSOP3      0x04a7
  82
  83 /* WoL Registers */
  84 #define MII_DP83822_WOL_CFG     0x04a0
  85 #define MII_DP83822_WOL_STAT    0x04a1
  86 #define MII_DP83822_WOL_DA1     0x04a2
  87 #define MII_DP83822_WOL_DA2     0x04a3
  88 #define MII_DP83822_WOL_DA3     0x04a4
  89
  90 /* WoL bits */
  91 #define DP83822_WOL_MAGIC_EN    BIT(0)
  92 #define DP83822_WOL_SECURE_ON   BIT(5)
  93 #define DP83822_WOL_EN          BIT(7)
  94 #define DP83822_WOL_INDICATION_SEL BIT(8)
  95 #define DP83822_WOL_CLR_INDICATION BIT(11)
  96
  97 /* RSCR bits */
  98 #define DP83822_RX_CLK_SHIFT    BIT(12)
  99 #define DP83822_TX_CLK_SHIFT    BIT(11)
 100
 101 /* SOR1 mode */
 102 #define DP83822_STRAP_MODE1     0
 103 #define DP83822_STRAP_MODE2     BIT(0)
 104 #define DP83822_STRAP_MODE3     BIT(1)
 105 #define DP83822_STRAP_MODE4     GENMASK(1, 0)
 106
 107 #define DP83822_COL_STRAP_MASK  GENMASK(11, 10)
 108 #define DP83822_COL_SHIFT       10
 109 #define DP83822_RX_ER_STR_MASK  GENMASK(9, 8)
 110 #define DP83822_RX_ER_SHIFT     8
 111
 112 #define MII_DP83822_FIBER_ADVERTISE    (ADVERTISED_TP | ADVERTISED_MII | \
 113                                         ADVERTISED_FIBRE | \
 114                                         ADVERTISED_Pause | ADVERTISED_Asym_Pause)
 115
 116 struct dp83822_private {
 117         bool fx_signal_det_low;
 118         int fx_enabled;
 119         u16 fx_sd_enable;
 120 };
 121
 122 static int dp83822_ack_interrupt(struct phy_device *phydev)
 123 {
 124         int err;
 125
 126         err = phy_read(phydev, MII_DP83822_MISR1);
 127         if (err < 0)
 128                 return err;
 129
 130         err = phy_read(phydev, MII_DP83822_MISR2);
 131         if (err < 0)
 132                 return err;
 133
 134         return 0;
 135 }
 136
 137 static int dp83822_set_wol(struct phy_device *phydev,
 138                            struct ethtool_wolinfo *wol)
 139 {
 140         struct net_device *ndev = phydev->attached_dev;
 141         u16 value;
 142         const u8 *mac;
 143
 144         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
 145                 mac = (const u8 *)ndev->dev_addr;
 146
 147                 if (!is_valid_ether_addr(mac))
 148                         return -EINVAL;
 149
 150                 /* MAC addresses start with byte 5, but stored in mac[0].
 151                  * 822 PHYs store bytes 4|5, 2|3, 0|1
 152                  */
 153                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
 154                               (mac[1] << 8) | mac[0]);
 155                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
 156                               (mac[3] << 8) | mac[2]);
 157                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
 158                               (mac[5] << 8) | mac[4]);
 159
 160                 value = phy_read_mmd(phydev, DP83822_DEVADDR,
 161                                      MII_DP83822_WOL_CFG);
 162                 if (wol->wolopts & WAKE_MAGIC)
 163                         value |= DP83822_WOL_MAGIC_EN;
 164                 else
 165                         value &= ~DP83822_WOL_MAGIC_EN;
 166
 167                 if (wol->wolopts & WAKE_MAGICSECURE) {
 168                         phy_write_mmd(phydev, DP83822_DEVADDR,
 169                                       MII_DP83822_RXSOP1,
 170                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 171                         phy_write_mmd(phydev, DP83822_DEVADDR,
 172                                       MII_DP83822_RXSOP2,
 173                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 174                         phy_write_mmd(phydev, DP83822_DEVADDR,
 175                                       MII_DP83822_RXSOP3,
 176                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 177                         value |= DP83822_WOL_SECURE_ON;
 178                 } else {
 179                         value &= ~DP83822_WOL_SECURE_ON;
 180                 }
 181
 182                 /* Clear any pending WoL interrupt */
 183                 phy_read(phydev, MII_DP83822_MISR2);
 184
 185                 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
 186                          DP83822_WOL_CLR_INDICATION;
 187
 188                 return phy_write_mmd(phydev, DP83822_DEVADDR,
 189                                      MII_DP83822_WOL_CFG, value);
 190         } else {
 191                 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
 192                                           MII_DP83822_WOL_CFG, DP83822_WOL_EN);
 193         }
 194 }
 195
 196 static void dp83822_get_wol(struct phy_device *phydev,
 197                             struct ethtool_wolinfo *wol)
 198 {
 199         int value;
 200         u16 sopass_val;
 201
 202         wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
 203         wol->wolopts = 0;
 204
 205         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 206
 207         if (value & DP83822_WOL_MAGIC_EN)
 208                 wol->wolopts |= WAKE_MAGIC;
 209
 210         if (value & DP83822_WOL_SECURE_ON) {
 211                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 212                                           MII_DP83822_RXSOP1);
 213                 wol->sopass[0] = (sopass_val & 0xff);
 214                 wol->sopass[1] = (sopass_val >> 8);
 215
 216                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 217                                           MII_DP83822_RXSOP2);
 218                 wol->sopass[2] = (sopass_val & 0xff);
 219                 wol->sopass[3] = (sopass_val >> 8);
 220
 221                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 222                                           MII_DP83822_RXSOP3);
 223                 wol->sopass[4] = (sopass_val & 0xff);
 224                 wol->sopass[5] = (sopass_val >> 8);
 225
 226                 wol->wolopts |= WAKE_MAGICSECURE;
 227         }
 228
 229         /* WoL is not enabled so set wolopts to 0 */
 230         if (!(value & DP83822_WOL_EN))
 231                 wol->wolopts = 0;
 232 }
 233
 234 static int dp83822_config_intr(struct phy_device *phydev)
 235 {
 236         struct dp83822_private *dp83822 = phydev->priv;
 237         int misr_status;
 238         int physcr_status;
 239         int err;
 240
 241         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 242                 misr_status = phy_read(phydev, MII_DP83822_MISR1);
 243                 if (misr_status < 0)
 244                         return misr_status;
 245
 246                 misr_status |= (DP83822_LINK_STAT_INT_EN |
 247                                 DP83822_ENERGY_DET_INT_EN |
 248                                 DP83822_LINK_QUAL_INT_EN);
 249
 250                 if (!dp83822->fx_enabled)
 251                         misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
 252                                        DP83822_DUP_MODE_CHANGE_INT_EN |
 253                                        DP83822_SPEED_CHANGED_INT_EN;
 254
 255
 256                 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
 257                 if (err < 0)
 258                         return err;
 259
 260                 misr_status = phy_read(phydev, MII_DP83822_MISR2);
 261                 if (misr_status < 0)
 262                         return misr_status;
 263
 264                 misr_status |= (DP83822_JABBER_DET_INT_EN |
 265                                 DP83822_SLEEP_MODE_INT_EN |
 266                                 DP83822_LB_FIFO_INT_EN |
 267                                 DP83822_PAGE_RX_INT_EN |
 268                                 DP83822_EEE_ERROR_CHANGE_INT_EN);
 269
 270                 if (!dp83822->fx_enabled)
 271                         misr_status |= DP83822_ANEG_ERR_INT_EN |
 272                                        DP83822_WOL_PKT_INT_EN;
 273
 274                 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
 275                 if (err < 0)
 276                         return err;
 277
 278                 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
 279                 if (physcr_status < 0)
 280                         return physcr_status;
 281
 282                 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
 283
 284         } else {
 285                 err = phy_write(phydev, MII_DP83822_MISR1, 0);
 286                 if (err < 0)
 287                         return err;
 288
 289                 err = phy_write(phydev, MII_DP83822_MISR2, 0);
 290                 if (err < 0)
 291                         return err;
 292
 293                 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
 294                 if (physcr_status < 0)
 295                         return physcr_status;
 296
 297                 physcr_status &= ~DP83822_PHYSCR_INTEN;
 298         }
 299
 300         return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
 301 }
 302
 303 static int dp8382x_disable_wol(struct phy_device *phydev)
 304 {
 305         return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,
 306                                   DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
 307                                   DP83822_WOL_SECURE_ON);
 308 }
 309
 310 static int dp83822_read_status(struct phy_device *phydev)
 311 {
 312         struct dp83822_private *dp83822 = phydev->priv;
 313         int status = phy_read(phydev, MII_DP83822_PHYSTS);
 314         int ctrl2;
 315         int ret;
 316
 317         if (dp83822->fx_enabled) {
 318                 if (status & DP83822_PHYSTS_LINK) {
 319                         phydev->speed = SPEED_UNKNOWN;
 320                         phydev->duplex = DUPLEX_UNKNOWN;
 321                 } else {
 322                         ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
 323                         if (ctrl2 < 0)
 324                                 return ctrl2;
 325
 326                         if (!(ctrl2 & DP83822_FX_ENABLE)) {
 327                                 ret = phy_write(phydev, MII_DP83822_CTRL_2,
 328                                                 DP83822_FX_ENABLE | ctrl2);
 329                                 if (ret < 0)
 330                                         return ret;
 331                         }
 332                 }
 333         }
 334
 335         ret = genphy_read_status(phydev);
 336         if (ret)
 337                 return ret;
 338
 339         if (status < 0)
 340                 return status;
 341
 342         if (status & DP83822_PHYSTS_DUPLEX)
 343                 phydev->duplex = DUPLEX_FULL;
 344         else
 345                 phydev->duplex = DUPLEX_HALF;
 346
 347         if (status & DP83822_PHYSTS_10)
 348                 phydev->speed = SPEED_10;
 349         else
 350                 phydev->speed = SPEED_100;
 351
 352         return 0;
 353 }
 354
 355 static int dp83822_config_init(struct phy_device *phydev)
 356 {
 357         struct dp83822_private *dp83822 = phydev->priv;
 358         struct device *dev = &phydev->mdio.dev;
 359         int rgmii_delay;
 360         s32 rx_int_delay;
 361         s32 tx_int_delay;
 362         int err = 0;
 363         int bmcr;
 364
 365         if (phy_interface_is_rgmii(phydev)) {
 366                 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
 367                                                       true);
 368
 369                 if (rx_int_delay <= 0)
 370                         rgmii_delay = 0;
 371                 else
 372                         rgmii_delay = DP83822_RX_CLK_SHIFT;
 373
 374                 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
 375                                                       false);
 376                 if (tx_int_delay <= 0)
 377                         rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
 378                 else
 379                         rgmii_delay |= DP83822_TX_CLK_SHIFT;
 380
 381                 if (rgmii_delay) {
 382                         err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
 383                                                MII_DP83822_RCSR, rgmii_delay);
 384                         if (err)
 385                                 return err;
 386                 }
 387         }
 388
 389         if (dp83822->fx_enabled) {
 390                 err = phy_modify(phydev, MII_DP83822_CTRL_2,
 391                                  DP83822_FX_ENABLE, 1);
 392                 if (err < 0)
 393                         return err;
 394
 395                 /* Only allow advertising what this PHY supports */
 396                 linkmode_and(phydev->advertising, phydev->advertising,
 397                              phydev->supported);
 398
 399                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 400                                  phydev->supported);
 401                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 402                                  phydev->advertising);
 403                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 404                                  phydev->supported);
 405                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 406                                  phydev->supported);
 407                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 408                                  phydev->advertising);
 409                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 410                                  phydev->advertising);
 411
 412                 /* Auto neg is not supported in fiber mode */
 413                 bmcr = phy_read(phydev, MII_BMCR);
 414                 if (bmcr < 0)
 415                         return bmcr;
 416
 417                 if (bmcr & BMCR_ANENABLE) {
 418                         err =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
 419                         if (err < 0)
 420                                 return err;
 421                 }
 422                 phydev->autoneg = AUTONEG_DISABLE;
 423                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 424                                    phydev->supported);
 425                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 426                                    phydev->advertising);
 427
 428                 /* Setup fiber advertisement */
 429                 err = phy_modify_changed(phydev, MII_ADVERTISE,
 430                                          MII_DP83822_FIBER_ADVERTISE,
 431                                          MII_DP83822_FIBER_ADVERTISE);
 432
 433                 if (err < 0)
 434                         return err;
 435
 436                 if (dp83822->fx_signal_det_low) {
 437                         err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
 438                                                MII_DP83822_GENCFG,
 439                                                DP83822_SIG_DET_LOW);
 440                         if (err)
 441                                 return err;
 442                 }
 443         }
 444         return dp8382x_disable_wol(phydev);
 445 }
 446
 447 static int dp8382x_config_init(struct phy_device *phydev)
 448 {
 449         return dp8382x_disable_wol(phydev);
 450 }
 451
 452 static int dp83822_phy_reset(struct phy_device *phydev)
 453 {
 454         int err;
 455
 456         err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
 457         if (err < 0)
 458                 return err;
 459
 460         return phydev->drv->config_init(phydev);
 461 }
 462
 463 #ifdef CONFIG_OF_MDIO
 464 static int dp83822_of_init(struct phy_device *phydev)
 465 {
 466         struct dp83822_private *dp83822 = phydev->priv;
 467         struct device *dev = &phydev->mdio.dev;
 468
 469         /* Signal detection for the PHY is only enabled if the FX_EN and the
 470          * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
 471          * is strapped otherwise signal detection is disabled for the PHY.
 472          */
 473         if (dp83822->fx_enabled && dp83822->fx_sd_enable)
 474                 dp83822->fx_signal_det_low = device_property_present(dev,
 475                                                                      "ti,link-loss-low");
 476         if (!dp83822->fx_enabled)
 477                 dp83822->fx_enabled = device_property_present(dev,
 478                                                               "ti,fiber-mode");
 479
 480         return 0;
 481 }
 482 #else
 483 static int dp83822_of_init(struct phy_device *phydev)
 484 {
 485         return 0;
 486 }
 487 #endif /* CONFIG_OF_MDIO */
 488
 489 static int dp83822_read_straps(struct phy_device *phydev)
 490 {
 491         struct dp83822_private *dp83822 = phydev->priv;
 492         int fx_enabled, fx_sd_enable;
 493         int val;
 494
 495         val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
 496         if (val < 0)
 497                 return val;
 498
 499         fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
 500         if (fx_enabled == DP83822_STRAP_MODE2 ||
 501             fx_enabled == DP83822_STRAP_MODE3)
 502                 dp83822->fx_enabled = 1;
 503
 504         if (dp83822->fx_enabled) {
 505                 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
 506                 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
 507                     fx_sd_enable == DP83822_STRAP_MODE4)
 508                         dp83822->fx_sd_enable = 1;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static int dp83822_probe(struct phy_device *phydev)
 515 {
 516         struct dp83822_private *dp83822;
 517         int ret;
 518
 519         dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
 520                                GFP_KERNEL);
 521         if (!dp83822)
 522                 return -ENOMEM;
 523
 524         phydev->priv = dp83822;
 525
 526         ret = dp83822_read_straps(phydev);
 527         if (ret)
 528                 return ret;
 529
 530         dp83822_of_init(phydev);
 531
 532         if (dp83822->fx_enabled)
 533                 phydev->port = PORT_FIBRE;
 534
 535         return 0;
 536 }
 537
 538 static int dp83822_suspend(struct phy_device *phydev)
 539 {
 540         int value;
 541
 542         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 543
 544         if (!(value & DP83822_WOL_EN))
 545                 genphy_suspend(phydev);
 546
 547         return 0;
 548 }
 549
 550 static int dp83822_resume(struct phy_device *phydev)
 551 {
 552         int value;
 553
 554         genphy_resume(phydev);
 555
 556         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 557
 558         phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
 559                       DP83822_WOL_CLR_INDICATION);
 560
 561         return 0;
 562 }
 563
 564 #define DP83822_PHY_DRIVER(_id, _name)                          \
 565         {                                                       \
 566                 PHY_ID_MATCH_MODEL(_id),                        \
 567                 .name           = (_name),                      \
 568                 /* PHY_BASIC_FEATURES */                        \
 569                 .probe          = dp83822_probe,                \
 570                 .soft_reset     = dp83822_phy_reset,            \
 571                 .config_init    = dp83822_config_init,          \
 572                 .read_status    = dp83822_read_status,          \
 573                 .get_wol = dp83822_get_wol,                     \
 574                 .set_wol = dp83822_set_wol,                     \
 575                 .ack_interrupt = dp83822_ack_interrupt,         \
 576                 .config_intr = dp83822_config_intr,             \
 577                 .suspend = dp83822_suspend,                     \
 578                 .resume = dp83822_resume,                       \
 579         }
 580
 581 #define DP8382X_PHY_DRIVER(_id, _name)                          \
 582         {                                                       \
 583                 PHY_ID_MATCH_MODEL(_id),                        \
 584                 .name           = (_name),                      \
 585                 /* PHY_BASIC_FEATURES */                        \
 586                 .soft_reset     = dp83822_phy_reset,            \
 587                 .config_init    = dp8382x_config_init,          \
 588                 .get_wol = dp83822_get_wol,                     \
 589                 .set_wol = dp83822_set_wol,                     \
 590                 .ack_interrupt = dp83822_ack_interrupt,         \
 591                 .config_intr = dp83822_config_intr,             \
 592                 .suspend = dp83822_suspend,                     \
 593                 .resume = dp83822_resume,                       \
 594         }
 595
 596 static struct phy_driver dp83822_driver[] = {
 597         DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
 598         DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
 599         DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
 600         DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
 601         DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
 602         DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
 603         DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
 604 };
 605 module_phy_driver(dp83822_driver);
 606
 607 static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
 608         { DP83822_PHY_ID, 0xfffffff0 },
 609         { DP83825I_PHY_ID, 0xfffffff0 },
 610         { DP83826C_PHY_ID, 0xfffffff0 },
 611         { DP83826NC_PHY_ID, 0xfffffff0 },
 612         { DP83825S_PHY_ID, 0xfffffff0 },
 613         { DP83825CM_PHY_ID, 0xfffffff0 },
 614         { DP83825CS_PHY_ID, 0xfffffff0 },
 615         { },
 616 };
 617 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
 618
 619 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
 620 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 621 MODULE_LICENSE("GPL v2");