drivers/net/phy/dp83822.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
   3  *
   4  * Copyright (C) 2017 Texas Instruments Inc.
   5  */
   6
   7 #include <linux/ethtool.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/netdevice.h>
  15
  16 #define DP83822_PHY_ID          0x2000a240
  17 #define DP83825S_PHY_ID         0x2000a140
  18 #define DP83825I_PHY_ID         0x2000a150
  19 #define DP83825CM_PHY_ID        0x2000a160
  20 #define DP83825CS_PHY_ID        0x2000a170
  21 #define DP83826C_PHY_ID         0x2000a130
  22 #define DP83826NC_PHY_ID        0x2000a110
  23
  24 #define DP83822_DEVADDR         0x1f
  25
  26 #define MII_DP83822_CTRL_2      0x0a
  27 #define MII_DP83822_PHYSTS      0x10
  28 #define MII_DP83822_PHYSCR      0x11
  29 #define MII_DP83822_MISR1       0x12
  30 #define MII_DP83822_MISR2       0x13
  31 #define MII_DP83822_FCSCR       0x14
  32 #define MII_DP83822_RCSR        0x17
  33 #define MII_DP83822_RESET_CTRL  0x1f
  34 #define MII_DP83822_GENCFG      0x465
  35 #define MII_DP83822_SOR1        0x467
  36
  37 /* GENCFG */
  38 #define DP83822_SIG_DET_LOW     BIT(0)
  39
  40 /* Control Register 2 bits */
  41 #define DP83822_FX_ENABLE       BIT(14)
  42
  43 #define DP83822_HW_RESET        BIT(15)
  44 #define DP83822_SW_RESET        BIT(14)
  45
  46 /* PHY STS bits */
  47 #define DP83822_PHYSTS_DUPLEX                   BIT(2)
  48 #define DP83822_PHYSTS_10                       BIT(1)
  49 #define DP83822_PHYSTS_LINK                     BIT(0)
  50
  51 /* PHYSCR Register Fields */
  52 #define DP83822_PHYSCR_INT_OE           BIT(0) /* Interrupt Output Enable */
  53 #define DP83822_PHYSCR_INTEN            BIT(1) /* Interrupt Enable */
  54
  55 /* MISR1 bits */
  56 #define DP83822_RX_ERR_HF_INT_EN        BIT(0)
  57 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
  58 #define DP83822_ANEG_COMPLETE_INT_EN    BIT(2)
  59 #define DP83822_DUP_MODE_CHANGE_INT_EN  BIT(3)
  60 #define DP83822_SPEED_CHANGED_INT_EN    BIT(4)
  61 #define DP83822_LINK_STAT_INT_EN        BIT(5)
  62 #define DP83822_ENERGY_DET_INT_EN       BIT(6)
  63 #define DP83822_LINK_QUAL_INT_EN        BIT(7)
  64
  65 /* MISR2 bits */
  66 #define DP83822_JABBER_DET_INT_EN       BIT(0)
  67 #define DP83822_WOL_PKT_INT_EN          BIT(1)
  68 #define DP83822_SLEEP_MODE_INT_EN       BIT(2)
  69 #define DP83822_MDI_XOVER_INT_EN        BIT(3)
  70 #define DP83822_LB_FIFO_INT_EN          BIT(4)
  71 #define DP83822_PAGE_RX_INT_EN          BIT(5)
  72 #define DP83822_ANEG_ERR_INT_EN         BIT(6)
  73 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
  74
  75 /* INT_STAT1 bits */
  76 #define DP83822_WOL_INT_EN      BIT(4)
  77 #define DP83822_WOL_INT_STAT    BIT(12)
  78
  79 #define MII_DP83822_RXSOP1      0x04a5
  80 #define MII_DP83822_RXSOP2      0x04a6
  81 #define MII_DP83822_RXSOP3      0x04a7
  82
  83 /* WoL Registers */
  84 #define MII_DP83822_WOL_CFG     0x04a0
  85 #define MII_DP83822_WOL_STAT    0x04a1
  86 #define MII_DP83822_WOL_DA1     0x04a2
  87 #define MII_DP83822_WOL_DA2     0x04a3
  88 #define MII_DP83822_WOL_DA3     0x04a4
  89
  90 /* WoL bits */
  91 #define DP83822_WOL_MAGIC_EN    BIT(0)
  92 #define DP83822_WOL_SECURE_ON   BIT(5)
  93 #define DP83822_WOL_EN          BIT(7)
  94 #define DP83822_WOL_INDICATION_SEL BIT(8)
  95 #define DP83822_WOL_CLR_INDICATION BIT(11)
  96
  97 /* RSCR bits */
  98 #define DP83822_RX_CLK_SHIFT    BIT(12)
  99 #define DP83822_TX_CLK_SHIFT    BIT(11)
 100
 101 /* SOR1 mode */
 102 #define DP83822_STRAP_MODE1     0
 103 #define DP83822_STRAP_MODE2     BIT(0)
 104 #define DP83822_STRAP_MODE3     BIT(1)
 105 #define DP83822_STRAP_MODE4     GENMASK(1, 0)
 106
 107 #define DP83822_COL_STRAP_MASK  GENMASK(11, 10)
 108 #define DP83822_COL_SHIFT       10
 109 #define DP83822_RX_ER_STR_MASK  GENMASK(9, 8)
 110 #define DP83822_RX_ER_SHIFT     8
 111
 112 #define MII_DP83822_FIBER_ADVERTISE    (ADVERTISED_TP | ADVERTISED_MII | \
 113                                         ADVERTISED_FIBRE | \
 114                                         ADVERTISED_Pause | ADVERTISED_Asym_Pause)
 115
 116 struct dp83822_private {
 117         bool fx_signal_det_low;
 118         int fx_enabled;
 119         u16 fx_sd_enable;
 120 };
 121
 122 static int dp83822_set_wol(struct phy_device *phydev,
 123                            struct ethtool_wolinfo *wol)
 124 {
 125         struct net_device *ndev = phydev->attached_dev;
 126         u16 value;
 127         const u8 *mac;
 128
 129         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
 130                 mac = (const u8 *)ndev->dev_addr;
 131
 132                 if (!is_valid_ether_addr(mac))
 133                         return -EINVAL;
 134
 135                 /* MAC addresses start with byte 5, but stored in mac[0].
 136                  * 822 PHYs store bytes 4|5, 2|3, 0|1
 137                  */
 138                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
 139                               (mac[1] << 8) | mac[0]);
 140                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
 141                               (mac[3] << 8) | mac[2]);
 142                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
 143                               (mac[5] << 8) | mac[4]);
 144
 145                 value = phy_read_mmd(phydev, DP83822_DEVADDR,
 146                                      MII_DP83822_WOL_CFG);
 147                 if (wol->wolopts & WAKE_MAGIC)
 148                         value |= DP83822_WOL_MAGIC_EN;
 149                 else
 150                         value &= ~DP83822_WOL_MAGIC_EN;
 151
 152                 if (wol->wolopts & WAKE_MAGICSECURE) {
 153                         phy_write_mmd(phydev, DP83822_DEVADDR,
 154                                       MII_DP83822_RXSOP1,
 155                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 156                         phy_write_mmd(phydev, DP83822_DEVADDR,
 157                                       MII_DP83822_RXSOP2,
 158                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 159                         phy_write_mmd(phydev, DP83822_DEVADDR,
 160                                       MII_DP83822_RXSOP3,
 161                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 162                         value |= DP83822_WOL_SECURE_ON;
 163                 } else {
 164                         value &= ~DP83822_WOL_SECURE_ON;
 165                 }
 166
 167                 /* Clear any pending WoL interrupt */
 168                 phy_read(phydev, MII_DP83822_MISR2);
 169
 170                 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
 171                          DP83822_WOL_CLR_INDICATION;
 172
 173                 return phy_write_mmd(phydev, DP83822_DEVADDR,
 174                                      MII_DP83822_WOL_CFG, value);
 175         } else {
 176                 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
 177                                           MII_DP83822_WOL_CFG, DP83822_WOL_EN);
 178         }
 179 }
 180
 181 static void dp83822_get_wol(struct phy_device *phydev,
 182                             struct ethtool_wolinfo *wol)
 183 {
 184         int value;
 185         u16 sopass_val;
 186
 187         wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
 188         wol->wolopts = 0;
 189
 190         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 191
 192         if (value & DP83822_WOL_MAGIC_EN)
 193                 wol->wolopts |= WAKE_MAGIC;
 194
 195         if (value & DP83822_WOL_SECURE_ON) {
 196                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 197                                           MII_DP83822_RXSOP1);
 198                 wol->sopass[0] = (sopass_val & 0xff);
 199                 wol->sopass[1] = (sopass_val >> 8);
 200
 201                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 202                                           MII_DP83822_RXSOP2);
 203                 wol->sopass[2] = (sopass_val & 0xff);
 204                 wol->sopass[3] = (sopass_val >> 8);
 205
 206                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 207                                           MII_DP83822_RXSOP3);
 208                 wol->sopass[4] = (sopass_val & 0xff);
 209                 wol->sopass[5] = (sopass_val >> 8);
 210
 211                 wol->wolopts |= WAKE_MAGICSECURE;
 212         }
 213
 214         /* WoL is not enabled so set wolopts to 0 */
 215         if (!(value & DP83822_WOL_EN))
 216                 wol->wolopts = 0;
 217 }
 218
 219 static int dp83822_config_intr(struct phy_device *phydev)
 220 {
 221         struct dp83822_private *dp83822 = phydev->priv;
 222         int misr_status;
 223         int physcr_status;
 224         int err;
 225
 226         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 227                 misr_status = phy_read(phydev, MII_DP83822_MISR1);
 228                 if (misr_status < 0)
 229                         return misr_status;
 230
 231                 misr_status |= (DP83822_LINK_STAT_INT_EN |
 232                                 DP83822_ENERGY_DET_INT_EN |
 233                                 DP83822_LINK_QUAL_INT_EN);
 234
 235                 if (!dp83822->fx_enabled)
 236                         misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
 237                                        DP83822_DUP_MODE_CHANGE_INT_EN |
 238                                        DP83822_SPEED_CHANGED_INT_EN;
 239
 240
 241                 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
 242                 if (err < 0)
 243                         return err;
 244
 245                 misr_status = phy_read(phydev, MII_DP83822_MISR2);
 246                 if (misr_status < 0)
 247                         return misr_status;
 248
 249                 misr_status |= (DP83822_JABBER_DET_INT_EN |
 250                                 DP83822_SLEEP_MODE_INT_EN |
 251                                 DP83822_LB_FIFO_INT_EN |
 252                                 DP83822_PAGE_RX_INT_EN |
 253                                 DP83822_EEE_ERROR_CHANGE_INT_EN);
 254
 255                 if (!dp83822->fx_enabled)
 256                         misr_status |= DP83822_MDI_XOVER_INT_EN |
 257                                        DP83822_ANEG_ERR_INT_EN |
 258                                        DP83822_WOL_PKT_INT_EN;
 259
 260                 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
 261                 if (err < 0)
 262                         return err;
 263
 264                 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
 265                 if (physcr_status < 0)
 266                         return physcr_status;
 267
 268                 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
 269
 270         } else {
 271                 err = phy_write(phydev, MII_DP83822_MISR1, 0);
 272                 if (err < 0)
 273                         return err;
 274
 275                 err = phy_write(phydev, MII_DP83822_MISR2, 0);
 276                 if (err < 0)
 277                         return err;
 278
 279                 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
 280                 if (physcr_status < 0)
 281                         return physcr_status;
 282
 283                 physcr_status &= ~DP83822_PHYSCR_INTEN;
 284         }
 285
 286         return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
 287 }
 288
 289 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
 290 {
 291         bool trigger_machine = false;
 292         int irq_status;
 293
 294         /* The MISR1 and MISR2 registers are holding the interrupt status in
 295          * the upper half (15:8), while the lower half (7:0) is used for
 296          * controlling the interrupt enable state of those individual interrupt
 297          * sources. To determine the possible interrupt sources, just read the
 298          * MISR* register and use it directly to know which interrupts have
 299          * been enabled previously or not.
 300          */
 301         irq_status = phy_read(phydev, MII_DP83822_MISR1);
 302         if (irq_status < 0) {
 303                 phy_error(phydev);
 304                 return IRQ_NONE;
 305         }
 306         if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
 307                 trigger_machine = true;
 308
 309         irq_status = phy_read(phydev, MII_DP83822_MISR2);
 310         if (irq_status < 0) {
 311                 phy_error(phydev);
 312                 return IRQ_NONE;
 313         }
 314         if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
 315                 trigger_machine = true;
 316
 317         if (!trigger_machine)
 318                 return IRQ_NONE;
 319
 320         phy_trigger_machine(phydev);
 321
 322         return IRQ_HANDLED;
 323 }
 324
 325 static int dp8382x_disable_wol(struct phy_device *phydev)
 326 {
 327         return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,
 328                                   DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
 329                                   DP83822_WOL_SECURE_ON);
 330 }
 331
 332 static int dp83822_read_status(struct phy_device *phydev)
 333 {
 334         struct dp83822_private *dp83822 = phydev->priv;
 335         int status = phy_read(phydev, MII_DP83822_PHYSTS);
 336         int ctrl2;
 337         int ret;
 338
 339         if (dp83822->fx_enabled) {
 340                 if (status & DP83822_PHYSTS_LINK) {
 341                         phydev->speed = SPEED_UNKNOWN;
 342                         phydev->duplex = DUPLEX_UNKNOWN;
 343                 } else {
 344                         ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
 345                         if (ctrl2 < 0)
 346                                 return ctrl2;
 347
 348                         if (!(ctrl2 & DP83822_FX_ENABLE)) {
 349                                 ret = phy_write(phydev, MII_DP83822_CTRL_2,
 350                                                 DP83822_FX_ENABLE | ctrl2);
 351                                 if (ret < 0)
 352                                         return ret;
 353                         }
 354                 }
 355         }
 356
 357         ret = genphy_read_status(phydev);
 358         if (ret)
 359                 return ret;
 360
 361         if (status < 0)
 362                 return status;
 363
 364         if (status & DP83822_PHYSTS_DUPLEX)
 365                 phydev->duplex = DUPLEX_FULL;
 366         else
 367                 phydev->duplex = DUPLEX_HALF;
 368
 369         if (status & DP83822_PHYSTS_10)
 370                 phydev->speed = SPEED_10;
 371         else
 372                 phydev->speed = SPEED_100;
 373
 374         return 0;
 375 }
 376
 377 static int dp83822_config_init(struct phy_device *phydev)
 378 {
 379         struct dp83822_private *dp83822 = phydev->priv;
 380         struct device *dev = &phydev->mdio.dev;
 381         int rgmii_delay;
 382         s32 rx_int_delay;
 383         s32 tx_int_delay;
 384         int err = 0;
 385         int bmcr;
 386
 387         if (phy_interface_is_rgmii(phydev)) {
 388                 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
 389                                                       true);
 390
 391                 if (rx_int_delay <= 0)
 392                         rgmii_delay = 0;
 393                 else
 394                         rgmii_delay = DP83822_RX_CLK_SHIFT;
 395
 396                 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
 397                                                       false);
 398                 if (tx_int_delay <= 0)
 399                         rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
 400                 else
 401                         rgmii_delay |= DP83822_TX_CLK_SHIFT;
 402
 403                 if (rgmii_delay) {
 404                         err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
 405                                                MII_DP83822_RCSR, rgmii_delay);
 406                         if (err)
 407                                 return err;
 408                 }
 409         }
 410
 411         if (dp83822->fx_enabled) {
 412                 err = phy_modify(phydev, MII_DP83822_CTRL_2,
 413                                  DP83822_FX_ENABLE, 1);
 414                 if (err < 0)
 415                         return err;
 416
 417                 /* Only allow advertising what this PHY supports */
 418                 linkmode_and(phydev->advertising, phydev->advertising,
 419                              phydev->supported);
 420
 421                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 422                                  phydev->supported);
 423                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 424                                  phydev->advertising);
 425                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 426                                  phydev->supported);
 427                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 428                                  phydev->supported);
 429                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 430                                  phydev->advertising);
 431                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 432                                  phydev->advertising);
 433
 434                 /* Auto neg is not supported in fiber mode */
 435                 bmcr = phy_read(phydev, MII_BMCR);
 436                 if (bmcr < 0)
 437                         return bmcr;
 438
 439                 if (bmcr & BMCR_ANENABLE) {
 440                         err =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
 441                         if (err < 0)
 442                                 return err;
 443                 }
 444                 phydev->autoneg = AUTONEG_DISABLE;
 445                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 446                                    phydev->supported);
 447                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 448                                    phydev->advertising);
 449
 450                 /* Setup fiber advertisement */
 451                 err = phy_modify_changed(phydev, MII_ADVERTISE,
 452                                          MII_DP83822_FIBER_ADVERTISE,
 453                                          MII_DP83822_FIBER_ADVERTISE);
 454
 455                 if (err < 0)
 456                         return err;
 457
 458                 if (dp83822->fx_signal_det_low) {
 459                         err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
 460                                                MII_DP83822_GENCFG,
 461                                                DP83822_SIG_DET_LOW);
 462                         if (err)
 463                                 return err;
 464                 }
 465         }
 466         return dp8382x_disable_wol(phydev);
 467 }
 468
 469 static int dp8382x_config_init(struct phy_device *phydev)
 470 {
 471         return dp8382x_disable_wol(phydev);
 472 }
 473
 474 static int dp83822_phy_reset(struct phy_device *phydev)
 475 {
 476         int err;
 477
 478         err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
 479         if (err < 0)
 480                 return err;
 481
 482         return phydev->drv->config_init(phydev);
 483 }
 484
 485 #ifdef CONFIG_OF_MDIO
 486 static int dp83822_of_init(struct phy_device *phydev)
 487 {
 488         struct dp83822_private *dp83822 = phydev->priv;
 489         struct device *dev = &phydev->mdio.dev;
 490
 491         /* Signal detection for the PHY is only enabled if the FX_EN and the
 492          * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
 493          * is strapped otherwise signal detection is disabled for the PHY.
 494          */
 495         if (dp83822->fx_enabled && dp83822->fx_sd_enable)
 496                 dp83822->fx_signal_det_low = device_property_present(dev,
 497                                                                      "ti,link-loss-low");
 498         if (!dp83822->fx_enabled)
 499                 dp83822->fx_enabled = device_property_present(dev,
 500                                                               "ti,fiber-mode");
 501
 502         return 0;
 503 }
 504 #else
 505 static int dp83822_of_init(struct phy_device *phydev)
 506 {
 507         return 0;
 508 }
 509 #endif /* CONFIG_OF_MDIO */
 510
 511 static int dp83822_read_straps(struct phy_device *phydev)
 512 {
 513         struct dp83822_private *dp83822 = phydev->priv;
 514         int fx_enabled, fx_sd_enable;
 515         int val;
 516
 517         val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
 518         if (val < 0)
 519                 return val;
 520
 521         fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
 522         if (fx_enabled == DP83822_STRAP_MODE2 ||
 523             fx_enabled == DP83822_STRAP_MODE3)
 524                 dp83822->fx_enabled = 1;
 525
 526         if (dp83822->fx_enabled) {
 527                 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
 528                 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
 529                     fx_sd_enable == DP83822_STRAP_MODE4)
 530                         dp83822->fx_sd_enable = 1;
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int dp83822_probe(struct phy_device *phydev)
 537 {
 538         struct dp83822_private *dp83822;
 539         int ret;
 540
 541         dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
 542                                GFP_KERNEL);
 543         if (!dp83822)
 544                 return -ENOMEM;
 545
 546         phydev->priv = dp83822;
 547
 548         ret = dp83822_read_straps(phydev);
 549         if (ret)
 550                 return ret;
 551
 552         dp83822_of_init(phydev);
 553
 554         if (dp83822->fx_enabled)
 555                 phydev->port = PORT_FIBRE;
 556
 557         return 0;
 558 }
 559
 560 static int dp83822_suspend(struct phy_device *phydev)
 561 {
 562         int value;
 563
 564         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 565
 566         if (!(value & DP83822_WOL_EN))
 567                 genphy_suspend(phydev);
 568
 569         return 0;
 570 }
 571
 572 static int dp83822_resume(struct phy_device *phydev)
 573 {
 574         int value;
 575
 576         genphy_resume(phydev);
 577
 578         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 579
 580         phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
 581                       DP83822_WOL_CLR_INDICATION);
 582
 583         return 0;
 584 }
 585
 586 #define DP83822_PHY_DRIVER(_id, _name)                          \
 587         {                                                       \
 588                 PHY_ID_MATCH_MODEL(_id),                        \
 589                 .name           = (_name),                      \
 590                 /* PHY_BASIC_FEATURES */                        \
 591                 .probe          = dp83822_probe,                \
 592                 .soft_reset     = dp83822_phy_reset,            \
 593                 .config_init    = dp83822_config_init,          \
 594                 .read_status    = dp83822_read_status,          \
 595                 .get_wol = dp83822_get_wol,                     \
 596                 .set_wol = dp83822_set_wol,                     \
 597                 .config_intr = dp83822_config_intr,             \
 598                 .handle_interrupt = dp83822_handle_interrupt,   \
 599                 .suspend = dp83822_suspend,                     \
 600                 .resume = dp83822_resume,                       \
 601         }
 602
 603 #define DP8382X_PHY_DRIVER(_id, _name)                          \
 604         {                                                       \
 605                 PHY_ID_MATCH_MODEL(_id),                        \
 606                 .name           = (_name),                      \
 607                 /* PHY_BASIC_FEATURES */                        \
 608                 .soft_reset     = dp83822_phy_reset,            \
 609                 .config_init    = dp8382x_config_init,          \
 610                 .get_wol = dp83822_get_wol,                     \
 611                 .set_wol = dp83822_set_wol,                     \
 612                 .config_intr = dp83822_config_intr,             \
 613                 .handle_interrupt = dp83822_handle_interrupt,   \
 614                 .suspend = dp83822_suspend,                     \
 615                 .resume = dp83822_resume,                       \
 616         }
 617
 618 static struct phy_driver dp83822_driver[] = {
 619         DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
 620         DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
 621         DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
 622         DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
 623         DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
 624         DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
 625         DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
 626 };
 627 module_phy_driver(dp83822_driver);
 628
 629 static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
 630         { DP83822_PHY_ID, 0xfffffff0 },
 631         { DP83825I_PHY_ID, 0xfffffff0 },
 632         { DP83826C_PHY_ID, 0xfffffff0 },
 633         { DP83826NC_PHY_ID, 0xfffffff0 },
 634         { DP83825S_PHY_ID, 0xfffffff0 },
 635         { DP83825CM_PHY_ID, 0xfffffff0 },
 636         { DP83825CS_PHY_ID, 0xfffffff0 },
 637         { },
 638 };
 639 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
 640
 641 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
 642 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 643 MODULE_LICENSE("GPL v2");