1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/broadcom.c
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
8 * Copyright (c) 2006 Maciej W. Rozycki
10 * Inspired by code written by Amy Fong.
13 #include "bcm-phy-lib.h"
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/phy.h>
17 #include <linux/brcmphy.h>
20 #define BRCM_PHY_MODEL(phydev) \
21 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
23 #define BRCM_PHY_REV(phydev) \
24 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
26 MODULE_DESCRIPTION("Broadcom PHY driver");
27 MODULE_AUTHOR("Maciej W. Rozycki");
28 MODULE_LICENSE("GPL");
30 static int bcm54xx_config_clock_delay(struct phy_device *phydev)
34 /* handling PHY's internal RX clock delay */
35 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
36 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
37 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
38 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
39 /* Disable RGMII RXC-RXD skew */
40 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
42 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
43 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
44 /* Enable RGMII RXC-RXD skew */
45 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
47 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
52 /* handling PHY's internal TX clock delay */
53 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
54 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
55 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
56 /* Disable internal TX clock delay */
57 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
59 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
60 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
61 /* Enable internal TX clock delay */
62 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
64 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
71 static int bcm54210e_config_init(struct phy_device *phydev)
75 bcm54xx_config_clock_delay(phydev);
77 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
78 val = phy_read(phydev, MII_CTRL1000);
79 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
80 phy_write(phydev, MII_CTRL1000, val);
86 static int bcm54612e_config_init(struct phy_device *phydev)
90 bcm54xx_config_clock_delay(phydev);
92 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
93 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
96 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
97 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
98 BCM54612E_LED4_CLK125OUT_EN | reg);
107 static int bcm54616s_config_init(struct phy_device *phydev)
111 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
112 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
115 /* Ensure proper interface mode is selected. */
116 /* Disable RGMII mode */
117 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
120 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
121 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
122 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
127 /* Select 1000BASE-X register set (primary SerDes) */
128 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
131 val |= BCM54XX_SHD_MODE_1000BX;
132 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
136 /* Power down SerDes interface */
137 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
141 /* Select proper interface mode */
142 val &= ~BCM54XX_SHD_INTF_SEL_MASK;
143 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
144 BCM54XX_SHD_INTF_SEL_SGMII :
145 BCM54XX_SHD_INTF_SEL_GBIC;
146 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
150 /* Power up SerDes interface */
151 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
155 /* Select copper register set */
156 val &= ~BCM54XX_SHD_MODE_1000BX;
157 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
161 /* Power up copper interface */
162 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
165 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
166 static int bcm50610_a0_workaround(struct phy_device *phydev)
170 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
171 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
172 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
176 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
177 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
181 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
182 MII_BCM54XX_EXP_EXP75_VDACCTRL);
186 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
187 MII_BCM54XX_EXP_EXP96_MYST);
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
192 MII_BCM54XX_EXP_EXP97_MYST);
197 static int bcm54xx_phydsp_config(struct phy_device *phydev)
201 /* Enable the SMDSP clock */
202 err = bcm54xx_auxctl_write(phydev,
203 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
204 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
205 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
209 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
210 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
211 /* Clear bit 9 to fix a phy interop issue. */
212 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
213 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
217 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
218 err = bcm50610_a0_workaround(phydev);
224 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
227 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
231 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
232 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
236 /* Disable the SMDSP clock */
237 err2 = bcm54xx_auxctl_write(phydev,
238 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
239 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
241 /* Return the first error reported. */
242 return err ? err : err2;
245 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
249 bool clk125en = true;
251 /* Abort if we are using an untested phy. */
252 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
253 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
254 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
255 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
256 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
257 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
260 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
266 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
267 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
268 BRCM_PHY_REV(phydev) >= 0x3) {
270 * Here, bit 0 _disables_ CLK125 when set.
271 * This bit is set by default.
275 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
276 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
277 /* Here, bit 0 _enables_ CLK125 when set */
278 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
284 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
285 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
287 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
289 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
290 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
291 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
292 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
293 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS;
295 val |= BCM54XX_SHD_SCR3_TRDDAPD;
299 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
301 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
307 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
308 val |= BCM54XX_SHD_APD_EN;
310 val &= ~BCM54XX_SHD_APD_EN;
313 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
316 static int bcm54xx_config_init(struct phy_device *phydev)
320 reg = phy_read(phydev, MII_BCM54XX_ECR);
324 /* Mask interrupts globally. */
325 reg |= MII_BCM54XX_ECR_IM;
326 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
330 /* Unmask events we are interested in. */
331 reg = ~(MII_BCM54XX_INT_DUPLEX |
332 MII_BCM54XX_INT_SPEED |
333 MII_BCM54XX_INT_LINK);
334 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
338 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
339 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
340 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
341 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
343 bcm54xx_adjust_rxrefclk(phydev);
345 switch (BRCM_PHY_MODEL(phydev)) {
346 case PHY_ID_BCM50610:
347 case PHY_ID_BCM50610M:
348 err = bcm54xx_config_clock_delay(phydev);
350 case PHY_ID_BCM54210E:
351 err = bcm54210e_config_init(phydev);
353 case PHY_ID_BCM54612E:
354 err = bcm54612e_config_init(phydev);
356 case PHY_ID_BCM54616S:
357 err = bcm54616s_config_init(phydev);
359 case PHY_ID_BCM54810:
360 /* For BCM54810, we need to disable BroadR-Reach function */
361 val = bcm_phy_read_exp(phydev,
362 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
363 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
364 err = bcm_phy_write_exp(phydev,
365 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
372 bcm54xx_phydsp_config(phydev);
374 /* For non-SFP setups, encode link speed into LED1 and LED3 pair
376 * Also flash these two LEDs on activity. This means configuring
377 * them for MULTICOLOR and encoding link/activity into them.
378 * Don't do this for devices on an SFP module, since some of these
379 * use the LED outputs to control the SFP LOS signal, and changing
380 * these settings will cause LOS to malfunction.
382 if (!phy_on_sfp(phydev)) {
383 val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
384 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
385 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
387 val = BCM_LED_MULTICOLOR_IN_PHASE |
388 BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
389 BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
390 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
396 static int bcm54xx_resume(struct phy_device *phydev)
400 /* Writes to register other than BMCR would be ignored
401 * unless we clear the PDOWN bit first
403 ret = genphy_resume(phydev);
407 /* Upon exiting power down, the PHY remains in an internal reset state
412 return bcm54xx_config_init(phydev);
415 static int bcm54811_config_init(struct phy_device *phydev)
419 /* Disable BroadR-Reach function. */
420 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
421 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
422 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
427 err = bcm54xx_config_init(phydev);
429 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
430 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
431 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
432 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
433 BCM54612E_LED4_CLK125OUT_EN | reg);
441 static int bcm5481_config_aneg(struct phy_device *phydev)
443 struct device_node *np = phydev->mdio.dev.of_node;
447 ret = genphy_config_aneg(phydev);
449 /* Then we can set up the delay. */
450 bcm54xx_config_clock_delay(phydev);
452 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
453 /* Lane Swap - Undocumented register...magic! */
454 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
463 struct bcm54616s_phy_priv {
467 static int bcm54616s_probe(struct phy_device *phydev)
469 struct bcm54616s_phy_priv *priv;
472 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
478 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
482 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
483 * is 01b, and the link between PHY and its link partner can be
484 * either 1000Base-X or 100Base-FX.
485 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
486 * support is still missing as of now.
488 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
489 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
493 /* Bit 0 of the SerDes 100-FX Control register, when set
494 * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
495 * When this bit is set to 0, it sets the GMII/RGMII ->
496 * 1000BASE-X configuration.
498 if (!(val & BCM54616S_100FX_MODE))
499 priv->mode_1000bx_en = true;
501 phydev->port = PORT_FIBRE;
507 static int bcm54616s_config_aneg(struct phy_device *phydev)
509 struct bcm54616s_phy_priv *priv = phydev->priv;
513 if (priv->mode_1000bx_en)
514 ret = genphy_c37_config_aneg(phydev);
516 ret = genphy_config_aneg(phydev);
518 /* Then we can set up the delay. */
519 bcm54xx_config_clock_delay(phydev);
524 static int bcm54616s_read_status(struct phy_device *phydev)
526 struct bcm54616s_phy_priv *priv = phydev->priv;
529 if (priv->mode_1000bx_en)
530 err = genphy_c37_read_status(phydev);
532 err = genphy_read_status(phydev);
537 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
541 val = phy_read(phydev, reg);
545 return phy_write(phydev, reg, val | set);
548 static int brcm_fet_config_init(struct phy_device *phydev)
550 int reg, err, err2, brcmtest;
552 /* Reset the PHY to bring it to a known state. */
553 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
557 /* The datasheet indicates the PHY needs up to 1us to complete a reset,
558 * build some slack here.
560 usleep_range(1000, 2000);
562 /* The PHY requires 65 MDC clock cycles to complete a write operation
563 * and turnaround the line properly.
565 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
566 * may flag the lack of turn-around as a read failure. This is
567 * particularly true with this combination since the MDIO controller
568 * only used 64 MDC cycles. This is not a critical failure in this
569 * specific case and it has no functional impact otherwise, so we let
570 * that one go through. If there is a genuine bus error, the next read
571 * of MII_BRCM_FET_INTREG will error out.
573 err = phy_read(phydev, MII_BMCR);
574 if (err < 0 && err != -EIO)
577 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
581 /* Unmask events we are interested in and mask interrupts globally. */
582 reg = MII_BRCM_FET_IR_DUPLEX_EN |
583 MII_BRCM_FET_IR_SPEED_EN |
584 MII_BRCM_FET_IR_LINK_EN |
585 MII_BRCM_FET_IR_ENABLE |
586 MII_BRCM_FET_IR_MASK;
588 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
592 /* Enable shadow register access */
593 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
597 reg = brcmtest | MII_BRCM_FET_BT_SRE;
599 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
603 /* Set the LED mode */
604 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
610 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
611 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
613 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
617 /* Enable auto MDIX */
618 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
619 MII_BRCM_FET_SHDW_MC_FAME);
623 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
624 /* Enable auto power down */
625 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
626 MII_BRCM_FET_SHDW_AS2_APDE);
630 /* Disable shadow register access */
631 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
638 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
642 /* Clear pending interrupts. */
643 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
650 static int brcm_fet_config_intr(struct phy_device *phydev)
654 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
658 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
659 err = brcm_fet_ack_interrupt(phydev);
663 reg &= ~MII_BRCM_FET_IR_MASK;
664 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
666 reg |= MII_BRCM_FET_IR_MASK;
667 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
671 err = brcm_fet_ack_interrupt(phydev);
677 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
681 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
682 if (irq_status < 0) {
690 phy_trigger_machine(phydev);
695 struct bcm54xx_phy_priv {
699 static int bcm54xx_phy_probe(struct phy_device *phydev)
701 struct bcm54xx_phy_priv *priv;
703 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
709 priv->stats = devm_kcalloc(&phydev->mdio.dev,
710 bcm_phy_get_sset_count(phydev), sizeof(u64),
718 static void bcm54xx_get_stats(struct phy_device *phydev,
719 struct ethtool_stats *stats, u64 *data)
721 struct bcm54xx_phy_priv *priv = phydev->priv;
723 bcm_phy_get_stats(phydev, priv->stats, stats, data);
726 static struct phy_driver broadcom_drivers[] = {
728 .phy_id = PHY_ID_BCM5411,
729 .phy_id_mask = 0xfffffff0,
730 .name = "Broadcom BCM5411",
731 /* PHY_GBIT_FEATURES */
732 .get_sset_count = bcm_phy_get_sset_count,
733 .get_strings = bcm_phy_get_strings,
734 .get_stats = bcm54xx_get_stats,
735 .probe = bcm54xx_phy_probe,
736 .config_init = bcm54xx_config_init,
737 .config_intr = bcm_phy_config_intr,
738 .handle_interrupt = bcm_phy_handle_interrupt,
740 .phy_id = PHY_ID_BCM5421,
741 .phy_id_mask = 0xfffffff0,
742 .name = "Broadcom BCM5421",
743 /* PHY_GBIT_FEATURES */
744 .get_sset_count = bcm_phy_get_sset_count,
745 .get_strings = bcm_phy_get_strings,
746 .get_stats = bcm54xx_get_stats,
747 .probe = bcm54xx_phy_probe,
748 .config_init = bcm54xx_config_init,
749 .config_intr = bcm_phy_config_intr,
750 .handle_interrupt = bcm_phy_handle_interrupt,
752 .phy_id = PHY_ID_BCM54210E,
753 .phy_id_mask = 0xfffffff0,
754 .name = "Broadcom BCM54210E",
755 /* PHY_GBIT_FEATURES */
756 .get_sset_count = bcm_phy_get_sset_count,
757 .get_strings = bcm_phy_get_strings,
758 .get_stats = bcm54xx_get_stats,
759 .probe = bcm54xx_phy_probe,
760 .config_init = bcm54xx_config_init,
761 .config_intr = bcm_phy_config_intr,
762 .handle_interrupt = bcm_phy_handle_interrupt,
764 .phy_id = PHY_ID_BCM5461,
765 .phy_id_mask = 0xfffffff0,
766 .name = "Broadcom BCM5461",
767 /* PHY_GBIT_FEATURES */
768 .get_sset_count = bcm_phy_get_sset_count,
769 .get_strings = bcm_phy_get_strings,
770 .get_stats = bcm54xx_get_stats,
771 .probe = bcm54xx_phy_probe,
772 .config_init = bcm54xx_config_init,
773 .config_intr = bcm_phy_config_intr,
774 .handle_interrupt = bcm_phy_handle_interrupt,
776 .phy_id = PHY_ID_BCM54612E,
777 .phy_id_mask = 0xfffffff0,
778 .name = "Broadcom BCM54612E",
779 /* PHY_GBIT_FEATURES */
780 .get_sset_count = bcm_phy_get_sset_count,
781 .get_strings = bcm_phy_get_strings,
782 .get_stats = bcm54xx_get_stats,
783 .probe = bcm54xx_phy_probe,
784 .config_init = bcm54xx_config_init,
785 .config_intr = bcm_phy_config_intr,
786 .handle_interrupt = bcm_phy_handle_interrupt,
788 .phy_id = PHY_ID_BCM54616S,
789 .phy_id_mask = 0xfffffff0,
790 .name = "Broadcom BCM54616S",
791 /* PHY_GBIT_FEATURES */
792 .soft_reset = genphy_soft_reset,
793 .config_init = bcm54xx_config_init,
794 .config_aneg = bcm54616s_config_aneg,
795 .config_intr = bcm_phy_config_intr,
796 .handle_interrupt = bcm_phy_handle_interrupt,
797 .read_status = bcm54616s_read_status,
798 .probe = bcm54616s_probe,
800 .phy_id = PHY_ID_BCM5464,
801 .phy_id_mask = 0xfffffff0,
802 .name = "Broadcom BCM5464",
803 /* PHY_GBIT_FEATURES */
804 .get_sset_count = bcm_phy_get_sset_count,
805 .get_strings = bcm_phy_get_strings,
806 .get_stats = bcm54xx_get_stats,
807 .probe = bcm54xx_phy_probe,
808 .config_init = bcm54xx_config_init,
809 .config_intr = bcm_phy_config_intr,
810 .handle_interrupt = bcm_phy_handle_interrupt,
811 .suspend = genphy_suspend,
812 .resume = genphy_resume,
814 .phy_id = PHY_ID_BCM5481,
815 .phy_id_mask = 0xfffffff0,
816 .name = "Broadcom BCM5481",
817 /* PHY_GBIT_FEATURES */
818 .get_sset_count = bcm_phy_get_sset_count,
819 .get_strings = bcm_phy_get_strings,
820 .get_stats = bcm54xx_get_stats,
821 .probe = bcm54xx_phy_probe,
822 .config_init = bcm54xx_config_init,
823 .config_aneg = bcm5481_config_aneg,
824 .config_intr = bcm_phy_config_intr,
825 .handle_interrupt = bcm_phy_handle_interrupt,
827 .phy_id = PHY_ID_BCM54810,
828 .phy_id_mask = 0xfffffff0,
829 .name = "Broadcom BCM54810",
830 /* PHY_GBIT_FEATURES */
831 .get_sset_count = bcm_phy_get_sset_count,
832 .get_strings = bcm_phy_get_strings,
833 .get_stats = bcm54xx_get_stats,
834 .probe = bcm54xx_phy_probe,
835 .config_init = bcm54xx_config_init,
836 .config_aneg = bcm5481_config_aneg,
837 .config_intr = bcm_phy_config_intr,
838 .handle_interrupt = bcm_phy_handle_interrupt,
839 .suspend = genphy_suspend,
840 .resume = bcm54xx_resume,
842 .phy_id = PHY_ID_BCM54811,
843 .phy_id_mask = 0xfffffff0,
844 .name = "Broadcom BCM54811",
845 /* PHY_GBIT_FEATURES */
846 .get_sset_count = bcm_phy_get_sset_count,
847 .get_strings = bcm_phy_get_strings,
848 .get_stats = bcm54xx_get_stats,
849 .probe = bcm54xx_phy_probe,
850 .config_init = bcm54811_config_init,
851 .config_aneg = bcm5481_config_aneg,
852 .config_intr = bcm_phy_config_intr,
853 .handle_interrupt = bcm_phy_handle_interrupt,
854 .suspend = genphy_suspend,
855 .resume = bcm54xx_resume,
857 .phy_id = PHY_ID_BCM5482,
858 .phy_id_mask = 0xfffffff0,
859 .name = "Broadcom BCM5482",
860 /* PHY_GBIT_FEATURES */
861 .get_sset_count = bcm_phy_get_sset_count,
862 .get_strings = bcm_phy_get_strings,
863 .get_stats = bcm54xx_get_stats,
864 .probe = bcm54xx_phy_probe,
865 .config_init = bcm54xx_config_init,
866 .config_intr = bcm_phy_config_intr,
867 .handle_interrupt = bcm_phy_handle_interrupt,
869 .phy_id = PHY_ID_BCM50610,
870 .phy_id_mask = 0xfffffff0,
871 .name = "Broadcom BCM50610",
872 /* PHY_GBIT_FEATURES */
873 .get_sset_count = bcm_phy_get_sset_count,
874 .get_strings = bcm_phy_get_strings,
875 .get_stats = bcm54xx_get_stats,
876 .probe = bcm54xx_phy_probe,
877 .config_init = bcm54xx_config_init,
878 .config_intr = bcm_phy_config_intr,
879 .handle_interrupt = bcm_phy_handle_interrupt,
881 .phy_id = PHY_ID_BCM50610M,
882 .phy_id_mask = 0xfffffff0,
883 .name = "Broadcom BCM50610M",
884 /* PHY_GBIT_FEATURES */
885 .get_sset_count = bcm_phy_get_sset_count,
886 .get_strings = bcm_phy_get_strings,
887 .get_stats = bcm54xx_get_stats,
888 .probe = bcm54xx_phy_probe,
889 .config_init = bcm54xx_config_init,
890 .config_intr = bcm_phy_config_intr,
891 .handle_interrupt = bcm_phy_handle_interrupt,
893 .phy_id = PHY_ID_BCM57780,
894 .phy_id_mask = 0xfffffff0,
895 .name = "Broadcom BCM57780",
896 /* PHY_GBIT_FEATURES */
897 .get_sset_count = bcm_phy_get_sset_count,
898 .get_strings = bcm_phy_get_strings,
899 .get_stats = bcm54xx_get_stats,
900 .probe = bcm54xx_phy_probe,
901 .config_init = bcm54xx_config_init,
902 .config_intr = bcm_phy_config_intr,
903 .handle_interrupt = bcm_phy_handle_interrupt,
905 .phy_id = PHY_ID_BCMAC131,
906 .phy_id_mask = 0xfffffff0,
907 .name = "Broadcom BCMAC131",
908 /* PHY_BASIC_FEATURES */
909 .config_init = brcm_fet_config_init,
910 .config_intr = brcm_fet_config_intr,
911 .handle_interrupt = brcm_fet_handle_interrupt,
913 .phy_id = PHY_ID_BCM5241,
914 .phy_id_mask = 0xfffffff0,
915 .name = "Broadcom BCM5241",
916 /* PHY_BASIC_FEATURES */
917 .config_init = brcm_fet_config_init,
918 .config_intr = brcm_fet_config_intr,
919 .handle_interrupt = brcm_fet_handle_interrupt,
921 .phy_id = PHY_ID_BCM5395,
922 .phy_id_mask = 0xfffffff0,
923 .name = "Broadcom BCM5395",
924 .flags = PHY_IS_INTERNAL,
925 /* PHY_GBIT_FEATURES */
926 .get_sset_count = bcm_phy_get_sset_count,
927 .get_strings = bcm_phy_get_strings,
928 .get_stats = bcm54xx_get_stats,
929 .probe = bcm54xx_phy_probe,
931 .phy_id = PHY_ID_BCM53125,
932 .phy_id_mask = 0xfffffff0,
933 .name = "Broadcom BCM53125",
934 .flags = PHY_IS_INTERNAL,
935 /* PHY_GBIT_FEATURES */
936 .get_sset_count = bcm_phy_get_sset_count,
937 .get_strings = bcm_phy_get_strings,
938 .get_stats = bcm54xx_get_stats,
939 .probe = bcm54xx_phy_probe,
940 .config_init = bcm54xx_config_init,
941 .config_intr = bcm_phy_config_intr,
942 .handle_interrupt = bcm_phy_handle_interrupt,
944 .phy_id = PHY_ID_BCM89610,
945 .phy_id_mask = 0xfffffff0,
946 .name = "Broadcom BCM89610",
947 /* PHY_GBIT_FEATURES */
948 .get_sset_count = bcm_phy_get_sset_count,
949 .get_strings = bcm_phy_get_strings,
950 .get_stats = bcm54xx_get_stats,
951 .probe = bcm54xx_phy_probe,
952 .config_init = bcm54xx_config_init,
953 .config_intr = bcm_phy_config_intr,
954 .handle_interrupt = bcm_phy_handle_interrupt,
957 module_phy_driver(broadcom_drivers);
959 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
960 { PHY_ID_BCM5411, 0xfffffff0 },
961 { PHY_ID_BCM5421, 0xfffffff0 },
962 { PHY_ID_BCM54210E, 0xfffffff0 },
963 { PHY_ID_BCM5461, 0xfffffff0 },
964 { PHY_ID_BCM54612E, 0xfffffff0 },
965 { PHY_ID_BCM54616S, 0xfffffff0 },
966 { PHY_ID_BCM5464, 0xfffffff0 },
967 { PHY_ID_BCM5481, 0xfffffff0 },
968 { PHY_ID_BCM54810, 0xfffffff0 },
969 { PHY_ID_BCM54811, 0xfffffff0 },
970 { PHY_ID_BCM5482, 0xfffffff0 },
971 { PHY_ID_BCM50610, 0xfffffff0 },
972 { PHY_ID_BCM50610M, 0xfffffff0 },
973 { PHY_ID_BCM57780, 0xfffffff0 },
974 { PHY_ID_BCMAC131, 0xfffffff0 },
975 { PHY_ID_BCM5241, 0xfffffff0 },
976 { PHY_ID_BCM5395, 0xfffffff0 },
977 { PHY_ID_BCM53125, 0xfffffff0 },
978 { PHY_ID_BCM89610, 0xfffffff0 },
982 MODULE_DEVICE_TABLE(mdio, broadcom_tbl);